Preparation method of heterojunction solar cell and heterojunction solar cell

Abstract

The invention provides a heterojunction solar cell preparation method and a heterojunction solar cell, and relates to the technical field of solar cells. The preparation method of the heterojunction solar cell comprises the step of respectively forming an intrinsic passivation layer, a doping layer, a transparent conductive layer and an electrode on a first surface and a second surface of a substrate. Before the first transparent conductive layer is formed on the first doping layer, at least one first transition layer is formed on the first doping layer, and / or before the second transparent conductive layer is formed on the second doping layer, at least one second transition layer is formed on the second doping layer. Therefore, the interface contact between the first doping layer and the first transparent conductive layer and / or the interface contact between the second doping layer and the second transparent conductive layer can be improved, so that the conversion efficiency of the heterojunction solar cell is improved, and the UV attenuation of the cell is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and particularly to a method for manufacturing a heterojunction solar cell and a heterojunction solar cell. Background Art

[0002] In existing heterojunction solar cells, the doped layer is in direct contact with the transparent conductive layer. Due to the large difference in lattice structure between the doped layer and the transparent conductive layer, the interface matching is poor, resulting in poor contact resistance performance and affecting the further improvement of the photovoltaic cell performance. Summary of the Invention

[0003] The first aspect of the present invention aims to provide a method for manufacturing a heterojunction solar cell, so as to solve the technical problem that in the existing heterojunction solar cell, the interface matching between the doped layer and the transparent conductive layer in direct contact is poor, resulting in poor contact resistance performance.

[0004] Another object of the first aspect of the present invention is to improve the conversion efficiency of the heterojunction solar cell.

[0005] The second aspect of the present invention aims to provide a heterojunction solar cell.

[0006] According to the object of the first aspect of the present invention, the present invention provides a method for manufacturing a heterojunction solar cell, and the manufacturing method includes the following steps:

[0007] Form at least one first intrinsic passivation layer and at least one second intrinsic passivation layer on the first surface and the second surface of the substrate respectively;

[0008] Form at least one first doped layer on the first intrinsic passivation layer, and the first doped layer has a first conductive doping type;

[0009] Form at least one second doped layer on the second intrinsic passivation layer, and the second doped layer has a second conductive doping type opposite to the first conductive doping type;

[0010] Form at least one first transparent conductive layer and at least one second transparent conductive layer on the first doped layer and the second doped layer respectively;

[0011] Form a first electrode and a second electrode on the first transparent conductive layer and the second transparent conductive layer respectively;

[0012] Before forming the first transparent conductive layer on the first doped layer, it further includes: forming at least one first transition layer on the first doped layer;

[0013] And / or,

[0014] Before forming the second transparent conductive layer on the second doping layer, the method further includes: forming at least one second transition layer on the second doping layer.

[0015] Optionally, the first transition layer is selected from one of amorphous silicon-based materials, microcrystalline silicon-based materials, or nanocrystalline silicon-based materials having the first conductive doping type; and / or, the second transition layer is selected from one of amorphous silicon-based materials, microcrystalline silicon-based materials, or nanocrystalline silicon-based materials having the second conductive doping type.

[0016] Optionally, the doping concentration of the first transition layer is greater than that of the first doping layer, and / or the doping concentration of the second transition layer is greater than that of the second doping layer.

[0017] Optionally, the first transition layer includes multiple layers, and in the direction from the first doping layer to the first transparent conductive layer, the doping concentration of the first transition layer gradually increases; and / or,

[0018] The second transition layer includes multiple layers, and in the direction from the second doping layer to the second transparent conductive layer, the doping concentration of the second transition layer gradually increases.

[0019] Optionally, before forming the first electrode on the first transparent conductive layer, the method further includes: forming at least one first buffer layer on the first transparent conductive layer;

[0020] and / or,

[0021] Before forming the second electrode on the second transparent conductive layer, the method further includes: forming at least one second buffer layer on the second transparent conductive layer.

[0022] Optionally, the material of the first buffer layer and / or the second buffer layer is doped microcrystalline silicon or VTTO.

[0023] Optionally, the first buffer layer is a microcrystalline silicon doping material having the first conductive doping type; and / or the second buffer layer is a microcrystalline silicon doping material having the second conductive doping type.

[0024] Optionally, the materials of the first doping layer and the second doping layer are selected from one of amorphous silicon-based materials, microcrystalline silicon-based materials, or nanocrystalline silicon-based materials; and / or

[0025] At least one of the first doping layer and the second doping layer includes multiple sub-doping layers, and the doping concentration of each sub-doping layer increases layer by layer in the direction away from the silicon wafer.

[0026] Optionally, before forming the first electrode and the second electrode, a heat treatment process is further included; the heat treatment process includes: annealing at 150 - 220 °C for 5 - 50 minutes.

[0027] According to the object of the second aspect of the present invention, the present invention further provides a heterojunction solar cell, which is prepared by the preparation method of the heterojunction solar cell described above.

[0028] In the preparation method of the heterojunction solar cell of the present invention, before forming the first transparent conductive layer on the first doping layer, at least one first transition layer is further included on the first doping layer; and / or, before forming the second transparent conductive layer on the second doping layer, at least one second transition layer is further included on the second doping layer. By adding at least one first transition layer between the first doping layer and the first transparent conductive layer, and / or adding at least one second transition layer between the second doping layer and the second transparent conductive layer, the above technical solution can reduce the interface contact, improve the interface contact between the first doping layer and the first transparent conductive layer, and / or improve the interface contact between the second doping layer and the second transparent conductive layer, thereby improving the conversion efficiency of the heterojunction solar cell and improving the UV attenuation of the battery.

[0029] Furthermore, in the present invention, a first buffer layer is further included between the first transparent conductive layer and the first electrode, and / or a second buffer layer is further included between the second transparent conductive layer and the second electrode. In this way, it can improve the deterioration of electrical performance caused by the direct contact between the surface transparent conductive layer and the electrode, improve the contact between the transparent conductive layer and the electrode, improve the transport efficiency of photo-generated carriers between the transparent conductive layer and the electrode, and improve the conversion efficiency of the heterojunction solar cell. In addition, the buffer layer can further act as a protective layer for the transparent conductive layer to prevent the transparent conductive layer from failing due to environmental invasion, thereby improving the photoelectric conversion efficiency of the heterojunction solar cell and extending the service life of the battery.

[0030] Based on the following detailed description of the specific embodiments of the present invention in conjunction with the drawings, those skilled in the art will become more clear about the above and other objects, advantages and features of the present invention. Description of the Drawings

[0031] Some specific embodiments of the present invention will be described in detail hereinafter with reference to the drawings in an exemplary but non-limiting manner. The same reference numerals in the drawings denote the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0032] Figure 1 is a schematic structural diagram of a heterojunction solar cell according to the first embodiment of the present invention;

[0033] Figure 2 Schematic structural diagram of a heterojunction solar cell according to the second embodiment of the present invention;

[0034] Figure 3 Schematic structural diagram of a heterojunction solar cell according to the third embodiment of the present invention;

[0035] Figure 4 Schematic structural diagram of a heterojunction solar cell according to the fourth embodiment of the present invention;

[0036] Figure 5 Schematic structural diagram of a heterojunction solar cell according to the fifth embodiment of the present invention;

[0037] Figure 6 Schematic structural diagram of a heterojunction solar cell according to the sixth embodiment of the present invention;

[0038] Figure 7 Schematic structural diagram of a heterojunction solar cell according to the seventh embodiment of the present invention;

[0039] Figure 8 Schematic structural diagram of a heterojunction solar cell according to the eighth embodiment of the present invention;

[0040] Figure 9 Schematic process flow of the preparation method of a heterojunction solar cell according to a specific embodiment of the present invention Figure 1 ;

[0041] Figure 10 Schematic process flow of the preparation method of a heterojunction solar cell according to a specific embodiment of the present invention Figure 2 ;

[0042] Figure 11 Schematic process flow of the preparation method of a heterojunction solar cell according to a specific embodiment of the present invention Figure 3 ;

[0043] Figure 12 Schematic process flow of the preparation method of a heterojunction solar cell according to a specific embodiment of the present invention Figure 4 ;

[0044] Figure 13 Schematic process flow of the preparation method of a heterojunction solar cell according to a specific embodiment of the present invention Figure 5 ;

[0045] Figure 14 Schematic process flow of the preparation method of a heterojunction solar cell according to a specific embodiment of the present invention Figure 6 。

[0046] Description of reference numerals:

[0047] 100 - Heterojunction solar cell, 10 - Substrate, 21 - First intrinsic passivation layer, 22 - Second intrinsic passivation layer, 31 - First doping layer, 32 - Second doping layer, 41 - First transparent conductive layer, 42 - Second transparent conductive layer, 51 - First electrode, 52 - Second electrode, 61 - First transition layer, 62 - Second transition layer, 71 - First buffer layer, 72 - Second buffer layer. Detailed implementation manners

[0048] In the description of this embodiment, it should be understood that the orientation or positional relationship indicated by terms such as "inner" and "outer" is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0049] Figure 1 is a schematic structural diagram of a heterojunction solar cell 100 according to the first embodiment of the present invention, Figure 2 is a schematic structural diagram of a heterojunction solar cell 100 according to the second embodiment of the present invention, Figure 3 is a schematic structural diagram of a heterojunction solar cell 100 according to the third embodiment of the present invention. As Figures 1 - 3 shown, the heterojunction solar cell 100 of the embodiment of the present invention may include a substrate 10, at least one layer of first intrinsic passivation layer 21, at least one layer of first doping layer 31, at least one layer of first transparent conductive layer 41, a first electrode 51, at least one layer of second intrinsic passivation layer 22, at least one layer of second doping layer 32, at least one layer of second transparent conductive layer 42, and a second electrode 52. The heterojunction solar cell 100 further includes at least one layer of first transition layer 61 and / or at least one layer of second transition layer 62.

[0050] Among them, the substrate 10 includes a first surface and a second surface. In some embodiments, the substrate 10 may adopt a silicon substrate. The substrate 10 can provide mechanical support for the heterojunction solar cell 100 and provide a stable path for electron transport inside the heterojunction solar cell 100. The first surface of the substrate 10 refers to the light-receiving surface of the heterojunction solar cell 100, and the second surface refers to the backlight surface of the heterojunction solar cell 100.

[0051] In an embodiment of the present invention, the substrate 10 may be a silicon substrate, such as a single-crystalline silicon substrate, a polycrystalline silicon substrate, or a quasi-single-crystalline silicon substrate, etc. The embodiment of the present invention does not limit the specific type of the substrate 10. And the semiconductor substrate may be P-type doped or N-type doped, that is, the substrate 10 may be a P-type semiconductor substrate or an N-type semiconductor substrate. The heterojunction solar cell 100 of the embodiment of the present invention may be an N-type heterojunction solar cell 100, or may be a P-type heterojunction solar cell 100. Exemplarily, in some embodiments, the substrate 10 is an N-type single-crystalline silicon substrate (also referred to as an N-type single-crystalline silicon wafer).

[0052] At least one layer of the first intrinsic passivation layer 21 is located on the first surface of the substrate 10. At least one layer of the second intrinsic passivation layer 22 is located on the second surface of the substrate 10. In some embodiments, the first intrinsic passivation layer 21 and the second intrinsic passivation layer 22 are made of amorphous silicon material. The first intrinsic passivation layer 21 and the second intrinsic passivation layer 22 can passivate the surface of the substrate 10, and can effectively reduce the recombination loss of carriers caused by surface defects and impurities. In some embodiments, referring to Figure 1 , the number of both the first intrinsic passivation layer 21 and the second intrinsic passivation layer 22 is one layer. In other embodiments, the number of the first intrinsic passivation layer 21 and the second intrinsic passivation layer 22 can be set according to actual needs, for example, it can be 2 layers, 3 layers, 4 layers, 5 layers.

[0053] At least one layer of the first doped layer 31 is located on the first intrinsic passivation layer 21, and the first doped layer 31 has a first conductive doping type. At least one layer of the second doped layer 32 is located on the second intrinsic passivation layer 22, and the second doped layer 32 has a second conductive doping type opposite to the first conductive doping type. In some embodiments, referring to Figure 1 , the number of both the first doped layer 31 and the second doped layer 32 is one layer. In other embodiments, the number of the first doped layer 31 and the second doped layer 32 can be set according to actual needs, for example, it can be 2 layers, 3 layers, 4 layers, 5 layers.

[0054] In some embodiments, the main components of the first doped layer 31 and the second doped layer 32 are a mixture of microcrystalline silicon and silicon oxide. The doping types of the first doped layer 31 and the second doped layer 32 are opposite, one of which is N-type doping, that is, phosphorus doping is used, and the other is P-type doping, that is, boron doping is used.

[0055] Specifically, the first conductive doping type is N-type. The first doped layer 31 and the first intrinsic passivation layer 21 jointly form a surface field, and the surface field can reduce carrier recombination and improve the open-circuit voltage and short-circuit current density of the heterojunction solar cell 100.

[0056] The second conductive doping type is P-type. The second doping layer 32 and the second intrinsic passivation layer 22 together form a p-n heterojunction on the back surface. Under illumination, this heterojunction can generate a built-in electric field, causing photo-generated carriers to be separated under the action of the built-in electric field and move in opposite directions, thereby realizing photoelectric conversion.

[0057] At least one layer of the first transparent conductive layer 41 is located on the first doping layer 31. At least one layer of the second transparent conductive layer 42 is located on the second doping layer 32. The transparent conductive layer allows light to pass through and collects the current generated by the heterojunction layer, and provides an electrical connection to the external circuit. In some embodiments, the transparent conductive layer is made of materials such as indium tin oxide (ITO) and is deposited on the doping layer by methods such as PVD (physical vapor deposition).

[0058] In some embodiments, referring to Figure 1 , the number of both the first transparent conductive layer 41 and the second transparent conductive layer 42 is one layer. In other embodiments, the number of the first transparent conductive layer 41 and the second transparent conductive layer 42 can be set according to actual needs.

[0059] The transparent conductive layer not only has a high transmittance, enabling sunlight to pass through as much as possible and reach the semiconductor absorption layer, but also has good electrical conductivity, capable of effectively collecting and transporting photo-generated carriers and reducing the series resistance when collecting current.

[0060] The first electrode 51 is located on the first transparent conductive layer 41. The second electrode 52 is located on the second transparent conductive layer 42. Specifically, the first electrode 51 is formed on the first transparent conductive layer 41 of the heterojunction solar cell 100 by screen printing or electroplating technology. As the electrode of the heterojunction solar cell 100, it is responsible for leading out the current collected by the first transparent conductive layer 41 from the heterojunction solar cell 100 for connection to the external circuit to achieve the output of electrical energy. The second electrode 52 is formed on the second transparent conductive layer 42 of the heterojunction solar cell 100 by screen printing or electroplating technology. As the electrode of the heterojunction solar cell 100, it is responsible for leading out the current collected by the second transparent conductive layer 42 from the heterojunction solar cell 100 for connection to the external circuit to achieve the output of electrical energy.

[0061] At least one layer of the first transition layer 61 is located between the first doping layer 31 and the first transparent conductive layer 41, and / or at least one layer of the second transition layer 62 is located between the second doping layer 32 and the second transparent conductive layer 42. The transition layer can reduce the contact resistance between the first doping layer 31 and the first transparent conductive layer 41, and / or reduce the contact resistance between the second doping layer 32 and the second transparent conductive layer 42.

[0062] In some embodiments, referring to Figure 3, the number of the first transition layer 61 and the second transition layer 62 is both one layer. In other embodiments, the number of the first transition layer 61 and the second transition layer 62 can be set according to actual needs, for example, it can be 2 layers, 3 layers, 4 layers, or 5 layers.

[0063] In the embodiment of the present invention, at least one first transition layer 61 is newly added between the first doping layer 31 and the first transparent conductive layer 41, and / or at least one second transition layer 62 is added between the second doping layer 32 and the second transparent conductive layer 42. By using the relatively better interface matching between the transition layer and the transparent conductive layer, the contact resistance can be reduced, the interface contact between the first doping layer 31 and the first transparent conductive layer 41 can be improved, and / or the interface contact between the second doping layer 32 and the second transparent conductive layer 42 can be improved, thereby improving the conversion efficiency of the heterojunction solar cell 100 and improving the UV attenuation of the battery.

[0064] In some embodiments, the first transition layer 61 can be selected from one of amorphous silicon-based materials, microcrystalline silicon-based materials, or nanocrystalline silicon-based materials with a first conductive doping type, and / or the second transition layer 62 can be selected from one of amorphous silicon-based materials, microcrystalline silicon-based materials, or nanocrystalline silicon-based materials with a second conductive doping type.

[0065] When the transition layer is selected from amorphous silicon-based materials, the contact between the transition layer and the transparent conductive layer is good. By using the relatively better interface matching between amorphous silicon and the transparent conductive layer, the carrier transport efficiency can be improved and the contact resistance can be reduced.

[0066] When the transition layer is selected from microcrystalline silicon-based materials, process optimization needs to be carried out under conditions of high impurity doping concentration and low oxygen doping content. Microcrystalline silicon-based materials have good crystal structures and electrical properties, but due to their poor interface contact with the transparent conductive layer, more interface defects will be formed when contacting the transparent conductive layer, and then a higher contact resistance will be generated, which is not conducive to the transport of carriers. It is necessary to adjust with impurity doping and oxygen content.

[0067] When the transition layer is selected as nanocrystalline silicon-based materials, due to the nanoscale microstructure of nanocrystalline silicon-based materials, the crystalline phase part can provide an efficient transport channel for carriers. When contacting the transparent conductive layer, the carriers can be quickly conducted, the contact resistance can be reduced, which is beneficial to improving the fill factor and conversion efficiency of the battery. Moreover, the crystal structure of nanocrystalline silicon-based materials is relatively regular, making the interface formed between the transition layer and the transparent conductive layer relatively ordered, and the interface state density is low, which can reduce the capture of carriers and is beneficial to improving the open circuit voltage and short circuit current of the battery.

[0068] In some embodiments, preferably, the doping concentration of the first transition layer 61 is greater than that of the first doping layer 31, and / or the doping concentration of the second transition layer 62 is greater than that of the second doping layer 32.

[0069] In this embodiment, since the doping concentration of the transition layer is greater than that of the doping layer, the contact resistance formed when the transition layer contacts the transparent conductive layer is relatively low, which can improve the carrier collection efficiency, increase the fill factor of the battery, and thus improve the conversion efficiency of the battery. By making the doping concentration of the transition layer greater than that of the doping layer, this embodiment can reduce the series resistance and contact resistance of the heterojunction solar cell 100.

[0070] In some embodiments, preferably, the substrate 10 is an N-type monocrystalline silicon substrate, the doping concentration of the first transition layer 61 is between 5% and 30%, and the doping concentration of the second transition layer 62 is between 1% and 20%, which can further reduce the resistance of the transition layer and improve the interface contact.

[0071] In some embodiments, the first transition layer 61 can include multiple layers, and in the direction from the first doping layer 31 to the first transparent conductive layer 41, the doping concentration of the first transition layer 61 gradually increases, and / or the second transition layer 62 includes multiple layers, and in the direction from the second doping layer 32 to the second transparent conductive layer 42, the doping concentration of the second transition layer 62 gradually increases.

[0072] It can be understood that from the perspective of electrical properties, the higher the doping concentration of the transition layer, the lower the resistance and the lower the contact resistance with the transparent conductive layer. However, for the heterojunction solar cell 100, it is necessary to take into account the optical properties of the heterojunction solar cell 100, especially the optical properties on the front side of the cell. A high doping concentration will cause a decrease in transmittance and deteriorate the optical performance. In the embodiment of the present invention, in the direction from the doping layer to the transparent conductive layer, the doping concentration of the multiple transition layers gradually increases, which can not only ensure the light transmittance and optical performance but also reduce the contact resistance between the transition layer and the transparent conductive layer.

[0073] In the prior art, the contact between the transparent conductive layer and the metal electrode is poor, which further limits the transport of photo-generated carriers at the interface of the transparent conductive layer - metal electrode, hindering the further improvement of the efficiency of the photovoltaic cell.

[0074] Figure 4 It is a schematic structural diagram of the heterojunction solar cell 100 according to the fourth embodiment of the present invention. Figure 5 It is a schematic structural diagram of the heterojunction solar cell 100 according to the fifth embodiment of the present invention. Figure 6 It is a schematic structural diagram of the heterojunction solar cell 100 according to the sixth embodiment of the present invention. As Figures 4 - 6As shown, in some embodiments, a first buffer layer 71 may be further included between the first transparent conductive layer 41 and the first electrode 51, and / or a second buffer layer 72 may be further included between the second transparent conductive layer 42 and the second electrode 52.

[0075] In this embodiment, a buffer layer is added between the transparent conductive layer and the electrode to form a transparent conductive layer / buffer layer / electrode interface, avoiding the deterioration of electrical performance caused by the direct contact between the transparent conductive layer and the electrode, improving the contact between the transparent conductive layer and the electrode, enhancing the transport efficiency of photo-generated carriers between the transparent conductive layer and the electrode, and increasing the photoelectric conversion efficiency of the heterojunction solar cell 100. The buffer layer can further act as a protective layer for the transparent conductive layer, preventing the transparent conductive layer from failing due to environmental invasion, and thus extending the service life of the battery.

[0076] In some embodiments, the material of the first buffer layer 71 and / or the second buffer layer 72 may be doped microcrystalline silicon or VTTO.

[0077] When doped microcrystalline silicon is used as the buffer layer, the carrier mobility is relatively high, enabling efficient separation and collection of photo-generated carriers, increasing the short-circuit current and fill factor, and further enhancing the photoelectric conversion efficiency of the battery.

[0078] When VTTO (mainly composed of indium oxide, with a small amount of tantalum pentoxide) is used as the buffer layer material, it can maintain good conductivity while having a high visible light transmittance, improving the photoelectric conversion efficiency of the battery. The VTTO buffer layer can also reduce the contact resistance between the transparent conductive layer and the electrode.

[0079] This embodiment uses a doped microcrystalline silicon buffer layer or a VTTO buffer layer to improve the interfacial contact between the transparent conductive layer and the electrode, thereby increasing the conversion efficiency of the battery. Moreover, the doped microcrystalline silicon or VTTO has good stability, enhancing the protection of the transparent conductive layer and further improving the long-term stability and service life of the heterojunction solar cell 100.

[0080] In some embodiments, the first buffer layer 71 may be a microcrystalline silicon doping material with a first conductive doping type; and / or the second buffer layer 72 may be a microcrystalline silicon doping material with a second conductive doping type.

[0081] In this embodiment, a layer of microcrystalline silicon doping material is added between the transparent conductive layer and the electrode as a transition layer to form a transparent conductive layer / microcrystalline silicon and microcrystalline silicon / electrode interface, avoiding the deterioration of the electrical performance of the battery caused by the direct contact between the transparent conductive layer and the electrode. Additionally, the newly added microcrystalline silicon doping buffer layer has a good protective effect when acting as a protective layer for the transparent conductive layer, preventing the transparent conductive layer from failing due to environmental invasion, and thus further extending the service life of the heterojunction solar cell 100.

[0082] In some embodiments, the first doping layer 31 may be selected from one of amorphous silicon-based materials, microcrystalline silicon-based materials, or nanocrystalline silicon-based materials, and / or the second doping layer 32 may be selected from one of amorphous silicon-based materials, microcrystalline silicon-based materials, or nanocrystalline silicon-based materials.

[0083] Specifically, amorphous silicon-based materials have a high optical absorption coefficient in the visible light range, can effectively absorb photons in sunlight, generate more photo-generated carriers, achieve a high light absorption rate, and can improve the photoelectric conversion efficiency of the battery. The electrical properties of amorphous silicon-based materials can be effectively adjusted by doping to form P-type or N-type semiconductors with good performance, which helps to increase the short-circuit current and fill factor of the battery.

[0084] Microcrystalline silicon-based materials have a high carrier mobility, which means that carriers can be transported more quickly in the microcrystalline silicon-based doping layer, reducing the recombination probability of carriers during the transport process. Using microcrystalline silicon-based materials for the transition layer can achieve a low resistivity, effectively conduct current, thereby increasing the fill factor and short-circuit current of the battery, and helping to improve the photoelectric conversion efficiency of the battery.

[0085] Due to its nanoscale structure, nanocrystalline silicon-based materials have unique quantum effects and crystal structures, resulting in a high mobility of carriers in the nanocrystalline silicon-based doping layer. The nanocrystalline silicon-based doping layer can quickly transport electrons and holes, reducing the scattering and recombination of carriers during the transport process, thereby increasing the short-circuit current and fill factor of the battery and improving the photoelectric conversion efficiency of the battery.

[0086] As a preferred embodiment, the doping layer uses microcrystalline silicon-based materials and the transition layer uses amorphous silicon-based materials. The microcrystalline doping layer has better electrical properties than the amorphous doping layer, can reduce the transport loss of carriers, and thus improve the photoelectric conversion efficiency of the battery. The amorphous transition layer is located between the transparent conductive layer and the microcrystalline doping layer, and can reduce the contact resistance between the transparent conductive layer and the microcrystalline doping layer.

[0087] Figure 9 is a schematic flow chart of the preparation method of the heterojunction solar cell 100 according to a specific embodiment of the present invention Figure 1 , Figure 10 is a schematic flow chart of the preparation method of the heterojunction solar cell 100 according to a specific embodiment of the present invention Figure 2 , Figure 11 is a schematic flow chart of the preparation method of the heterojunction solar cell 100 according to a specific embodiment of the present invention Figure 3 . As Figures 9 - 11 shown, the embodiment of the present invention also provides a preparation method of a heterojunction solar cell 100, and the method includes the following steps:

[0088] Step S100, form at least one layer of first intrinsic passivation layer 21 and at least one layer of second intrinsic passivation layer 22 on the first surface and the second surface of the substrate 10 respectively;

[0089] Step S200, form at least one layer of first doped layer 31 on the first intrinsic passivation layer 21, and the first doped layer 31 has a first conductive doping type;

[0090] Form at least one layer of second doped layer 32 on the second intrinsic passivation layer 22, and the second doped layer 32 has a second conductive doping type opposite to the first conductive doping type.

[0091] After step S200, it further includes:

[0092] Step S320, form at least one layer of first transition layer 61 on the first doped layer 31;

[0093] Step S420, form at least one layer of transparent conductive layer on the first transition layer 61, and form at least one layer of second transparent conductive layer 42 on the second doped layer 32;

[0094] Step S600, form a first electrode 51 and a second electrode 52 on the first transparent conductive layer 41 and the second transparent conductive layer 42 respectively.

[0095] Or, after step S300, it further includes:

[0096] Step S340, form at least one layer of second transition layer 62 on the second doped layer 32,

[0097] Step S440, form at least one layer of transparent conductive layer on the second transition layer 62, and form at least one layer of second transparent conductive layer 42 on the first doped layer 31;

[0098] Step S600, form a first electrode 51 and a second electrode 52 on the first transparent conductive layer 41 and the second transparent conductive layer 42 respectively.

[0099] Or, after step S300, it further includes:

[0100] Step S360, form at least one layer of first transition layer 61 on the first doped layer 31 and form at least one layer of second transition layer 62 on the second doped layer 32;

[0101] Step S460, form at least one layer of transparent conductive layer on the second transition layer 62, and form at least one layer of second transparent conductive layer 42 on the first transition layer 61;

[0102] Step S600, form a first electrode 51 and a second electrode 52 on the first transparent conductive layer 41 and the second transparent conductive layer 42 respectively.

[0103] In an embodiment of the present invention, at least one first transition layer 61 is added between the first doped layer 31 and the first transparent conductive layer 41, and / or at least one second transition layer 62 is added between the second doped layer 32 and the second transparent conductive layer 42. By utilizing the relatively better interface matching between the transition layer and the transparent conductive layer, the contact resistance can be reduced, the interface contact between the first doped layer 31 and the first transparent conductive layer 41 can be improved, and / or the interface contact between the second doped layer 32 and the second transparent conductive layer 42 can be improved, thereby improving the conversion efficiency of the heterojunction solar cell 100 and improving the UV attenuation of the battery.

[0104] In some embodiments, the first transition layer 61 can be selected from one of amorphous silicon-based materials, microcrystalline silicon-based materials, or nanocrystalline silicon-based materials having a first conductive doping type; and / or the second transition layer 62 can be selected from one of amorphous silicon-based materials, microcrystalline silicon-based materials, or nanocrystalline silicon-based materials having a second conductive doping type.

[0105] When the transition layer is selected from amorphous silicon-based materials, the contact between the transition layer and the transparent conductive layer is good. By utilizing the relatively better interface matching between amorphous silicon and the transparent conductive layer, the carrier transport efficiency can be improved and the contact resistance can be reduced.

[0106] When the transition layer is selected from microcrystalline silicon-based materials, process optimization is required under conditions of high impurity doping concentration and low oxygen doping content. Microcrystalline silicon-based materials have good crystal structures and electrical properties. However, due to the poor interface contact with the transparent conductive layer, more interface defects will be formed when contacting the transparent conductive layer, resulting in a relatively high contact resistance, which is not conducive to carrier transport and requires adjustment with impurity doping and oxygen content.

[0107] When the transition layer is selected as a nanocrystalline silicon-based material, due to the nanoscale microstructure of the nanocrystalline silicon-based material, the crystalline phase part can provide an efficient transport channel for carriers. When contacting the transparent conductive layer, carriers can be quickly conducted, the contact resistance can be reduced, which is beneficial to improving the fill factor and conversion efficiency of the battery. Moreover, the crystal structure of the nanocrystalline silicon-based material is relatively regular, making the interface formed between the transition layer and the transparent conductive layer relatively ordered and the interface state density relatively low, which can reduce the capture of carriers and is beneficial to improving the open-circuit voltage and short-circuit current of the battery.

[0108] In some embodiments, preferably, the doping concentration of the first transition layer 61 is greater than the doping concentration of the first doped layer 31, and / or the doping concentration of the second transition layer 62 is greater than the doping concentration of the second doped layer 32.

[0109] In this embodiment, the doping concentration of the transition layer is greater than that of the doped layer, so the contact resistance formed when the transition layer contacts the transparent conductive layer is relatively low, the carrier collection efficiency can be improved, the fill factor of the battery can be increased, and thus the conversion efficiency of the battery can be improved.

[0110] In some embodiments, preferably, the substrate 10 is an N-type single-crystalline silicon substrate, the doping concentration of the first transition layer 61 is between 5% and 30%, and the doping concentration of the second transition layer 62 is between 1% and 20%, which can further reduce the resistance of the transition layer and improve the interface contact.

[0111] In some embodiments, the first transition layer 61 can include multiple layers, and in the direction from the first doping layer 31 to the first transparent conductive layer 41, the doping concentration of the first transition layer 61 gradually increases, and / or the second transition layer 62 includes multiple layers, and in the direction from the second doping layer 32 to the second transparent conductive layer 42, the doping concentration of the second transition layer 62 gradually increases.

[0112] It can be understood that from the perspective of electrical properties, the higher the doping concentration of the transition layer, the lower the resistance and the lower the contact resistance with the transparent conductive layer. However, for the heterojunction solar cell 100, it is necessary to take into account the optical properties of the heterojunction solar cell 100, especially the optical properties of the front side of the cell. A high doping concentration will cause a decrease in transmittance and deteriorate the optical performance. In the embodiments of the present invention, in the direction from the doping layer to the transparent conductive layer, the doping concentration of the multiple transition layers gradually increases, which can not only ensure the light transmittance and optical performance but also reduce the contact resistance between the transition layer and the transparent conductive layer.

[0113] Figure 12 is a schematic flowchart of a method for manufacturing a heterojunction solar cell 100 according to a specific embodiment of the present invention Figure 4 , Figure 13 is a schematic flowchart of a method for manufacturing a heterojunction solar cell 100 according to a specific embodiment of the present invention Figure 5 , Figure 14 is a schematic flowchart of a method for manufacturing a heterojunction solar cell 100 according to a specific embodiment of the present invention Figure 6 . As Figures 12 - 14 shown, in some embodiments, after step S420, or step S440, or step S460 ( Figure 12 taking step S460 as an example in

[0114] step S520, forming at least one first buffer layer 71 on the first transparent conductive layer 41;

[0115] step S620, forming a first electrode 51 on the first buffer layer 71 and a second electrode 52 on the second transparent conductive layer 42, respectively.

[0116] Or after step S420, or step S440, or step S460 ( Figure 13 taking step S460 as an example in

[0117] Step S540: form at least one second buffer layer 72 on the second transparent conductive layer 42;

[0118] Step S640: form a second electrode 52 on the second buffer layer 72 and form a first electrode 51 on the first transparent conductive layer 41 respectively.

[0119] Or after step S420, or step S440, or step S460 ( Figure 14 taking step S460 as an example), it further includes:

[0120] Step S560: form at least one first buffer layer 71 on the first transparent conductive layer 41 and form at least one second buffer layer 72 on the second transparent conductive layer 42 respectively.

[0121] Step S660: form a first electrode 51 on the first buffer layer 71 and form a second electrode 52 on the second buffer layer 72 respectively.

[0122] In this embodiment, a buffer layer is added between the transparent conductive layer and the electrode to form a transparent conductive layer / buffer layer / electrode interface, avoiding the deterioration of electrical performance caused by the direct contact between the transparent conductive layer and the electrode, improving the contact between the transparent conductive layer and the electrode, enhancing the transport efficiency of photo-generated carriers between the transparent conductive layer and the electrode, and improving the photoelectric conversion efficiency of the heterojunction solar cell 100. The buffer layer can further act as a protective layer for the transparent conductive layer to prevent the transparent conductive layer from failing due to environmental attack, thereby extending the service life of the battery.

[0123] In some embodiments, the material of the first buffer layer 71 and / or the second buffer layer 72 can be doped microcrystalline silicon or VTTO.

[0124] When doped microcrystalline silicon is used as the buffer layer, it has a relatively high carrier mobility, enabling efficient separation and collection of photo-generated carriers, increasing the short-circuit current and fill factor, and thus further improving the photoelectric conversion efficiency of the battery.

[0125] When VTTO (mainly composed of indium oxide and containing a small amount of tantalum pentoxide) is used as the buffer layer material, it can maintain good conductivity while having a relatively high visible light transmittance, improving the photoelectric conversion efficiency of the battery. The VTTO buffer layer can also reduce the contact resistance between the transparent conductive layer and the electrode.

[0126] This embodiment can improve the interface contact between the transparent conductive layer and the electrode by using a doped microcrystalline silicon buffer layer or a VTTO buffer layer, thereby improving the conversion efficiency of the battery. Moreover, doped microcrystalline silicon or VTTO has good stability, which can enhance the protection of the transparent conductive layer, and further improve the long-term stability and service life of the heterojunction solar cell 100.

[0127] In some embodiments, the first buffer layer 71 can be made of a microcrystalline silicon doped material having a first conductive doping type; and / or, the second buffer layer 72 can be made of a microcrystalline silicon doped material having a second conductive doping type.

[0128] In this embodiment, a layer of microcrystalline silicon doped material is added between the transparent conductive layer and the electrode as a transition layer, forming a transparent conductive layer / microcrystalline silicon and microcrystalline silicon / electrode interface, which avoids the deterioration of the electrical performance of the battery caused by the direct contact between the transparent conductive layer and the electrode. Moreover, the newly added microcrystalline silicon doped buffer layer has a good protection effect when acting as a protective layer for the transparent conductive layer, preventing the transparent conductive layer from failing due to environmental invasion, thereby further extending the service life of the heterojunction solar cell 100.

[0129] In some embodiments, the first doping layer 31 can be selected from one of amorphous silicon-based materials, microcrystalline silicon-based materials, or nanocrystalline silicon-based materials, and / or, the second doping layer 32 can be selected from one of amorphous silicon-based materials, microcrystalline silicon-based materials, or nanocrystalline silicon-based materials.

[0130] Specifically, the electrical properties of amorphous silicon-based materials can be effectively adjusted by doping to form P-type or N-type semiconductors with good performance, which helps to increase the short-circuit current and fill factor of the battery.

[0131] Microcrystalline silicon-based materials have a high carrier mobility, which means that carriers can be transported more quickly in the microcrystalline silicon-based doping layer, reducing the recombination probability of carriers during transmission. Using microcrystalline silicon-based materials for the transition layer can achieve a lower resistivity, effectively conduct current, thereby increasing the fill factor and short-circuit current of the battery, and helping to improve the photoelectric conversion efficiency of the battery.

[0132] Due to its nanoscale structure, nanocrystalline silicon-based materials have unique quantum effects and crystal structures, resulting in a high carrier mobility in the nanocrystalline silicon-based doping layer. The nanocrystalline silicon-based doping layer can quickly transport electrons and holes, reducing the scattering and recombination of carriers during transmission, thereby increasing the short-circuit current and fill factor of the battery and improving the photoelectric conversion efficiency of the battery.

[0133] Since the annealing conditions of the coating film layer after PVD do not match the temperature requirements of the silver paste, in order to match the pull-off force of the silver paste and the line group contact resistance, the annealing of the PVD coating film layer may not reach the required temperature.

[0134] In some embodiments, before forming the first electrode 51 and the second electrode 52, a heat treatment process can also be included; the heat treatment process includes: annealing at 150 - 220°C for 5 - 50 minutes.

[0135] In this embodiment, annealing treatment is first performed after PVD to anneal and recrystallize the blue film (i.e., the TCO film layer) in advance. This can improve the crystallization performance of the transparent conductive layer and the contact between the transparent conductive layer and the electrode.

[0136] In some other embodiments, the heating method can be hot air or infrared, which can increase the electrical injection. The process treatment can be carried out under vacuum, and the vacuum range is between 0 and 1E-07 mbar. The heat treatment process can be a separate machine treatment, or integrated with PVD, or integrated with screen printing, and then screen printing is carried out. When forming the electrode by screen printing, a furnace can be added before screen printing for annealing the blue film.

[0137] The following combines Figures 1 - 8 to describe in detail the preparation method of the heterojunction solar cell 100 in the embodiment of the present invention.

[0138] Embodiment 1

[0139] 1) The N-type monocrystalline silicon wafer is processed into a double-sided pyramid textured structure. Among them, the processing methods can include chemical etching, plasma etching, photolithography, metal-assisted catalytic etching and other processes.

[0140] 2) The first intrinsic passivation layer 21 is deposited on the first surface of the silicon wafer, and the second intrinsic passivation layer 22 is deposited on the second surface of the silicon wafer. The deposition methods can adopt techniques such as plasma-enhanced chemical vapor deposition, hot-wire chemical vapor deposition, low-pressure chemical vapor deposition or atomic layer deposition. The intrinsic passivation layer can be any one of amorphous silicon or silicon dioxide or a mixture of both.

[0141] 3) The first doped layer 31 is deposited on the first intrinsic passivation layer 21, and the second doped layer 32 is deposited on the second intrinsic passivation layer 22. Among them, the deposition method is the same as that in step 2). The doped layer can adopt microcrystalline silicon material or polycrystalline silicon carbide material.

[0142] 4) The first transition layer 61 is deposited on the first doped layer 31, and the second doped layer 32 is not processed. Among them, the deposition method is the same as that in step 2). The first transition layer 61 is N-type doped. The material of the first transition layer 61 is amorphous silicon material.

[0143] 5) The first transparent conductive layer 41 is deposited on the first transition layer 61, and the second transparent conductive layer 42 is deposited on the second doped layer 32. Among them, the deposition methods can include magnetron sputtering deposition, reactive plasma deposition, printing, spraying, spin coating, etc. The material of the transparent conductive layer can be ITO (indium tin oxide), FTO (fluorine-doped tin oxide), AZO (aluminum-doped zinc oxide), IZO (indium zinc oxide), IWO (tungsten-doped indium oxide), graphene, conductive polymer, etc.

[0144] 6) Prepare the first electrode 51 on the first transparent conductive layer 41, and prepare the second electrode 52 on the second transparent conductive layer 42. Among them, the electrode preparation methods can include printing, electroplating, electroless plating, inkjet printing, laser-induced transfer, etc. The electrode material can be one or a mixture of silver, copper, nickel, chromium, titanium, aluminum, tungsten, etc.

[0145] See Figure 1 , in this embodiment, a first transition layer 61 is added between the first doping layer 31 and the first transparent conductive layer 41. Between the first doping layer 31 and the first transparent conductive layer 41, by using the relatively better interface matching between the first transition layer 61 and the first transparent conductive layer 41, the effect of reducing the contact resistance can be achieved, the interface contact between the first doping layer 31 and the first transparent conductive layer 41 can be improved, thereby improving the conversion efficiency of the heterojunction solar cell 100 and improving the UV attenuation of the battery.

[0146] Example 2

[0147] 1) The same as step 1) of Example 1.

[0148] 2) The same as step 2) of Example 1.

[0149] 3) The same as step 3) of Example 1.

[0150] 4) Deposit a second transition layer 62 on the second doping layer 32, and do not process the first doping layer 31. Among them, the deposition method is the same as step 2). The second transition layer 62 is P-type doped. The material of the second transition layer 62 is amorphous silicon material.

[0151] 5) Deposit the second transparent conductive layer 42 on the second transition layer 62, and deposit the first transparent conductive layer 41 on the first doping layer 31. Among them, the deposition methods can include magnetron sputtering deposition, reactive plasma deposition, printing, spraying, spin coating, etc. The material of the transparent conductive layer can be ITO (indium tin oxide), FTO (fluorine-doped tin oxide), AZO (aluminum-doped zinc oxide), IZO (indium zinc oxide), IWO (tungsten-doped indium oxide), graphene, conductive polymer, etc.

[0152] 6) The same as step 6) of Example 1.

[0153] See Figure 2 , in this embodiment, a second transition layer 62 is newly added between the second doping layer 32 and the second transparent conductive layer 42. By using the relatively better interface matching between the second transition layer 62 and the second transparent conductive layer 42, the effect of reducing the contact resistance can be achieved, the interface contact between the second doping layer 32 and the second transparent conductive layer 42 can be improved, thereby improving the conversion efficiency of the heterojunction solar cell 100 and improving the UV attenuation of the battery.

[0154] Example 3

[0155] 1) The same as step 1) of Example 1.

[0156] 2) The same as step 2) of Example 1.

[0157] 3) The same as step 3) of Example 1.

[0158] 4) Deposit a first transition layer 61 on the first doping layer 31 and a second transition layer 62 on the second doping layer 32 respectively. Among them, the deposition method is the same as step 2). The first transition layer 61 is N-type doped, and the second transition layer 62 is P-type doped. The materials of the first transition layer 61 and the second transition layer 62 are both amorphous silicon materials.

[0159] 5) Deposit a first transparent conductive layer 41 on the first transition layer 61 and a second transparent conductive layer 42 on the second transition layer 62. Among them, the deposition method can adopt magnetron sputtering deposition, reactive plasma deposition, printing, spraying, spin coating, etc. The materials of the transparent conductive layer can be ITO (indium tin oxide), FTO (fluorine-doped tin oxide), AZO (aluminum-doped zinc oxide), IZO (indium zinc oxide), IWO (tungsten-doped indium oxide), graphene, conductive polymers, etc.

[0160] 6) The same as step 6) of Example 1.

[0161] See Figure 3 , in this example, a first transition layer 61 is newly added between the first doping layer 31 and the first transparent conductive layer 41, and a second transition layer 62 is added between the second doping layer 32 and the second transparent conductive layer 42. By using the relatively better interface matching between the transition layer and the transparent conductive layer, the contact resistance can be reduced, the interface contact between the first doping layer 31 and the first transparent conductive layer 41 can be improved, and the interface contact between the second doping layer 32 and the second transparent conductive layer 42 can be improved, which can further improve the conversion efficiency of the heterojunction solar cell 100 and improve the UV attenuation of the battery.

[0162] Example 4

[0163] Steps 1) to 5) of this example are respectively the same as steps 1) to 5) of Example 3. The difference is that after step 5), it further includes:

[0164] 6) Deposit a first buffer layer 71 on the first transparent conductive layer 41, and do not process the second transparent conductive layer 42. Among them, when the first buffer layer 71 is made of microcrystalline silicon material, the deposition method can adopt techniques such as plasma-enhanced chemical vapor deposition, hot-wire chemical vapor deposition, low-pressure chemical vapor deposition or atomic layer deposition. When the first buffer layer 71 is made of VTTO, the deposition method can adopt magnetron sputtering deposition, reactive plasma deposition, printing, spraying, spin coating, etc.

[0165] 7) Deposit a first electrode 51 on the first buffer layer 71, and deposit a second electrode 52 on the second transparent conductive layer 42. Among them, the electrode preparation methods can adopt printing, electroplating, electroless plating, inkjet printing and laser-induced transfer, etc. The electrode material can be one or a mixture of silver, copper, nickel, chromium, titanium, aluminum, tungsten, etc.

[0166] See Figure 4 , in this embodiment, a first buffer layer 71 is added between the first transparent conductive layer 41 and the first electrode 51 to form the interfaces of the first transparent conductive layer 41 / first buffer layer 71 and the first buffer layer 71 / first electrode 51, avoiding the deterioration of the electrical performance of the battery caused by the direct contact between the first transparent conductive layer 41 and the first electrode 51, and the newly added first buffer layer 71 can further act as a protective layer for the first transparent conductive layer 41 to prevent the first transparent conductive layer 41 from failing due to environmental invasion, thereby extending the service life of the battery.

[0167] Example 5

[0168] Steps 1) - 5) of this embodiment are respectively the same as steps 1) - 5) of Example 3. The difference is that after step 5), it further includes:

[0169] 6) Do not process the first transparent conductive layer 41, and deposit a second buffer layer 72 on the second transparent conductive layer 42. Among them, when the second buffer layer 72 is made of microcrystalline silicon material, the deposition method can adopt techniques such as plasma-enhanced chemical vapor deposition, hot-wire chemical vapor deposition, low-pressure chemical vapor deposition or atomic layer deposition. When the second buffer layer 72 is made of VTTO, the deposition method can adopt magnetron sputtering deposition, reactive plasma deposition, printing, spraying, spin coating, etc.

[0170] 7) Deposit a first electrode 51 on the first transparent conductive layer 41, and deposit a second electrode 52 on the second buffer layer 72. Among them, the electrode preparation methods can adopt printing, electroplating, electroless plating, inkjet printing and laser-induced transfer, etc. The electrode material can be one or a mixture of silver, copper, nickel, chromium, titanium, aluminum, tungsten, etc.

[0171] See Figure 5, in this embodiment, a second buffer layer 72 is added between the second transparent conductive layer 42 and the second electrode 52, forming the interfaces of the second transparent conductive layer 42 / the second buffer layer 72 and the second buffer layer 72 / the second electrode 52, avoiding the deterioration of the electrical performance of the battery caused by the direct contact between the second transparent conductive layer 42 and the second electrode 52, and the newly added second buffer layer 72 can further act as a protective layer for the second transparent conductive layer 42, preventing the second transparent conductive layer 42 from failing due to environmental attack, thereby extending the service life of the battery.

[0172] Embodiment 6

[0173] Steps 1) to 5) of this embodiment are respectively the same as steps 1) to 5) of Embodiment 3. The difference lies in that after step 5), it further includes:

[0174] 6) Deposit a first buffer layer 71 on the first transparent conductive layer 41 and a second buffer layer 72 on the second transparent conductive layer 42 respectively. When the buffer layer is made of microcrystalline silicon material, the deposition method can adopt techniques such as plasma enhanced chemical vapor deposition, hot wire chemical vapor deposition, low pressure chemical vapor deposition or atomic layer deposition. When the buffer layer is made of VTTO, the deposition method can adopt magnetron sputtering deposition, reactive plasma deposition, printing, spraying, spin coating, etc.

[0175] 7) Deposit a first electrode 51 on the first buffer layer 71 and a second electrode 52 on the second buffer layer 72. Among them, the electrode preparation methods can adopt printing, electroplating, electroless plating, inkjet printing and laser induced transfer, etc. The electrode materials can be one or a mixture of silver, copper, nickel, chromium, titanium, aluminum, tungsten, etc.

[0176] See Figure 6 , in this embodiment, a buffer layer is added between the transparent conductive layers and the electrodes on both sides of the substrate 10 respectively, forming the interfaces of the transparent conductive layer / microcrystalline silicon and microcrystalline silicon / electrode, avoiding the deterioration of the electrical performance caused by the direct contact between the transparent conductive layer and the electrode, and the newly added buffer layer can further act as a protective layer for the transparent conductive layer, preventing the transparent conductive layer from failing due to environmental attack, thereby extending the service life of the battery.

[0177] Embodiment 7

[0178] 1) Use wet etching technology to process the N-type monocrystalline silicon wafer into a double-sided pyramid textured structure. Among them, the alkaline solution selected for the wet etching technology is KOH or NaOH, or a mixture of both, with the temperature between 40°C and 90°C; the selected acidic solution can be HF, HCl, HNO 3 or any mixture of the three, with the temperature between 20°C and 70°C.

[0179] 2) Deposit an N-type first intrinsic passivation layer 21 on the first surface of the silicon wafer, and deposit a P-type second intrinsic passivation layer 22 on the second surface of the silicon wafer. Among them, the deposition method can adopt chemical vapor deposition technology. The intrinsic passivation layer includes at least two sub-intrinsic passivation layers. The intrinsic passivation layer close to the silicon wafer is amorphous silicon deposited by pure silane, or amorphous silicon oxide formed by mixing silane with carbon dioxide or nitrous oxide. The temperature of the intrinsic passivation layer process is between 150°C and 250°C, and the pressure is between 0.2 tor and 2.0 tor. When using the hydrogenated amorphous silicon process, the ratio of silane to hydrogen is controlled between 1:1 and 1:30, and the thickness of the overall amorphous passivation layer should be controlled between 3 and 10 nm.

[0180] 3) Deposit a first doped layer 31 on the first intrinsic passivation layer 21, and deposit a second doped layer 32 on the second intrinsic passivation layer 22. Among them, the deposition method is the same as that in step 2). The doped layer uses a microcrystalline silicon-based material.

[0181] Preferably, at least one of the first doped layer 31 and the second doped layer 32 includes a plurality of sub-doped layers, and the doping concentration of each sub-doped layer increases layer by layer as the distance from the silicon wafer increases, that is, the closer to the outer surface of the battery, the higher the doping concentration, so as to improve the conductivity of the doped layer. Among them, the number of sub-layers can be 2 layers, 3 layers, 4 layers, etc.

[0182] Specifically, Figure 7 is a schematic structural diagram of the heterojunction solar cell 100 according to the seventh embodiment of the present invention, as Figure 7 shown, the microcrystalline doped layer includes three sub-doped layers. The doping concentration of the sub-doped layer close to the silicon wafer is zero or the lowest doping concentration, which can prevent doping atoms from diffusing into the passivation layer to form impurity energy levels and affect the passivation effect. The ratio of silane to hydrogen is controlled between 1:200 and 1:500, and the proportion of hydrogen in the gas mixture of silane and hydrogen in each sub-layer remains the same or gradually decreases as the distance from the silicon wafer increases. That is, the microcrystalline doped layer close to the passivation layer has the highest hydrogen ratio, which can improve its crystallization performance while reducing the etching of the underlying intrinsic passivation layer.

[0183] The process temperature of the microcrystalline doped layer is between 150°C and 250°C, and the pressure is between 3 tor and 9 tor. The N-type doped layer is doped with phosphine, and the doping concentration is between 0% and 12%, and the overall thickness is controlled between 10 and 40 nm. The P-type doped layer is doped with borane, and the doping concentration is controlled between 0% and 3%, and the overall thickness is controlled between 10 and 60 nm.

[0184] 4) Deposit a first transition layer 61 on the first doping layer 31 and deposit a second transition layer 62 on the second doping layer 32. Among them, the deposition method is the same as that in step 2). Among them, the first transition layer 61 is N-type doped, and the second transition layer 62 is P-type doped. The materials of the first transition layer 61 and the second transition layer 62 are both amorphous silicon materials. The N-type amorphous transition layer can be deposited by mixing silane and phosphine gases, or a mixture of silane, phosphine and hydrogen. The P-type amorphous transition layer can be deposited by mixing silane and borane gases, or a mixture of silane, borane and hydrogen.

[0185] The process temperatures of the two amorphous transition layers are between 150 °C and 250 °C, the pressures are between 0.2 tor and 5.0 tor, and the thicknesses are controlled between 1 nm and 5 nm. The doping concentration of the N-type amorphous transition layer is between 12% and 40%, and the doping concentration of the P-type amorphous transition layer is between 1% and 6%. The doping concentration of the amorphous transition layer is greater than or equal to the concentration of the adjacent microcrystalline doping layer.

[0186] Here, using the amorphous doping layer as the transition layer between the microcrystalline doping layer and the transparent conductive layer can effectively utilize the passivation and low-resistance characteristics of the amorphous doping layer, improve the interfacial contact resistance of the battery, reduce the transport loss of carriers, and thus improve the conversion efficiency of the battery.

[0187] 5) Deposit a first transparent conductive layer 41 on the first transition layer 61 and deposit a second transparent conductive layer 42 on the second transition layer 62. Among them, the physical vapor deposition method is adopted for the deposition. The material of the transparent conductive layer is selected as ITO (indium tin oxide). The process temperature is between 100 °C and 300 °C. The process gas is mainly a mixture of argon, oxygen and hydrogen. Among them, the proportion of oxygen is between 0.3% and 3.5%, and the proportion of hydrogen is between 0.5% and 3.5%. The thickness is controlled between 60 nm and 150 nm.

[0188] 6) Deposit a first buffer layer 71 on the first transparent conductive layer 41 and deposit a second buffer layer 72 on the second transparent conductive layer 42 respectively. Among them, the material of the buffer layer is VTTO or doped microcrystalline silicon.

[0189] When the buffer layer material is selected as VTTO, the process is carried out by physical vapor deposition. The process temperature is between 100 °C and 300 °C. The process gas is mainly a mixture of argon, oxygen and hydrogen. Among them, the proportion of oxygen is between 0.3% and 3.5%, and the proportion of hydrogen is between 0.5% and 3.5%. The thickness is controlled between 10 nm and 50 nm. Compared with ITO, VTTO has a higher mobility and is more conducive to the transport of carriers.

[0190] When the buffer layer material is microcrystalline silicon material, the process is carried out by chemical vapor deposition. The temperature of the microcrystalline buffer layer process is between 150°C and 250°C, and the pressure is between 3 tor and 9 tor. Further, the N-type buffer layer is doped with phosphine, and the doping concentration is between 0% and 12%, and the overall thickness is controlled between 10 and 40 nm. The P-type buffer layer is doped with borane, and the doping concentration is controlled between 0% and 3%, and the overall thickness is controlled between 10 and 60 nm.

[0191] The buffer layer has a better ability to block environmental water and oxygen than the transparent conductive layer. Therefore, it can act as a protective layer for the transparent conductive layer to prevent the transparent conductive layer from failing due to environmental invasion, thereby extending the service life of the battery.

[0192] 7) Prepare the first electrode 51 on the first buffer layer 71 and the second electrode 52 on the second buffer layer 72 respectively. Among them, the electrodes are prepared by screen printing technology to form a complete carrier transport path, so that the current generated by photo-generated carriers (electrons and holes) can be transmitted from the inside of the battery to the external circuit.

[0193] Example 8

[0194] Steps 1) - 3) of this example are respectively the same as steps 1) - 3) of Example 3. The difference is that after step 3), it includes:

[0195] 4) Deposit the first transition layer 61 on the first doping layer 31 and the second transition layer 62 on the second doping layer 32 respectively.

[0197] Figure 8 It is a schematic structural diagram of the heterojunction solar cell 100 according to the eighth embodiment of the present invention. As Figure 8 shown, the heterojunction solar cell 100 includes two layers of the first transition layer 61 and two layers of the second transition layer 62, and in the direction from the first doping layer 31 to the first transparent conductive layer 41, the doping concentration of the first transition layer 61 gradually increases, and in the direction from the second doping layer 32 to the second transparent conductive layer 42, the doping concentration of the second transition layer 62 gradually increases.

[0198] Among them, the first transition layer 61 is N-type doped, and the second transition layer 62 is P-type doped. The materials of the first transition layer 61 and the second transition layer 62 are both amorphous silicon materials. The N-type amorphous transition layer can be deposited by mixing silane and phosphine gas, or a mixture of silane, phosphine and hydrogen gas. The P-type amorphous transition layer can be deposited by mixing silane and borane gas, or a mixture of silane, borane and hydrogen gas.

[0199] The temperatures of the two amorphous transition layers are between 150°C and 250°C, the pressures are between 0.2 tor and 5.0 tor, and the thicknesses are controlled between 1 nm and 5 nm. The doping concentration of the N-type amorphous transition layer is between 12% and 40%, and the doping concentration of the P-type amorphous transition layer is between 1% and 6%. The doping concentration of the amorphous transition layer is greater than or equal to the doping concentration of the adjacent microcrystalline layer.

[0200] 5) The same as step 5) of Example 3.

[0201] 6) The same as step 6) of Example 3.

[0202] See Figure 8 , in this embodiment, the doping concentration of the layer closest to the silicon wafer in the transition layer is the lowest, and the doping concentration of other layers increases layer by layer in the direction away from the silicon wafer, that is, the closer to the outer surface of the battery, the higher the doping concentration, which can reduce the contact resistance between the transition layer and the transparent conductive layer, thereby improving the conductive performance of the battery.

[0203] Example 9

[0204] Steps 1) to 6) of this embodiment are respectively the same as steps 1) to 6) of Example 3. The difference is that before step 6), it further includes:

[0205] An infrared heating annealing furnace is used to perform an annealing heat treatment process on the heterojunction solar cell 100. The heat treatment process is: annealing for 5 - 50 minutes at 150 - 220°C. This can improve the crystallization performance of the transparent conductive layer and the contact between the transparent conductive layer and the electrode.

[0206] In this embodiment, by performing the annealing treatment after PVD, the annealing and recrystallization of the blue film can be completed in advance. After annealing, the curing time of the blue film after printing and LED can be shortened. The curing time is shortened to 5 - 35 min, and the mobility of the annealed PVD blue film can reach more than 85 cm / (V·s), and the carrier concentration reaches 2.5E - 20 cm - 2 or more.

[0207] At this point, those skilled in the art should recognize that although multiple exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications that conform to the principles of the present invention can still be directly determined or derived from the disclosed content of the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be understood and determined to cover all these other variations or modifications.

Claims

1. A method for preparing a heterojunction solar cell, the method comprising the following steps: forming at least one first intrinsic passivation layer and at least one second intrinsic passivation layer on the first surface and the second surface of the substrate respectively; forming at least one first doping layer on the first intrinsic passivation layer, wherein the first doping layer has a first conductive doping type; forming at least one second doped layer on the second intrinsic passivation layer, wherein the second doped layer has a second conductive doping type opposite to the first conductive doping type; forming at least one first transparent conductive layer and at least one second transparent conductive layer on the first doped layer and the second doped layer respectively; A first electrode and a second electrode are formed on the first transparent conductive layer and the second transparent conductive layer respectively; characterized in that: Before forming the first transparent conductive layer on the first doped layer, the method further includes: forming at least one first transition layer on the first doped layer; and / or, Before forming the second transparent conductive layer on the second doping layer, the method further includes: forming at least one second transition layer on the second doping layer.

2. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The first transition layer is selected from one of an amorphous silicon-based material, a microcrystalline silicon-based material or a nano-silicon-based material having the first conductive doping type; and / or the second transition layer is selected from one of an amorphous silicon-based material, a microcrystalline silicon-based material or a nano-silicon-based material having the second conductive doping type.

3. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The doping concentration of the first transition layer is greater than the doping concentration of the first doping layer, and / or the doping concentration of the second transition layer is greater than the doping concentration of the second doping layer.

4. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The first transition layer includes multiple layers, and the doping concentration of the first transition layer gradually increases from the first doping layer to the first transparent conductive layer; and / or, The second transition layer includes multiple layers, and the doping concentration of the second transition layer gradually increases in a direction from the second doping layer to the second transparent conductive layer.

5. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: Before forming the first electrode on the first transparent conductive layer, the method further includes: forming at least one first buffer layer on the first transparent conductive layer; and / or, Before forming the second electrode on the second transparent conductive layer, the method further includes: forming at least one second buffer layer on the second transparent conductive layer.

6. The method for preparing a heterojunction solar cell according to claim 5, characterized in that: The material of the first buffer layer and / or the second buffer layer is doped microcrystalline silicon or VTTO.

7. The method for preparing a heterojunction solar cell according to claim 6, characterized in that: The first buffer layer is a microcrystalline silicon doped material having the first conductive doping type; and / or the second buffer layer is a microcrystalline silicon doped material having the second conductive doping type.

8. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The material of the first doping layer and the second doping layer is selected from one of an amorphous silicon-based material, a microcrystalline silicon-based material or a nano-silicon-based material; and / or At least one of the first doping layer and the second doping layer includes a plurality of sub-doping layers, and the doping concentration of each sub-doping layer increases layer by layer as it moves away from the silicon wafer.

9. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: Before forming the first electrode and the second electrode, a heat treatment process is further included; the heat treatment process includes: annealing at 150-220° C. for 5-50 minutes.

10. A heterojunction solar cell, characterized in that: The heterojunction solar cell is prepared by the preparation method of any one of claims 1 to 9.

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