Imaging apparatus and imaging system

Abstract

An imaging device (2, 2a) includes: a pixel array (PA) in which a plurality of pixels are arranged in a plurality of rows and a plurality of columns, the pixel array (PA) including a first pixel group (PG1) and a second pixel group (PG2), the first pixel group (PG1) including two or more pixels of the plurality of pixels corresponding to a first color, the second pixel group (PG2) including two or more pixels of the plurality of pixels corresponding to a second color; and a control circuit (CC) configured to perform a read-out scan to read out a pixel signal from each column of pixels of a selected row when a plurality of rows are sequentially selected, the control circuit (CC) performing a first read-out scan to read out a pixel signal from pixels of the first pixel group (PG1) within a single frame period, and a second read-out scan to read out a pixel signal from pixels of the second pixel group (PG2) within a single frame period. And performing a second readout scan to read out pixel signals from the pixels of the first pixel group (PG1) and the second pixel group (PG2).

Description

Technical Field

[0001] The present application relates to an imaging device and an imaging system. Background Art

[0002] In an imaging device including a pixel array, a plurality of pixels are arranged in multiple rows and columns in the pixel array. In the imaging device, each pixel generates a pixel signal corresponding to an object image formed by the pixel array, and when sequentially selecting multiple rows, the control circuit performs a readout scan in units of rows to read out the pixel signals.

[0003] In an imaging device, when a plurality of pixels in the pixel array correspond to multiple colors, the saturation susceptibility of the pixel signals of pixels of different colors is different. On the other hand, by performing multiple readout scans on pixels of a color that is prone to saturation and performing one readout scan on pixels of a color that is difficult to saturate within one frame period, the dynamic range of the pixel signals of each color can be expanded. When the time of each readout scan in multiple readout scans remains unchanged, the operation time of the readout scan within one frame period will be extended, and the power consumption of the control circuit will increase. Summary of the Invention

[0004] Based on this situation, the present application provides an imaging device and an imaging system that can reduce power consumption.

[0005] To solve the above problems and achieve the object of the present application, according to one aspect of the present application, an imaging device includes a pixel array in which a plurality of pixels are arranged to form multiple rows and columns, the pixel array includes a first pixel group and a second pixel group, the first pixel group includes two or more pixels corresponding to a first color among the plurality of pixels, and the second pixel group includes two or more pixels corresponding to a second color among the plurality of pixels; and a control circuit configured to perform a readout scan to read out pixel signals from each column of pixels in the selected rows when sequentially selecting multiple rows, wherein the control circuit performs a first readout scan within a single frame period to read out pixel signals from the pixels of the first pixel group, and performs a second readout scan to read out pixel signals from the pixels of the first pixel group and the second pixel group.

[0006] According to one aspect of the present application, power consumption can be reduced. Brief Description of the Drawings

[0007] These and / or other aspects and advantages of the embodiments of the present application will become apparent and more readily understood from the following description in conjunction with the drawings, in which:

[0008] Figure 1 A configuration block diagram of an imaging system including an imaging device according to an embodiment is shown.

[0009] Figure 2Shows a configuration circuit diagram of an image sensor according to an embodiment.

[0010] Figure 3 Shows a timing diagram of the operation of a control circuit according to an embodiment.

[0011] Figure 4 Shows a configuration circuit diagram of a pixel according to an embodiment.

[0012] Figure 5 Shows a waveform diagram of the operation of a pixel according to an embodiment.

[0013] Figure 6 Shows a configuration cross-sectional view of a pixel according to an embodiment.

[0014] Figure 7 Shows a schematic diagram of the transmission characteristics of a color filter according to an embodiment.

[0015] Figure 8 Shows a timing diagram of the operation of the configuration of a pixel array and a control circuit according to an embodiment.

[0016] Figure 9 Shows a timing diagram of the operation of the configuration of a pixel array and a control circuit according to the first modification of an embodiment.

[0017] Figure 10 Shows a timing diagram of the operation of the configuration of a pixel array and a control circuit according to the second modification of an embodiment.

[0018] Figure 11 Shows a timing diagram of the operation of the configuration of a pixel array and a control circuit according to the third modification of an embodiment.

[0019] Figure 12 Shows a timing diagram of the operation of the configuration of a pixel array and a control circuit according to the fourth modification of an embodiment.

[0020] Figure 13 Shows a configuration circuit diagram of a pixel unit according to the fourth modification of an embodiment.

[0021] Figure 14 Shows an operation waveform diagram of a pixel unit according to the fourth modification of an embodiment.

[0022] Figure 15 Shows a timing diagram of the operation of the configuration of a pixel array and a control circuit according to the fifth modification of an embodiment.

[0023] Figure 16 Shows a timing diagram of the operation of the configuration of a pixel array and a control circuit according to the sixth modification of an embodiment.

[0024] Figure 17 Shows a timing diagram of the operation of a control circuit according to the seventh modification of an embodiment.

[0025] Figure 18 A diagram showing the determination process of pixel saturation according to the seventh modification of the embodiment.

[0026] Figure 19 A circuit configuration diagram of a pixel according to the seventh modification of the embodiment.

[0027] Figure 20 A configuration diagram of a frame image according to the eighth modification of the embodiment.

[0028] Figure 21 An operation diagram of an imaging device according to the ninth modification of the embodiment.

[0029] Description of reference numerals:

[0030] 1: Imaging system, 2, 2a: Imaging devices, 21, 21a: Optical systems, 22, 22a: Image sensors, 23, 23a: Signal processing units, 24, 24a: Controllers, CC: Control circuit, P, P(1,1) to P(8,8): Pixels, PA: Pixel array, PG1, PG2, PG3: Pixel groups, PR, PR-1 to PR-4: Local pixel regions. Detailed description of the specific embodiment

[0031] Hereinafter, an imaging device will be described in detail with reference to the accompanying drawings according to the embodiments. Note that the present application is not limited to these embodiments.

[0032] The imaging device according to the embodiment includes a pixel array in which a plurality of pixels are arranged in multiple rows and multiple columns, and a control circuit sequentially selects multiple rows and performs a readout scan row by row to read out pixel signals. The imaging device aims to reduce the power consumption of the readout scan.

[0033] For example, the imaging system 1 including the imaging device 2 can be configured as shown in Figure 1 shown. Figure 1 A block diagram showing the configuration of the imaging system 1 including the imaging device 2. Figure 1 An example is given of the case where the imaging system 1 includes, in addition to the imaging device 2, an imaging device 2a. The imaging system 1 can be a portable electronic device. For example, the portable electronic device can be, for example, a smart phone, a tablet computer, a video camera, or a still electronic camera.

[0034] The imaging device 2 includes an optical system 21, an image sensor 22, a signal processing unit 23, and a controller 24. The optical system 21 is disposed on the optical axis PX of the image sensor 22 and forms an object image on the imaging surface of the image sensor 22. The image sensor 22 generates an image signal corresponding to the object image and supplies it to the signal processing unit 23. The signal processing unit 23 performs predetermined image processing on the image signal to generate image data and supplies the image data to the controller 24. The controller 24 performs predetermined processing using the image data.

[0035] Similarly, the imaging device 2a includes an optical system 21a, an image sensor 22a, a signal processing unit 23a, and a controller 24a. The optical system 21a is disposed on the optical axis PXa of the image sensor 22a and forms an object image on the imaging surface of the image sensor 22a. The image sensor 22a generates an image signal corresponding to the object image and supplies it to the signal processing unit 23a. The signal processing unit 23a performs predetermined image processing on the image signal to generate image data and supplies the image data to the controller 24a. The controller 24a performs predetermined processing using the image data.

[0036] In the imaging device 2 and the imaging device 2a, the configurations of the optical system 21 and the optical system 21a may be different from each other. The viewing angle of the optical system 21a may be wider than that of the optical system 21. For example, the optical system 21 may be a standard optical system. The optical system 21a may be a wide-angle optical system (e.g., wide-angle type or ultra-wide-angle type).

[0037] In the imaging device 2 and the imaging device 2a, the image sensors 22 and 22a, the signal processing units 23 and 23a, and the controllers 24 and 24a may have similar configurations.

[0038] As Figure 2 shown, each of the image sensors 22 and 22a includes a pixel array PA and a control circuit CC. Figure 2 The configuration circuit diagram of the image sensor 22 is shown. Figure 2 The configuration of the image sensor 22 is exemplified, but the image sensor 22a also has a similar configuration.

[0039] The pixel array PA is disposed on the imaging surface of the image sensor 22. In the pixel array PA, a plurality of pixels P(1,1) to P(8,8) may be arranged two-dimensionally. The pixels P(1,1) to P(8,8) may also be arranged in multiple rows and multiple columns. Figure 2 The arrangement configuration of the pixels P(1,1) to P(8,8) in 8 rows and 8 columns in the pixel array PA is exemplified. Hereinafter, the direction along the row is referred to as the row direction, and the direction along the column is referred to as the column direction.

[0040] The pixel array PA corresponds to multiple colors. The pixel array PA includes a pixel group PG1 and a pixel group PG2. The pixel group PG1 includes two or more pixels P1 corresponding to a first color among pixels P(1,1) to P(8,8). The pixel group PG2 includes two or more pixels P2 corresponding to a second color among pixels P(1,1) to P(8,8). The second color is different from the first color.

[0041] In the pixel array PA, the first column and the second column are arranged alternately in the row direction. Here, when counting from Figure 2 the left side, the first column can be defined as an odd-numbered column. When counting from Figure 2 the left side, the second column can be defined as an even-numbered column. In the first column, the pixels of the pixel group PG2 and the pixels of the pixel group PG1 are arranged alternately in the column direction. In the second column, the pixels of the pixel group PG2 are arranged in the column direction.

[0042] Between the pixel group PG1 and the pixel group PG2, the ease of saturation of the pixel signals tends to be different. The ease of saturation of the pixels in the pixel group PG1 by the light of the first color is greater than the ease of saturation of the pixels in the pixel group PG2 by the light of the second color.

[0043] The first color corresponds to light in a first wavelength band. The second color corresponds to light in a second wavelength band. The first wavelength band may include the second wavelength band. Each pixel P1 in the pixel group PG1 includes a first color filter. Each pixel P2 in the pixel group PG2 includes a second color filter. The light transmittance of the first color filter is greater than that of the second color filter.

[0044] For example, the transmission wavelength band of the first color filter may include the transmission wavelength band of the second color filter. With this characteristic, the amount of light transmitted by the first color filter can be more than the amount of light transmitted by the second color filter. The first color may be white, and the second color may be any one of red, green, and blue.

[0045] Hereinafter, without distinguishing between the pixels P1 in the pixel group PG1 and the pixels P2 in the pixel group PG2, in some cases they are simply referred to as pixels P respectively.

[0046] When the image sensor 22 uses the pixel array PA for multi-color imaging, the pixels P1 in the pixel group PG1 are preferably evenly distributed in the pixel array PA, and the pixels P2 in the pixel group PG2 are preferably evenly distributed in the pixel array PA. As Figure 2 indicated by the slashes, the pixels P1 are distributed in some rows and some columns. The pixels P2 are distributed at other positions other than the positions of the pixels P1 in the pixel array PA. In Figure 2In the example, pixel group PG1 includes pixels P1 located at even rows and odd column positions, and pixel group PG2 includes pixels P2 located at other positions.

[0047] Each pixel P performs photoelectric conversion and performs a charge storage operation to store charges corresponding to light. The charges of each pixel P are reset. When the reset is cancelled, each pixel P starts the charge storage operation. A pixel signal corresponding to the stored charge amount is read out from each pixel P. The charges of each pixel P are reset again, and when the reset is cancelled, each pixel P starts the charge storage operation. In each pixel P, the time period from the moment when the reset is cancelled to the moment when the readout is performed is the charge storage period. During the charge storage period, the charge storage operation is performed.

[0048] The control circuit CC controls the pixel array PA so as to read out pixel signals from the pixel array PA within each frame period. The control circuit CC includes a row scanning circuit 4, a timing control circuit 5, a plurality of column processing circuits 6-1 to 6-8, and a column scanning circuit 7. The row scanning circuit 4 controls the pixel array PA in units of rows. The column scanning circuit 7 controls the pixel array PA in units of columns. The timing control circuit 5 controls the operation timings of the row scanning circuit 4 and the column scanning circuit 7.

[0049] The timing control circuit 5 receives a clock signal from the controller 24 (see Figure 1 ) and generates a first timing signal and a second timing signal corresponding to the clock signal. The timing control circuit 5 supplies the first timing signal to the row scanning circuit 4 and supplies the second timing signal to the column scanning circuit 7.

[0050] The row scanning circuit 4 is provided adjacent to the pixel array PA in the row direction. The row scanning circuit 4 is connected to multiple rows of pixels P(1,1) to P(8,8) through a plurality of control line groups CL-1 to CL-8. The control line groups CL-1 to CL-8 correspond to multiple rows. Each control line group CL extends in the row direction. Each control line group CL is connected to each pixel P in the corresponding row. The row scanning circuit 4 can perform selective scanning on the pixel array PA in units of rows according to the first timing signal.

[0051] For example, the row scanning circuit 4 performs a reset scan, sequentially selects multiple rows in the pixel array PA within each frame period, and resets each pixel in the selected rows. The row scanning circuit 4 performs a reset cancellation scan, sequentially selects multiple rows in the pixel array PA within each frame period, and cancels the reset of each pixel in the selected rows. The row scanning circuit 4 performs a readout scan, sequentially selects multiple rows in the pixel array PA within each frame period, and reads out pixel signals from each column pixel in the selected rows.

[0052] Column processing circuits 6-1 to 6-8 are arranged adjacent to the pixel array PA in the column direction. The column processing circuits 6-1 to 6-8 are connected to multiple columns of signal lines SL-1 to SL-8. The multiple columns of signal lines SL-1 to SL-8 correspond to multiple columns. Each signal line SL extends in the column direction. Each signal line SL is connected to each pixel P in the corresponding column. The column processing circuits 6-1 to 6-8 correspond to the multiple columns of signal lines SL-1 to SL-8.

[0053] In each frame period, through readout scanning, pixel signals are read from the pixels P to each column processing circuit 6 through the signal lines SL in the corresponding columns. Each column processing circuit 6 can convert the read pixel signals (analog signals) into pixel signals (digital signals). The column processing circuit 6 stores the converted pixel signals.

[0054] The column scanning circuit 7 is arranged relative to the pixel array PA in the column direction. The column scanning circuit 7 is arranged on the side of the pixel array PA opposite to the column processing circuits 6-1 to 6-8. The column scanning circuit 7 is connected to the column processing circuits 6-1 to 6-8.

[0055] In each frame period, the column scanning circuit 7 can selectively scan the column processing circuits 6-1 to 6-8 in sequence according to the second timing signal. Therefore, the column scanning circuit 7 can perform selective scanning on the pixel array PA column by column. The column scanning circuit 7 provides the pixel signals stored by the selected column processing circuit 6 to the signal processing unit 23 (see Figure 1 ).

[0056] In each pixel P in the pixel array PA, the amount of charge stored in the charge storage operation may exceed the tolerable amount of the pixel P in each frame period and become saturated. It is necessary to prevent the saturation of the pixel P and ensure a wide dynamic range.

[0057] For example, in the case of acquiring a moving image by the imaging device 2, when the frame rate is increased by n times (n is an integer equal to or greater than 2), the signal amount per frame is reduced by 1 / n, and it is difficult for the pixel P to become saturated. For example, in the case of acquiring a moving image by the imaging device 2 at 30 fps (frames per second), when the frame rate is increased by 2 times (to 60 fps), the signal amount per frame is reduced by 1 / 2, and it is difficult for the pixel P not to become saturated. By adding the pixel signals of n frames, the imaging device 2 can acquire pixel signals equivalent to the original one frame and ensure the wide dynamic range of the signal.

[0058] However, if the operating frequency of the control circuit CC is increased to perform readout at high speed, the power consumption may increase. In the case where the imaging system 1 applying the imaging device 2 and the imaging device 2a is a portable electronic device such as a smartphone, it is preferable to reduce the power consumption while ensuring the wide dynamic range of the signal.

[0059] On the other hand, the imaging devices 2 and 2a can operate as Figure 3 shown. Figure 3 Fig. shows the operation timing chart of the imaging device 2. Figure 3 The operation of the imaging device 2 is exemplified, but the imaging device 2a can also operate in a similar manner. In Figure 3 the upper figure of, the vertical axis represents the row position of the pixel P1, and the horizontal axis represents time. In Figure 3 the lower figure of, the vertical axis represents the row position of the pixel P2, and the horizontal axis represents time.

[0060] When the pixel P1 of the pixel group PG1 in the pixel array PA is more likely to be saturated than the pixel P2 of the pixel group PG2, the imaging device 2 performs a reset cancellation scan RC on all pixels P once, and performs readout scans RD-1 and RD-2 on the pixel P1 of the pixel group PG1 multiple times within one frame period FT, and performs a one-time readout scan RD-2 on the pixel P2 of the pixel group PG2.

[0061] The imaging device 2 can obtain the pixel signal of the pixel P1 corresponding to one frame by adding the pixel signals read out by performing the readout scans RD-1 and RD-2 in multiple times, and can obtain the pixel signal of the pixel P2 corresponding to one frame by performing the readout scan RD-2 intensively. Therefore, the pixel signal corresponding to one frame can be obtained without increasing the frame rate, and the power consumption can be reduced while ensuring the wide dynamic range of the signal.

[0062] At this time, the readout scan RD-1 is performed on the pixel P1 of the pixel group PG1, and the readout scan RD-2 is performed on the pixels P1 and P2 of the pixel groups PG1 and PG2. The number of pixels of the readout scan RD-1 is less than the number of pixels of the readout scan RD-2. For example, in the pixel array PA, Figure 2 the pixels P1 of the pixel group PG1 shown by the slashes are distributed in some rows, while the pixels P2 of the pixel group PG2 without the slashes are distributed in all rows. The number of pixel rows involved in the readout scan RD-1 is less than the number of pixel rows involved in the readout scan RD-2. The imaging device 2 can perform the readout scan RD-1 as a downsampling scan and perform the readout scan RD-2 as a full-frame scan. The downsampling scan means performing the scan by skipping some rows.

[0063] Therefore, as Figure 3As shown, the time RT-1 of the readout scan RD-1 is shorter than the time RT-2 of the readout scan RD-2. Therefore, without increasing the operating frequency of the control circuit CC, the operating time of the control circuit CC in the readout scan RD-1 can be shortened compared to that in the readout scan RD-2. Therefore, the power consumption of the control circuit CC can be reduced compared to the case where the time of the readout scan RD is uniformly equal. In other words, the power consumption can be reduced while ensuring the signal dynamic range.

[0064] A reset cancellation scan RC is performed on the pixel P1 of the pixel group PG1 and the pixel P2 of the pixel group PG2, and a readout scan RD-2 is performed on the pixel P1 of the pixel group PG1 and the pixel P2 of the pixel group PG2. The number of pixels involved in the reset cancellation scan RC is approximately equal to the number of pixels involved in the readout scan RD-2. The number of pixel rows involved in the reset cancellation scan RC is approximately equal to the number of pixels involved in the readout scan RD-2. The imaging device 2 can perform the reset cancellation scan RC as a full-frame scan and perform the readout scan RD-2 as a full-frame scan. Therefore, the time CT of the reset cancellation scan RC is approximately equal to the time RT-2 of the readout scan RD-2.

[0065] As Figure 3 shown, the pixel P1 of the pixel group PG1 performs a charge storage operation multiple times within one frame period FT, and the pixel signal is read out multiple times. One frame period FT is substantially equal to the sum of multiple charge accumulation times. Figure 3 An example of the operation in which the pixel P1 of the pixel group PG1 divides the charge storage operation into two times within one frame period FT is shown. The first charge accumulation times of the pixels P1 in the second row, fourth row, sixth row, and eighth row ( Figure 2 the pixels P indicated by the slashes) are ST1_2, ST1_4, ST1_6, and ST1_8, respectively. The second charge accumulation times of the pixels P1 in the second row, fourth row, sixth row, and eighth row are ST2_2, ST2_4, ST2_6, and ST2_8, respectively. In this case, the following Expression 1 holds:

[0066] FT = ST1_2 + ST2_2 = ST1_4 + ST2_4 = ST1_6 + ST2_6 = ST1_8 + ST2_8... Expression 1

[0067] Based on the fact that the time RT-1 of the readout scan RD-1 is shorter than the time RT-2 of the readout scan RD-2, the first charge accumulation times of the pixels P1 of the pixel group PG1 in the second row, fourth row, sixth row, and eighth row are different, and the charge accumulation times are successively shortened, as shown in the following Expression 2:

[0068] ST1_2 > ST1_4 > ST1_6 > ST1_8... Expression 2

[0069] Based on the fact that the readout scan time RT-1 of the readout scan RD-1 is shorter than the readout scan time RT-2 of the readout scan RD-2, the second charge accumulation times of the pixels P in the pixel group PG1 in the second, fourth, sixth, and eighth rows are different from each other, and the charge accumulation times increase successively, as shown in the following Expression 3.

[0070] ST2_2 < ST2_4 < ST2_6 < ST2_8... Expression 3

[0071] The pixels P2 in the pixel group PG2 perform charge storage operations intensively within one frame period FT, and the pixel signals are read out intensively. One frame period FT is equal to the charge accumulation time. The charge accumulation times of the pixels P2 ( Figure 2 the pixels P not shown with a slash in

[0072] from the first row to the eighth row) are substantially the same, assuming the charge accumulation time is assumed to be ST3. In this case, the following Expression 4 holds.

[0073] FT = ST3... Expression 4 Figure 4 Next, the circuit configuration of the pixel P will be described in conjunction with Figure 4 The configuration circuit diagram of the pixel P is shown. Figure 4 (a) shows the configuration of each pixel P1 in the pixel group PG1, Figure 4 (b) shows the configuration of each pixel P2 in the pixel group PG2.

[0074] As Figure 4 (a) shows, for example, each pixel P1 includes a photoelectric conversion unit PD, a transmission unit TX, a charge-voltage conversion unit FD, a reset unit RES, an amplification unit AM, and a selection unit SEL. The control line group CL includes a power supply line VDD, control lines Control lines Control lines and control lines The power supply line VDD supplies a power supply voltage VDD. The control line supplies a control signal Control lines supplies a control signal Control lines supplies a control signal Control lines supplies a control signal

[0075] The photoelectric conversion unit PD performs photoelectric conversion and generates charges corresponding to the received light for storage. The photoelectric conversion unit PD includes, for example, a photodiode.

[0076] The transmission unit TX transfers the charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD in the active state, and does not transfer the charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD in the non-active state. When receiving a control signal at the active level from the row scanning circuit 4 the transmission unit TX transfers the charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD. When receiving a control signal at the non-active level from the row scanning circuit 4 the transmission unit TX does not transfer the charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD. For example, the transmission unit TX includes a transmission transistor as a transmission gate. When its gate receives a control signal at the active level the transmission unit TX turns on the transmission transistor and transfers the charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD; when its gate receives a control signal at the non-active level the transmission unit TX turns off the transmission transistor so as not to transfer the charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD.

[0077] The charge-voltage conversion unit FD converts the transferred charge into a voltage using its parasitic capacitance CFD. The charge-voltage conversion unit FD includes, for example, a floating diffusion layer.

[0078] When receiving a control signal at the active level from the row scanning circuit 4 the reset unit RES resets the potential of the charge-voltage conversion unit FD to a predetermined potential (e.g., VDD). For example, the reset unit RES includes a reset transistor. When its gate receives a control signal at the active level the reset unit RES turns on the reset transistor and resets the potential of the charge-voltage conversion unit FD to a predetermined potential (e.g., VDD).

[0079] When the pixel P1 is placed in the selected state, the amplification unit AM outputs a signal to the signal line SL according to the voltage of the charge-voltage conversion unit FD. For example, the amplification unit AM includes an amplification transistor. When the pixel P1 is placed in the selected state, the amplification unit AM performs a source follower operation together with the load current source CS connected to the signal line SL, and outputs the signal corresponding to the voltage of the charge-voltage conversion unit FD to the column processing circuit 6 through the signal line SL. The load current source CS includes a load transistor.

[0080] When receiving a control signal at the active level from the row scanning circuit 4 the selection unit SEL makes the pixel P1 in the selected state; when receiving a control signal at the non-active level from the row scanning circuit 4 When the selection unit SEL causes the pixel P1 to be in an unselected state. For example, the selection unit SEL includes a selection transistor. When its gate receives a control signal at an active level the selection unit SEL turns on the selection transistor, causing the pixel P1 to be in a selected state; when its gate receives a control signal at an inactive level the selection unit SEL turns off the selection transistor, causing the pixel P1 to be in an unselected state.

[0081] The pixel P1 can be configured to omit the selection unit SEL. In this case, the reset unit RES can perform an operation to make the pixel P1 in a selected state / unselected state. For example, the reset unit RES can make the pixel P1 in a selected state by resetting the potential of the charge-voltage conversion unit FD to a first potential (e.g., VDD level), and can make the pixel P1 in an unselected state by resetting the potential of the charge-voltage conversion unit FD to a second potential (the potential at which the amplification unit AM (amplification transistor) is turned off, e.g., GND level).

[0082] As Figure 4 (b) shows, each pixel P2 includes a photoelectric conversion unit PD, a transmission unit TX, a charge-voltage conversion unit FD, a reset unit RES, an amplification unit AM, and a selection unit SEL. The configuration and function of each unit in each pixel P2 are basically similar to those of each pixel P1, but there are the following differences.

[0083] The transmission unit TX of the pixel P2 receives a control signal from the row scanning circuit 4 instead of the control signal When receiving a control signal at an inactive level from the row scanning circuit 4 the transmission unit TX does not transfer the charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD. For example, the transmission unit TX includes a transmission transistor that functions as a transmission gate. When its gate receives a control signal at an active level the transmission unit TX turns on the transmission transistor and transfers the charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD; when its gate receives a control signal at an inactive level the transmission unit TX turns off the transmission transistor so as not to transfer the charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD.

[0084] Next, the specific operation of each pixel P will be described in conjunction with Figure 5 is a waveform diagram showing the operation of the pixel P. Figure 5 Examples the operation of the pixels P in the first row to the fourth row, but similar operations also apply to the pixels P after the fourth row. Figure 5 ​

[0085] Before time point t1, the control circuit CC sets the control signals of the first row and to the active level. Therefore, the control circuit CC resets each pixel P2 in the first row. At the same time, the control circuit CC sets the control signal to the inactive level. Therefore, the control circuit CC makes each pixel P2 in the first row in the unselected state.

[0086] At time point t1, the control circuit CC sets the control signals of the first row that are at the active level and to the inactive level. Therefore, the control circuit CC cancels the reset of each pixel P in the first row and starts the charge storage operation. At the same time, the control circuit CC sets the control signal that is at the inactive level to the active level. Therefore, the control circuit CC makes each pixel P2 in the first row in the selected state.

[0087] Similarly, at time point t2, the control circuit CC sets the control signals of the second row that are at the active level and to the inactive level, cancels the reset of each pixel P1 and pixel P2 in the second row, and starts the charge storage operation.

[0088] At time point t3, the control circuit CC sets the control signals of the third row that are at the active level and to the inactive level, cancels the reset of each pixel P2 in the third row, and starts the charge storage operation.

[0089] At time point t4, the control circuit CC sets the control signals of the fourth row that are at the active level and to the inactive level, cancels the reset of each pixel P1 and pixel P2 in the fourth row, and starts the charge storage operation.

[0090] In this way, the control circuit CC sequentially performs a reset cancellation scan (RC) on the first row to the fourth row. The control circuit CC also sequentially performs a reset cancellation scan (RC) on the rows after the fourth row.

[0091] At time point t5, the control circuit CC sets the control signal of the second row that is at the inactive level to the active level. Therefore, the control circuit CC reads out the pixel signal corresponding to the charge stored in pixel P1 of the second row to the column processing circuit 6 through the signal line SL.

[0092] At time point t6, the control circuit CC sets the control signal of the second row that is at the inactive level is set to the activation level. Thus, the control circuit CC reads out the pixel signal from the pixel P1 in the second row and resets the pixel P1 in the second row.

[0093] At time point t7, the control circuit CC sets the control signal and of the second row at the activation level to the non-activation level. Thus, the control circuit CC cancels the reset of each pixel P1 in the second row and starts the charge storage operation again.

[0094] At time point t8, the control circuit CC sets the control signal of the fourth row at the non-activation level to the activation level. Thus, the control circuit CC reads out the pixel signal corresponding to the charge stored in the pixel P1 in the fourth row to the column processing circuit 6 through the signal line SL.

[0095] At time point t9, the control circuit CC sets the control signal of the fourth row at the non-activation level to the activation level. Thus, the control circuit CC reads out the pixel signal from the pixel P1 in the fourth row and resets the pixel P1 in the fourth row.

[0096] At time point t10, the control circuit CC sets the control signal and of the fourth row at the activation level to the non-activation level. Thus, the control circuit CC cancels the reset of each pixel P1 in the fourth row and starts the charge storage operation again.

[0097] In this way, the control circuit CC sequentially performs the readout scan RD-1 on the second row and the fourth row. In other words, the control circuit CC performs the readout scan RD-1 on the second row and the fourth row in a decimated scan manner among the first row to the fourth row. The control circuit CC also performs the readout scan RD-1 on the rows after the fourth row in a decimated scan manner in a similar way.

[0098] At time point t11, the control circuit CC sets the control signal and of the first row at the non-activation level to the activation level. Thus, the control circuit CC reads out the pixel signal corresponding to the charge stored in the pixel P2 in the first row to the column processing circuit 6 through the signal line SL.

[0099] At time point t12, the control circuit CC sets the control signal and of the first row at the activation level to the non-activation level. Thus, the control circuit CC finishes reading out the pixel signal from the pixel P2 in the first row.

[0100] At time point t13, the control circuit CC sets the control signal of the second row at the non-activation level and is placed at the activation level. Accordingly, the control circuit CC reads out pixel signals corresponding to the charges stored in the pixels P1 and P2 of the second row to the column processing circuit 6 through the signal line SL.

[0101] At time point t14, the control circuit CC sets the control signal and of the second row at the non-activation level. Accordingly, the control circuit CC completes reading out the pixel signals from the pixels P1 and P2 of the second row.

[0102] At time point t15, the control circuit CC sets the control signal and of the third row at the activation level. Accordingly, the control circuit CC reads out pixel signals corresponding to the charges stored in the pixel P2 of the third row to the column processing circuit 6 through the signal line SL.

[0103] At time point t16, the control circuit CC sets the control signal and of the third row at the non-activation level. Accordingly, the control circuit CC completes reading out the pixel signals from the pixel P2 of the third row.

[0104] At time point t17, the control circuit CC sets the control signal and of the fourth row at the activation level. Accordingly, the control circuit CC reads out pixel signals corresponding to the charges stored in the pixels P1 and P2 of the fourth row to the column processing circuit 6 through the signal line SL.

[0105] At time point t18, the control circuit CC sets the control signal and of the fourth row at the non-activation level. Accordingly, the control circuit CC completes reading out the pixel signals from the pixels P1 and P2 of the fourth row.

[0106] In this way, the control circuit CC sequentially performs the readout scan RD-2 on the first row to the fourth row. The control circuit CC also sequentially performs the readout scan RD-2 on the rows after the fourth row in a similar manner.

[0107] As Figure 6 shown, a color filter CF can be provided in each pixel P, and the color filter CF is used to selectively guide light in a specific wavelength range from the incident light of the optical system 21 to the photoelectric conversion unit PD. Figure 6 is a cross-sectional configuration view of the pixel P of the image sensor 22. Figure 6Illustrates the configuration of pixel P of image sensor 22, but pixel P of image sensor 22a also has a similar configuration. Figure 6 Illustrates the configuration related to the photoelectric conversion unit PD in pixel P. For simplicity, Figure 6 the configurations related to the transmission unit TX, charge-voltage conversion unit FD, reset unit RES, amplification unit AM, and selection unit SEL in pixel P are not shown.

[0108] Pixel P1 in pixel group PG1 can correspond to white (W). For example, its configuration is as Figure 6 (a) shown. Pixel P1 includes, in addition to the photoelectric conversion unit PDw, a color filter CFw and a microlens MLw. The photoelectric conversion unit PDw includes a charge storage region SRw. The charge storage region SRw is located near the surface of the substrate SB. The substrate SB includes a semiconductor region containing impurities of the first conductivity type near the charge storage region SRw. The charge storage region SRw can be formed by a semiconductor region containing impurities of the second conductivity type. The second conductivity type is opposite to the first conductivity type. The color filter CFw is provided above the charge storage region SRw through an interlayer insulating film DFw. The color filter CFw has a transmission wavelength band corresponding to white (W). The microlens MLw is provided above the color filter CFw. Therefore, white (W) light is selectively guided to the charge storage region SRw through the microlens MLw and the color filter CFw. Accordingly, photoelectric conversion occurs near the interface between the charge storage region SRw and the substrate SB, and charges are stored in the charge storage region SRw. Pixel P1 corresponding to white (W) can also be referred to as a W pixel.

[0109] Pixel P2 in pixel group PG2 can correspond to red (R). For example, its configuration is as Figure 6 (b) shown. Pixel P2 includes, in addition to the photoelectric conversion unit PDr, a color filter CFr and a microlens MLr. The photoelectric conversion unit PDr includes a charge storage region SRr. The charge storage region SRr is located near the surface of the substrate SB. The substrate SB includes a semiconductor region containing impurities of the first conductivity type near the charge storage region SRr. The charge storage region SRr can be formed by a semiconductor region containing impurities of the second conductivity type. The color filter CFr is provided above the charge storage region SRr through an interlayer insulating film DFr. The color filter CFr has a transmission wavelength band corresponding to red (R). The microlens MLr is provided above the color filter CFr. Therefore, red (R) light is selectively guided to the charge storage region SRr through the microlens MLr and the color filter CFr. Accordingly, photoelectric conversion occurs near the interface between the charge storage region SRr and the substrate SB, and charges are stored in the charge storage region SRr. Pixel P2 corresponding to red (R) can also be referred to as an R pixel.

[0110] The pixel P2 in the pixel group PG2 can correspond to green (G). For example, its configuration is as Figure 6 (c) shown. In addition to the photoelectric conversion unit PDg, the pixel P2 further includes a color filter CFg and a microlens MLg. The photoelectric conversion unit PDg includes a charge storage region SRg. The charge storage region SRg is located near the surface of the substrate SB. The substrate SB includes a semiconductor region containing impurities of the first conductivity type near the charge storage region SRg. The charge storage region SRg can be formed by a semiconductor region containing impurities of the second conductivity type. The color filter CFg is located above the charge storage region SRg through an interlayer insulating film DFg. The color filter CFg has a transmission wavelength band corresponding to green (G). The microlens MLg is disposed above the color filter CFg. Therefore, green (G) light is selectively guided to the charge storage region SRg through the microlens MLg and the color filter CFg. Accordingly, photoelectric conversion is performed near the interface between the charge storage region SRg and the substrate SB, and charges are stored in the charge storage region SRg. The pixel P2 corresponding to green (G) can also be referred to as a G pixel.

[0111] The pixel P2 in the pixel group PG2 can correspond to blue (B). For example, its configuration is as Figure 6 (d) shown. In addition to the photoelectric conversion unit PDb, the pixel P2 further includes a color filter CFb and a microlens MLb. The photoelectric conversion unit PDb includes a charge storage region SRb. The charge storage region SRb is located near the surface of the substrate SB. The substrate SB includes a semiconductor region containing impurities of the first conductivity type near the charge storage region SRb. The charge storage region SRb can be formed by a semiconductor region containing impurities of the second conductivity type. The color filter CFb is disposed above the charge storage region SRb through an interlayer insulating film DFb. The blue color filter CFb has a transmission wavelength band corresponding to blue (B). The microlens MLb is disposed above the blue color filter CFb. Therefore, blue (B) light is selectively guided to the charge storage region SRb through the microlens MLb and the color filter CFb. Accordingly, photoelectric conversion is performed near the interface between the charge storage region SRb and the substrate SB, and charges are stored in the charge storage region SRb. The pixel P2 corresponding to blue (B) can also be referred to as a B pixel.

[0112] The transmission characteristics of each of the color filters CFw, CFr, CFg, and CFb can be as Figure 7 shown. Figure 7It is a schematic diagram of the transmission characteristics of the color filter CFw, color filter CFr, color filter CFg, and color filter CFb. The color filter CFw has a transmission characteristic WFw. The transmission characteristic WFw has a transmission wavelength band corresponding to white (W). The transmission wavelength band is assumed to be a wavelength band where the transmittance is equal to or higher than the required transmittance TRth. The color filter CFr has a transmission characteristic WFr corresponding to red (R). The transmission characteristic WFr has a transmission wavelength band corresponding to red (R). The color filter CFg has a transmission characteristic WFg corresponding to green (G). The transmission characteristic WFg has a transmission wavelength band corresponding to green (G). The blue filter CFb has a transmission characteristic WFb corresponding to blue (B). The transmission characteristic WFb has a transmission wavelength band corresponding to blue (B).

[0113] As Figure 7 shown, the transmission wavelength band of the color filter CFw includes the transmission wavelength band of the color filter CFr. The transmission wavelength band of the color filter CFw includes the transmission wavelength band of the color filter CFg. The transmission wavelength band of the color filter CFw includes the transmission wavelength band of the color filter CFb.

[0114] Furthermore, as Figure 7 shown, the maximum transmittance of the color filter CFw is higher than the maximum transmittance of the color filter CFr. The maximum transmittance of the color filter CFw is higher than the maximum transmittance of the color filter CFg. The maximum transmittance of the color filter CFw is higher than the maximum transmittance of the color filter CFb.

[0115] Therefore, when the charge accumulation times are approximately equal, compared with the charge storage region SRr of the photoelectric conversion unit PDr, the charge in the charge storage region SRw of the photoelectric conversion unit PDw is more likely to saturate. Compared with the charge storage region SRg of the photoelectric conversion unit PDg, the charge in the charge storage region SRw of the photoelectric conversion unit PDw is more likely to saturate. Compared with the charge storage region SRb of the photoelectric conversion unit PDb, the charge in the charge storage region SRw of the photoelectric conversion unit PDw is more likely to saturate.

[0116] For example, in the case where the pixel array PA is configured as a two-dimensional array of the unit array UA as Figure 8 (a) shown, the control circuit CC can perform the control as Figure 8 (b) shown. Figure 8 (a) shows a schematic diagram of the configuration of the pixel array PA. Figure 8 (b) shows an operation timing diagram of the control circuit CC.

[0117] In the pixel array PA, the unit array UA is repeatedly arranged in the row direction and the column direction. The unit array UA includes pixels P arranged in two rows and two columns. The unit array UA can be obtained by replacing one G pixel in a Bayer array including R pixels, B pixels, and two G pixels with a W pixel. In the unit array UA, the R pixels and the B pixels are arranged diagonally opposite to each other, and the G pixels and the W pixels are arranged diagonally opposite to each other. In the unit array UA, the W pixel corresponds to the pixel P1 of the pixel group PG1 ( Figure 2 the pixel P indicated by a slash in Figure 2 ), and the R pixel, the B pixel, and the G pixel correspond to the pixel P2 of the pixel group PG2 (

[0118] the pixel P not indicated by a slash in Figure 8 ).

[0119] The control circuit CC performs a reset cancellation scan RC on the pixels P in each row of the pixel array PA in a full-row scan manner within one frame period FT shown in Figure 2 (b). The control circuit CC performs a reset cancellation operation on the R pixels and the G pixels in the first row. The control circuit CC performs a reset cancellation operation on the W pixels and the B pixels in the second row. The control circuit CC performs a reset cancellation operation on the R pixels and the G pixels in the third row. The control circuit CC performs a reset cancellation operation on the W pixels and the B pixels in the fourth row. The control circuit CC performs a reset cancellation operation on the R pixels and the G pixels in the fifth row. The control circuit CC performs a reset cancellation operation on the W pixels and the B pixels in the sixth row. The control circuit CC performs a reset cancellation operation on the R pixels and the G pixels in the seventh row. The control circuit CC performs a reset cancellation operation on the W pixels and the B pixels in the eighth row. Therefore, the pixels P (W pixels, R pixels, B pixels, and G pixels) in each row start to perform a charge storage operation.

[0120] The control circuit CC performs a readout scan RD-2 on the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC performs a readout operation on the R pixels and G pixels in the first row. The control circuit CC performs a readout operation on the W pixels and B pixels in the second row. The control circuit CC performs a readout operation on the R pixels and G pixels in the third row. The control circuit CC performs a readout operation on the W pixels and B pixels in the fourth row. The control circuit CC performs a readout operation on the R pixels and G pixels in the fifth row. The control circuit CC performs a readout operation on the W pixels and B pixels in the sixth row. The control circuit CC performs a readout operation on the R pixels and G pixels in the seventh row. The control circuit CC performs a readout operation on the W pixels and B pixels in the eighth row. Thus, the pixel P1 (W pixel) has completed the second charge storage operation, and the pixels P2 (R pixel, B pixel, and G pixel) have completed the charge storage operation. The pixel signal corresponding to the charge stored in the second charge storage operation is read out from the pixel P1 (W pixel) to the control circuit CC (column processing circuit 6). The control circuit CC transmits the read pixel signal to the signal processing unit 23. The pixel signal corresponding to the charge stored in the charge storage operation is read out from the pixel P2 (R pixel, B pixel, and G pixel) to the control circuit CC (column processing circuit 6). The control circuit CC transmits the read pixel signal to the signal processing unit 23.

[0121] For the pixel P1, the signal processing unit 23 generates a pixel signal corresponding to one frame by adding the pixel signal read out by the readout scan RD-1 and the pixel signal read out by the readout scan RD-2. For the pixel P2, the signal processing unit 23 regards the pixel signal read out by the readout scan RD-2 as the pixel signal corresponding to one frame. The signal processing unit 23 performs a predetermined signal processing on each pixel signal and two-dimensionally processes the pixel signal to generate image data. The signal processing unit 23 provides the image data to the controller 24. Thus, the controller 24 can display an image (e.g., a moving image or a still image) on a display screen (not shown) according to the image data.

[0122] As described above, in the imaging device 2 of the present embodiment, within one frame period FT, the control circuit CC performs a readout scan RD-1 on the pixels P1 of the pixel group PG1 to read out pixel signals, and performs a readout scan RD-2 on the pixels P1 of the pixel group PG1 and the pixels P2 of the pixel group PG2 to read out pixel signals. Through this operation, the time RT-1 of the readout scan RD-1 can be shorter than the time RT-2 of the readout scan RD-2. Therefore, without increasing the operating frequency of the control circuit CC, the operation time of the control circuit CC in the readout scan RD-1 can be shorter than that in the readout scan RD-2. Therefore, compared with the case where the time of the readout scan RD is uniformly equal, the power consumption of the control circuit CC can be reduced. In other words, the power consumption can be reduced while ensuring the signal dynamic range.

[0123] It should be noted that in the first modification of the present embodiment, the pixel array PA may, as Figure 9 (a) shows, arrange the pixels P2 of the pixel group PG2 and the pixels P1 of the pixel group PG1 alternately row by row in the column direction. In this case, the control circuit CC may perform the control as Figure 9 (b) shows. Figure 9 (a) shows a schematic configuration diagram of the pixel array PA according to the first modification of the embodiment. Figure 9 (b) shows an operation timing diagram of the control circuit CC according to the first modification of the embodiment.

[0124] In the pixel array PA, the first column and the second column are arranged alternately in the row direction. Here, when counting from the Figure 9 left side, the first column may be defined as an odd-numbered column. When counting from the Figure 9 left side, the second column may be defined as an even-numbered column. In the first column, the pixels of the pixel group PG2 and the pixels of the pixel group PG1 are arranged alternately in the row direction. In the second column, the pixels of the pixel group PG2 and the pixels of the pixel group PG1 are arranged alternately in the row direction. The row position of the pixel group PG1 in the first column corresponds to the row position of the pixel group PG2 in the second column. The row position of the pixel group PG1 in the first column corresponds to the row position of the pixel group PG1 in the second column.

[0125] The pixel array PA corresponds to multiple colors. The pixel group PG1 corresponds to the first color. The pixel group PG2 corresponds to the second color. In Figure 9 this case, the first color is any one of white or blue, and the second color is any one of red or green. In other words, the pixel group PG1 includes W pixels and B pixels, and the pixel group PG2 includes R pixels and G pixels.

[0126] In the pixel array PA, for any B pixel in an even row, the configuration of the pixel P2 (see Figure 4(b)) is replaced with the configuration of pixel P1 (see Figure 4 (a)). The control line group CL of any odd row is replaced with the control line group CL2, and the control line group CL of any even row is replaced with the control line group CL1. In the control line group CL2, the control line is omitted from the control line group CL In the control line group CL1, the control line is omitted from the control line group CL This can reduce the number of control lines and ensure a wide light receiving area of the photoelectric conversion unit PD.

[0127] In Figure 9 (b), within one frame period FT, the control circuit CC resets and cancels the scan RC for the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC performs a reset cancellation operation on the R pixels and G pixels in the first row. The control circuit CC performs a reset cancellation operation on the W pixels and B pixels in the second row. The control circuit CC performs a reset cancellation operation on the R pixels and G pixels in the third row. The control circuit CC performs a reset cancellation operation on the W pixels and B pixels in the fourth row. The control circuit CC performs a reset cancellation operation on the R pixels and G pixels in the fifth row. The control circuit CC performs a reset cancellation operation on the W pixels and B pixels in the sixth row. The control circuit CC performs a reset cancellation operation on the R pixels and G pixels in the seventh row. The control circuit CC performs a reset cancellation operation on the W pixels and B pixels in the eighth row. Thus, the pixels P (W pixels, R pixels, B pixels, and G pixels) in each row start the charge storage operation.

[0128] The control circuit CC performs a readout scan RD-1 on the pixels P1 (W pixels and B pixels) of the pixel group PG1 in a downsampling scan manner. The control circuit CC performs a readout operation on the W pixels and B pixels in the second row. The control circuit CC performs a readout operation on the W pixels and B pixels in the fourth row. The control circuit CC performs a readout operation on the W pixels and B pixels in the sixth row. The control circuit CC performs a readout operation on the W pixels and B pixels in the eighth row. Thus, the pixels P1 (W pixels and B pixels) complete the first charge storage operation, and the pixel signals corresponding to the charges stored in the first charge storage operation are read out from the pixels P1 (W pixels and B pixels) to the control circuit CC. The control circuit CC transmits the read pixel signals to the signal processing unit 23. At the same time, the pixels P1 (W pixels and B pixels) start the second charge storage operation. At this time, the pixels P2 (R pixels and G pixels) continue to perform the charge storage operation.

[0129] The control circuit CC performs a readout scan RD-2 on the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC performs a readout operation on the R pixels and G pixels in the first row. The control circuit CC performs a readout operation on the W pixels and B pixels in the second row. The control circuit CC performs a readout operation on the R pixels and G pixels in the third row. The control circuit CC performs a readout operation on the W pixels and B pixels in the fourth row. The control circuit CC performs a readout operation on the R pixels and G pixels in the fifth row. The control circuit CC performs a readout operation on the W pixels and B pixels in the sixth row. The control circuit CC performs a readout operation on the R pixels and G pixels in the seventh row. The control circuit CC performs a readout operation on the W pixels and B pixels in the eighth row. Thus, the pixels P1 (W pixels and B pixels) complete the second charge storage operation, and the pixels P2 (R pixels and G pixels) complete the charge storage operation. The pixel signals corresponding to the charges stored in the second charge storage operation are read out from the pixels P1 (W pixels and B pixels) to the control circuit CC (column processing circuit 6). The control circuit CC forwards the read pixel signals to the signal processing unit 23. The pixel signals corresponding to the charges stored in the charge storage operation are read out from the pixels P2 (R pixels and G pixels) to the control circuit CC (column processing circuit 6). The control circuit CC transmits the read pixel signals to the signal processing unit 23.

[0130] For the pixels P1, the signal processing unit 23 adds the pixel signals read out by the readout scan RD-1 and the pixel signals read out by the readout scan RD-2 to generate the pixel signals of one frame. For the pixels P2, the signal processing unit 23 uses the pixel signals read out by the readout scan RD-2 as the pixel signals of one frame. The signal processing unit 23 performs predetermined signal processing on each pixel signal and two-dimensionally processes them to generate image data. The signal processing unit 23 provides the image data to the controller 24. Thus, the controller 24 can display an image (e.g., a moving image or a still image) on a display screen (not shown) according to the image data.

[0131] In the imaging device 2 as described above, the time RT-1 of the readout scan RD-1 is still shorter than the time RT-2 of the readout scan RD-2. Therefore, without increasing the operating frequency of the control circuit CC, the operation time of the control circuit CC for the readout scan RD-1 can be shorter than the operation time for the readout scan RD-2. Thus, compared with the case where the time of the readout scan RD is uniformly equal, the power consumption of the control circuit CC can be reduced. In other words, the power consumption can be reduced while ensuring the signal dynamic range.

[0132] In the second modification of this embodiment, the pixel array PA can have the configuration as shown in Figure 10 (a), where the W pixels are omitted. In this case, the control circuit CC can perform asFigure 10 The control shown in (b). Figure 10 (a) shows a schematic configuration diagram of a pixel array PA according to a second modification of an embodiment. Figure 10 (b) shows an operation timing diagram of a control circuit CC according to a second modification of an embodiment.

[0133] In the pixel array PA, the first column and the second column are alternately arranged in the row direction. Here, when counting starts from the Figure 2 left side of, the first column can be defined as an odd-numbered column. When counting starts from the Figure 2 left side of, the second column can be defined as an even-numbered column. In the first column, the pixels of the pixel group PG2 and the pixels of the pixel group PG1 are alternately arranged in the column direction. In the second column, the pixels of the pixel group PG2 are arranged in the column direction.

[0134] The pixel array PA corresponds to multiple colors. The pixel group PG1 corresponds to a first color. The pixel group PG2 corresponds to a second color. In the Figure 10 case of, the first color is green, and the second color is any one of red, green, or blue. In other words, the pixel group PG1 includes G pixels with thick dot shading, and the pixel group PG2 includes R pixels, G pixels with thin dot shading, and B pixels.

[0135] The unit array UA is formed of a Bayer array including R pixels, B pixels, and two G pixels. As Figure 7 shown, the maximum transmittance of the color filter CFg is higher than the maximum transmittance of the color filter CFr. The maximum transmittance of the color filter CFg is higher than the maximum transmittance of the color filter CFb. With this configuration, when accumulating charges during the same charge accumulation time, the charge storage region SRg of the photoelectric conversion unit PDg is more likely to be saturated than the charge storage region SRr of the photoelectric conversion unit PDr. The charge storage region SRg of the photoelectric conversion unit PDg is more likely to be saturated than the charge storage region SRb of the photoelectric conversion unit PDb. Therefore, in the unit array UA, one of the two G pixels located in the even rows has the configuration of pixel P1 (see Figure 4 (a)), and the other G pixel located in the odd rows has the configuration of pixel P2 (see Figure 4 (b)).

[0136] In Figure 10Within one frame period FT as shown in (b), the control circuit CC performs a reset cancellation scan RC on the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC performs a reset cancellation operation on the R pixels and G pixels in the first row. The control circuit CC performs a reset cancellation operation on the G pixels and B pixels in the second row. The control circuit CC performs a reset cancellation operation on the R pixels and G pixels in the third row. The control circuit CC performs a reset cancellation operation on the G pixels and B pixels in the fourth row. The control circuit CC performs a reset cancellation operation on the R pixels and G pixels in the fifth row. The control circuit CC performs a reset cancellation operation on the G pixels and B pixels in the sixth row. The control circuit CC performs a reset cancellation operation on the R pixels and G pixels in the seventh row. The control circuit CC performs a reset cancellation operation on the G pixels and B pixels in the eighth row. Thus, the pixels P (G pixels, R pixels, B pixels, and G pixels) in each row start the charge storage operation.

[0137] The control circuit CC performs a readout scan RD-1 on the pixels P1 of the pixel group PG1 ( Figure 2 the pixels P indicated by slashes therein) in a downsampling scan manner. The control circuit CC performs a readout operation on the G pixels in the second row. The control circuit CC performs a readout operation on the G pixels in the fourth row. The control circuit CC performs a readout operation on the G pixels in the sixth row. The control circuit CC performs a readout operation on the G pixels in the eighth row. Thus, the pixels P1 (G pixels) complete the first charge storage operation, and the pixel signals corresponding to the charges stored in the first charge storage operation are read out from the pixels P1 (G pixels) to the control circuit CC. The control circuit CC forwards the read pixel signals to the signal processing unit 23. At the same time, the pixels P1 (G pixels) start the second charge storage operation. At this time, the pixels P2 (R pixels, B pixels, and G pixels) continue the charge storage operation.

[0138] The control circuit CC performs a readout scan RD-2 on the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC performs a readout operation on the R pixels and G pixels in the first row. The control circuit CC performs a readout operation on the G pixels and B pixels in the second row. The control circuit CC performs a readout operation on the R pixels and G pixels in the third row. The control circuit CC performs a readout operation on the G pixels and B pixels in the fourth row. The control circuit CC performs a readout operation on the R pixels and G pixels in the fifth row. The control circuit CC performs a readout operation on the G pixels and B pixels in the sixth row. The control circuit CC performs a readout operation on the R pixels and G pixels in the seventh row. The control circuit CC performs a readout operation on the G pixels and B pixels in the eighth row. Thus, the pixel P1 (G pixel) has completed the second charge storage operation, and the pixels P2 (R pixel, B pixel, and G pixel) have completed the charge storage operation. The pixel signal corresponding to the charge stored in the second charge storage operation is read out from the pixel P1 (G pixel) to the control circuit CC (column processing circuit 6). The control circuit CC forwards the read pixel signal to the signal processing unit 23. The pixel signal corresponding to the charge stored in the charge storage operation is read out from the pixel P2 (R pixel, B pixel, and G pixel) to the control circuit CC (column processing circuit 6). The control circuit CC forwards the read pixel signal to the signal processing unit 23.

[0139] For the pixel P1, the signal processing unit 23 adds the pixel signal read out by the readout scan RD-1 and the pixel signal read out by the readout scan RD-2 to generate a pixel signal for one frame. For the pixel P2, the signal processing unit 23 uses the pixel signal read out by the readout scan RD-2 as the pixel signal for one frame. The signal processing unit 23 performs a predetermined signal processing on each pixel signal and arranges them two-dimensionally to generate image data. The signal processing unit 23 provides the image data to the controller 24. Thus, the controller 24 can display an image (e.g., a moving image or a still image) on a display screen (not shown) according to the image data.

[0140] In the imaging device 2 as described above, the time RT-1 of the readout scan RD-1 is still shorter than the time RT-2 of the readout scan RD-2. Therefore, without increasing the operating frequency of the control circuit CC, the operating time of the control circuit CC in the readout scan RD-1 can be shortened compared to the operating time in the readout scan RD-2. Therefore, compared with the case where the time of the readout scan RD is uniformly equal, the power consumption of the control circuit CC can be reduced. In other words, the power consumption can be reduced while ensuring the signal dynamic range.

[0141] In the third modification of this embodiment, the pixel array PA may have as Figure 11(a) The configuration shown, where the W pixels are omitted, and the pixels P2 of the pixel group PG2 and the pixels P1 of the pixel group PG1 are arranged alternately row by row in the column direction. In this case, the control circuit CC can perform as Figure 11 (b) The control shown. Figure 11 (a) shows a schematic configuration diagram of a pixel array PA according to a third modification of an embodiment. Figure 11 (b) shows an operation timing chart of the control circuit CC according to a third modification of an embodiment.

[0142] In the pixel array PA, the first column and the second column are arranged alternately in the row direction. Here, when counting from the Figure 11 left side, the first column can be defined as an odd-numbered column. When counting from the Figure 11 left side, the second column can be defined as an even-numbered column. In the first column, the pixels of the pixel group PG2 and the pixels of the pixel group PG1 are arranged alternately in the row direction. In the second column, the pixels of the pixel group PG2 and the pixels of the pixel group PG1 are arranged alternately in the row direction. The row position of the pixel group PG1 in the first column corresponds to the row position of the pixel group PG2 in the second column. The row position of the pixel group PG1 in the first column corresponds to the row position of the pixel group PG1 in the second column.

[0143] The pixel array PA corresponds to multiple colors. The pixel group PG1 corresponds to a first color. The pixel group PG2 corresponds to a second color. In Figure 11 this case, the first color is any one of green or blue, and the second color is any one of red or green. In other words, the pixel group PG1 includes G pixels and B pixels with thick dot shading, and the pixel group PG2 includes R pixels and G pixels with thin dot shading.

[0144] As Figure 11 (a) The pixel array PA shown is formed by modifying the pixel array PA shown in Figure 10 (a). Specifically, for the B pixels in any even row, the configuration of the pixel P2 (see Figure 4 (b)) is replaced with the configuration of the pixel P1 (see Figure 4 (a)). The control line group CL in any odd row is replaced with the control line group CL2, and the control line group CL in any even row is replaced with the control line group CL1. In the control line group CL2, the control line is omitted from the control line group CL. In the control line group CL1, the control line is omitted from the control line group CL. This can reduce the number of control lines and ensure a wide light reception area of the photoelectric conversion unit PD.

[0145] In Figure 11Within one frame period FT shown in (b), the control circuit CC performs a reset cancellation scan RC on the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC performs a reset cancellation operation on the R pixels and G pixels in the first row. The control circuit CC performs a reset cancellation operation on the G pixels and B pixels in the second row. The control circuit CC performs a reset cancellation operation on the R pixels and G pixels in the third row. The control circuit CC performs a reset cancellation operation on the G pixels and B pixels in the fourth row. The control circuit CC performs a reset cancellation operation on the R pixels and G pixels in the fifth row. The control circuit CC performs a reset cancellation operation on the G pixels and B pixels in the sixth row. The control circuit CC performs a reset cancellation operation on the R pixels and G pixels in the seventh row. The control circuit CC performs a reset cancellation operation on the G pixels and B pixels in the eighth row. Thus, the pixels P (G pixels, R pixels, B pixels, and G pixels) in each row start to perform a charge storage operation.

[0146] The control circuit CC performs a readout scan RD-1 on the pixels P1 (G pixels and B pixels) of the pixel group PG1 in a downsampling scan manner. The control circuit CC performs a readout operation on the G pixels and B pixels in the second row. The control circuit CC performs a readout operation on the G pixels and B pixels in the fourth row. The control circuit CC performs a readout operation on the G pixels and B pixels in the sixth row. The control circuit CC performs a readout operation on the G pixels and B pixels in the eighth row. Thus, the pixels P1 (G pixels and B pixels) complete the first charge storage operation, and the pixel signals corresponding to the charges stored in the first charge storage operation are read out from the pixels P1 (G pixels and B pixels) to the control circuit CC. The control circuit CC forwards the read pixel signals to the signal processing unit 23. At the same time, the pixels P1 (G pixels and B pixels) start the second charge storage operation. At this time, the pixels P2 (R pixels and G pixels) continue to perform the charge storage operation.

[0147] The control circuit CC performs a readout scan RD-2 on the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC performs a readout operation on the R pixels and G pixels in the first row. The control circuit CC performs a readout operation on the G pixels and B pixels in the second row. The control circuit CC performs a readout operation on the R pixels and G pixels in the third row. The control circuit CC performs a readout operation on the G pixels and B pixels in the fourth row. The control circuit CC performs a readout operation on the R pixels and G pixels in the fifth row. The control circuit CC performs a readout operation on the G pixels and B pixels in the sixth row. The control circuit CC performs a readout operation on the R pixels and G pixels in the seventh row. The control circuit CC performs a readout operation on the G pixels and B pixels in the eighth row. Thus, the pixel P1 (G pixels and B pixels) completes the second charge storage operation, and the pixel P2 (R pixels and G pixels) completes the charge storage operation. The pixel signals corresponding to the charges stored in the second charge storage operation are read out from the pixel P1 (G pixels and B pixels) to the control circuit CC (column processing circuit 6). The control circuit CC forwards the read pixel signals to the signal processing unit 23. The pixel signals corresponding to the charges stored in the charge storage operation are read out from the pixel P2 (R pixels and G pixels) to the control circuit CC (column processing circuit 6). The control circuit CC forwards the read pixel signals to the signal processing unit 23.

[0148] For the pixel P1, the signal processing unit 23 adds the pixel signals read out by the readout scan RD-1 and the pixel signals read out by the readout scan RD-2 to generate the pixel signals of one frame. For the pixel P2, the signal processing unit 23 uses the pixel signals read out by the readout scan RD-2 as the pixel signals of one frame. The signal processing unit 23 performs predetermined signal processing on each pixel signal and two-dimensionally processes them to generate image data. The signal processing unit 23 provides the image data to the controller 24. Thus, the controller 24 can display an image (e.g., a moving image or a still image) on a display screen (not shown) according to the image data.

[0149] In the imaging device 2 as described above, the time RT-1 of the readout scan RD-1 is still shorter than the time RT-2 of the readout scan RD-2. Therefore, without increasing the operating frequency of the control circuit CC, the operating time of the control circuit CC in the readout scan RD-1 can be shortened compared to the operating time in the readout scan RD-2. Therefore, compared with the case where the time of the readout scan RD is uniformly equal, the power consumption of the control circuit CC can be reduced. In other words, the power consumption can be reduced while ensuring the signal dynamic range.

[0150] In the fourth modification of this embodiment, the pixel array PA can be configured to enable charge accumulation of two or more pixels. In this case, the control circuit CC can perform as Figure 12(b) The control as shown. Figure 12 (a) shows a schematic configuration diagram of a pixel array PA according to a fourth modification of an embodiment. Figure 12 (b) shows an operation timing diagram of a control circuit CC according to a fourth modification of an embodiment.

[0151] In the pixel array PA, the first column and the second column are alternately arranged in the row direction. Here, when counting from the Figure 12 left side, the first column can be defined as an odd-numbered column. When counting from the Figure 12 left side, the second column can be defined as an even-numbered column. In the first column, the pixels of the pixel group PG2 and the pixels of the pixel group PG1 are alternately arranged in the column direction. In the second column, the pixels of the pixel group PG1 and the pixels of the pixel group PG2 are alternately arranged in the column direction. The row positions of the pixel group PG2 in the first column correspond to the row positions of the pixel group PG1 in the second column. The row positions of the pixel group PG1 in the first column correspond to the row positions of the pixel group PG2 in the second column.

[0152] The pixel array PA corresponds to multiple colors. The pixel group PG1 corresponds to a first color. The pixel group PG2 corresponds to a second color. In the Figure 12 case, the first color is white, and the second color is any one of red, green, or blue. In other words, the pixel group PG1 includes W pixels, and the pixel group PG2 includes R pixels, G pixels, and B pixels.

[0153] The pixel array PA has a cell array UA as shown in Figure 12 (a), and these cell arrays UA are arranged in a two-dimensional manner. The cell array UA includes pixel units PU having two rows and two columns. Each pixel unit PU contains four pixels P. The cell array UA corresponds to a Bayer array, and it includes an R pixel unit PUr, a B pixel unit PUb, and two G pixel units PUg. The R pixel unit PUr has two R pixels arranged diagonally and two other W pixels arranged along the other diagonal. The B pixel unit PUb has two B pixels arranged diagonally and two other W pixels arranged along the other diagonal. The G pixel unit PUg has two G pixels arranged diagonally and two other W pixels arranged along the other diagonal.

[0154] The configuration of each pixel unit PU can be as shown in Figure 13 . Figure 13 shows a circuit diagram of a pixel unit PU according to a fourth modification of an embodiment.

[0155] In the R pixel unit PUr, the charge-voltage conversion unit FD, the reset unit RES, the amplification unit AM, and the selection unit SEL are shared by four pixels P, and each pixel P is provided with a photoelectric conversion unit PD and a transmission unit TX. The photoelectric conversion unit PDr and the transmission unit TXr correspond to the R pixel, and the photoelectric conversion unit PDw and the transmission unit TXw correspond to the W pixel. In the R pixel unit PUr, two photoelectric conversion units PDr and two transmission units TXr are arranged in a diagonal direction, and the other two photoelectric conversion units PDw and two transmission units TXw are arranged in the other diagonal direction.

[0156] In the B pixel unit PUb, the charge-voltage conversion unit FD, the reset unit RES, the amplification unit AM, and the selection unit SEL are shared by four pixels P, and each pixel P is provided with a photoelectric conversion unit PD and a transmission unit TX. The photoelectric conversion unit PDb and the transmission unit TXb correspond to the B pixel, and the photoelectric conversion unit PDw and the transmission unit TXw correspond to the W pixel. In the B pixel unit PUb, two photoelectric conversion units PDb and two transmission units TXb are arranged in a diagonal direction, and the other two photoelectric conversion units PDw and two transmission units TXw are arranged in the other diagonal direction.

[0157] In the G pixel unit PUg, the charge-voltage conversion unit FD, the reset unit RES, the amplification unit AM, and the selection unit SEL are shared by four pixels P, and each pixel P is provided with a photoelectric conversion unit PD and a transmission unit TX. The photoelectric conversion unit PDg and the transmission unit TXg correspond to the G pixel, and the photoelectric conversion unit PDw and the transmission unit TXw correspond to the W pixel. In the G pixel unit PUg, two photoelectric conversion units PDg and two transmission units TXg are arranged in a diagonal direction, and the other two photoelectric conversion units PDw and two transmission units TXw are arranged in the other diagonal direction.

[0158] In Figure 12 During one frame period FT shown in (b), the control circuit CC performs a reset cancellation scan RC on the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC performs a reset cancellation operation on each pixel P of the R pixel unit PUr and each pixel P of the G pixel unit PUg in the first row. The control circuit CC performs a reset cancellation operation on each pixel P of the G pixel unit PUg and each pixel P of the B pixel unit PUb in the second row. The control circuit CC performs a reset cancellation operation on each pixel P of the R pixel unit PUr and each pixel P of the G pixel unit PUg in the third row. The control circuit CC performs a reset cancellation operation on each pixel P of the G pixel unit PUg and each pixel P of the B pixel unit PUb in the fourth row. Therefore, each pixel P (W pixel, R pixel, B pixel, and G pixel) in each pixel unit PU of each row starts to perform a charge storage operation.

[0159] The control circuit CC performs a readout scan RD-1 that is substantially a downsampling scan on the pixels P1 (W pixels) of the pixel group PG1. The control circuit CC performs a readout operation by adding the charges of each W pixel of the R pixel unit PUr and each W pixel of the G pixel unit PUG in the first row.

[0160] As Figure 14 shown at time t21, the control circuit CC sets the control signal from the inactive level to the active level. Figure 14 Shows an operation waveform diagram of the pixel unit PU according to a fourth modification of the embodiment. The control circuit CC thus transfers the charges of the two photoelectric conversion units PDw of the R pixel unit PUr in the first row and causes the charge-voltage conversion unit FD to add them, while transferring the charges of the two photoelectric conversion units PDw of the G pixel unit PUG in the first row and causing the charge-voltage conversion unit FD to add them. The control circuit CC thus reads out, through the signal line SL, the W pixel signals corresponding to the charge addition results from the R pixel unit PUr and the G pixel unit PUG in the first row, respectively, and transmits them to the column processing circuit 6.

[0161] At time t22, the control circuit CC sets the control signal from the inactive level to the active level. Thus, the control circuit CC completes reading out the pixel signals from the W pixels (photoelectric conversion units PDw) of the R pixel unit PUr and the G pixel unit PUG in the first row and resets those W pixels (photoelectric conversion units PDw).

[0162] At time t23, the control circuit CC sets the control signals and from the active level to the inactive level. Thus, the control circuit CC cancels the reset of the W pixels (photoelectric conversion units PDw) of the R pixel unit PUr and the G pixel unit PUG in the first row and resumes the charge storage operation.

[0163] As described above, in the readout scan RD-1, the operations related to the R pixels in the R pixel unit PUr in the first row and the operations related to the G pixels in the G pixel unit Pug in the first row are skipped.

[0164] Return to Figure 12, the control circuit CC performs a readout operation by adding the charges of each W pixel of the G pixel units PUg in the second row and each W pixel of the B pixel units PUb. The control circuit CC performs a readout operation by adding the charges of each W pixel of the R pixel units PUr in the third row and each W pixel of the G pixel units PUg. The control circuit CC performs a readout operation by adding the charges of each W pixel of the G pixel units PUg in the fourth row and each W pixel of the B pixel units PUb. Thus, the W pixels (photoelectric conversion units PDw) of the pixel unit PU complete the first charge storage operation, and the pixel signals corresponding to the charges stored in the first charge storage operation are read out from the pixel unit PU to the control circuit CC. The control circuit CC transmits the read pixel signals to the signal processing unit 23. At the same time, the W pixels (photoelectric conversion units PDw) start the second charge storage operation. At this time, the R pixels, G pixels, and B pixels (photoelectric conversion units PDr, PDg, and PDb) of the pixel unit PU continue to perform the charge storage operation.

[0165] The control circuit CC performs a readout scan RD-2 on the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC performs a readout operation by adding the charges of each W pixel of the R pixel units PUr in the first row and each W pixel of the G pixel units PUg. The control circuit CC performs a readout operation by adding the charges of each R pixel of the R pixel units PUr in the first row and each G pixel of the G pixel units PUg.

[0166] For example, at Figure 14 the moment t24 as shown, the control circuit CC sets the control signal of the first row from the inactive level to the active level. The control circuit CC thus transfers the charges of the two photoelectric conversion units PDw of the R pixel unit PUr in the first row and causes the charge-voltage conversion unit FD to add them. At the same time, it transfers the charges of the two photoelectric conversion units PDw of the G pixel unit PUg in the first row and causes the charge-voltage conversion unit FD to add them. The control circuit CC thereby reads out the W pixel signals corresponding to the charge addition results from the R pixel unit PUr and the G pixel unit PUg in the first row through the signal line SL and transmits them to the column processing circuit 6.

[0167] At the moment t25, the control circuit CC sets the control signal from the inactive level to the active level and sets the control signal from the active level to the inactive level. Thus, the control circuit CC completes reading out the pixel signals from the W pixels (photoelectric conversion units PDw) of the R pixel unit PUr and the G pixel unit PUg in the first row and resets the charge-voltage conversion unit FD.

[0168] At time point t26, the control circuit CC sets the control signal φRES from the active level to the inactive level, and sets the control signal φTX2 from the inactive level to the active level. Therefore, the control circuit CC transfers the charges of the two photoelectric conversion units PDr of the R pixel unit PUr in the first row, and causes the charge-voltage conversion unit FD to add them up; at the same time, it transfers the charges of the two photoelectric conversion units PDg of the G pixel unit PUg in the first row, and causes the charge-voltage conversion unit FD to add them up. The control circuit CC reads out the R pixel signal and the G pixel signal corresponding to the charge addition result from the R pixel unit PUr and the G pixel unit Pug in the first row respectively through the signal line SL, and transmits them to the column processing circuit 6.

[0169] At time point t27, the control circuit CC sets the control signal φTX2 from the active level to the inactive level. Therefore, the control circuit CC completes the operation of reading out the pixel signals from the R pixels (photoelectric conversion units PDr) of the R pixel unit PUr in the first row and the G pixels (photoelectric conversion units PDg) of the G pixel unit Pug.

[0170] Back to Figure 12 , the control circuit CC performs the readout operation by performing charge addition on each W pixel of the G pixel unit Pug and each W pixel of the B pixel unit PUb in the second row. The control circuit CC performs the readout operation by performing charge addition on each G pixel of the G pixel unit Pug and each B pixel of the B pixel unit PUb in the second row; the control circuit CC performs the readout operation by performing charge addition on each W pixel of the R pixel unit PUr and each W pixel of the G pixel unit Pug in the third row; the control circuit CC performs the readout operation by performing charge addition on each R pixel of the R pixel unit PUr and each G pixel of the G pixel unit Pug in the third row; the control circuit CC performs the readout operation by performing charge addition on each W pixel of the G pixel unit Pug and each W pixel of the B pixel unit PUb in the fourth row; the control circuit CC performs the readout operation by performing charge addition on each G pixel of the G pixel unit Pug and each B pixel of the B pixel unit PUb in the fourth row. Therefore, the pixel P1 (W pixel) completes the second charge storage operation, and the pixels P2 (R pixel, G pixel, and B pixel) complete the charge storage operation. The W pixel signal corresponding to the charge stored in the second charge storage operation is read out from the pixel unit PU to the control circuit CC (column processing circuit 6). The control circuit CC forwards the read pixel signal to the signal processing unit 23.

[0171] For pixel P1, the signal processing unit 23 generates the W pixel signals of one frame by adding the W pixel signals read out by the readout scan RD-1 and the W pixel signals read out by the readout scan RD-2. For pixel P2, the signal processing unit 23 uses the pixel signals read out by the readout scan RD-2 as the R, G, and B pixel signals of one frame. The signal processing unit 23 performs predetermined signal processing on each pixel signal and two-dimensionally arranges them to generate image data. The signal processing unit 23 provides the image data to the controller 24. The controller 24 can thus display an image (e.g., a moving image or a still image) on the display screen (not shown) based on the image data.

[0172] As described above, the time RT-1 of the readout scan RD-1 of the imaging device 2 is still shorter than the time RT-2 of the readout scan RD-2. Therefore, without increasing the operating frequency of the control circuit CC, the operation time of the control circuit CC in the readout scan RD-1 can be shorter than that in the readout scan RD-2. Therefore, compared with the case where the readout scan times are uniformly equal, the power consumption of the control circuit CC can be reduced. In other words, the power consumption can be reduced while ensuring the signal dynamic range.

[0173] In the fifth modification of the present embodiment, the imaging device 2 and the imaging device 2a can perform the readout scan in a multi-step manner.

[0174] In addition to the pixel groups PG1 and PG2, the pixel array PA further includes a pixel group PG3. The pixel group PG1 includes two or more pixels P1 corresponding to the first color. The pixel group PG2 includes two or more pixels P2 corresponding to the second color. The second color is different from the first color. The pixel group PG3 includes two or more pixels P3 corresponding to the third color. The third color is different from the first color and also different from the second color.

[0175] The first color corresponds to light in the first wavelength band. The second color corresponds to light in the second wavelength band. The third color corresponds to light in the third wavelength band. The first wavelength band may include the second wavelength band. The first wavelength band may include the third wavelength band. Each pixel P1 in the pixel group PG1 includes a first color filter. Each pixel P2 in the pixel group PG2 includes a second color filter. Each pixel P3 in the pixel group PG3 includes a third color filter. The transmission wavelength band of the first color filter may include the transmission wavelength band of the second color filter. The transmission wavelength band of the first color filter may include the transmission wavelength band of the third color filter. The first color may be white. The second color may be red or blue. The third color may be green.

[0176] When the saturation susceptibility order of the pixels in the pixel array PA is Pixel P1 > Pixel P3 > Pixel P2, the control circuit CC of the imaging device 2 can gradually change the readout scan times of Pixel P1, Pixel P3, and Pixel P2, as Figure 15 shown. Within one frame period FT, the control circuit CC performs a reset cancellation scan RC for all pixels P; the pixel P1 is read out by performing three readout scans, namely readout scans RD-1, RD-3, and RD-2, in batches; the pixel P3 is read out by performing two readout scans, namely readout scans RD-3 and RD-2, in batches; and the pixel P2 in the pixel group PG2 is subjected to a one-time readout scan RD-2. The control circuit CC supplies the pixel signals read out in each readout scan to the signal processing unit 23.

[0177] For the imaging device 2, for pixel P1, the signal processing unit 23 can obtain a frame of pixel signals by adding the pixel signals read out in the readout scans RD-1, RD-3, and RD-2 performed in batches; for pixel P3, the signal processing unit 23 obtains a frame of pixel signals by adding the pixel signals read out in the readout scans RD-3 and RD-2 performed in batches; for pixel P2, the signal processing unit 23 obtains a frame of pixel signals by the pixel signals read out in the one-time performed readout scan RD-2. With this configuration, a frame of pixel signals can be obtained without increasing the frame rate, and the power consumption can be reduced while ensuring the wide dynamic range of the signal.

[0178] In this case, the readout scan RD-1 is performed for pixel P1, the readout scan RD-3 is performed for pixel P1 and pixel P3, and the readout scan RD-2 is performed for pixel P1, pixel P3, and pixel P2. The number of pixels involved in the readout scan RD-1 is less than the number of pixels involved in the readout scan RD-3. The number of pixels involved in the readout scan RD-3 is less than the number of pixels involved in the readout scan RD-2. The imaging device 2 can perform the readout scan RD-1 as a substantially downsampling scan, perform the readout scan RD-3 as a substantially downsampling scan, and perform the readout scan RD-3 as a full-frame scan. The downsampling scan refers to a scan that achieves downsampling by excluding some rows from multiple rows. The downsampling rate of the readout scan RD-1 may be higher than the downsampling rate of the readout scan RD-3.

[0179] Therefore, as Figure 15As shown, the time RT-1 of the readout scan RD-1 is shorter than the time RT-3 of the readout scan RD-3. The time RT-3 of the readout scan RD-3 is shorter than the time RT-2 of the readout scan RD-2. Therefore, without increasing the operating frequency of the control circuit CC, the operation time of the control circuit CC for the readout scan RD can be shortened in a multi-step manner. The operation time of the control circuit CC for the readout scan RD-1 can be shorter than that for the readout scan RD-3. The operation time of the control circuit CC for the readout scan RD-3 can be shorter than that for the readout scan RD-2. Therefore, compared with the case where the time of the readout scan RD is uniformly equal, the power consumption of the control circuit CC can be reduced. In other words, the power consumption can be reduced while ensuring the signal dynamic range.

[0180] In the sixth modification of the present embodiment, the pixel array PA may have a configuration capable of adding the charges of two or more pixels as shown in Figure 16 (a), and the control circuit CC may perform the readout scan in a multi-step manner as shown in Figure 16 (b).

[0181] In the pixel array PA, the first column and the second column are alternately arranged in the row direction. Here, when counting from the Figure 16 left side, the first column can be defined as an odd-numbered column. When counting from the Figure 16 left side, the second column can be defined as an even-numbered column. In the first column, the pixels of the pixel group PG2 or PG3 and the pixels of the pixel group PG1 are alternately arranged in the column direction. In the second column, the pixels of the pixel group PG1 and the pixels of the pixel group PG2 or the pixel group PG3 are alternately arranged in the column direction. The row positions of the pixel group PG2 or the pixel group PG3 in the first column correspond to the row positions of the pixel group PG1 in the second column. The row positions of the pixel group PG1 in the first column correspond to the row positions of the pixel group PG2 or the pixel group PG3 in the second column.

[0182] The pixel array PA corresponds to multiple colors. The pixel group PG1 corresponds to the first color. The pixel group PG2 corresponds to the second color. The pixel group PG3 corresponds to the third color. In the Figure 16 case, the first color is white, the second color is any one of red or blue. The third color is green. In other words, the pixel group PG1 contains W pixels, the pixel group PG2 contains R pixels and B pixels, and the pixel group PG3 contains G pixels.

[0183] As Figure 16 (a) shows, the pixel array PA is similar to the pixel array PA shown in Figure 12 (a). The unit array UA corresponds to a Bayer array, which includes an R pixel unit PUr, a B pixel unit PUb, and two G pixel units PG. The configuration of each pixel unit PU is the same asFigure 13 The configurations shown are similar.

[0184] As Figure 16 Within one frame period FT as shown in (b), the control circuit CC performs a reset cancellation scan RC on the pixels P (W pixels, R pixels, B pixels, and G pixels) in each row of the pixel array PA in a full-row scan manner. Thus, each pixel P (W pixels, R pixels, B pixels, and G pixels) in each pixel unit PU of each row starts a charge storage operation.

[0185] The control circuit CC performs a readout scan RD-1, which is essentially a downsampling scan, on the pixel P1 (W pixel). The control circuit CC performs a readout operation by adding the charges of the respective W pixels of the R pixel units PUr in the first row and the respective W pixels of the G pixel units PUg. The control circuit CC performs a readout operation by adding the charges of the respective W pixels of the G pixel units PUg and the respective W pixels of the B pixel units PUb in the second row. The control circuit CC performs a readout operation by adding the charges of the respective W pixels of the R pixel units PUr in the third row and the respective W pixels of the G pixel units PUg. The control circuit CC performs a readout operation by adding the charges of the respective W pixels of the G pixel units PUg and the respective W pixels of the B pixel units PUb in the fourth row. Thus, the W pixels (photoelectric conversion units PDw) in the pixel units PU complete the first charge storage operation, and the pixel signals corresponding to the charges stored in the first charge storage operation are read out from the pixel units PU to the control circuit CC. The control circuit CC transmits the read pixel signals to the signal processing unit 23. At the same time, the W pixels (photoelectric conversion units PDw) start the second charge storage operation. At this time, the R pixels, G pixels, and B pixels (photoelectric conversion units PDr, PDg, and PDb) in the pixel units PU continue the charge storage operation.

[0186] The control circuit CC performs a readout scan RD-3 that is substantially a downsampling scan for pixel P1 (W pixel) and pixel P3 (G pixel). The control circuit CC performs a readout operation by adding charges for each W pixel of the R pixel unit PUr and each W pixel of the G pixel unit PUg in the first row. The control circuit CC performs a readout operation by adding charges for each G pixel of the G pixel unit PUg in the first row. The control circuit CC performs a readout operation by adding charges for each W pixel of the G pixel unit PUg and each W pixel of the B pixel unit PUb in the second row. The control circuit CC performs a readout operation by adding charges for each G pixel of the G pixel unit PUg in the second row. The control circuit CC performs a readout operation by adding charges for each W pixel of the R pixel unit PUr and each W pixel of the G pixel unit PUg in the third row. The control circuit CC performs a readout operation by adding charges for each G pixel of the G pixel unit PUg in the third row. The control circuit CC performs a readout operation by adding charges for each W pixel of the G pixel unit PUg and each W pixel of the B pixel unit PUb in the fourth row. The control circuit CC performs a readout operation by adding charges for each G pixel of the G pixel unit PUg in the fourth row.

[0187] Accordingly, the W pixel (photoelectric conversion unit PDw) of the pixel unit PU has completed the second charge storage operation, and the pixel signal corresponding to the charge stored in the second charge storage operation is read out from the pixel unit PU to the control circuit CC. The G pixel (photoelectric conversion unit PDg) in the pixel unit PU has completed the first charge storage operation, and the pixel signal corresponding to the charge stored in the first charge storage operation is read out from the pixel unit PU to the control circuit CC. The control circuit CC forwards the read pixel signal to the signal processing unit 23. At the same time, the W pixel (photoelectric conversion unit PDw) starts the third charge storage operation. The G pixel (photoelectric conversion unit PDg) starts the second charge storage operation. At this time, the R pixel and B pixel (photoelectric conversion units PDr and PDb) in the pixel unit PU continue the charge storage operation.

[0188] The control circuit CC performs a readout scan RD-2 on the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC performs a readout operation by adding the charges of each W pixel of the R pixel unit PUr and each W pixel of the G pixel unit PUg in the first row. The control circuit CC performs a readout operation by adding the charges of each R pixel of the R pixel unit PUr and each G pixel of the G pixel unit PUg in the first row. The control circuit CC performs a readout operation by adding the charges of each W pixel of the G pixel unit PUg and each W pixel of the B pixel unit PUb in the second row. The control circuit CC performs a readout operation by adding the charges of each G pixel of the G pixel unit PUg and each B pixel of the B pixel unit PUb in the second row. The control circuit CC performs a readout operation by adding the charges of each W pixel of the R pixel unit PUr and each W pixel of the G pixel unit PUg in the third row. The control circuit CC performs a readout operation by adding the charges of each R pixel of the R pixel unit PUr and each G pixel of the G pixel unit PUg in the third row. The control circuit CC performs a readout operation by adding the charges of each W pixel of the G pixel unit PUg and each W pixel of the B pixel unit PUb in the fourth row. The control circuit CC performs a readout operation by adding the charges of each G pixel of the G pixel unit PUg and each B pixel of the B pixel unit PUb in the fourth row.

[0189] Therefore, the pixel P1 (W pixel) has completed the third charge storage operation, the pixel P3 (G pixel) has completed the second charge storage operation, and the pixels P2 (R pixel and B pixel) have completed the charge storage operation. The W pixel signal corresponding to the charge stored in the third charge storage operation is read out from the pixel unit PU to the control circuit CC (column processing circuit 6). The G pixel signal corresponding to the charge stored in the second charge storage operation is read out from the pixel unit PU to the control circuit CC (column processing circuit 6). The R pixel signal and the B pixel signal corresponding to the charge stored in the charge storage operation are read out from the pixel unit PU to the control circuit CC (column processing circuit 6). The control circuit CC forwards the read pixel signals to the signal processing unit 23.

[0190] For pixel P1 (W pixel), the signal processing unit 23 adds the W pixel signals read out by readout scan RD-1, the W pixel signals read out by readout scan RD-3, and the W pixel signals read out by readout scan RD-2, thereby generating the W pixel signals for one frame. For pixel P3 (G pixel), the signal processing unit 23 adds the G pixel signals read out by readout scan RD-3 and the G pixel signals read out by readout scan RD-2, thereby generating the G pixel signals for one frame. For pixel P2, the signal processing unit 23 uses the pixel signals read out by readout scan RD-2 as the R pixel signals and B pixel signals for one frame. The signal processing unit 23 performs predetermined signal processing on each pixel signal and two-dimensionally processes them, thereby generating image data. The signal processing unit 23 provides the image data to the controller 24. Therefore, the controller 24 can display an image (e.g., a moving image or a still image) on a display screen (not shown) based on the image data.

[0191] In the imaging device 2 as described above, the time RT-1 of readout scan RD-1 is shorter than the time RT-3 of readout scan RD-3. The time RT-3 of readout scan RD-3 is shorter than the time RT-2 of readout scan RD-2. Therefore, without increasing the operating frequency of the control circuit CC, the operation time of the control circuit CC for readout scan RD can be gradually shortened. The operation time of the control circuit CC for readout scan RD-1 can be shorter than the operation time for readout scan RD-3. The operation time of the control circuit CC for readout scan RD-3 can be shorter than the operation time for readout scan RD-2. Therefore, compared with the case where the times of readout scan RD are all equal, the power consumption of the control circuit CC can be reduced. In other words, the power consumption can be reduced while ensuring the signal dynamic range.

[0192] In the seventh modification of the present embodiment, the pixel array PA can switch between reading out pixels P in batches and reading out pixels P at once. For example, operations as shown in Figure 17 and Figure 18 can be performed. Figure 17 is an operation timing diagram showing the control circuit according to the seventh modification. Figure 18 is a determination process diagram showing the pixel saturation according to the seventh modification.

[0193] In frame period FT1, the control circuit CC performs a reset cancellation scan RC on the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC performs a readout scan RD on the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC forwards the read pixel signals to the signal processing unit 23. Batch readout is not performed in frame period FT1.

[0194] The signal processing unit 23 determines whether the color-based pixel signals read out in the frame period FT1 should be read out in batches or all at once, as Figure 18 shown.

[0195] For example, the signal processing unit 23 averages the R pixel signals of all R pixels to calculate the amount of R pixel signals. The signal processing unit 23 averages the G pixel signals of all G pixels to calculate the amount of G pixel signals. The signal processing unit 23 averages the B pixel signals of all B pixels to calculate the amount of B pixel signals. The signal processing unit 23 averages the W pixel signals of all W pixels to calculate the amount of W pixel signals. The signal processing unit 23 compares the amount of R pixel signals, the amount of G pixel signals, the amount of B pixel signals, and the amount of W pixel signals with the signal amount threshold Ath, respectively.

[0196] When the pixel array PA includes W pixels, as Figure 18 (a) to Figure 18 (d) shown for determination.

[0197] In Figure 18 (a), the amount of W pixel signals is higher than the signal amount threshold Ath, while the amounts of R pixel signals, G pixel signals, and B pixel signals are all lower than the signal amount threshold Ath; therefore, the signal processing unit 23 determines that the W pixels are saturated pixels, and the R, G, and B pixels are non-saturated pixels. Saturated pixels are pixels whose signals should be read out in batches. Non-saturated pixels are pixels whose signals should be read out all at once.

[0198] In Figure 18 (b), the amount of R pixel signals is higher than the signal amount threshold Ath, while the amounts of G pixel signals, B pixel signals, and W pixel signals are all lower than the signal amount threshold Ath; therefore, the signal processing unit 23 determines that the R pixels are saturated pixels, and the G, B, and W pixels are non-saturated pixels.

[0199] In Figure 18 (c), the amount of G pixel signals is higher than the signal amount threshold Ath, while the amounts of R pixel signals, B pixel signals, and W pixel signals are all lower than the signal amount threshold Ath; therefore, the signal processing unit 23 determines that the G pixels are saturated pixels, and the R, B, and W pixels are non-saturated pixels.

[0200] In Figure 18 (d), the amount of B pixel signals is higher than the signal amount threshold Ath, while the amounts of R pixel signals, G pixel signals, and W pixel signals are all lower than the signal amount threshold Ath; therefore, the signal processing unit 23 determines that the B pixels are saturated pixels, and the R, G, and W pixels are non-saturated pixels.

[0201] When the pixel array PA does not include W pixels, as shown in Figure 18 (e) to Figure 18 (g), the determination is made as follows.

[0202] In Figure 18 (e), the signal level of the R pixel is higher than the signal level threshold Ath, while the signal levels of the G pixel and the B pixel are both lower than the signal level threshold Ath; therefore, the signal processing unit 23 determines that the R pixel is a saturated pixel, and the G and B pixels are non-saturated pixels.

[0203] In Figure 18 (f), the signal level of the G pixel is higher than the signal level threshold Ath, while the signal levels of the R pixel and the B pixel are both lower than the signal level threshold Ath; therefore, the signal processing unit 23 determines that the G pixel is a saturated pixel, and the R and B pixels are non-saturated pixels.

[0204] In Figure 18 (g), the signal level of the B pixel is higher than the signal level threshold Ath, while the signal levels of the R pixel and the G pixel are both lower than the signal level threshold Ath; therefore, the signal processing unit 23 determines that the B pixel is a saturated pixel, and the R and G pixels are non-saturated pixels.

[0205] The signal processing unit 23 generates a control signal according to the determination result and provides the control signal to the control circuit CC. According to the control signal, the control circuit CC performs signal sub-reading on the color pixels determined to be saturated pixels and performs signal one-time reading on the color pixels determined to be non-saturated pixels in the pixel array PA.

[0206] For example, as shown in Figure 19 , each pixel P can be designed to be able to switch between saturated pixels and non-saturated pixels. Figure 19 Fig. shows a configuration circuit diagram of the pixel P according to the seventh modification of the embodiment.

[0207] The control line group CL may further include a control line φSW. The control line φSW provides a control signal φSW. Each pixel P1 further includes a switch unit SW. When receiving the control signal φSW at the active level from the row scanning circuit 4, the switch unit SW switches to the state shown by the solid line, so that the control signal φTX1 can be provided to the transmission unit TX. Therefore, the switch unit SW allows the pixel P to operate as a saturated pixel. When receiving the control signal φSW at the non-active level from the row scanning circuit 4, the switch unit SW switches to the state shown by the dotted line, so that the control signal φTX2 can be provided to the transmission unit TX. Therefore, the switch unit SW allows the pixel P to operate as a non-saturated pixel.

[0208] In Figure 17Before the frame period FT2 shown, the control circuit CC switches each pixel P to a saturated pixel or an unsaturated pixel according to a control signal.

[0209] In the frame period FT2, the control circuit CC performs a reset cancellation scan RC on the saturated pixels P and the unsaturated pixels P in a full-line scan manner. Thus, the saturated pixels P and the unsaturated pixels P each start a charge storage operation.

[0210] The control circuit CC performs a readout scan RD-1 on the saturated pixels P in a downsampling scan manner. Thus, the saturated pixels P complete the first charge storage operation, and a pixel signal corresponding to the charge stored in the first charge storage operation is read out from the saturated pixels P to the control circuit CC. The control circuit CC forwards the read pixel signal to the signal processing unit 23. At the same time, the saturated pixels P start the second charge storage operation. At this time, the unsaturated pixels P continue the charge storage operation.

[0211] The control circuit CC performs a readout scan RD-2 on the saturated pixels P and the unsaturated pixels P in a full-line scan manner. Thus, the saturated pixels P complete the second charge storage operation, and the unsaturated pixels P complete the charge storage operation. A pixel signal corresponding to the charge stored in the second charge storage operation is read out from the saturated pixels P to the control circuit CC (column processing circuit 6). The control circuit CC forwards the read pixel signal to the signal processing unit 23. A pixel signal corresponding to the charge stored in the charge storage operation is read out from the unsaturated pixels P to the control circuit CC (column processing circuit 6). The control circuit CC transmits the read pixel signal to the signal processing unit 23.

[0212] For the saturated pixels P, the signal processing unit 23 adds the pixel signal read out by the readout scan RD-1 and the pixel signal read out by the readout scan RD-2 to form a pixel signal for one frame. For the unsaturated pixels P, the signal processing unit 23 uses the pixel signal read out by the readout scan RD-2 as the pixel signal for one frame. The signal processing unit 23 performs a predetermined signal processing on each pixel signal and two-dimensionalizes it, thereby generating image data. The signal processing unit 23 provides the image data to the controller 24. The controller 24 can thus display an image (e.g., a moving image or a still image) on a display screen (not shown) according to the image data.

[0213] In the frame period FT3, the same operations as in the frame period FT2 are performed.

[0214] With the above imaging device 2, the time RT-1 for the readout scan RD-1 is still shorter than the time RT-2 for the readout scan RD-2. Therefore, without increasing the operating frequency of the control circuit CC, the operating time of the control circuit CC in the readout scan RD-1 can be shorter than that in the readout scan RD-2. Therefore, compared with the case where the readout scan RD times are uniformly equal, the power consumption of the control circuit CC can be reduced. In other words, the power consumption can be reduced while ensuring the signal dynamic range.

[0215] In the eighth modification of the embodiment, in each local area of the pixel array PA, it is possible to switch between the pixel P read out in multiple times and the pixel P read out once.

[0216] For example, when the frame image FI captured by the imaging device 2 includes a plurality of local images PI-1 to PI-4, as Figure 20 shown, the imaging device 2 can switch between the pixel P read out in multiple times or the pixel P read out once in each local image PI-1 to PI-4. Figure 20 is a schematic configuration diagram showing the frame image FI according to the eighth modification of the embodiment.

[0217] The pixel array PA includes a plurality of local pixel regions PR-1 to PR-4, as Figure 2 the part surrounded by the dotted line in. These local pixel regions PR-1 to PR-4 respectively correspond to the plurality of local images PI-1 to PI-4.

[0218] At this time, operations similar to those shown in Figure 17 and Figure 18 can be performed on each local pixel region PR-1 to PR-4.

[0219] In the frame period FT1, the control circuit CC performs a reset cancellation scan RC on the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC performs a readout scan RD on the pixels P in each row of the pixel array PA in a full-row scan manner. The control circuit CC forwards the read pixel signals to the signal processing unit 23. Multiple readouts are not performed in the frame period FT1.

[0220] The signal processing unit 23 calculates the color-based pixel signal amounts read out in the frame period FT1 for each local pixel region PR, as Figure 18 shown. The signal processing unit 23 determines whether the color-based pixel signals in each local pixel region PR should be read out in multiple times or once according to the color-based pixel signal amounts.

[0221] When the local pixel region PR-1 includes W pixels, as Figure 18 (a) to Figure 18(d) as shown. When a partial pixel region PR-1 does not include W pixels, as Figure 18 (e) to Figure 18 (g) as shown.

[0222] When a local pixel region PR-4 includes W pixels, as Figure 18 (a) to Figure 18 (d) as shown. When a partial pixel region PR-4 does not include W pixels, as Figure 18 (e) to Figure 18 (g) as shown.

[0223] For example, in each of the local pixel regions PR-1 to PR-4, each pixel P can be designed to be able to switch between a saturated pixel and a non-saturated pixel, as Figure 19 shown. In this case, for each pixel P in each of the local pixel regions PR-1 to PR-4, the switching unit SW can be connected to a control line φSW different from the control line of another local pixel region PR, so that the switching unit SW can be controlled independently of the switching unit SW in another local pixel region PR.

[0224] Before Figure 17 the frame period FT2 shown, the control circuit CC switches each pixel P in each local pixel region PR to a saturated pixel or a non-saturated pixel according to the control signal. The control circuit CC switches each pixel P in the local pixel region PR-1 to a saturated pixel or a non-saturated pixel according to the control signal. The control circuit CC switches each pixel P in the local pixel region PR-4 to a saturated pixel or a non-saturated pixel according to the control signal.

[0225] The operation after the frame period FT2 is similar to the operation in the seventh modification of the embodiment.

[0226] In the imaging device 2 as described above, the time RT-1 of the readout scan RD-1 is still shorter than the time RT-2 of the readout scan RD-2. Therefore, without increasing the operating frequency of the control circuit CC, the operation time of the control circuit CC in the readout scan RD-1 can be shortened compared to the operation time in the readout scan RD-2. Therefore, compared with the case where the time of the readout scan RD is uniformly equal, the power consumption of the control circuit CC can be reduced. In other words, the power consumption can be reduced while ensuring the signal dynamic range.

[0227] In the ninth modification of the embodiment, through the cooperation of a plurality of imaging devices, such as the imaging devices 2 and 2a, the pixel array PA can be switched between reading out pixels P in batches and reading out pixels P at once.

[0228] For example, when the viewing angle of the optical system 21a of the imaging device 2a is wider than that of the optical system 21 of the imaging device 2, the imaging device 2a acquires a frame image FIa as shown in Figure 21 (a), while the imaging device 2 acquires a frame image FI as shown in Figure 21 (b). The frame image FIa includes a partial image PIa corresponding to the frame image FI. Therefore, as shown in Figure 1 , the controller 24 of the imaging device 2 acquires the data of the frame image FIa from the controller 24a of the imaging device 2a, and crops out the partial image PIa from the frame image FIa. The controller 24 provides the partial image PIa to the signal processing unit 23. The signal processing unit 23 determines whether the color-based pixel signals should be read out in batches or all at once according to the amount of color-based pixel signals in the partial image PIa.

[0229] In this case, operations similar to those shown in Figure 17 and Figure 18 can be performed.

[0230] In the frame period FT1, for the imaging device 2a, the control circuit CC performs a reset cancellation scan RC on the pixels P in each row of the pixel array PA in a full-row scan manner, and performs a readout scan RD on the pixels P in each row in a full-row scan manner. The control circuit CC forwards the read pixel signals to the signal processing unit 23. No batch readout is performed in the frame period FT1.

[0231] In the imaging device 2a, the signal processing unit 23a performs predetermined signal processing on the pixel signals of each pixel P, two-dimensionally processes them to generate the data of the frame image FIa, and then provides the data to the controller 24a. The controller 24a provides the data of the frame image FIa to the controller 24 of the imaging device 2. The controller 24 crops out the partial image PIa from the frame image FIa. The controller 24 provides the partial image PIa to the signal processing unit 23.

[0232] In the imaging device 2, the signal processing unit 23 can calculate the amount of color-based pixel signals in the partial image PIa, as shown in Figure 18 . The signal processing unit 23 can determine whether the color-based pixel signals should be read out in batches or all at once according to the amount of color-based pixel signals.

[0233] When the pixel array PA contains W pixels, the determination shown in Figure 18 (a) to Figure 18 (d) is performed; when the pixel array PA does not contain W pixels, the determination shown in Figure 18 (e) to Figure 18 (g) is performed.

[0234] InFigure 17 Before the frame period FT2 shown, the control circuit CC switches each pixel P to a saturated pixel or a non-saturated pixel according to a control signal.

[0235] The operation after the frame period FT2 is similar to the seventh modification.

[0236] In the imaging device 2 as described above, the time RT-1 of the readout scan RD-1 is still shorter than the time RT-2 of the readout scan RD-2. Therefore, without increasing the operating frequency of the control circuit CC, the operation time of the control circuit CC in the readout scan RD-1 can be shortened compared to the operation time in the readout scan RD-2. Therefore, compared with the case where the time of the readout scan RD is uniformly equal, the power consumption of the control circuit CC can be reduced. In other words, the power consumption can be reduced while ensuring the signal dynamic range.

[0237] Although some embodiments have been described, these embodiments are presented only by way of example and are not intended to limit the scope of the present application. In fact, the novel embodiments described herein can be embodied in many other forms; furthermore, various omissions, substitutions, and changes can be made to the forms of the embodiments described herein without departing from the spirit of the present application. The accompanying patent applications and their equivalents are intended to cover deformations or modifications that fall within the scope and spirit of the present application.

Claims

1. An imaging device, characterized in that, comprising: a pixel array in which a plurality of pixels are arranged in multiple rows and multiple columns, the pixel array including a first pixel group and a second pixel group, the first pixel group including two or more pixels corresponding to a first color among the plurality of pixels, and the second pixel group including two or more pixels corresponding to a second color among the plurality of pixels; and a control circuit configured to perform a readout scan to read out pixel signals from the pixels in each column of a selected row when sequentially selecting multiple rows, wherein the control circuit performs a first readout scan within a single frame period to read out pixel signals from the pixels of the first pixel group, and performs a second readout scan to read out pixel signals from the pixels of the first pixel group and the second pixel group.

2. The imaging device according to claim 1, characterized in that, the number of pixels in the first readout scan is less than the number of pixels in the second readout scan.

3. The imaging device according to claim 1, characterized in that, in the pixel array, a first column and a second column are alternately arranged in the row direction; in the first column, the pixels of the second pixel group and the pixels of the first pixel group are alternately arranged in the column direction; and in the second column, the pixels of the second pixel group are arranged in the column direction.

4. The imaging device according to claim 1, characterized in that, in the pixel array, a first column and a second column are alternately arranged in the row direction; in the first column, the pixels of the second pixel group and the pixels of the first pixel group are alternately arranged in the row direction; and in the second column, the pixels of the second pixel group and the pixels of the first pixel group are alternately arranged in the row direction; the row positions of the second pixel group in the first column correspond to the row positions of the second pixel group in the second column, and the row positions of the first pixel group in the first column correspond to the row positions of the first pixel group in the second column.

5. The imaging device according to claim 1, characterized in that, in the pixel array, a first column and a second column are alternately arranged in the row direction; in the first column, the pixels of the second pixel group and the pixels of the first pixel group are alternately arranged in the column direction; and in the second column, the pixels of the first pixel group and the pixels of the second pixel group are alternately arranged in the column direction; the row positions of the second pixel group in the first column correspond to the row positions of the first pixel group in the second column, and the row positions of the first pixel group in the first column correspond to the row positions of the second pixel group in the second column.

6. The imaging device according to claim 1, characterized in that, before the first readout scan and the second readout scan, the control circuit further performs a reset cancellation scan to cancel the pixels of the first pixel group and the second pixel group within a single frame period.

7. The imaging device according to claim 6, characterized in that, the number of pixels in the first readout scan is less than the number of pixels in the reset cancellation scan.

8. The imaging device according to claim 6, characterized in that, The number of rows in which the pixels of the first readout scan are arranged is less than the number of rows in which the pixels of the reset cancellation scan are arranged.

9. The imaging device according to claim 1, wherein, The ease with which the light of the first color saturates the pixels of the first pixel group is greater than the ease with which the light of the second color saturates the pixels of the second pixel group.

10. The imaging device according to claim 1, wherein, Each pixel of the first pixel group includes a first color filter, and each pixel of the second pixel group includes a second color filter; and The light transmittance of the first color filter is greater than that of the second color filter.

11. The imaging device according to claim 9, wherein, The first color corresponds to light in a first wavelength band, the second color corresponds to light in a second wavelength band, and the first wavelength band includes the second wavelength band.

12. The imaging device according to claim 11, wherein, The first color is white, and the second color is any one of red, green, or blue.

13. The imaging device according to claim 10, wherein, Each pixel of the first pixel group includes a first color filter, and each pixel of the second pixel group includes a second color filter; and The maximum transmittance of the first color filter is higher than the maximum transmittance of the second color filter.

14. The imaging device according to claim 13, wherein, The first color is white, and the second color is any one of red, green, or blue.

15. The imaging device according to claim 13, wherein, The first color is green, and the second color is red or blue.

16. The imaging device according to claim 1, wherein, The imaging device determines whether the pixel signals of the first pixel group are read out in batches or all at once according to the number of pixel signals of the first pixel group read out in the first frame period; When it is determined that the pixel signals of the first pixel group are read out in batches, the control circuit reads out the pixel signals of the first pixel group in batches by performing the first readout scan and the second readout scan in the second frame period; and When it is determined that the pixel signals of the first pixel group are read out all at once, the control circuit reads out the pixel signals of the first pixel group all at once by performing the second readout scan in the second frame period.

17. The imaging device according to claim 1, wherein, The pixel array is divided into multiple regions, and the imaging device determines whether the pixel signals of the first pixel group are read out in batches or all at once for each of the multiple regions according to the number of pixel signals of the first pixel group read out in the first frame period; and The control circuit reads out the pixel signals of the first pixel group in the second frame period, reads out in batches for the regions determined to be read out in batches by performing the first readout scan and the second readout scan, and reads out all at once for the regions determined to be read out all at once by performing the second readout scan.

18. The imaging device according to claim 1, wherein, the imaging device determines whether the pixel signals of the first pixel group are read out in batches or at once according to the number of pixel signals of the fourth pixel group read out from the second imaging device within a first frame period, the second imaging device includes a pixel array, the pixel array includes the fourth pixel group and a fifth pixel group, the fourth pixel group corresponds to the first pixel group, and the fifth pixel group corresponds to the second pixel group; when it is determined that the pixel signals of the first pixel group are read out in batches, the control circuit reads out the pixel signals of the first pixel group in batches by performing the first readout scan and the second readout scan within a second frame period; and when it is determined that the pixel signals of the first pixel group are read out at once, the control circuit reads out the pixel signals of the first pixel group at once by performing the second readout scan within the second frame period.

19. An imaging system, wherein, it includes: a first imaging device, which is the imaging device according to claim 1; a first optical system configured to form an object image on the imaging surface of the first imaging device; a second imaging device; and a second optical system configured to form an object image on the imaging surface of the second imaging device; wherein, the first imaging device includes a pixel array, in which a plurality of pixels are arranged in multiple rows and multiple columns, the pixel array includes a first pixel group and a second pixel group, the first pixel group includes two or more pixels corresponding to a first color among the plurality of pixels, and the second pixel group includes two or more pixels corresponding to a second color among the plurality of pixels; the second imaging device includes a pixel array, the pixel array includes a fourth pixel group and a fifth pixel group, the fourth pixel group corresponds to the first pixel group, and the fifth pixel group corresponds to the second pixel group; the first imaging device determines whether the pixel signals of the first pixel group are read out in batches or at once according to the number of pixel signals of the fourth pixel group read out from the pixel array of the second imaging device within a first frame period; and the first imaging device further includes a control circuit configured to, when it is determined that the pixel signals of the first pixel group are read out in batches, read out the pixel signals of the first pixel group in batches by performing the first readout scan and the second readout scan within a second frame period; and when it is determined that the pixel signals of the first pixel group are read out at once, read out the pixel signals of the first pixel group at once by performing the second readout scan within the second frame period.

20. The imaging system according to claim 19, wherein, the field of view angle of the second optical system is greater than the viewing angle of the first optical system; the first imaging device determines whether the pixel signals of the first pixel group are read out in batches or at once according to the number of pixel signals of the fourth pixel group read out from the area of the pixel array of the second imaging device within a first frame period, and the area corresponds to the viewing angle of the first optical system.

Images