C-PHY receiver corrupted POST mode filter

Abstract

A communication interface circuit has a shift register configured to convert a serial stream of 3-bit symbols into a parallel multi-symbol word including a plurality of symbols ordered according to a time to an input of the shift register; a set of symbol comparators, each symbol comparator configured to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; and a synchronization detection circuit configured to provide a control signal that is valid when a synchronization mode is detected in the serial stream of 3-bit symbols, and the synchronization detection circuit is further configured to suppress the control signal when at least one symbol comparator in the set of symbol comparators indicates the presence of the false synchronization pattern of 3-bit symbols.

Description

[0001] Cross - Reference to Related Applications

[0002] This patent application claims priority to pending U.S. Utility Application No. 17 / 986,631, filed on November 14, 2022, which is assigned to the assignee of the present application and is hereby incorporated by reference in its entirety as if fully set forth herein and for all applicable purposes. Technical Field

[0003] The present disclosure generally relates to serial communication via a serial bus in a wireless communication device, and more particularly, to error detection in control signaling in a C - PHY interface. Background Art

[0004] Mobile communication devices typically include various components such as circuit boards, integrated circuit (IC) devices, application - specific integrated circuit (ASIC) devices, and / or system - on - a - chip (SoC) devices. The types of these components can include processing circuitry, user interface components, storage devices, and other peripheral components that communicate via a serial bus. The serial bus can operate according to a standardized protocol or a proprietary protocol. In one example, the serial bus can operate according to the Inter - Integrated Circuit (I2C or I 2 C) communication protocol. The I2C bus is configured as a multi - point bus and is developed for connecting low - speed peripheral devices to a processor. The two wires of the I2C bus include a Serial Data Line (SDA) that carries data signals and a Serial Clock Line (SCL) that carries clock signals.

[0005] Multiple standards are defined for interconnecting certain types of components in mobile communication devices. For example, different types of interfaces can be used for communication between an application processor and a display or camera component in a mobile communication device. Some display or camera components employ interfaces that conform to standards or protocols specified by the MIPI Alliance, which are used for Camera Serial Interface (CSI) and Display Serial Interface (DSI).

[0006] The MIPI Alliance DSI, DSI-2 (collectively and individually referred to herein as DSI), and CSI and CSI-2 (collectively and individually referred to herein as CSI) standards define wired interfaces that can be deployed within an IC or between certain combinations of IC devices and SoC devices. The CSI protocol can be used to couple a camera and an application processor. The DSI protocol can be used to couple an application processor and a display subsystem. The low-level physical layer (PHY) interfaces in each of these applications can be implemented according to the MIPI Alliance C-PHY or D-PHY standards and protocols. High-speed and low-power modes of communication are defined for the C-PHY interface and the D-PHY interface. The C-PHY high-speed mode uses low-voltage multi-phase signals transmitted in different phases over a 3-wire link. The D-PHY high-speed mode uses multiple 2-wire channels to carry low-voltage differential signals. The low-power modes of the C-PHY interface and the D-PHY interface provide lower rates than the high-speed modes and transmit signals at higher voltages.

[0007] As device technology has improved, in some cases the combination of increasing the clock rate for controlling signaling on a serial interface has been used to meet the demand for higher data rates on a serial bus. For example, the version 2.0 specification for the MIPI C-PHY interface provides a transmit clock rate between 4.5 GHz and 6.0 GHz. Increasing the transmit clock frequency can reduce the tolerances and margins defined for data signals. When the transmit clock rate is increased, certain control patterns transmitted during a C-PHY transaction may be more prone to corruption, and failures to detect or respond to such corruption can result in a loss of data throughput on the C-PHY interface. For these and other reasons, there is a continuing need to improve error detection in the C-PHY interface. SUMMARY

[0008] Certain aspects of the present disclosure relate to systems, devices, methods, and techniques that enable a mobile communication device and other portable devices to detect and ignore error control signals caused by corrupt transmissions on a C-PHY three-wire communication link.

[0009] In various aspects of the present disclosure, a communication interface circuit includes: a shift register configured to convert a serial stream of 3-bit symbols into a parallel multi-symbol word including a plurality of symbols sorted according to the time of arrival at an input terminal of the shift register; a set of symbol comparators, each symbol comparator configured to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; and a synchronization detection circuit configured to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols, and the synchronization detection circuit is further configured to suppress the control signal when at least one of the set of symbol comparators indicates the presence of a false synchronization pattern of 3-bit symbols.

[0010] In various aspects of the present disclosure, a method for operating a communication interface circuit includes: configuring a shift register to convert a serial stream of 3-bit symbols into a parallel multi-symbol word, the parallel multi-symbol word including a plurality of symbols sorted according to the time of arrival at the input of the shift register; configuring each symbol comparator in a set of symbol comparators to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; configuring a synchronization detection circuit to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols; and suppressing the control signal when at least one symbol comparator in the set of symbol comparators indicates the presence of a false synchronization pattern of 3-bit symbols.

[0011] In various aspects of the present disclosure, an apparatus includes: means for converting a serial stream of 3-bit symbols into a parallel multi-symbol word, the parallel multi-symbol word including a plurality of symbols sorted according to the time of arrival at the input of the means for converting a serial stream of 3-bit symbols into a parallel multi-symbol word; means for comparing a sequence of symbols, the means for comparing a sequence of symbols including a set of symbol comparators, wherein each symbol comparator is configured to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; and means for detecting a synchronization pattern, the means for detecting a synchronization pattern being configured to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols, and the means for detecting a synchronization pattern being further configured to suppress the control signal when at least one symbol comparator in the set of symbol comparators indicates the presence of a false synchronization pattern of 3-bit symbols.

[0012] In various aspects of the present disclosure, a processor-readable storage medium includes code for configuring a shift register to convert a serial stream of 3-bit symbols into a parallel multi-symbol word, the parallel multi-symbol word including a plurality of symbols sorted according to the time of arrival at the input of the shift register; configuring each symbol comparator in a set of symbol comparators to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; configuring a synchronization detection circuit to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols; and suppressing the control signal when at least one symbol comparator in the set of symbol comparators indicates the presence of a false synchronization pattern of 3-bit symbols.

[0013] In some aspects, each symbol in a serial stream of 3-bit symbols represents a transition in the signaling state of a three-wire differential serial communication link. A synchronization pattern transmitted on the three-wire differential serial communication link may include a sequence of symbols each having a first value, the symbol sequence being followed in transmission by a symbol having a second value. In one example, a false synchronization pattern includes a corrupted symbol having a second value, and the corrupted symbol may be followed in transmission by a sequence of symbols each having a first value. In some examples, the corrupted symbol is included in a POST pattern configured according to the C-PHY protocol.

[0014] In some aspects, a symbol comparator in the set of symbol comparators receives different sequences of parallel multi-symbol words. In some aspects, a demapper may be configured to output a 16-bit data word mapped to seven symbols in a parallel multi-symbol word. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Illustrates apparatus that employs a data link between IC devices and operates selectively according to a standard or proprietary protocol.

[0016] Figure 2 Illustrates an example of an interface circuit that may be adapted according to certain aspects of the present disclosure.

[0017] Figure 3 Illustrates the system architecture of an apparatus that employs a C-PHY data link between IC devices.

[0018] Figure 4 Illustrates an example of a C-PHY interface that may be adapted according to certain aspects disclosed herein.

[0019] Figure 5 Illustrates signaling in an example of an N-phase polar encoding interface.

[0020] Figure 6 Is a state diagram that illustrates transitions between signaling states and signaling states in a C-PHY interface implemented according to certain aspects disclosed herein.

[0021] Figure 7 Illustrates certain aspects of data transmission in a C-PHY interface that may be adapted according to certain aspects disclosed herein.

[0022] Figure 8 Illustrates certain aspects of a filter circuit provided in a device configured as a C-PHY receiver according to certain aspects of the present disclosure.

[0023] Figure 9 Illustrates an example of an apparatus that employs a processing circuit that may be adapted according to certain aspects disclosed herein.

[0024] Figure 10is a flowchart illustrating a method for operating a display or a camera in a mobile communication device in accordance with certain aspects disclosed herein.

[0025] Figure 11 Illustrates a first example of a hardware implementation of a communication device adapted in accordance with certain aspects disclosed herein. Detailed Description

[0026] The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. It will be apparent, however, to those skilled in the art that the concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0027] Several aspects of the present invention will now be presented with reference to various devices and methods. These devices and methods will be described in detail below and illustrated in the drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

[0028] The data communication links employed by an SoC and other IC devices to connect a processor to a modem and other peripherals may operate in accordance with industry or proprietary standards or protocols associated with certain functions or types of devices. In the example of a display panel, display subsystem, and display driver, communication standards and protocols defined by the MIPI Alliance are often used. For example, the Display Serial Interface provides the C-PHY and D-PHY standards and protocols for defining, configuring, and controlling a high-speed serial interface between a host processor and a display module.

[0029] In accordance with certain aspects of the present disclosure, a serial data link can be used to interconnect electronic devices that are sub-components of devices such as: cellular phones, smartphones, session initiation protocol (SIP) phones, laptop computers, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, global positioning system (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, gaming consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multi-rotor helicopters, or any other similar functional devices.

[0030] Figure 1 An example of an apparatus 100 is illustrated that includes a plurality of devices or circuits coupled by one or more data communication buses. The processing circuitry 102 of the apparatus 100 includes a plurality of circuits, or devices 104, 106, and / or 108. In some examples, the processing circuitry 102 is implemented using one or more application specific integrated circuits (ASICs). In other examples, the processing circuitry 102 is implemented in a system on a chip (SoC). In one example, the apparatus 100 can be configured to operate as a communication device, and the processing circuitry 102 includes an ASIC 104, one or more peripherals 106, and a transceiver 108 that cooperate to enable the apparatus to communicate with a radio access network, a core access network, the Internet, and / or another network via an antenna 122.

[0031] The ASIC 104 may have one or more processors 112, one or more modems 110, on-board memory 114, bus interface circuitry 116, and / or other logic circuits or functions. The processing circuitry 102 may be controlled by an operating system that provides an application programming interface (API) layer that enables one or more processors 112 to execute software modules resident in the on-board memory 114 or other processor-readable storage devices 118 provided on the processing circuitry 102. The software modules may include instructions and data stored in the on-board memory 114 or processor-readable storage devices 118. The ASIC 104 may access its on-board memory 114, processor-readable storage devices 118, and / or storage devices external to the processing circuitry 102. The on-board memory 114, processor-readable storage devices 118 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device usable in processing systems and computing platforms. The processing circuitry 102 may include, implement, or access a local database or other parameter storage device that may maintain operating parameters and other information for configuring and operating the device 100 and / or the processing circuitry 102. The local database may be implemented using registers, database modules, flash memory, magnetic media, EEPROM, floppy disks, or hard disks. The processing circuitry 102 may also be operatively coupled to external devices such as an antenna 122, a display 138, operator controls (such as switches or buttons 136, 130, and / or an integrated or external keyboard 132), and other components. The user interface module may be configured to operate with the display 138, external keyboard 132, etc. via a dedicated communication link or via one or more serial data interconnections.

[0032] The processing circuitry 102 may provide a plurality of buses 120 that enable two or more devices 104, 106, and / or 108 to communicate. In one example, the ASIC 104 may include bus interface circuitry 116 coupled to one or more of the buses 120. Each bus interface circuitry in the bus interface circuitry 116 may include a combination of circuitry, counters, timers, control logic components, and other configurable circuits or modules. In one example, certain bus interface circuitry 116 may be configured to operate according to communication specifications or protocols defined by standards. The processing circuitry 102 may include or control power management functions that configure and manage the operation of the device 100.

[0033] Figure 2Illustrates an example of an interface circuit that can be adopted or adapted according to certain aspects of the present disclosure. The first interface circuit is configured as a camera subsystem 200, and the second interface circuit is configured as a display subsystem 250. For example, the interface circuit can be deployed in a mobile communication device. The camera subsystem 200 can include a CSI-2 defined communication link between an image sensor 202 and an application processor 212. The communication link can include a high data rate data transmission link 210 used by the image sensor 202 to transmit image data to the application processor 212 using a transmitter 206. The high data rate data transmission link 210 can be configured and operated according to the C-PHY protocol. The application processor 212 can include a crystal oscillator (XO 214) or other clock source to generate a clock signal 222 that controls the operation of the transmitter 206. The clock signal 222 can be processed by a phase locked loop (PLL) 204 in the image sensor 202. In some cases, the clock signal 222 can also be used by a C-PHY receiver 216 in the application processor 212. The communication link can include a camera control interface (CCI), which is essentially similar to an inter-integrated circuit bus (I2C) interface. The CCI bus can include a serial clock (SCL) line that carries the clock signal and a serial data (SDA) line that carries the data. The CCI link 220 can be bidirectional and can operate at a lower data rate than the high data rate data transmission link 210. The application processor 212 can use the CCI link 220 to exchange control and configuration information with the image sensor 202. The application processor 212 can include a CCI bus master 218, and the image sensor 202 can include a CCI slave 208.

[0034] The display subsystem 250 can include a unidirectional data link 258 that can be configured and operated according to the C-PHY protocol. In the application processor 252, a clock source such as a PLL 254 can be used to generate a bit clock signal used by the C-PHY receiver 256 to control transmission on the data link 258. At the display device 260, the C-PHY receiver 262 can extract embedded clock information from the symbol sequence transmitted on the data link or from the clock channel provided in the data link 258.

[0035] Certain aspects disclosed herein relate to systems, apparatuses, and methods that support a wide range of interface protocols and can operate using different physical media. As Figure 2 shown, for example, the camera subsystem 200 and / or the display subsystem 250 can use the C-PHY protocol to convey high data rate information. In some configurations, the camera subsystem 200 and / or the display subsystem 250 can communicate using a reverse channel (e.g., the CCI link 220) for configuring the image sensor 202 or other devices. In some cases, a low power operation mode can be defined for links using either of the C-PHY protocols.

[0036] Figure 3 Illustrates an example of apparatus 300 employing a data link that can be used to communicatively couple two or more devices, sub-components, or circuits. Here, apparatus 300 includes a plurality of devices 302 and 322 coupled to a two-wire serial bus 320 0 -322 N Devices 302 and 322 0 -322 N may be implemented in one or more semiconductor IC devices such as an application processor, an SoC, or an ASIC. In various embodiments, some of devices 302 and 322 0 -322 N may include, support, operate as, or otherwise be a modem, a signal processing device, a display driver, a camera, a user interface, a sensor, a sensor controller, a media player, a transceiver, and / or other such components or devices. In some examples, one or more devices 322 0 -322 N may be used to control, manage, or monitor sensor devices. Communication between devices 302 and 322 0 -322 N over serial bus 320 is controlled by bus master 302. Some types of buses may support multiple bus masters 302.

[0037] In one example, bus master 302 includes interface controller 304, which may be configured to manage access to the serial bus, configure dynamic addresses for slave devices, and / or generate a clock signal 328 to be sent on the clock line 318 of serial bus 320. Bus master 302 may include configuration register 306 or other storage means 324 and other control logic 312 configured to handle protocols and / or higher-level functions. Control logic 312 may include processing circuitry such as a state machine, an sequencer, a signal processor, or a general-purpose processor. Bus master 302 includes transceiver 310 and line drivers / receivers 314a and 314b. Transceiver 310 may include a receiver, a transmitter, and common circuitry, where the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on the timing in clock signal 328 provided by clock generation circuitry 308. Control logic 312 and other functions, circuits, or modules may use other timing clocks 326.

[0038] At least one device 322 0 -322 Ncan be configured to operate as a slave device on serial bus 320 and can include circuitry and modules that support a display, an image sensor, and / or one or more sensors that control and communicate with the one or more sensors for measuring ambient conditions. In one example, a device 322 configured to operate as a slave device 0 can provide control functionality, a physical layer circuit 332 that includes circuitry and modules that support a display, an image sensor, and / or one or more sensors that control and communicate with the one or more sensors for measuring ambient conditions. In this example, device 322 0 can include a configuration register 334 or other storage device 336, control logic 342, a transceiver 340, and line drivers / receivers 344a and 344b. Control logic 342 can include processing circuitry such as a state machine, sequencer, signal processor, or general-purpose processor. Transceiver 340 can include a receiver, a transmitter, and common circuitry, where the common circuitry can include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in a clock signal 348 provided by a clock generation and / or recovery circuit 346. In some instances, clock signal 348 can be derived from a signal received from a clock line 318. Control logic 342 and other functions, circuitry, or modules can use another timing clock 338.

[0039] Serial bus 320 can operate according to a standard-defined protocol or a proprietary protocol. In some cases, two or more devices 302, 322 0 -322 N can be configured to operate as bus master devices on serial bus 320. In some cases, apparatus 300 includes multiple serial buses 320, 352a, and / or 352b that couple devices 302, 322 0 -322 N two or more of the devices or devices 302, 322 0 -322 N one of the devices and a peripheral device such as a display or camera 350 or a radio frequency IC (RFIC). In some examples, one slave device 322 0 is configured to operate as a display or camera coupled to a display or camera 350. This latter slave device 322 0 can include a physical layer circuit 332 configured to operate as a C-PHY interface controller that communicates with a display or camera 350 via a serial bus 352a or 352b operating according to the C-PHY protocol.

[0040] In certain aspects of the present disclosure, systems and devices can employ a multi-phase data encoding and decoding interface method to communicate between IC devices. A multi-phase encoder can drive multiple conductors (i.e., 3 conductors). Each conductor can be referred to as a wire, but the conductor can include a conductive trace on a circuit board or a trace or interconnect within a conductive layer of a semiconductor IC device. In one example, a physical layer interface (i.e., C-PHY interface) implemented using the C-PHY technology and protocol defined by the MIPI Alliance can be used to connect a camera or a display to an application processor. The C-PHY interface employs a three-phase symbol encoding to transmit data symbols over a 3-wire channel or "triplet", where each triplet includes an embedded clock. The triplet can be referred to as a channel herein. Multiple triplets can be used to establish a multi-channel C-PHY communication channel to carry data exchanged between a pair of devices, where each channel includes one triplet carrying a portion of the data, and the data can be independently encoded according to the C-PHY protocol.

[0041] The C-PHY interface provides a three-phase encoding scheme for a three-wire system. The three-phase encoding scheme defines three-phase states and two polarities, thus providing 6 states and 5 possible transitions from each state. Deterministic voltage and / or current changes can be detected and decoded to extract data from the three wires.

[0042] Figure 4 An example of a C-PHY interface that can be used to implement Figure 3 certain aspects of the serial buses 352a or 352b depicted in. The example illustrated can relate to a three-wire link configured to carry three-phase polarity-encoded data according to the DSI protocol. The use of 3-phase polarity encoding provides high-speed data transmission and may consume half or less power of other interfaces at a desired operating frequency, as less than 3 drivers are active at any time in a C-PHY link. The C-PHY interface uses 3-phase polarity encoding to encode multiple bits for each symbol transition on a three-wire link. In one example, a combination of three-phase encoding and polarity encoding can be used to support a wide video graphics array (WVGA), a liquid crystal display driver IC at 80 frames per second, without a frame buffer, delivering pixel data at 810 Mbp over three or more wires for display refresh.

[0043] In the depicted C-PHY interface, three-phase polarity coding is used to control the signaling states of connectors, wires, traces, and other interconnects that provide a communication channel. In the illustrated example, a combination of three wires (the triplet 440) is used to provide a single unidirectional channel or lane. Each wire of the triplet 440 can be undriven, positively driven, or negatively driven during any symbol transmission interval. In some cases, the undriven signal wire of the triplet 440 can be in a high impedance state. In some cases, the undriven signal wire of the triplet 440 can be driven or pulled to a voltage level that is substantially intermediate between the positive voltage level and the negative voltage level provided on the driven signal wires. In some cases, no current flows through the undriven signal wire of the triplet 440. The driver 408 in the transmitter 400 that controls the signal wires coupled to the triplet 440 is configured such that only one wire of the triplet 440 is in each of three states (represented as +1, -1, or 0) during each symbol interval.

[0044] In one example, the driver 408 includes a cell-level current-mode driver. In another example, the driver 408 drives opposite-polarity voltages on two signals transmitted on two signal wires of the triplet 440 while the third signal wire is in a high impedance and / or pulled to ground. For each transmission symbol interval, at least one signal is in an undriven (0) state while one signal is driven positive (+1 state) and one signal is driven negative (-1 state) such that the sum of the currents flowing into the receiver 420 is zero amperes. For each symbol, the state of at least one signal wire of the triplet 440 changes from the symbol transmitted in the previous transmission interval.

[0045] In the transmitter 400, the mapper 402 may receive a 16-bit input data word 418, and the mapper 402 may map the input data word 418 to seven symbols 412 for sequential transmission over the signal wires of the triplet 440. The M-line, N-phase encoder 406, configured for three-wire, three-phase coding, receives the seven symbols 412 produced by the mapper one input symbol 414 at a time and calculates the state of each signal wire of the triplet 440 for each symbol interval based on the previous state of the signal wires of the triplet 440. The seven symbols 412 may be serialized using, for example, a parallel-to-serial converter 404. The encoder 406 provides a control signal 416 to define the output of the driver 408. The encoder 406 selects the state of the signal wires of the triplet 440 based on the input symbol 414 and the previous state of the signal wires of the triplet 440 and may provide the control signal 416 to cause the driver 408 to produce the desired signaling state on the triplet 440.

[0046] The use of three-wire, three-phase coding allows multiple bits to be encoded in multiple symbols, where the bits per symbol are not integers. In an example of a three-wire, three-phase system, there are 3 available combinations of 2 wires that can be driven simultaneously, and 2 possible polarity combinations on a pair of wires that are driven simultaneously, resulting in 6 possible states. Since each transition starts from the current state, 5 of the 6 states are available for each transition. For 5 states, each symbol transition can encode fractional bits. Thus, the mapper can accept a 16-bit word and convert it to a 7-symbol sequence, since 7 symbols with 2.32 bits per symbol can encode 16.24 bits. In other words, the combination of seven symbols encoding five states has 5 7 (78,125) permutations. Thus, 7 symbols can be used to encode the 2 16 (65,536) permutations of 16 bits.

[0047] In the illustrated example, the receiver 420 includes a comparator 422 and a decoder 424 that are configured to provide a digital representation of the state of each of the three signal lines of the triple 440, and the change in the state of the three signal lines compared to the state transmitted in the previous symbol period. The seven consecutive states are combined by the serial-to-parallel converter 426 and used to generate a set of 7 symbols to be processed by the demapper 428 to obtain 16-bit data that can be buffered in a first-in, first-out (FIFO) storage device 430, which can be implemented using, for example, registers.

[0048] Figure 5 An example of signaling 500 employing a 3-phase modulation data coding scheme based on the cyclic state transition diagram 550 is illustrated. According to the data coding scheme, the 3-phase signal can be rotated in two directions and can be transmitted on three wires 514a, 514b, and 514c identified as connectors A, B, and C. Each of the three signals is driven independently on the wires 514a, 514b, 514c. Each of the three signals includes a 3-phase signal, where each signal has a 120-degree phase difference relative to the other two signals. At any point in time, each of the three wires 514a, 514b, 514c is in a different one of the states {+1, 0, -1}. At any point in time, each of the three wires 514a, 514b, 514c in the 3-wire system is in a state different from the other two wires. When more than three conductors or wires are used, two or more pairs of wires can be in the same state. The illustrated coding scheme can also encode information in the polarities of two wires 514a, 514b, and / or 514c that are actively driven to the +1 and -1 states. For the depicted state sequence, the polarity is indicated at 508.

[0049] In any phase state in the illustrated three-wire example, exactly two of the wires 514a, 514b, 514c carry signals that effectively act as differential signals for that phase state, while the third wire 514a, 514b, or 514c is undriven. The phase state of each wire 514a, 514b, 514c can be determined by the voltage difference between the wire 514a, 514b, or 514c and at least one other wire 514a, 514b, and / or 514c, or by the direction of current flow or lack of current flow in the wire 514a, 514b, or 514c. As shown in the state transition diagram 550, three phase states (S 1 , S 2 , and S 3 ) are defined. Signals can flow clockwise from phase state S 1 to phase state S 2 , from phase state S 2 to phase state S 3 , and / or from phase state S 3 to phase state S 1 , and signals can flow counterclockwise from phase state S 1 to phase state S 3 , from phase state S 3 to phase state S 2 , and / or from phase state S 2 to phase state S 1 . For other values of N, the transitions between N states can optionally be defined according to the corresponding state diagram to obtain a cyclic rotation between state transitions.

[0050] In the example of a three-wire, three-phase communication link, a clockwise rotation (S 1 to S 2 ), (S 2 to S 3 ), and / or (S 3 to S 1 ) at the phase transition 510 can be used to encode a logic 1, while a counterclockwise rotation (S 1 to S 3 ), (S 3 to S 2 ), and / or (S 2 to S 1 ) at the phase transition 510 can be used to encode a logic 0. Thus, a bit can be encoded at each transition by controlling whether the signal "rotates" clockwise or counterclockwise. For example, when the three wires 514a, 514b, 514c transition from phase state S 1 to phase state S 2When it is, logic 1 can be encoded, and when the three wires 514a, 514b, 514c transition from phase state S 1 to phase state S 3 When it is, logic 0 can be encoded. In the depicted 3 - wire example, the direction of rotation can be easily determined based on which of the three wires 514a, 514b, 514c is not driven before and after the transition.

[0051] The information can also be encoded in the polarity and / or polarity change of the state 508 of the driven wires 514a, 514b, 514c, or in the direction of current flow or change in the direction of current flow between two of the wires 514a, 514b, 514c. Signals 502, 504, and 506 illustrate the voltage levels applied to the wires 514a, 514b, 514c at each phase state in a 3 - wire, 3 - phase link respectively. At any time, the first wire 514a, 514b, 514c is coupled to a more positive voltage (e.g., +V), the second wire 514a, 514b, 514c is coupled to a more negative voltage (e.g., -V), while the third wire 514a, 514b, 514c can be open - circuited. Thus, one polarity - encoded state can be determined by the current flow between the first and second wires 514a, 514b, 514c or the voltage polarities of the first and second wires 514a, 514b, 514c. In some embodiments, two bits of data 512 can be encoded in each phase transition 510. The decoder can determine the direction of signal phase rotation to obtain the first bit. The second bit can be determined based on the polarity difference between two of the signals 502, 504, and 506. In some instances, the second bit can be determined based on the change or non - change in the polarity of the differential signal sent on a pair of wires 514a, 514b, 514c. A decoder with the ability to determine the direction of rotation can determine the phase state and polarity of the voltage applied between two active wires 514a, 514b and / or 514c, or the direction of the current flowing through two active wires 514a, 514b and / or 514c.

[0052] In the example of the 3 - wire, 3 - phase link described herein, one bit of data can be encoded during the rotation or phase change in the 3 - wire, 3 - phase link, and additional bits can be encoded in the polarity or polarity change of two driven lines. In certain embodiments, by allowing a transition from the current state to any of the possible states, more than two bits can be encoded in each transition of a 3 - wire, 3 - phase coding system. Given three rotational phases and two polarities for each phase, 6 states are defined such that 5 states can be obtained from any current state. Thus, there can be bits per symbol (transition), and the mapper can accept a 16 - bit word and convert it into 7 symbols.

[0053] Figure 6 FIG. 600 is a state transition diagram of possible signaling states 602, 604, 606, 612, 614, 616 of three conductors in an exemplary 3-wire, 3-phase interface (e.g., including a MIPI Alliance C-PHY high-speed mode interface). All possible transitions from each signaling state 602, 604, 606, 612, 614, 616 are illustrated. The transitions in state transition diagram 600 can be represented by a flip, rotate, polarity (FRP) symbol 626 having one of the three-bit binary values in the set {000, 001, 010, 011, 100}. The rotate bit 622 of the FRP symbol 626 indicates the direction of phase rotation associated with the transition to the next state. When the transition to the next state involves a polarity change, the polarity bit 624 of the FRP symbol 626 is set to the binary value 1. When the flip bit 620 of the FRP symbol 626 is set to the binary value 1, the rotate and polarity values can be ignored and / or reset to zero. A flip represents a state transition that involves only a polarity change. Thus, when a flip occurs, the phase of the 3-phase signal is not considered to be rotating, and when a flip occurs, the polarity bit is redundant. The FRP symbol 626 corresponds to the line state change for each transition. State transition diagram 600 can be divided into an inner circle 608 including positive polarity signaling states 602, 604, 606 and an outer circle 618 surrounding negative polarity signaling states 612, 614, 616.

[0054] Figure 7 Certain aspects of signaling on a data communication link 702 operating in accordance with the C-PHY protocol are illustrated. A high-speed transaction 700 is illustrated, in which the C-PHY interface is initially configured for a low-power operation mode 712. Starting at a first time 704, a SoT sequence 718 is sent to switch the C-PHY interface to a low-voltage, high-speed operation mode 714 for transmitting data. In the speed operation mode 714, low-voltage differential (3-phase) signaling is used. Starting at a second time 708, an EoT sequence 728 is sent to return the C-PHY interface to the low-power operation mode 716. A POST mode 726 is provided at the end of the high-speed data transmission to provide a reliable notification of the end of the high-speed burst to the receiver. In some instances, the receiver can determine that the C-PHY interface is configured for the low-power operation mode 716 based on the detection of signaling at a higher voltage level associated with the low-power mode.

[0055] A C-PHY interface adapted according to certain aspects of the present disclosure transitions from a high-speed mode to a low-power mode after transmitting a POST pattern 726 defined by the C-PHY protocol. According to the C-PHY protocol, the POST pattern 726 is provided at the end of high-speed data transmission to provide a reliable notification of the end of high-speed data transmission. The POST pattern 726 includes a series of unmapped codewords (e.g., a sequence in which all symbols have a value of "4"). The unmapped codewords may refer to 7-symbol sequences that are not used for encoding data. The SoT sequence 718 is transmitted to initiate the high-speed operation mode 714, and in one example, it may be defined as the sequence {LP-111, LP-001, LP-000}. During transmission, pauses may be made before and after the SoT sequence 718.

[0056] High-speed data transmission includes data packets 724, which include one or more 7-symbol sequences, and each 7-symbol sequence encodes a data word. Encoding and decoding may be implemented using a mapping table that associates each permutation of 16 bits with a combination of 7 symbols. Each symbol may be an FRP symbol that determines the next signaling state of a triplet state based on the current signaling state of a defined triplet state. The C-PHY encoding scheme employs symbols, and 7-symbol combinations result in a total of 78,125 permutations (5 7 ), of which 65,536 (2 16 ) are uniquely associated with one of the possible values of the 16-bit possible values of the data word. Thus, 12,589 7-symbol combinations are nominally available for control use in control sequences.

[0057] The C-PHY protocol defines certain 7-symbol sequences that may be reserved for training, synchronization, and control purposes. For example, the data packet 724 is preceded by a preamble 720 and a sync word 722 during transmission, and the data transmission is terminated by the POST pattern 726. The preamble 720, the sync word 722, and the POST pattern 726 each include one or more reserved 7-symbol sequences. In the illustrated example, two initial sequences 740 and 750 are shown. The initial sequences 740 and 750 have different types of preambles.

[0058] In the first initial sequence 740, the preamble 742 includes a programmable sequence 746, which may be used to configure, train, or otherwise communicate control information to the receiver. The preamble 742 includes a preamble_start sequence 744, followed by the programmable sequence 746, and is completed by a preamble_end sequence 748.

[0059] In the illustrated example, the preamble_start sequence 744 includes repeated instances of a 7-symbol sequence, where each symbol has a value of "3". The number of repetitions can be defined by the protocol, application, or configuration during calibration. The programmable sequence 746 includes a number of 7-symbol sequences, which may include reserved symbols or encoded data words. The number, type, and interpretation of the 7-symbol sequences in the programmable sequence 746 are defined by the protocol, application, or configuration during calibration. In the illustrated example, the preamble_end sequence 748 includes a single 7-symbol sequence, where each symbol has a value of "3".

[0060] In the second initial sequence 750, the preamble 752 includes the preamble_start sequence 754, followed immediately by the preamble_end sequence 756. In the illustrated example, the preamble_start sequence 754 includes repeated instances of a 7-symbol sequence, where each symbol has a value of "3". The number of repetitions can be defined by the protocol, application, or configuration during calibration. In the illustrated example, the preamble_end sequence 756 includes a single 7-symbol sequence, where each symbol has a value of "3".

[0061] Both initial sequences 740 and 750 end with the sync word 722. In the illustrated example, the preamble_end sequences 748, 756 include a single 7-symbol sequence having a first transmitted symbol and a last transmitted symbol with a value of "3" and five intermediate symbols with a value of "4". The data packet 724 follows the sync word 722 in transmission. According to the C-PHY protocol, the receiver is configured to recognize and respond to the sync word 722 after receiving five symbols with a value of "4" followed by a symbol with a value of "3".

[0062] In the illustrated example, the POST mode 726 includes repeated instances of a 7-symbol sequence, where each symbol has a value of "4". The number of repetitions can be defined by the protocol, application, or configuration during calibration.

[0063] Increased data throughput rates specified by subsequent versions of the MIPI C-PHY interface specification (e.g., MIPI C-PHY version 2.0 and later versions) may cause or exacerbate signal integrity issues. For example, a loss of signal integrity may cause the symbol recovery circuitry at the receiver to generate a corrupted symbol sequence or pattern, which may pose complex challenges to the physical layer circuitry and modules (RxPHY) in the receiver. In one example, corruption may occur when one of the fixed patterns of symbols with a value of "4" in POST pattern 726 flips to a different value due to signal distortion or a non-optimized analog front end (AFE) in the receiver or transmitter. In the latter example, when a symbol in POST pattern 726 is flipped to a symbol with a value of "3", corruption of the symbol pattern in POST pattern 726 may cause the RxPHY to misread the transmitted POST pattern 726 as the sync word 722. Certain receivers may be configured to support a packet delimiter qualifier (PDQ) synchronization mode according to the C-PHY protocol, which allows the sync word 722 to be transmitted at any time during high-speed data transmission. Reception of the PDQ synchronization mode causes the receiver to discard any ongoing data reception and begin receiving a new data packet 724.

[0064] In accordance with certain aspects of the present disclosure, a device operable according to the C-PHY protocol may be configured or adapted to ignore or discard corrupted symbols in a POST pattern. In one aspect, the device may be configured with a filter that may identify and mark symbols with a value of "3" received in the middle of a symbol sequence, where the other symbols each have a value of "4". The symbol sequence with a value of "4" may be included in the POST pattern, and the marked symbols may be considered as error symbols or corrupted symbols. A synchronization detector in the device may be configured to ignore or remove the error symbols or corrupted symbols, and it may prevent false detection of the PDQ synchronization mode.

[0065] Figure 8 Illustrates certain aspects of a filter circuit 800 in a device configured as a C-PHY receiver in accordance with certain aspects of the present disclosure. In certain aspects, the filter circuit 800 may correspond to Figure 4 the receiver 420 of the C-PHY interface illustrated in. In one example, the filter circuit 800 may be configured to filter or discard any error symbols with a value of "3" that occur in the middle of a symbol sequence with a value of "4" in the POST pattern.

[0066] In the illustrated example, filter circuit 800 includes shift register 802, comparison circuit 804, and controller 806. Shift register 802 may be provided in a circuit that converts a received symbol stream into a set of seven or more symbols, which may be used to index a lookup table or a demapper to decode data from the received symbol stream. In one example, shift register 802 may be used to implement Figure 4 the serial-to-parallel converter 426 illustrated in 0 -812 k Shift register 802 has an input terminal 808 through which a 3-bit symbol stream is received from the decoder circuit. In one example, each symbol in the 3-bit symbol stream is an FRP symbol representing a transition of the signaling state of a C-PHY triple. The 3 bits are propagated through a plurality (k + 1) of 3-bit flip-flops 812 0 -812 k timed by a received symbol clock signal 810 typically provided by a clock recovery circuit. An edge in the received symbol clock signal 810 is generated in response to a transition in the signaling state of the C-PHY triple. In one example, 3-bit flip-flops 812 0 -812 k are timed by an edge in the received symbol clock signal 810 having a period corresponding to the duration of a single symbol transmission interval. In another example, 3-bit flip-flops 812 0 -812 k are timed by both the rising and falling edges in a half received symbol clock signal 810 that toggles back and forth in response to each transition in the signaling state of the C-PHY triple.

[0067] In the illustrated example, the outputs of 3-bit flip-flops 812 0 -812 k contribute to a symbol bus 824 having a (k + 1) × 3-bit width. Referring again to Figure 4 , demapper 428 is configured to receive a 7-symbol input represented by 21 bits of symbol bus 824, and k ≥ 6. In some embodiments, a k value greater than 6 is used to support or enable filtering performed in accordance with certain aspects of the present disclosure. Filtering decisions may be made based on comparisons of symbols present on symbol bus 824. Symbol bus 824 enables the most recently received symbol (S[n]) to be compared with any combination of k previous symbols. Symbol bus 824 enables filtering to be performed using combinations of symbols (S[n + i]) compared with earlier or later received symbols. Filtering may be used to identify invalid or corrupted control patterns.

[0068] The illustrated comparison circuit 804 includes a plurality (j) of symbol comparators 814 1 -814 j. Each comparator 814 1 through 814 j is configured to compare 8 symbols. In one example, each comparator 814 1 through 814 j includes eight XOR-based circuits, each of which compares corresponding bits of corresponding symbols in a pair of input symbol sequences. The symbol comparators 814 1 through 814 j output can be configured to indicate the comparison result involving the corresponding 8 input symbols. In one example, the result output by the symbol comparators 814 1 through 814 j can indicate that all of its input symbols are the same. In another example, the result output by the symbol comparators 814 1 through 814 j can indicate that all of its input symbols match a predefined or preconfigured value. In another example, the result output by the symbol comparators 814 1 through 814 j can indicate that its input matches a predefined or preconfigured symbol combination.

[0069] In the illustrated example, the comparison circuit 804 is used to filter out invalid synchronization patterns caused by corrupted symbols received during the POST mode. For example, a symbol in the POST mode that flips to a symbol with a value of "3" can be detected using the illustrated filter circuit 800. Each symbol comparator in the symbol comparators 814 1 through 814 j is configured to identify a symbol sequence that contains a symbol with a value of "3", followed by a sequence of seven sequentially received symbols with a value of "4". The sequence of "4" symbols corresponds to the POST mode, and the occurrence of seven sequentially received symbols with a value of "4" indicates that the previous symbol with a value of "3" belongs to a valid synchronization pattern. When an output in the outputs 818 of the symbol comparators 814 1 through 814 j indicates that the symbol sequence is detected, the combinational logic (here the "OR" gate 816) is configured to generate a result signal 820 indicating a determined false synchronization pattern, and the symbol sequence includes a symbol with a value of "3", followed by a sequence of seven sequentially received symbols with a value of "4".

[0070] The result signal 820 is provided to the controller 806, which is configured to detect the synchronization pattern. When the result signal 820 indicates that a false synchronization pattern has been detected, the controller 806 can block the synchronization pattern detection decision. When the result signal 820 indicates a determined false synchronization pattern, the controller 806 can ignore the false PDQ synchronization pattern.

[0071] Example of a processing circuit and method

[0072] Figure 9 FIG. is an illustration of an example of a hardware implementation for apparatus 900. In some examples, apparatus 900 may perform one or more functions disclosed herein. In accordance with various aspects of the present disclosure, processing circuitry 902 may be used to implement elements, any portion of an element, or any combination of elements disclosed herein. Processing circuitry 902 may include one or more processors 904 controlled by some combination of hardware modules and software modules. Examples of processors 904 include microprocessors, microcontrollers, digital signal processors (DSPs), system-on-chips (SoCs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic components, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout the present disclosure. One or more processors 904 may include dedicated processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 916. One or more processors 904 may be configured by a combination of software modules 916 loaded during initialization and may also be configured by loading or unloading one or more software modules 916 during operation.

[0073] In the example illustrated, processing circuitry 902 may be implemented with a bus architecture, generally represented by bus 910. Depending on the particular application of processing circuitry 902 and overall design constraints, bus 910 may include any number of interconnecting buses and bridges. Bus 910 links together various circuits, including one or more processors 904 and storage device 906. Storage device 906 may include memory devices and mass storage devices and may be referred to herein as computer-readable media and / or processor-readable media. Bus 910 may also link various other circuits, such as a timing source, a timer, peripherals, voltage regulators, and power management circuits. Bus interface 908 may provide an interface between bus 910 and one or more transceivers 912a, 912b. Transceivers 912a, 912b may be provided for each networking technology supported by the processing circuitry. In some instances, multiple networking technologies may share some or all of the circuits or processing modules found in transceivers 912a, 912b. Each transceiver 912a, 912b provides components for communicating with various other devices via a transmission medium. In one example, transceiver 912a may be used to couple apparatus 900 to a multi-wire bus. In another example, transceiver 912b may be used to connect apparatus 900 to a radio access network. Depending on the nature of apparatus 900, a user interface 918 (e.g., keypad, display, speaker, microphone, joystick) may also be provided and may be communicatively coupled to bus 910 directly or through bus interface 908.

[0074] The processor 904 may be responsible for managing the bus 910 and for general processing, which may include executing software stored in a computer-readable medium that may include the storage device 906. In this regard, the processing circuitry 902 (including the processor 904) may be used to implement any of the methods, functions, and techniques disclosed herein. The storage device 906 may be used to store data manipulated by the processor 904 when executing the software, and the software may be configured to implement certain methods disclosed herein.

[0075] One or more processors 904 in the processing circuitry 902 may execute the software. Software should be broadly interpreted to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in the storage device 906 in a computer-readable form or within an external computer-readable medium. The external computer-readable medium and / or the storage device 906 may include a non-transitory computer-readable medium. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips), optical disks (e.g., compact disks (CDs) or digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., "flash drives", cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. The computer-readable medium and / or the storage device 906 may also, for example, include a carrier wave, a transmission line, and any other suitable medium for transmitting software and / or instructions that can be accessed and read by a computer. The computer-readable medium and / or the storage device 906 may reside within the processing circuitry 902, within the processor 904, external to the processing circuitry 902, or be distributed across multiple entities including the processing circuitry 902. The computer-readable medium and / or the storage device 906 may be embodied as a computer program product. By way of example, the computer program product may include a computer-readable medium in a packaging material. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure, depending on the particular application and overall design constraints imposed on the overall system.

[0076] The storage device 906 may maintain software that is maintained and / or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules 916. Each software module in the software modules 916 may include instructions and data that, when installed or loaded into the processing circuitry 902 and executed by one or more processors 904, contribute to the runtime image 914 that controls the operation of the one or more processors 904. Certain instructions, when executed, may cause the processing circuitry 902 to perform functions in accordance with certain methods, algorithms, and processes described herein.

[0077] Some of the software modules 916 may be loaded during initialization of the processing circuitry 902, and these software modules 916 may configure the processing circuitry 902 to enable the performance of the various functions disclosed herein. For example, some software modules 916 may configure the internal devices and / or logic circuitry 922 of the processor 904 and may manage access to external devices such as transceivers 912a, 912b, bus interface 908, user interface 918, timer, math coprocessor, etc. The software modules 916 may include control programs and / or operating systems that interact with interrupt processors and device drivers and control access to the various resources provided by the processing circuitry 902. Resources may include memory, processing time, access to transceivers 912a, 912b, user interface 918, etc.

[0078] One or more of the processors 904 of the processing circuitry 902 may be multifunctional, whereby some of the software modules in the software modules 916 are loaded and configured to perform different functions or different instances of the same function. The one or more processors 904 may additionally be adapted to manage background tasks initiated in response to inputs from, for example, the user interface 918, transceivers 912a, 912b, and device drivers. To support the performance of multiple functions, the one or more processors 904 may be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks to be served by the one or more processors 904 as needed or desired. In one example, a time-sharing program 920 that transfers control of the processor 904 between different tasks may be used to implement the multitasking environment, whereby each task returns control of the one or more processors 904 to the time-sharing program 920 upon completion of any outstanding operations and / or in response to an input such as an interruption. When a task controls the one or more processors 904, the processing circuitry is effectively specialized for the purpose of being resolved by the function associated with the control task. The time-sharing program 920 may include an operating system, a main loop that transfers control on a cyclic basis, functions that allocate control of the one or more processors 904 based on the priority of the functions, and / or an interrupt-driven main loop that provides control of the one or more processors 904 to processing functions to respond to external events.

[0079] Figure 10 FIG. 1000 is a flow chart of a method for operating a display or a camera in a mobile communication device configured in accordance with certain aspects of the present disclosure. In some instances, the method is implemented using a processor in a mobile communication device that includes a display or a camera subsystem.

[0080] At block 1002 in the illustrated method, a shift register is configured to convert a serial stream of 3-bit symbols into a parallel multi-symbol word that includes a plurality of symbols sorted according to the time of arrival at the input of the shift register. At block 1004, each symbol comparator in a set of symbol comparators is configured to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols. At block 1006, a synchronization detection circuit is configured to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols. At block 1008, the control signal is inhibited when at least one symbol comparator in the set of symbol comparators indicates the presence of a false synchronization pattern of 3-bit symbols.

[0081] In certain embodiments, each symbol in the serial stream of 3-bit symbols represents a transition in the signaling state of a three-wire differential serial communication link. A synchronization pattern transmitted on the three-wire differential serial communication link may include a sequence of symbols each having a first value, the sequence of symbols being followed in transmission by a symbol having a second value. In one example, a false synchronization pattern includes a corrupted symbol having a second value, and the corrupted symbol may be followed in transmission by a sequence of symbols each having a first value. In some examples, the corrupted symbol is included in a POST pattern configured according to the C-PHY protocol.

[0082] In some embodiments, the symbol comparators in the set of symbol comparators receive different sequences of the parallel multi-symbol word. In some embodiments, a demapper may be configured to output a 16-bit data word mapped to seven symbols in the parallel multi-symbol word.

[0083] Figure 11FIG. 0 is a diagram illustrating a first example of a hardware implementation of apparatus 1100 employing processing circuitry 1102. The processing circuitry generally includes one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines, and is generally represented by processor 1116. Processing circuitry 1102 may be implemented with a bus architecture, which is generally represented by bus 1120. Depending on the particular application of processing circuitry 1102 and overall design constraints, bus 1120 may include any number of interconnecting buses and bridges. Bus 1120 links together various circuits including a plurality of processors 1116, modules or circuits 1104, 1106, and 1108, and processor-readable storage medium 1118. A bus interface circuit and / or module 1114 may be provided to support communication on a plurality of serial data links 1112. Bus 1120 may also link various other circuits (such as timing sources, peripherals, voltage regulators, and power management circuits), which are well known in the art and will not be described further herein.

[0084] Processor 1116 may be responsible for general processing, including the execution of software, code, and / or instructions stored on processor-readable storage medium 1118. Processor-readable storage medium 1118 may include non-transitory storage media. The software, when executed by processor 1116, causes processing circuitry 1102 to perform the various functions described above for any particular apparatus. The processor-readable storage medium may be used to store data manipulated by processor 1116 when executing the software. Processing circuitry 1102 also includes at least one of modules 1104, 1106, and 1108. Modules 1104, 1106, and 1108 may be software modules running in processor 1116, hardware modules coupled to processor 1116, or some combination thereof, residing / stored on processor-readable storage medium 1118. Modules 1104, 1106, and 1108 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0085] In one configuration, apparatus 1100 includes: module and / or circuit 1104, which is adapted to convert a 3-bit symbol stream into a parallel multi-bit word representing a plurality of symbols; module and / or circuit 1106, which is adapted to compare symbol sequences; and module and / or circuit 1108, which is adapted to detect a synchronization pattern in the symbol stream and ignore false synchronization patterns.

[0086] Apparatus 1100 may include components for converting a serial stream of 3-bit symbols into a parallel multi-symbol word, the parallel multi-symbol word including a plurality of symbols sorted according to the time of arrival at an input terminal of the components for converting the serial stream of 3-bit symbols into a parallel multi-symbol word; components for comparing symbol sequences, the components for comparing symbol sequences including a set of symbol comparators, wherein each symbol comparator is configured to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; and components for detecting a synchronization pattern, the components for detecting a synchronization pattern being configured to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols, and the components for detecting a synchronization pattern being further configured to suppress the control signal when at least one symbol comparator in the set of symbol comparators indicates the presence of a false synchronization pattern of 3-bit symbols.

[0087] In some specific implementations, each symbol in the serial stream of 3-bit symbols represents a transition of the signaling state of a three-wire differential serial communication link. The synchronization pattern transmitted on the three-wire differential serial communication link may include a sequence of symbols each having a first value, the sequence of symbols being followed in transmission by a symbol having a second value. In one example, the false synchronization pattern includes a corrupted symbol having a second value, and the corrupted symbol may be followed in transmission by a sequence of symbols each having a first value. In some examples, the corrupted symbol is included in a POST pattern configured according to the C-PHY protocol.

[0088] In some instances, the symbol comparators in the set of symbol comparators receive different sequences of the parallel multi-symbol word.

[0089] In some specific implementations, apparatus 1100 includes a demapping component configured to output a 16-bit data word mapped to seven symbols in the parallel multi-symbol word.

[0090] In one example, apparatus 1100 is configured to operate as a communication interface circuit having a shift register configured to convert a serial stream of 3-bit symbols into a parallel multi-symbol word, the parallel multi-symbol word including a plurality of symbols sorted according to the time of arrival at an input terminal of the shift register; a set of symbol comparators, each symbol comparator being configured to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; and a synchronization detection circuit configured to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols, and the synchronization detection circuit being further configured to suppress the control signal when at least one symbol comparator in the set of symbol comparators indicates the presence of a false synchronization pattern of 3-bit symbols.

[0091] In some specific implementations, each symbol in a serial stream of 3-bit symbols represents a transition in the signaling state of a three-wire differential serial communication link. A synchronization pattern transmitted on the three-wire differential serial communication link may include a sequence of symbols each having a first value, and the sequence of symbols is followed in transmission by a symbol having a second value. In one example, a false synchronization pattern includes a corrupted symbol having a second value, and the corrupted symbol may be followed in transmission by a sequence of symbols each having a first value. In some examples, the corrupted symbol is included in a POST pattern configured according to the C-PHY protocol. In some examples, the symbol comparators in the set of symbol comparators receive different sequences of parallel multi-symbol words.

[0092] In certain specific implementations, apparatus 1100 includes a demapper that may be configured to output a 16-bit data word mapped to seven symbols in a parallel multi-symbol word.

[0093] The processor-readable storage medium 1118 may include instructions that cause the processing circuitry 1102 to configure a shift register to convert a serial stream of 3-bit symbols into a parallel multi-symbol word that includes a plurality of symbols sorted according to the time of arrival at the input of the shift register; configure each symbol comparator in a set of symbol comparators to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; configure a synchronization detection circuit to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols; and inhibit the control signal when at least one symbol comparator in the set of symbol comparators indicates the presence of a false synchronization pattern of 3-bit symbols.

[0094] In some specific implementations, each symbol in a serial stream of 3-bit symbols represents a transition in the signaling state of a three-wire differential serial communication link. A synchronization pattern transmitted on the three-wire differential serial communication link may include a sequence of symbols each having a first value, and the sequence of symbols is followed in transmission by a symbol having a second value. In one example, a false synchronization pattern includes a corrupted symbol having a second value, and the corrupted symbol may be followed in transmission by a sequence of symbols each having a first value. In some examples, the corrupted symbol is included in a POST pattern configured according to the C-PHY protocol. In some examples, the symbol comparators in the set of symbol comparators receive different sequences of parallel multi-symbol words.

[0095] In certain specific implementations, the processor-readable storage medium 1118 includes code that causes the processing circuitry 1102 to output a 16-bit data word mapped to seven symbols in a parallel multi-symbol word. The processing circuitry 1102 may use the demapper to output the 16-bit data word.

[0096] Some specific implementation examples are described in the following numbered clauses:

[0097] 1. A communication interface circuit, the communication interface circuit comprising: a shift register configured to convert a serial stream of 3-bit symbols into a parallel multi-symbol word, the parallel multi-symbol word comprising a plurality of symbols sorted according to the time of arrival at the input of the shift register; a set of symbol comparators, each symbol comparator being configured to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; and

[0098] a synchronization detection circuit configured to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols, and the synchronization detection circuit is further configured to inhibit the control signal when at least one of the set of symbol comparators indicates the presence of the false synchronization pattern in the 3-bit symbols.

[0099] 2. The communication interface circuit according to clause 1, wherein each symbol in the serial stream of 3-bit symbols represents a transition in the signaling state of a three-wire differential serial communication link.

[0100] 3. The communication interface circuit according to clause 2, wherein the synchronization pattern transmitted on the three-wire differential serial communication link comprises a sequence of symbols each having a first value, the sequence of symbols being followed in transmission by a symbol having a second value.

[0101] 4. The communication interface circuit according to clause 3, wherein the false synchronization pattern comprises a corrupted symbol having the second value.

[0102] 5. The communication interface circuit according to clause 4, wherein the corrupted symbol is followed in transmission by a sequence of symbols each having the first value.

[0103] 6. The communication interface circuit according to any one of clauses 4 or 5, wherein the corrupted symbol is included in a POST pattern configured according to the C-PHY protocol.

[0104] 7. The communication interface circuit according to any one of clauses 1 to 6, wherein the symbol comparators in the set of symbol comparators receive different sequences of the parallel multi-symbol word.

[0105] 8. The communication interface circuit according to any one of clauses 1 to 7, the communication interface circuit further comprising: a demapper configured to output a 16-bit data word mapped to seven symbols in the parallel multi-symbol word.

[0106]

[0107] ​9. A method for operating a display or a camera in a mobile communication device, the method comprising configuring a shift register to convert a serial stream of 3-bit symbols into a parallel multi-symbol word, the parallel multi-symbol word including a plurality of symbols sorted according to the time of arrival at an input end of the shift register; configuring each symbol comparator in a set of symbol comparators to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols;

[0108] configuring a synchronization detection circuit to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols; and suppressing the control signal when at least one symbol comparator in the set of symbol comparators indicates the presence of the false synchronization pattern of 3-bit symbols.

[0109] 10. The method according to clause 9, wherein each symbol in the serial stream of 3-bit symbols represents a transition of a signaling state of a three-wire differential serial communication link.

[0110] 11. The method according to clause 10, wherein the synchronization pattern transmitted on the three-wire differential serial communication link includes a sequence of symbols each having a first value, the sequence of symbols being followed in transmission by a symbol having a second value.

[0111] 12. The method according to clause 11, wherein the false synchronization pattern includes a corrupted symbol having the second value.

[0112] 13. The method according to clause 12, wherein the corrupted symbol is followed in transmission by a sequence of symbols each having the first value.

[0113] 14. The method according to any one of clause 12 or clause 13, wherein the corrupted symbol is included in a POST mode configured according to the C-PHY protocol.

[0114] 15. The method according to any one of clauses 8 to 14, wherein the symbol comparators in the set of symbol comparators receive different subsets of the parallel multi-symbol word.

[0115] 16. The method according to any one of clauses 8 to 15, the method further comprising: using a demapper to output a 16-bit data word mapped to seven symbols in the parallel multi-symbol word.

[0116] 17. A device, the device comprising: means for converting a serial stream of 3-bit symbols into a parallel multi-symbol word, the parallel multi-symbol word comprising a plurality of symbols sorted according to the time of arrival at an input of the means for converting the serial stream of 3-bit symbols into the parallel multi-symbol word; means for comparing symbol sequences, the means for comparing symbol sequences comprising a set of symbol comparators, wherein each symbol comparator is configured to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; and means for detecting a synchronization pattern, the means for detecting a synchronization pattern being configured to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols, and the means for detecting a synchronization pattern is further configured to suppress the control signal when at least one symbol comparator in the set of symbol comparators indicates the presence of the false synchronization pattern in the 3-bit symbols.

[0117] 18. The device according to clause 17, wherein each symbol in the serial stream of 3-bit symbols represents a transition in the signaling state of a three-wire differential serial communication link.

[0118] 19. The device according to clause 18, wherein the synchronization pattern transmitted on the three-wire differential serial communication link comprises a sequence of symbols each having a first value, the sequence of symbols being followed in transmission by a symbol having a second value.

[0119] 20. The device according to clause 19, wherein the false synchronization pattern comprises a corrupted symbol having the second value, and the corrupted symbol is followed in transmission by a sequence of symbols each having the first value.

[0120] 21. The device according to clause 20, wherein the corrupted symbol is included in a POST pattern configured according to the C-PHY protocol.

[0121] 22. The device according to any one of clauses 17 to 21, wherein the symbol comparators in the set of symbol comparators receive different subsets of the parallel multi-symbol word.

[0122] 23. The device according to any one of clauses 17 to 22, the device further comprising: a demapping component configured to output a 16-bit data word mapped to seven symbols in the parallel multi-symbol word.

[0123] 24. A processor-readable storage medium, the processor-readable storage medium including code for: configuring a shift register to convert a serial stream of 3-bit symbols into a parallel multi-symbol word, the parallel multi-symbol word including a plurality of symbols sorted according to the time of arrival at an input of the shift register; configuring each symbol comparator in a set of symbol comparators to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; configuring a synchronization detection circuit to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols; and suppressing the control signal when at least one symbol comparator in the set of symbol comparators indicates the presence of the false synchronization pattern of 3-bit symbols.

[0124] 25. The storage medium according to clause 24, wherein each symbol in the serial stream of 3-bit symbols represents a transition in the signaling state of a three-wire differential serial communication link.

[0125] 26. The storage medium according to clause 25, wherein the synchronization pattern transmitted on the three-wire differential serial communication link includes a sequence of symbols each having a first value, the sequence of symbols being followed in transmission by a symbol having a second value.

[0126] 27. The storage medium according to clause 26, wherein the false synchronization pattern includes a corrupted symbol having the second value, and the corrupted symbol is followed in transmission by a sequence of symbols each having the first value.

[0127] 28. The storage medium according to clause 27, wherein the corrupted symbol is included in a POST pattern configured according to the C-PHY protocol.

[0128] 29. The storage medium according to any one of clauses 24 to 28, wherein the symbol comparators in the set of symbol comparators receive different subsets of the parallel multi-symbol word.

[0129] 30. The storage medium according to any one of clauses 24 to 29, the storage medium further including code for:

[0130] using a demapper to output a 16-bit data word mapped to seven symbols in the parallel multi-symbol word.

[0131] It should be understood that the specific order or hierarchy of steps in the disclosed processes is illustrative of exemplary methods. It should be understood that, according to design preferences, the specific order or hierarchy of steps in these processes may be rearranged. Additionally, some steps may be combined or omitted. The appended method claims present the elements of multiple steps in a sample order and are not meant to be limited to the specific order or hierarchy presented.

[0132] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein but are to be accorded the full scope consistent with the language of the claims, wherein elements recited in the singular are not intended to mean "one and only one" but rather "one or more" unless specifically stated otherwise. The term "some" is, unless specifically stated otherwise, meant one or more. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or later will be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed as a means-plus-function unless the element is expressly recited using the phrase "means for".

Claims

1. A communication interface circuit, the communication interface circuit comprising: a shift register configured to convert a serial stream of 3-bit symbols into a parallel multi-symbol word, the parallel multi-symbol word comprising a plurality of symbols sorted according to the time of arrival at the input of the shift register; a set of symbol comparators, each symbol comparator configured to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; and a synchronization detection circuit configured to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols, and the synchronization detection circuit is further configured to inhibit the control signal when at least one symbol comparator in the set of symbol comparators indicates the presence of the false synchronization pattern of 3-bit symbols.

2. The communication interface circuit according to claim 1, wherein each symbol in the serial stream of 3-bit symbols represents a transition of the signaling state of a three-wire differential serial communication link.

3. The communication interface circuit according to claim 2, wherein the synchronization pattern transmitted on the three-wire differential serial communication link comprises a sequence of symbols each having a first value, the sequence of symbols being followed in transmission by a symbol having a second value.

4. The communication interface circuit according to claim 3, wherein the false synchronization pattern comprises a corrupted symbol having the second value.

5. The communication interface circuit according to claim 4, wherein the corrupted symbol is followed in transmission by a sequence of symbols each having the first value.

6. The communication interface circuit according to claim 4, wherein the corrupted symbol is included in a POST pattern configured according to the C-PHY protocol.

7. The communication interface circuit according to claim 1, wherein the symbol comparators in the set of symbol comparators receive different sequences of the parallel multi-symbol word.

8. The communication interface circuit according to claim 1, the communication interface circuit further comprising: a demapper configured to output a 16-bit data word mapped to seven symbols in the parallel multi-symbol word.

9. A method for operating a display or a camera in a mobile communication device, the method comprising: configuring a shift register to convert a serial stream of 3-bit symbols into a parallel multi-symbol word, the parallel multi-symbol word comprising a plurality of symbols sorted according to the time of arrival at the input of the shift register; configuring each symbol comparator in a set of symbol comparators to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; configuring a synchronization detection circuit to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols; and inhibiting the control signal when at least one symbol comparator in the set of symbol comparators indicates the presence of the false synchronization pattern of 3-bit symbols.

10. The method according to claim 9, wherein each symbol in the serial stream of 3-bit symbols represents a transition of the signaling state of a three-wire differential serial communication link.

11. The method according to claim 10, wherein the synchronization pattern transmitted on the three-wire differential serial communication link includes a sequence of symbols each having a first value, the sequence of symbols being followed in transmission by a symbol having a second value.

12. The method according to claim 11, wherein the false synchronization pattern includes a corrupted symbol having the second value.

13. The method according to claim 12, wherein the corrupted symbol is followed in transmission by a sequence of symbols each having the first value.

14. The method according to claim 12, wherein the corrupted symbol is included in a POST pattern configured according to the C-PHY protocol.

15. The method according to claim 9, wherein the symbol comparators in the group of symbol comparators receive different subsets of the parallel multi-symbol word.

16. The method according to claim 9, the method further comprises: using a demapper to output a 16-bit data word mapped to seven symbols in the parallel multi-symbol word.

17. An apparatus, the apparatus comprises: means for converting a serial stream of 3-bit symbols into a parallel multi-symbol word, the parallel multi-symbol word including a plurality of symbols sorted according to the time of arrival at an input of the means for converting the serial stream of 3-bit symbols into the parallel multi-symbol word; means for comparing symbol sequences, the means for comparing symbol sequences including a group of symbol comparators, wherein each symbol comparator is configured to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; and means for detecting a synchronization pattern, the means for detecting a synchronization pattern being configured to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols, and the means for detecting a synchronization pattern being further configured to inhibit the control signal when at least one symbol comparator in the group of symbol comparators indicates the presence of the false synchronization pattern in the serial stream of 3-bit symbols.

18. The apparatus according to claim 17, wherein each symbol in the serial stream of 3-bit symbols represents a transition of the signaling state of a three-wire differential serial communication link.

19. The apparatus according to claim 18, wherein the synchronization pattern transmitted on the three-wire differential serial communication link includes a sequence of symbols each having a first value, the sequence of symbols being followed in transmission by a symbol having a second value.

20. The apparatus according to claim 19, wherein the false synchronization pattern includes a corrupted symbol having the second value, and the corrupted symbol is followed in transmission by a sequence of symbols each having the first value.

21. The apparatus according to claim 20, wherein the corrupted symbol is included in a POST pattern configured according to the C-PHY protocol.

22. The apparatus according to claim 17, wherein the symbol comparators in the group of symbol comparators receive different subsets of the parallel multi-symbol word.

23. The apparatus according to claim 17, the apparatus further comprises: A demapping component, the demapping component being configured to output a 16-bit data word mapped to seven symbols in the parallel multi-symbol word.

24. A processor-readable storage medium, the processor-readable storage medium including code configured to cause a processing circuit to perform the following operations: Configure a shift register to convert a serial stream of 3-bit symbols into a parallel multi-symbol word, the parallel multi-symbol word including a plurality of symbols sorted according to the time of arrival at the input end of the shift register; Configure each symbol comparator in a set of symbol comparators to determine whether a symbol pattern in the parallel multi-symbol word indicates the presence of a false synchronization pattern in the serial stream of 3-bit symbols; Configure a synchronization detection circuit to provide a control signal that is valid when a synchronization pattern is detected in the serial stream of 3-bit symbols; And Suppress the control signal when at least one symbol comparator in the set of symbol comparators indicates the presence of the false synchronization pattern of 3-bit symbols.

25. The processor-readable storage medium according to claim 24, wherein each symbol in the serial stream of 3-bit symbols represents a transition of the signaling state of a three-wire differential serial communication link.

26. The processor-readable storage medium according to claim 25, wherein the synchronization pattern transmitted on the three-wire differential serial communication link includes a sequence of symbols each having a first value, the sequence of symbols being followed in transmission by a symbol having a second value.

27. The processor-readable storage medium according to claim 26, wherein the false synchronization pattern includes a corrupted symbol having the second value, and the corrupted symbol is followed in transmission by a sequence of symbols each having the first value.

28. The processor-readable storage medium according to claim 27, wherein the corrupted symbol is included in a POST pattern configured according to the C-PHY protocol.

29. The processor-readable storage medium according to claim 24, wherein the symbol comparators in the set of symbol comparators receive different subsets of the parallel multi-symbol word.

30. The processor-readable storage medium according to claim 24, the processor-readable storage medium further including code configured to cause the processing circuit to perform the following operation: Use a demapper to output a 16-bit data word mapped to seven symbols in the parallel multi-symbol word.

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