Display panel, driving method thereof and display device

Abstract

The invention provides a display panel, a driving method thereof and a display device, which are applied to the technical field of display, and the display panel comprises a fault detection circuit which comprises at least one sensor module arranged in a display area and a detection module arranged in a non-display area and electrically coupled with the sensor module, the orthographic projection of the sensor module on the substrate is partially overlapped with the at least one first wire to form at least one coupling capacitor; the shift register unit is configured to send a gate driving signal through the first wire; the sensor module is configured to generate a corresponding coupling signal through a coupling capacitor based on a gate driving signal on the first wire; and the detection module is configured to perform anomaly detection on the shift register unit according to the coupling signal. According to the invention, the detection precision of the shift register unit is improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel, a driving method thereof, and a display device. Background Art

[0002] In liquid crystal display technology, the gate driver on array (GOA) technology effectively reduces the border width and manufacturing cost of a display module by directly integrating a gate driving circuit into a non-display area of an array substrate. This technology has been widely applied to Incell liquid crystal display panels (i.e., a structure where a touch sensor is integrated inside the display panel). The gate driving circuit is composed of cascaded shift register units, and each unit outputs a gate driving signal to a pixel circuit of a corresponding row through a gate line. However, characteristic offsets of transistors in the gate driving circuit (such as threshold voltage drift and abnormal load capacitance) can cause waveform distortion of the gate driving signal, thereby leading to local display abnormalities. Summary of the Invention

[0003] In view of this, an object of the present application is to provide a display panel, a driving method thereof, and a display device to solve or partially solve the above problems to a certain extent.

[0004] Based on the above object, the present application provides a display panel, including a display area and a non-display area surrounding the display area, and including:

[0005] A substrate;

[0006] A plurality of pixel units, disposed on the substrate and arranged in an array in the display area, and the pixel units include pixel circuits;

[0007] A gate driving circuit, disposed on the substrate and located in the non-display area, including a plurality of cascaded shift register units, and the plurality of shift register units are electrically coupled to a plurality of rows of the pixel circuits through a plurality of first traces, and are configured to provide gate driving signals to the plurality of rows of the pixel circuits;

[0008] A fault detection circuit, disposed on the substrate, including at least one sensor module disposed in the display area and a detection module disposed in the non-display area and electrically coupled to the sensor module, and a positive projection of the sensor module on the substrate overlaps at least a part of at least one of the first traces to form at least one coupling capacitance;

[0009] The shift register unit is configured to: send a gate driving signal through the first trace;

[0010] The sensor module is configured to generate a corresponding coupling signal through the coupling capacitor based on the gate driving signal on the first trace;

[0011] The detection module is configured to perform anomaly detection on the shift register unit according to the coupling signal.

[0012] Based on the same inventive concept, the present application further provides a display driving method, including:

[0013] The gate driving circuit sends a gate driving signal through the first trace;

[0014] The sensor module generates a corresponding coupling signal through the coupling capacitor based on the gate driving signal on the first trace;

[0015] The detection module performs anomaly detection on the shift register unit of the gate driving circuit according to the coupling signal.

[0016] Based on the same inventive concept, the present application further provides a display device including the above display panel.

[0017] As can be seen from the above, the display panel, its driving method, and the display device provided by the present application, wherein the display panel includes a display area and a non-display area surrounding the display area, and includes: a substrate; a plurality of pixel units disposed on the substrate and arranged in an array in the display area, the pixel units including pixel circuits; a gate driving circuit disposed on the substrate and located in the non-display area, including a plurality of cascaded shift register units, the plurality of shift register units being electrically coupled to multiple rows of the pixel circuits through multiple first traces for providing gate driving signals to the multiple rows of the pixel circuits; a fault detection circuit disposed on the substrate, including at least one sensor module disposed in the display area and a detection module disposed in the non-display area and electrically coupled to the sensor module, the sensor module having a positive projection on the substrate that partially overlaps at least one of the first traces to form at least one coupling capacitor; the shift register unit is configured to send a gate driving signal through the first trace; the sensor module is configured to generate a corresponding coupling signal through the coupling capacitor based on the gate driving signal on the first trace; the detection module is configured to perform anomaly detection on the shift register unit according to the coupling signal. The sensor module forms a coupling capacitor by partially overlapping with the first trace of the gate driving circuit, and can detect minute changes in the gate driving signal. The detection module processes the coupling signal to generate an anomaly detection signal, thereby determining whether there is an anomaly in the shift register unit corresponding to a certain row of traces, so the detection accuracy is significantly improved. Description of the Drawings

[0018] To more clearly illustrate the technical solutions in the present application or related technologies, the following will briefly introduce the drawings required for use in the embodiments or descriptions of related technologies. Obviously, the drawings in the following description are only embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1A Shows a schematic block diagram of a display device according to an embodiment of the present application.

[0020] Figure 1B Shows a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present application.

[0021] Figure 2A Shows a schematic block diagram of a display panel according to an embodiment of the present application.

[0022] Figure 2B Shows a partial circuit structure diagram of a display panel according to an embodiment of the present application.

[0023] Figure 2C Shows a top view structure diagram of a display panel provided by an embodiment of the present application.

[0024] Figure 2D Shows a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application.

[0025] Figure 3 Is a circuit schematic diagram of an exemplary detection module according to an embodiment of the present application.

[0026] Figure 4 Is an exemplary circuit diagram of a detection module according to an embodiment of the present application.

[0027] Figure 5 Is another exemplary circuit diagram of a detection module according to an embodiment of the present application.

[0028] In the figure, 1 is a substrate substrate, 100 is a display device, 102 is a gate driver, 104 is a timing controller, 106 is a data driver, 200 is a display panel, 240 is a display structure, 220 is a touch structure, 230 is a second trace, 2011 is a pixel circuit, 2021 is a shift register unit, 2201 is a first electrode, 2202 is a second electrode, 201 is a pixel unit, 201A is a gate line, 201B is a data line, 202 is a gate driving circuit, 203 is a first trace, 204 is a sensor module, 205 is a detection module, 206 is a coupling capacitor, 207 is an operational amplifier module, 208 is an analog-to-digital conversion module, 209 is a compensation module, 210 is a first switch, 211 is a second switch, 212 is a third switch, 213 is a tunable capacitor, 214 is a first tunable capacitor, 215 is a second tunable capacitor, 216 is an operational amplifier, 217 is a feedback capacitor, 218 is an analog-to-digital converter. Detailed implementation manners

[0029] To make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0030] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the ordinary meanings understood by those of ordinary skill in the art to which the present application belongs. The "first", "second" and similar terms used in the embodiments of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. The terms such as "comprising" or "including" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0031] Figure 1A A schematic block diagram of a display device according to an embodiment of the present application is shown.

[0032] As Figure 1AAs shown, the display device 100 includes a display panel 200, a gate driver 102, a timing controller 104, and a data driver 106. The display panel 200 includes a plurality of pixel units P defined by the intersection of a plurality of scan lines Scan and a plurality of data lines Data. The display panel 200 can be, for example, the display panel provided in any embodiment of the present application. The gate driver 102 is used to drive a plurality of scan lines GL; the data driver 106 is used to drive a plurality of data lines DL; the timing controller 104 is used to process the image data RGB input from outside the display device 100, provide the processed image data RGB to the data driver 106, and output a scan control signal GCS and a data control signal DCS to the gate driver 102 and the data driver 106 to control the gate driver 102 and the data driver 106.

[0033] For example, the gate driver 102 can be implemented as a semiconductor chip or integrated in the display panel 200 to form a gate driver on array (GOA) circuit.

[0034] For example, the data driver 106 converts the digital image data RGB input from the timing controller 104 into a data signal according to a plurality of data control signals DCS from the timing controller 104 using a reference gamma voltage. The data driver 106 provides the converted data signal to a plurality of data lines DL. For example, the data driver 106 can be implemented as a semiconductor chip.

[0035] For example, the timing controller 104 processes the externally input image data RGB to match the size and resolution of the display panel 200, and then provides the processed image data to the data driver 106. The timing controller 104 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using the synchronization signals (such as dot clock DCLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) input from outside the display device 100. The timing controller 104 respectively provides the generated scan control signal GCS and data control signal DCS to the gate driver 102 and the data driver 106 for controlling the gate driver 102 and the data driver 106. The display device 100 may further include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components can be, for example, existing conventional components and will not be described in detail here. The display device 100 can be applied to any product or component with a display function, such as an e-book, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0036] In some embodiments, the display panel 200 may further have a touch function, that is, the display panel 200 can be a touch display panel.

[0037] As Figure 1B shown, optionally, the display panel 200 may further include a display structure 240 and a touch structure 220. The display structure 240 is used to implement the display function, and the touch structure 220 is used to implement the touch function.

[0038] When the display panel 200 is implemented as an external touch display screen, the touch structure 220 can be separately manufactured and then assembled with the display structure 240 into one body, so that the touch structure 220 and the display structure 240 can be separately manufactured, which can improve the manufacturing efficiency.

[0039] In some embodiments, the display panel 200 can also be implemented as a display panel in which after the display structure 240 is manufactured, the surface is flattened and then the touch structure 220 is continuously manufactured on the display structure 240 (that is, the touch structure integrated inside the display panel 200, Incell structure), so that the thickness of the display panel 200 can be reduced.

[0040] As Figure 1B shown, optionally, the touch structure 220 may further include a first electrode 2201 and a second electrode 2202. Among them, the first electrode 2201 can be implemented as a sensing electrode or a receiving electrode (Rx), and the second electrode 2202 can be implemented as a driving electrode or a transmitting electrode (Tx). In this way, the second electrode 2202 receives a driving signal. When a touch operation occurs on the display panel 200, the corresponding first electrode 2201 can sense the corresponding signal, and then determine the touch position according to the sensed signal.

[0041] It can be understood that in addition to being implemented as the above mutual capacitance touch structure, the touch structure 220 can also be implemented as a self-capacitance touch structure, so that it can include only one layer of touch electrodes arranged in an array to implement touch detection.

[0042] Figure 2A A schematic block diagram of a display panel provided in some embodiments of the present application.

[0043] As Figure 2A shown, in some embodiments, the display panel 200 may include a plurality of pixel units 201 (that is, Figure 1A the pixel unit P) and a gate driving circuit 202. Among them, the plurality of pixel units 201, for example, can be arranged in an array. Each pixel unit 201 may further include a pixel circuit 2011.

[0044] To reduce the bezel of the display device 100, the gate driver on array (GOA) technology effectively reduces the bezel width and manufacturing cost of the display module by directly integrating the gate driving circuit into the non-display area of the array substrate. Therefore, as Figure 2A shown, the gate driving circuit 202 (which can be implemented as Figure 1A the gate driver 102) may include a plurality of cascaded shift register units 2021, and each shift register unit 2021 can be used to provide a gate driving signal for the pixel circuit of the corresponding row.

[0045] For example, the display panel 200 can be a liquid crystal display (LCD) panel, an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, or other applicable display panels. Each pixel unit 201 not only includes a pixel circuit 2011, but may also include a light-emitting element (such as an OLED, a QLED, etc.).

[0046] For example, the display panel 200 can be a rectangular panel, a circular panel, an oval panel, or a polygonal panel, etc. In addition, the display panel 200 can be not only a flat panel, but also a curved panel, or even a spherical panel, etc. For example, the display panel 200 can be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc. For example, the display panel 200 can be a flexible display panel, so as to meet various actual application requirements. For example, the display panel 200 can be applied to a curved screen, etc.

[0047] For clarity and conciseness, the embodiments of the present application do not show all the constituent units of the display panel 200. To implement the basic functions of the display panel 200, those skilled in the art can provide and set other structures not shown according to specific needs, and the embodiments of the present application do not limit this.

[0048] Figure 2B shows a partial circuit structure diagram of the display panel 200 provided by some embodiments of the present application.

[0049] Combined with Figure 2A and Figure 2B shown, the display panel 200 includes pixel units 201 and a gate driving circuit 202 arranged in an array. In the display panel 200, a plurality of gate lines 201A (i.e., Figure 1A the scan lines GL) extend along the first direction X and are arranged at intervals along the second direction Y, and a plurality of data lines 201B (i.e., Figure 1AThe data lines DL extend along the second direction Y and are arranged at intervals along the first direction X. Moreover, a plurality of gate lines 201A and a plurality of data lines 201B intersect to define a plurality of pixel units 201 and their pixel circuits 2011.

[0050] Exemplarily, taking a liquid crystal display panel as an example, as Figure 2B shown, the pixel circuit used in the display panel 200 can be a 1T1C pixel circuit, that is, using one thin-film transistor (abbreviated as TFT) and one storage capacitor Cs to realize the basic function of driving the light-emitting device OLED to emit light. As Figure 2B shown, in a 1T1C pixel circuit, a switching transistor T0 and a storage capacitor Cs can be included. For example, the gate of the switching transistor T0 is connected to the gate line 201A (i.e., Figure 1A the scan line GL) to receive the scan signal Scan1, the first pole of the switching transistor T0 is connected to the data line 201B (i.e., the data line DL in FIG. 1) to receive the data signal Vdata, the second pole of the switching transistor T0 is connected to the pixel electrode ( Figure 2B not shown in the figure) and the first pole of the storage capacitor Cs, and the second pole of the storage capacitor Cs is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).

[0051] The driving method of this 1T1C pixel circuit is to control the brightness (gray scale) of the pixel via one TFT and the storage capacitor Cs. When the scan signal Scanl is applied through the gate line 201A to turn on the switching transistor T0, the data signal Vdata sent by the data driving circuit through the data line 201B will charge the storage capacitor Cs via the switching transistor T0, thereby storing the data signal Vdata in the storage capacitor Cs, and the stored data signal Vdata controls the gray scale voltage on the pixel electrode, thereby controlling the deflection angle of the liquid crystal molecules to determine the gray scale of the pixel. In Figure 2B the 1T1C pixel circuit shown, the switching transistor T0 can be an N-type transistor and the driving transistor N0 can be a P-type transistor. Accordingly, the polarity of the scan signal Scanl for controlling its conduction or cutoff can be changed.

[0052] It should be understood that the above embodiments are described with the display panel 200 being a liquid crystal display panel. In fact, other types of display panels (for example, OLED) also set pixel circuits as needed to realize the lighting and gray scale control of pixel units, and these display panels also fall within the protection scope of this application.

[0053] Return to Figure 2B, the shift register unit 2021 of the gate driving circuit 202 can correspond to the pixel circuit 2011 of the nth row (n is greater than or equal to 2), and can further include a transistor T1, a transistor T2, a transistor T3, a transistor T4, and a storage capacitor C1.

[0054] The transistor T1 in the shift register unit 2021 is the output transistor of the signal output end of the shift register unit. For example, the first pole of the transistor T1 is connected to the first clock signal CLK1, and the second pole of the transistor T1 is connected to the first pole of the transistor T2 to obtain the output end of the shift register unit, and can output the gate driving signal Gn for the pixel circuit 2011 of the nth row (this signal is a square wave pulse signal, and correspondingly, the pulse part is the on level and the non - pulse part is the off level), and the input signal for the next - stage shift register unit (for example, the shift register unit corresponding to the pixel unit of the n + 1th row). As Figure 2B shown, the gate driving signal Gn can provide the scanning signal Scan1 for the pixel circuit 2011. The gate of the transistor T1 is connected to the pull - up node PU, and thus connected to the first pole of the transistor T3 and the second pole of the transistor T4.

[0055] The second pole of the transistor T2 is connected to the second pole of the transistor T3 and the low - level signal VGL. The gate of the transistor T2 is connected to the gate of the transistor T3 and the output end of the shift register unit of the next row (i.e., the n + 1th row) to receive the output of the gate driving signal G(n + 1) as the pull - down control signal. The first pole of the transistor T2 is connected to the second pole of the transistor T1, so it can be turned on under the control of the pull - down control signal, and pull down the output signal of the output end to the low - level signal VGL when the gate driving signal Gn does not need to be output.

[0056] The first pole of the transistor T3 is also connected to the pull - up node PU, and thus electrically connected to the second pole of the transistor T4 and the gate of the transistor T1. The second pole of the transistor T3 is connected to the low - level signal VGL. The gate of the transistor T3 is also connected to the output end of the shift register unit of the next row, i.e., the n + 1th row, to receive the gate driving signal G(n + 1) as the reset control signal (i.e., the pull - down control signal), so that it can be turned on under the control of this reset control signal, reset the pull - up node PU to the low - level signal VGL, and thus turn off the transistor T1.

[0057] The first pole of transistor T4 is connected to its own gate and is connected to the output terminal of the shift register unit in the previous row (i.e., the (n - 1)-th row) to receive the gate driving signal G(n - 1) as the input signal (and the input control signal). The second pole of transistor T4 is connected to the pull-up node PU, so that when transistor T4 is turned on, the pull-up node PU can be charged, and the voltage of the pull-up node PU can turn on transistor T1, so that the first clock signal CLK1 is output through the output terminal. One end of the storage capacitor C1 is connected to the gate of transistor T1, i.e., the pull-up node PU, and the other end is connected to the second pole of transistor T1, so that the level of the pull-up node PU can be stored, and when transistor T1 is turned on for output, the level of the pull-up node PU can be further pulled up through its own bootstrap effect to improve the output performance.

[0058] When the shift register unit 2021 works, when the gate driving signal G(n - 1) is at a high level, transistor T4 is turned on and charges the pull-up node PU. The increased level of the pull-up node PU turns on transistor T1. Therefore, the first clock signal CLK1 can be output through transistor T1 at the output terminal, that is, the gate driving signal Gn is equal to the first clock signal CLK1. When the first clock signal CLK1 is at a high level, the gate driving signal Gn also outputs a high level. When the gate driving signal Gn is at a high level, the shift register unit 2021 inputs the high-level signal Gn to the gate line 201A of the corresponding row of the display panel 200, so that the gates of all the switching transistors T0 in all the pixel circuits 2011 corresponding to this row of gate lines 201A are applied with this signal (for example, the scan signal Scan1), so that these switching transistors T0 are all turned on, and the data signal Vdata is input to the storage capacitor Cs of the corresponding pixel circuit 2011 through the switching transistor T0 in each pixel circuit to charge the storage capacitor Cs in the corresponding pixel circuit 2011, thereby realizing the writing and holding of the signal voltage of this pixel circuit 2011. When the gate driving signal G(n + 1) is at a high level, transistors T2 and T3 are turned on, achieving the effect of resetting the pull-up node PU and pulling down the output terminal.

[0059] According to the above principle, the (n - 1)-th row shift register unit, the (n + 1)-th row shift register unit of the gate driving circuit 202, and other cascaded shift register units can all output the gate driving signal in sequence to drive the pixel circuits of the corresponding rows. Therefore, through the multiple cascaded shift register units in the gate driving circuit 202, the function of driving the display panel 200 by progressive scanning can be realized.

[0060] Since the source and drain of each of the above transistors are symmetric, the source and drain can be interchanged. The first pole can be, for example, the source or the drain, and the second pole can be, for example, the drain or the source. In this application, the source and drain of the thin-film transistor are collectively referred to as the "source-drain", and are distinguished as the first source-drain and the second source-drain. For example, each of the above transistors can be an N-type transistor. Of course, each of the above transistors is not limited to an N-type transistor, and can also be at least partially a P-type transistor. Accordingly, the corresponding turn-on signal STV and the polarity of the output scan signal can be changed accordingly.

[0061] It should be noted that in the embodiments of this application, the structure of the shift register unit of the gate driving circuit 202 is not limited to the structure described above. The shift register unit of the gate driving circuit 202 can be any applicable structure, and can also include more or fewer transistors and / or capacitors. For example, sub-circuits for implementing functions such as pull-up node control, pull-down node control, and noise reduction can be added. The embodiments of this application do not limit this.

[0062] As described above, the gate driving circuit is composed of cascaded shift register units, and each shift register unit outputs a gate driving signal to the pixel circuit of the corresponding row through a gate line. However, as Figure 2B shown, the shift register unit 2021 of the gate driving circuit 202 includes multiple transistors (for example, transistors T1 to T4), and the characteristic offset of the transistors (such as threshold voltage drift and abnormal load capacitance) will cause the waveform of the gate driving signal of the corresponding shift register unit to be distorted, thereby causing local display abnormalities of the display panel 200.

[0063] In order to detect faults in the gate driving circuit, in the related art, fault judgment can be made by monitoring the waveform characteristics of the end output signal of the gate driving circuit (the gate driving signal output by the last-stage shift register unit). The specific implementation method is to feedback the output signal of the gate line connected to the end shift register unit to the driving unit (for example, the driving IC), and the driving unit determines whether there is a fault in the gate driving circuit by comparing the voltage, timing, or waveform slope of the output signal with a preset value.

[0064] The inventors of the present application have found that the above solution has the following key problems: The transistor characteristics offset of the intermediate unit (i.e., the non-terminal shift register unit) of the gate driving circuit will cause the distortion of the output signal waveform (such as abnormal rise / fall edge slope, amplitude attenuation). Such distorted signals may be compensated by subsequent circuits or masked by noise when transmitted to the terminal, resulting in the driving unit (e.g., driving IC) being unable to identify the faults of the intermediate unit through the terminal feedback signal, and there is no effective detection means for partial distortion and failure of the intermediate unit. When local display anomalies (such as horizontal lines, afterimages) are caused by the faults of the intermediate unit, the prior art needs to wait for the faults to spread to the terminal to trigger an alarm, resulting in a delay in the maintenance response. Especially in scenarios with strict reliability requirements such as outdoor advertising screens and in-vehicle displays, such lag may cause customer complaints or even safety accidents. In addition, this solution relies on the global characteristics of the terminal signal (such as overall timing offset) and cannot achieve fine-grained detection at the line-by-line level, resulting in insufficient detection sensitivity.

[0065] Based on the above problems, an embodiment of the present application provides a display panel, including a display area and a non-display area surrounding the display area, and including: a substrate; a plurality of pixel units disposed on the substrate and arranged in an array in the display area, the pixel units including pixel circuits; a gate driving circuit disposed on the substrate and located in the non-display area, including a plurality of cascaded shift register units, the plurality of shift register units being electrically coupled to multiple rows of the pixel circuits through a plurality of first traces for providing gate driving signals to the multiple rows of the pixel circuits; a fault detection circuit disposed on the substrate, including at least one sensor module disposed in the display area and a detection module disposed in the non-display area and electrically coupled to the sensor module, a positive projection of the sensor module on the substrate overlapping at least a part of at least one of the first traces to form at least one coupling capacitor; the shift register unit is configured to: send a gate driving signal through the first trace; the sensor module is configured to: generate a corresponding coupling signal based on the gate driving signal on the first trace through the coupling capacitor; the detection module is configured to: perform anomaly detection on the shift register unit according to the coupling signal. The sensor module generates a corresponding coupling signal based on the gate driving signal on the first trace through the coupling capacitor, and the detection module can detect the anomaly of the shift register unit according to the coupling signal, solving the problem in the prior art that the faults of the shift register unit cannot be comprehensively detected, improving the detection accuracy of the shift register unit, and thus improving the reliability and stability of the display panel.

[0066] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0067] Figure 2CThe top view structural schematic diagram of the display panel provided by the embodiment of the present application is shown. Figure 2D The sectional view of the display panel provided by the embodiment of the present application along Figure 2C the CC direction is shown.

[0068] In some embodiments, the display panel 200, as Figure 2C , Figure 2D shown, includes a display area AA and a non-display area BB surrounding the display area AA, and includes:

[0069] Substrate 1.

[0070] A plurality of pixel units (for example, Figure 1A pixel unit P, Figure 2B pixel unit 201), are arranged on the substrate 1 and are arrayed in the display area AA. The pixel unit may further include a pixel circuit (for example, Figure 2B pixel circuit 2011).

[0071] Gate driving circuit 202 is arranged on the substrate 1 and is located in the non-display area BB, and may include a plurality of cascaded shift register units 2021. Optionally, the gate driving circuit 202 may be arranged on both sides of the display panel 200, so as to provide gate driving signals for the pixel units from both sides of the display panel 200 to ensure the full turn-on of the switching transistors. Optionally, as Figure 2C shown, the plurality of shift register units are electrically coupled to multiple rows of the pixel circuits through a plurality of first traces 203 (for example, Figure 1A scan line GL, Figure 2B gate line 201A) to provide gate driving signals for the multiple rows of the pixel circuits (for example, each shift register unit can provide gate driving signals for each row of pixel circuits one by one).

[0072] Fault detection circuit is arranged on the substrate 1, and includes at least one sensor module 204 arranged in the display area and a detection module 205 arranged in the non-display area and electrically coupled to the sensor module 204. Optionally, as Figure 2C shown, the sensor module 204 can be electrically coupled to the detection module 205 through a second trace 230, so as to transmit the signal of the sensor module 204 located in the display area AA to the detection module 205 located in the non-display area BB by using the second trace 230. Optionally, the orthographic projection of the sensor module 204 on the substrate 1 overlaps with at least one of the first traces 203 to form at least one coupling capacitor 206, as Figure 2D shown.

[0073] The shift register unit 2021 is configured to: send a gate driving signal through the first trace 203;

[0074] The sensor module 204 is configured to: generate a corresponding coupling signal through the coupling capacitor 206 based on the gate driving signal on the first trace 203;

[0075] The detection module 205 is configured to: perform anomaly detection on the shift register unit 2021 according to the coupling signal.

[0076] Specifically, the substrate 1 is the basic structure of the display panel, providing physical support for the pixel units, the gate driving circuit 202, and the fault detection circuit, and ensuring the structural stability of the entire display panel. The pixel unit is the basic display unit of the display panel, usually including pixels of three colors: red, green, and blue, to achieve full-color display. Each pixel unit contains a pixel circuit, which is usually composed of thin-film transistors (TFTs), storage capacitors, and other passive components, and is used to control the brightness and switching state of the pixel unit. The gate driving circuit 202 (GOA circuit) is responsible for sending gate driving signals to the pixel circuits to control the switching state of the pixel units. The gate driving circuit 202 includes a plurality of cascaded shift register units, and each shift register unit is electrically coupled to the corresponding pixel circuit through the first trace 203. The gate driving signals are scanned row by row through these traces to ensure that each pixel unit is activated or turned off at the correct time. The fault detection circuit includes a sensor module 204 and a detection module 205. The sensor module 204 is disposed in the display area and partially overlaps with the first trace 203 of the gate driving circuit 202 to form a coupling capacitor 206. The sensor module 204 usually includes a sensor block. When the gate driving signal passes through the first trace 203, that is, when the level of the gate driving signal jumps, the sensor module 204 will detect the corresponding change in the electrical signal and generate a coupling signal. This coupling signal reflects the state of the gate driving signal, including the amplitude, edge slope, and stability of the signal. The detection module 205 is disposed in the non-display area and is electrically coupled to the sensor module 204. The detection module 205 processes the coupling signal to generate an abnormality detection signal, so as to determine whether there is an abnormality in the shift register unit corresponding to a certain row of traces, and thus the detection accuracy is significantly improved. Optionally, the detection module 205 may further include an operational amplifier module 207 and an analog-to-digital conversion module 208. When the operational amplifier module 207 receives the coupling signal, it generates a characteristic signal corresponding to the coupling signal and sends the characteristic signal to the analog-to-digital conversion module 208 through the output terminal. The analog-to-digital conversion module 208 generates an abnormality detection signal corresponding to the characteristic signal based on the characteristic signal. The detection module 205 calculates the difference between the abnormality detection value corresponding to the abnormality detection signal and a preset detection value, and determines whether there is an abnormality in the corresponding shift register unit according to the difference.

[0077] The sensor module 204 forms a coupling capacitor 206 by partially overlapping with the first trace 203 of the gate driving circuit 202, and can detect minute changes in the gate driving signal. The detection module 205 amplifies and processes the coupled signal through the operational amplifier module 207 and the analog-to-digital conversion module 208 to generate a characteristic signal and an anomaly detection signal. The row-by-row detection method can capture detailed information such as the amplitude, edge slope, and stability of the gate driving signal, thereby accurately determining whether there is an anomaly in the shift register unit corresponding to a certain row of traces, rather than just the anomaly in the last shift register unit. Therefore, the detection accuracy is significantly improved.

[0078] In some embodiments, the detection module 205 is configured to: generate a corresponding anomaly detection signal according to the coupled signal, and determine that the shift register unit is abnormal when the difference between the anomaly detection value corresponding to the anomaly detection signal and the preset detection value is greater than or equal to the anomaly detection threshold.

[0079] Specifically, the sensor module 204 forms a coupling capacitor 206 by partially overlapping with the first trace 203 of the gate driving circuit 202. When the gate driving signal passes through the first trace 203, the sensor module 204 detects the corresponding change in the electrical signal through the coupling capacitor 206 and generates a coupled signal. The detection module 205 receives the coupled signal generated by the sensor module 204 and generates a corresponding anomaly detection signal. The anomaly detection signal reflects the state of the gate driving signal, including the amplitude, edge slope, and stability of the signal. The detection module 205 calculates the difference between the anomaly detection value corresponding to the anomaly detection signal and the preset detection value (the preset detection value is the reference value corresponding to the anomaly detection signal under normal operating conditions. The preset detection value reflects the typical characteristics of the gate driving signal without faults). If the difference is greater than or equal to the anomaly detection threshold (the setting of the anomaly detection threshold needs to comprehensively consider the normal fluctuation range of the signal and the sensitivity of the fault. Exemplarily, the anomaly detection threshold can be set to 80), it is determined that the corresponding shift register unit is abnormal. In this way, using the difference comparison to judge whether the shift register unit has an anomaly can realize anomaly detection with a relatively simple structure and reduce the manufacturing cost.

[0080] In some embodiments, as Figure 2C shown, the fault detection circuit may include a plurality of sensor modules 204 arranged in an array. The plurality of sensor modules 204 can be arranged at equal intervals in the first direction X and the second direction Y in the entire display area AA, so as to realize the fault detection of the shift register units 2021 on the entire display panel 200.

[0081] Optionally, as Figure 2C shown, one shift register unit 2021 (for example, Figure 2CThe first shift register unit 2021 in the top-to-bottom order of the left-side gate driving circuit 202 is connected to a first trace 203 (for example, Figure 2C the first first trace 203 in the top-to-bottom order) extends along a first direction, and a plurality of first sensor modules arranged in the X order of the first direction among the plurality of sensor modules 204 (for example, Figure 2C the first row of sensor modules 204 in the top-to-bottom order) are orthogonally projected on the substrate 1 and all overlap with the first trace 203 to form a plurality of coupling capacitors 206 (as Figure 2C shown, there are 4 coupling capacitors, and this quantity is only illustrative);

[0082] The detection module 205 is configured to: generate corresponding plurality of abnormal detection signals according to the plurality of coupling signals generated by the plurality of coupling capacitors 206. When the difference between the abnormal detection value corresponding to at least one of the plurality of abnormal detection signals and a preset detection value is greater than or equal to an abnormal detection threshold, it can be determined that there is an abnormality in the shift register unit corresponding to the first trace.

[0083] In this way, using a plurality of sensor modules 204 to form a plurality of coupling capacitors with the first trace 203 can improve the detection accuracy.

[0084] It can be understood that setting the determination condition as the difference between the abnormal detection value corresponding to at least one of the plurality of abnormal detection signals and a preset detection value being greater than or equal to an abnormal detection threshold can ensure the detection accuracy. However, according to different actual requirements, the standard can be set as, for example, the difference between the abnormal detection values corresponding to two (or more) of the plurality of abnormal detection signals and a preset detection value being greater than or equal to an abnormal detection threshold, then it is determined that there is an abnormality in the shift register unit corresponding to the first trace. These embodiments all fall within the protection scope of the present application.

[0085] In some embodiments, the abnormal detection values corresponding to the plurality of abnormal detection signals can also be compared, and the abnormal detection signal with the largest abnormal degree among them is used as the value of the final abnormal detection signal for subtraction operation with a preset detection value, and then based on the difference, it is determined whether there is an abnormality in the corresponding shift register unit, so as to further improve the detection accuracy.

[0086] In other embodiments, as Figure 2C shown, at least two of the shift register units (for example, Figure 2C the first to fourth shift register units 2021 in the top-to-bottom order of the left-side gate driving circuit 202) are connected to at least two of the first traces (for example, Figure 2CThe first to fourth first wirings 203 in the order from top to bottom extend along the first direction X. Orthographic projections of multiple first sensor modules arranged in sequence along the first direction among the multiple sensor modules on the substrate substrate all partially overlap at least two of the first wirings to form multiple coupling capacitors. In this way, multiple sensor modules in the same row can implement fault detection for multiple shift register units, thereby reducing the number of sensor modules and lowering the manufacturing cost.

[0087] In some embodiments, as Figure 3 shown, the detection module 205 includes: an operational amplifier module 207 and an analog-to-digital conversion module 208. Among them, the inverting input terminal of the operational amplifier module 207 is electrically coupled to the sensor module 204, and the output terminal of the operational amplifier module 207 is electrically coupled to the input terminal of the analog-to-digital conversion module 208;

[0088] The operational amplifier module 207 is configured to: in response to receiving the coupling signal, generate a characteristic signal corresponding to the coupling signal, and send the characteristic signal to the analog-to-digital conversion module 208 through the output terminal;

[0089] The analog-to-digital conversion module 208 is configured to: based on the characteristic signal, generate an anomaly detection signal corresponding to the characteristic signal.

[0090] Specifically, the operational amplifier module 207 amplifies and processes the coupling signal detected by the sensor module 204 so that the subsequent analog-to-digital conversion module 208 can perform signal conversion more accurately. The inverting input terminal of the operational amplifier module 207 is electrically coupled to the sensor module 204 (the non-inverting input terminal is electrically coupled to the reference voltage terminal VREF for accessing the reference voltage), receives the coupling signal generated by the sensor module 204, and the operational amplifier module 207 amplifies the input coupling signal to improve the amplitude and stability of the signal. The operational amplifier module 207 generates a characteristic signal according to the amplified coupling signal, and this characteristic signal reflects the state of the gate drive signal. The analog-to-digital conversion module 208 is used to convert the analog characteristic signal generated by the operational amplifier module 207 into a digital signal for further processing and judgment. The input terminal of the analog-to-digital conversion module 208 is electrically coupled to the output terminal of the operational amplifier module 207, receives the characteristic signal generated by the operational amplifier module 207, and converts the characteristic signal into a digital signal (i.e., the anomaly detection signal) through steps such as sampling, quantization, and encoding. This signal is used to determine whether there is an anomaly in the shift register unit of the gate drive circuit 202.

[0091] The operational amplifier module 207 amplifies and processes the coupled signal of the sensor module 204, enhancing the amplitude and stability of the signal. The analog-to-digital conversion module 208 converts the analog signal into a digital signal, ensuring the accuracy and reliability of the signal. This collaborative work improves the sensitivity and accuracy of the detection, enabling more precise detection of abnormalities in the shift register unit.

[0092] In some embodiments, as Figure 3 shown, the detection module 205 further includes: a compensation module 209, a first end of the compensation module 209 is electrically coupled to the coupling capacitor 206, a second end of the compensation module 209 is electrically coupled to a compensation signal terminal P0, and is configured to: compensate the coupling capacitor 206 under the control of a compensation signal accessed at the compensation signal terminal P0.

[0093] Specifically, the coupling capacitor 206 is a parasitic capacitance between the sensor module 204 and the first trace 203 of the gate driving circuit 202. Its capacitance value may change due to environmental factors (such as temperature, humidity) or differences in the manufacturing process of the sensor module 204, thereby affecting the consistency of the coupled signal. The compensation module 209 may include an adjustable capacitor 213 or other compensation elements, and these elements can adjust their capacitance values according to the instructions of the compensation signal. The compensation module 209 accesses the compensation signal through the compensation signal terminal P0, and the compensation signal is used to control the compensation module 209 to compensate the coupling capacitor 206 to adapt to the change of the coupling capacitor 206, eliminate the consistency problem of the coupling capacitor 206, and thus ensure the stability and accuracy of the abnormal detection signal.

[0094] Through the compensation of the coupling capacitor 206 by the compensation module 209, it is possible to avoid problems such as differences in the manufacturing process of the sensor module 204 from affecting the consistency of the coupled signal, thereby ensuring that the coupled signal received by the detection module 205 more accurately reflects the state of the gate driving signal, and thus improving the sensitivity and accuracy of the detection of the shift register unit.

[0095] In some embodiments, as Figure 4 shown, the detection module 205 further includes: a first switch 210, a second switch 211, and a third switch 212. A first end of the first switch 210 is electrically coupled to the coupling capacitor 206, a second end of the first switch 210 is grounded, the second switch 211 is connected between the coupling capacitor 206 and the inverting input terminal of the operational amplifier module 207, a first end of the third switch 212 is electrically coupled to the inverting input terminal of the operational amplifier module 207, and a second end of the third switch 212 is electrically coupled to the output terminal of the operational amplifier module 207; the detection module 205 is configured to:

[0096] At a first moment, control the second switch 211 to open, and control the first switch 210 and the third switch 212 to close, so as to initialize the coupling capacitor 206 and the operational amplifier module 207;

[0097] At a second moment, control the first switch 210 and the third switch 212 to open, and control the second switch 211 to close, so that the compensation module 209 compensates the coupling capacitor 206;

[0098] At a third moment, control the first switch 210 and the third switch 212 to open, and control the second switch 211 to close, so that the operational amplifier module 207 generates a corresponding characteristic signal according to the coupling signal;

[0099] At a fourth moment, control the first switch 210, the second switch 211 and the third switch 212 to open, so that the analog-to-digital conversion module 208 generates a corresponding anomaly detection signal based on the characteristic signal;

[0100] At a fifth moment, control the first switch 210 to close, so as to discharge the coupling capacitor 206.

[0101] Specifically, the first end of the first switch 210 is electrically coupled to the sensor module 204. Since the coupling capacitor 206 is the parasitic capacitance between the sensor module 204 and the first trace 203 of the gate drive circuit 202, the first end of the first switch 210 is equivalent to being electrically coupled to the coupling capacitor 206, and the second end of the first switch 210 is grounded; the second switch 211 is connected between the coupling capacitor 206 and the inverting input terminal of the operational amplifier module 207 (i.e., the second switch 211 is connected between the sensor module 204 and the inverting input terminal of the operational amplifier module 207). The first end of the third switch 212 is electrically coupled to the inverting input terminal of the operational amplifier module 207, and the second end is electrically coupled to the output terminal of the operational amplifier module 207. During the initialization phase (the first moment), the detection module 205 controls the second switch 211 to open, controls the first switch 210 to close, releases the residual charge on the coupling capacitor 206 to the ground, realizes the initialization of the coupling capacitor 206, avoids the influence on the coupling signal, controls the third switch 212 to close, shorts the inverting input terminal and the output terminal of the operational amplifier module 207, and consumes the residual charge to ensure that the operational amplifier module 207 is in a known initial state. During the compensation phase (the second moment), the detection module 205 controls the first switch 210 and the third switch 212 to open, controls the second switch 211 to close, connects the compensation module 209 to the circuit, and compensates the coupling capacitor 206 to offset the influence of the characteristic change of the coupling capacitor 206 on the detection signal. During the signal processing phase (the third moment), the detection module 205 controls the first switch 210 and the third switch 212 to remain open, maintains the current states of the coupling capacitor 206 and the operational amplifier module 207, controls the second switch 211 to close, enables the operational amplifier module 207 to receive the coupling signal, generates a corresponding characteristic signal according to the signal, and the operational amplifier module 207 amplifies and processes the coupling signal to generate a characteristic signal, preparing for the subsequent analog-to-digital conversion. During the analog-to-digital conversion phase (the fourth moment), the detection module 205 controls the first switch 210, the second switch 211, and the third switch 212 to all open, blocks all signal paths, enables the analog-to-digital conversion module 208 to stably receive and process the characteristic signal, and the analog-to-digital conversion module 208 generates a corresponding anomaly detection signal based on the characteristic signal, completing the conversion from the analog signal to the digital signal and providing a basis for the subsequent anomaly judgment. During the discharging phase (the fifth moment), the detection module 205 controls the first switch 210 to close, releases the charge on the coupling capacitor 206 to the ground, and completes the discharging of the coupling capacitor 206; during the result output phase (the sixth moment), the analog-to-digital conversion module 208 outputs the anomaly detection signal.

[0102] By precisely controlling the disconnection of the second switch 211 and controlling the closure of the first switch 210 and the third switch 212, the coupling capacitor 206 and the operational amplifier module 207 are initialized, eliminating the interference of residual charges and signals, ensuring that the coupling capacitor 206 and the operational amplifier module 207 can be in the best working state at each stage, thereby improving the accuracy and reliability of the detection signal. By precisely controlling the orderly closing and disconnection of the switch at each stage, the efficiency of the detection process is ensured, and the detection of the shift register unit can be completed orderly in a relatively short time.

[0103] In some embodiments, as Figure 4 shown, the compensation module 209 includes a tunable capacitor 213. The first end of the tunable capacitor 213 is electrically coupled to the coupling capacitor 206, and the second end of the tunable capacitor 213 is electrically coupled to the compensation signal terminal P0; the detection module 205 is configured to: adjust the capacitance value of the tunable capacitor 213 by using the compensation signal so that the equivalent capacitance of the tunable capacitor 213 and the coupling capacitor 206 is adjusted to a target capacitance value.

[0104] Specifically, the first end of the tunable capacitor 213 is electrically coupled to the coupling capacitor 206 (i.e., the first end of the tunable capacitor 213 is connected to the sensor module 204), the second end of the tunable capacitor 213 is electrically coupled to the compensation signal terminal P0, and the compensation signal applied to the compensation signal terminal P0 is used to control the capacitance value of the tunable capacitor 213. The compensation module 209 adjusts the capacitance value of the tunable capacitor 213 by using the compensation signal, so that the equivalent capacitance of the tunable capacitor 213 and the coupling capacitor 206 is adjusted to the target capacitance value, offsetting the characteristic change of the coupling capacitor 206 caused by the manufacturing process difference of the sensor module 204, improving the consistency of the detection module 205 in response to the gate drive signal, and ensuring the stability and accuracy of the detection signal.

[0105] By precisely adjusting the capacitance value of the tunable capacitor 213, the compensation module 209 can offset the characteristic change of the coupling capacitor 206, so that the equivalent capacitance of the tunable capacitor 213 and the coupling capacitor 206 corresponding to each pixel circuit has better consistency, thereby improving the consistency and accuracy of the detection signal.

[0106] In some embodiments, as Figure 5As shown, the compensation module 209 includes a first adjustable capacitor 214 and a second adjustable capacitor 215. A first end of the first adjustable capacitor 214 is electrically coupled to the coupling capacitor 206. A second end of the first adjustable capacitor 214 is electrically coupled to a first compensation signal terminal P1. A first end of the second adjustable capacitor 215 is electrically coupled to the coupling capacitor 206. A second end of the second adjustable capacitor 215 is electrically coupled to a second compensation signal terminal P2. A maximum capacitance value of the second adjustable capacitor 215 is less than a maximum capacitance value of the first adjustable capacitor 214.

[0107] The detection module 205 is configured to: adjust a capacitance value of the first adjustable capacitor 214 by using a first compensation signal applied to the first compensation signal terminal P1 and adjust a capacitance value of the second adjustable capacitor 215 by using a second compensation signal applied to the second compensation signal terminal P2 so that an equivalent capacitance of the first adjustable capacitor 214, the second adjustable capacitor 215, and the coupling capacitor 206 is adjusted to a target capacitance value; or,

[0108] The detection module 205 is configured to: adjust a capacitance value of the second adjustable capacitor 215 by using a second compensation signal applied to the second compensation signal terminal P2 so that an equivalent capacitance of the second adjustable capacitor 215 and the coupling capacitor 206 is adjusted to a target capacitance value.

[0109] Specifically, a first end of the first adjustable capacitor 214 is electrically coupled to the coupling capacitor 206, and a second end is electrically coupled to the first compensation signal terminal P1. A first end of the second adjustable capacitor 215 is electrically coupled to the coupling capacitor 206, and a second end is electrically coupled to the second compensation signal terminal P2. The maximum capacitance value of the second adjustable capacitor 215 is less than the maximum capacitance value of the first adjustable capacitor 214. Generally, a capacitance value range of the first adjustable capacitor 214 is 100 - 1000 picofarads, and a capacitance value range of the second adjustable capacitor 215 is 1 - 10 picofarads. When compensating the coupling capacitor 206, coarse adjustment can be performed through the first adjustable capacitor 214, which has a larger maximum capacitance value and is suitable for quickly adjusting the equivalent capacitance. Fine adjustment can be performed through the second adjustable capacitor 215, whose maximum capacitance value is less than that of the first adjustable capacitor 214 and is suitable for finely adjusting the equivalent capacitance. Or when a touch control function needs to be implemented, compensation can be performed through the first adjustable capacitor 214. When detecting the shift register unit, only the capacitance value of the second adjustable capacitor 215 is adjusted by using the second compensation signal so that the equivalent capacitance of the second adjustable capacitor 215 and the coupling capacitor 206 is adjusted to the target capacitance value.

[0110] Coarse adjustment is performed through the first adjustable capacitor 214 to quickly adjust the equivalent capacitance to be close to the target value, and fine adjustment is performed through the second adjustable capacitor 215 to accurately adjust the equivalent capacitance to the target value, thereby improving the stability and accuracy of the detection signal. The compensation module 209 includes the first adjustable capacitor 214 and the second adjustable capacitor 215, which can adapt to different types of tasks and different working environments, and has wide applicability and compatibility. The combination compensation of the first adjustable capacitor 214 and the second adjustable capacitor 215, or only the separate compensation of the second adjustable capacitor 215, can be selected according to needs, providing a flexible compensation method.

[0111] In some embodiments, such as Figure 4 shown, the operational amplifier module 207 includes an operational amplifier 216 and a feedback capacitor 217. The first end of the feedback capacitor 217 is electrically coupled to the inverting input terminal of the operational amplifier 216, and the second end of the feedback capacitor 217 is electrically coupled to the output terminal of the operational amplifier 216;

[0112] The analog-to-digital conversion module 208 includes an analog-to-digital converter 218. The input terminal of the analog-to-digital converter 218 is electrically coupled to the output terminal of the operational amplifier 216.

[0113] Specifically, the operational amplifier 216 has the characteristics of high gain and high input impedance. The inverting input terminal of the operational amplifier 216 is electrically coupled to the sensor module 204 to receive the coupled signal. The non-inverting input terminal of the operational amplifier 216 is electrically coupled to the reference voltage terminal VREF, and the reference voltage terminal VREF provides a reference voltage for the operational amplifier 216. The output terminal of the operational amplifier 216 is electrically coupled to the analog-to-digital conversion module 208 for outputting the characteristic signal. The first end of the feedback capacitor 217 is electrically coupled to the inverting input terminal of the operational amplifier 216, and the second end of the feedback capacitor 217 is electrically coupled to the output terminal of the operational amplifier 216. The feedback capacitor 217 is used to form a closed-loop amplification. The output signal of the operational amplifier 216 is fed back to the inverting input terminal through the feedback capacitor 217, thereby forming a negative feedback loop. The function of the negative feedback is to make the output signal of the operational amplifier 216 maintain a linear relationship with the input signal, ensuring the stability and accuracy of the amplification factor. The coupled signal detected by the sensor module 204 is input to the operational amplifier module 207 through the inverting input terminal of the operational amplifier 216. The operational amplifier 216 amplifies the input coupled signal, and the amplified signal is used as the characteristic signal and sent to the analog-to-digital converter 218 through the output terminal of the operational amplifier 216. The analog-to-digital converter 218 converts the characteristic signal (analog signal) into a digital signal for subsequent anomaly detection.

[0114] The high - gain and high - input - impedance characteristics of the operational amplifier 216 enable the input signal to be precisely amplified, thereby improving the sensitivity and accuracy of detection. The introduction of the feedback capacitor 217 ensures the stability of the amplification factor and reduces signal drift caused by environmental changes or component aging. The op - amp module 207 can process weak coupling signals, amplify them to an amplitude suitable for analog - to - digital conversion, and obtain characteristic signals, ensuring the reliability and stability of the characteristic signals.

[0115] In some embodiments, as Figure 1B shown, the display panel 200 further includes a touch structure 220 integrated inside the display panel 200. The touch structure 220 is disposed on the side of the plurality of pixel units (e.g., Figure 1A the pixel unit P of Figure 2B or the pixel unit 201 of Figure 1B ) away from the substrate 1. The touch structure 220 includes a plurality of touch electrodes (e.g., Figure 1B the first electrode 2201 or the second electrode 2202, or the touch electrodes of a self - capacitive touch screen). The sensor module 204 includes the touch electrodes. In this way, using the touch electrodes in the touch structure 220 to implement the sensor module 204 can streamline the structure of the display panel 200 and reduce the manufacturing cost.

[0116] Furthermore, in some embodiments, the sensor module 204 is further configured to: generate a corresponding touch - sensing signal during the touch stage when a touch operation (e.g., being subjected to an external force) is detected;

[0117] The first adjustable capacitor 214 is further configured to: compensate the touch - sensing signal of the sensor module 204 during the touch stage.

[0118] Specifically, during the touch stage, when the sensor module 204 is subjected to an external force (such as finger touch), a touch - sensing signal is generated. The touch - sensing signal reflects information such as the touch position and intensity. The first adjustable capacitor 214 compensates the touch - sensing signal of the sensor module 204 during the touch stage to offset capacitance changes caused by environmental changes (such as temperature, humidity) or manufacturing process differences, so as to ensure that the touch - sensing signal of the sensor module 204 remains stable and accurate.

[0119] By compensation, the stability and accuracy of the touch - sensing signal are ensured, thereby improving the accuracy of touch - position detection. The compensation mechanism can adapt to environmental changes, reduce signal fluctuations caused by capacitance changes, and enhance the stability of the system.

[0120] In some embodiments, the detection module 205 can be implemented as a driving IC, so that the excellent electrical performance of the IC chip can be used to implement the detection function of the above - mentioned embodiments of the present application.

[0121] An embodiment of the present application also provides a display driving method, which is applied to the display panel (for example, display panel 200), and may include the following steps:

[0122] The gate driving circuit 202 sends a gate driving signal through the first trace 203;

[0123] The sensor module 204 generates a corresponding coupling signal based on the gate driving signal on the first trace 203 through the coupling capacitor 206;

[0124] The detection module 205 performs an abnormality detection on the shift register unit 2021 of the gate driving circuit 202 according to the coupling signal.

[0125] In the embodiment of the present application, the sensor module 204 forms the coupling capacitor 206 by partially overlapping with the first trace 203 of the gate driving circuit 202, and can detect minute changes in the gate driving signal. The detection module 205 processes the coupling signal generated by the coupling capacitor 206 to generate an abnormality detection signal, so as to determine whether there is an abnormality in the shift register unit corresponding to a certain row of traces. Therefore, the detection accuracy is significantly improved.

[0126] The detection module 205 performs an abnormality detection on the shift register unit of the gate driving circuit 202 according to the coupling signal, including:

[0127] The detection module 205 generates a corresponding abnormality detection signal according to the coupling signal;

[0128] When the difference between the abnormality detection value corresponding to the abnormality detection signal and the preset detection value is greater than or equal to the abnormality detection threshold, the detection module 205 determines that the shift register unit is abnormal.

[0129] In this embodiment, the detection module 205 calculates the difference between the abnormality detection value corresponding to the abnormality detection signal and the preset detection value (the preset detection value is the reference value corresponding to the abnormality detection signal under normal working conditions. The preset detection value reflects the typical characteristics of the gate driving signal without faults). If the difference is greater than or equal to the abnormality detection threshold (the setting of the abnormality detection threshold needs to comprehensively consider the normal fluctuation range of the signal and the sensitivity of the fault. Exemplarily, the abnormality detection threshold can be set to 80), it is determined that the corresponding shift register unit is abnormal. In this way, using the difference comparison to determine whether the shift register unit is abnormal can implement the abnormality detection with a relatively simple structure and reduce the manufacturing cost.

[0130] An embodiment of the present application also provides a display device (for example, Figure 1AThe display device 100) includes the display panel described in any of the above embodiments (for example, the display panel 200). This display device can have the technical effects of the display panel in the corresponding embodiment, which will not be elaborated here.

[0131] Optionally, the display device provided by the embodiments of the present application may include: a display, a mobile phone, a television, an outdoor advertising screen, a laptop, and / or a navigator, etc. Other essential components of the display device are understood to be possessed by those of ordinary skill in the art and will not be elaborated.

[0132] It should be noted that some embodiments of the present application are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the above embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0133] Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present application is limited to these examples; under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.

[0134] In addition, for simplicity of description and discussion, and in order not to make the embodiments of the present application difficult to understand, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the devices may be shown in block diagram form to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (i.e., these details should be fully within the understanding of those skilled in the art). In the case where specific details (such as circuits) are set forth to describe the exemplary embodiments of the present application, it will be apparent to those skilled in the art that the present application can be implemented without these specific details or with variations of these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0135] Although the present application has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0136] Embodiments of the present application are intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the claims of the present application. Accordingly, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the embodiments of the present application shall be included within the protection scope of the present application.

Claims

1. A display panel, characterized in that: The device comprises a display area and a non-display area surrounding the display area, and includes: substrate substrate; A plurality of pixel units are disposed on the substrate and arranged in an array in the display area, wherein the pixel units include pixel circuits; A gate driving circuit, arranged on the substrate and located in the non-display area, comprising a plurality of cascaded shift register units, the plurality of shift register units being electrically coupled to a plurality of rows of pixel circuits through a plurality of first wirings, and being used for providing gate driving signals to the plurality of rows of pixel circuits; a fault detection circuit, arranged on the substrate, comprising at least one sensor module arranged in the display area and a detection module arranged in the non-display area and electrically coupled to the sensor module, wherein the orthographic projection of the sensor module on the substrate overlaps with at least one of the first traces to form at least one coupling capacitor; The shift register unit is configured to: send a gate drive signal through the first wiring; The sensor module is configured to: generate a corresponding coupling signal through the coupling capacitor based on the gate driving signal on the first wiring; The detection module is configured to perform abnormality detection on the shift register unit according to the coupling signal.

2. The display panel according to claim 1, characterized in that: The detection module is configured to: generate a corresponding abnormality detection signal according to the coupling signal, and determine that an abnormality exists in the shift register unit when the difference between the abnormality detection value corresponding to the abnormality detection signal and the preset detection value is greater than or equal to the abnormality detection threshold.

3. The display panel according to claim 1, characterized in that: The fault detection circuit comprises a plurality of sensor modules arranged in an array, the first wiring connected to the shift register unit extends along a first direction, and the orthographic projections of a plurality of first sensor modules sequentially arranged along the first direction on the substrate of the plurality of sensor modules overlap with a portion of the first wiring to form a plurality of coupling capacitors; The detection module is configured to: generate corresponding multiple abnormal detection signals based on the multiple coupling signals generated by the multiple coupling capacitors, and when the difference between the abnormal detection value corresponding to at least one of the multiple abnormal detection signals and the preset detection value is greater than or equal to the abnormal detection threshold, determine that the shift register unit has an abnormality.

4. The display panel according to claim 1, characterized in that: The fault detection circuit includes a plurality of sensor modules arranged in an array, at least two of the first routing lines connected to at least two of the shift register units extend along a first direction, and the orthographic projections of a plurality of first sensor modules arranged sequentially along the first direction among the plurality of sensor modules on the substrate partially overlap with at least two of the first routing lines to form a plurality of coupling capacitors.

5. The display panel according to any one of claims 1 to 4, characterized in that: The detection module comprises: an operational amplifier module and an analog-to-digital conversion module, wherein the inverting input terminal of the operational amplifier module is electrically coupled to the sensor module, and the output terminal of the operational amplifier module is electrically coupled to the input terminal of the analog-to-digital conversion module; The operational amplifier module is configured to: in response to receiving the coupling signal, generate a characteristic signal corresponding to the coupling signal, and send the characteristic signal to the analog-to-digital conversion module through the output terminal; The analog-to-digital conversion module is configured to generate an abnormality detection signal corresponding to the characteristic signal based on the characteristic signal.

6. The display panel according to claim 5, characterized in that: The detection module also includes: a compensation module, a first end of the compensation module is electrically coupled to the coupling capacitor, a second end of the compensation module is electrically coupled to the compensation signal end, and is configured to: compensate the coupling capacitor under the control of the compensation signal connected to the compensation signal end.

7. The display panel according to claim 6, characterized in that: The detection module further includes: a first switch, a second switch and a third switch, wherein a first end of the first switch is electrically coupled to the coupling capacitor, a second end of the first switch is grounded, the second switch is connected between the coupling capacitor and the inverting input end of the operational amplifier module, a first end of the third switch is electrically coupled to the inverting input end of the operational amplifier module, and a second end of the third switch is electrically coupled to the output end of the operational amplifier module; the detection module is configured as follows: At a first moment, controlling the second switch to be opened, and controlling the first switch and the third switch to be closed, so as to initialize the coupling capacitor and the operational amplifier module; At a second moment, controlling the first switch and the third switch to be opened, and controlling the second switch to be closed, so that the compensation module compensates the coupling capacitor; At a third moment, controlling the first switch and the third switch to be opened, and controlling the second switch to be closed, so that the operational amplifier module generates a corresponding characteristic signal according to the coupling signal; At a fourth moment, controlling the first switch, the second switch, and the third switch to be disconnected, so that the analog-to-digital conversion module generates a corresponding abnormality detection signal based on the characteristic signal; At a fifth moment, the first switch is controlled to be closed to discharge the coupling capacitor.

8. The display panel according to claim 6, characterized in that: The compensation module includes an adjustable capacitor, a first end of the adjustable capacitor is electrically coupled to the coupling capacitor, and a second end of the adjustable capacitor is electrically coupled to the compensation signal end; the detection module is configured to: use the compensation signal to adjust the capacitance value of the adjustable capacitor so that the equivalent capacitance of the adjustable capacitor and the coupling capacitor is adjusted to a target capacitance value.

9. The display panel according to claim 6, characterized in that: The compensation module includes a first adjustable capacitor and a second adjustable capacitor, wherein a first end of the first adjustable capacitor is electrically coupled to the coupling capacitor, a second end of the first adjustable capacitor is electrically coupled to a first compensation signal end, a first end of the second adjustable capacitor is electrically coupled to the coupling capacitor, a second end of the second adjustable capacitor is electrically coupled to a second compensation signal end, and a maximum capacitance value of the second adjustable capacitor is less than a maximum capacitance value of the first adjustable capacitor; The detection module is configured to: adjust the capacitance value of the first adjustable capacitor using the first compensation signal connected to the first compensation signal terminal and adjust the capacitance value of the second adjustable capacitor using the second compensation signal connected to the second compensation signal terminal so that the equivalent capacitance of the first adjustable capacitor, the second adjustable capacitor and the coupling capacitor is adjusted to a target capacitance value; or The detection module is configured to adjust the capacitance value of the second adjustable capacitor using the second compensation signal connected to the second compensation signal terminal so that the equivalent capacitance of the second adjustable capacitor and the coupling capacitor is adjusted to a target capacitance value.

10. The display panel according to claim 5, characterized in that: The operational amplifier module includes an operational amplifier and a feedback capacitor, wherein a first end of the feedback capacitor is electrically coupled to an inverting input end of the operational amplifier, and a second end of the feedback capacitor is electrically coupled to an output end of the operational amplifier; The analog-to-digital conversion module includes an analog-to-digital converter, and an input terminal of the analog-to-digital converter is electrically coupled to an output terminal of an operational amplifier.

11. The display panel according to claim 9, characterized in that: The display panel further includes a touch structure, the touch structure is arranged on a side of the plurality of pixel units away from the base substrate, the touch structure includes a plurality of touch electrodes, and the sensor module includes the touch electrodes; The sensor module is further configured to: generate a corresponding touch sensing signal when a touch operation is detected during the touch stage; The first adjustable capacitor is further configured to: compensate the touch sensing signal of the sensor module during the touch stage.

12. A display driving method, applied to the display panel according to any one of claims 1 to 11, characterized in that: The gate drive circuit sends a gate drive signal through the first wiring; The sensor module generates a corresponding coupling signal through a coupling capacitor based on the gate drive signal on the first wiring; The detection module performs abnormality detection on the shift register unit of the gate driving circuit according to the coupling signal.

13. The display driving method according to claim 12, characterized in that: The detection module performs abnormality detection on the shift register unit of the gate driving circuit according to the coupling signal, including: The detection module generates a corresponding abnormality detection signal according to the coupling signal; When the difference between the abnormality detection value corresponding to the abnormality detection signal and the preset detection value is greater than or equal to the abnormality detection threshold, the detection module determines that an abnormality exists in the shift register unit.

14. A display device, characterized in that: A display panel comprising any one of claims 1 to 11.

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