Voltage regulator control with scalable power stages

Abstract

The invention relates to voltage regulator control with scalable power stages. Devices, devices, and systems for controlling a power supply to a load are described. A system may include a power stage and a power management integrated circuit (PMIC). The PMIC may include a controller configured to determine that the load is operating in the low power mode. The controller may operate the PMIC to power the load in response to the load operating in the low power mode. The controller may determine that the load is operating in a high power mode. The controller may operate at least one of the PMIC and the power stage to power the load in response to the load operating in the high power mode.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices. More specifically, the present disclosure relates to an architecture for a scalable system, in which at least one of a local power management integrated circuit (PMIC) and an external power stage can be operated to power a load. Background Art

[0002] In one aspect, most of the lifespan of computing devices (such as computers, laptops, smartphones, wearable devices, tablet devices, or other computing devices) may be spent in an idle or low-power mode. The low-power mode may be a situation where the computing device consumes a relatively low level of power. When a computing device performs low-power tasks (such as web browsing, audio or video playback, or other low-power tasks), the computing device may operate in the low-power mode. During the operation of the computing device in the low-power mode, tasks that consume a relatively high level of power may cause the computing device to switch from the low-power mode to the high-power mode. When a computing device performs high-power tasks (such as processing new inputs or launching new applications), the computing device may operate in the high-power mode. Summary of the Invention

[0003] In one embodiment, a system for controlling power to a load is described. The system may include a power stage and a power management integrated circuit (PMIC). The PMIC may include a controller configured to determine that the load is operating in a low-power mode. The controller may also be configured to: in response to the load operating in the low-power mode, operate the PMIC to power the load. The controller may also be configured to determine that the load is operating in a high-power mode. The controller may also be configured to: in response to the load operating in the high-power mode, operate at least one of the PMIC and the power stage to power the load.

[0004] In one embodiment, a device having a scalable power supply to a load is described. The device may include a battery, a load, a power stage, and a power management integrated circuit (PMIC). The PMIC may include a controller configured to determine that the load is operating in a low-power mode. The controller may also be configured to: in response to the load operating in the low-power mode, operate the PMIC to convert an input voltage from the battery into a first output voltage to power the load. The controller may also be configured to determine that the load is operating in a high-power mode. The controller may also be configured to: in response to the load operating in the high-power mode, operate at least one of the PMIC and the power stage to convert an input voltage from the battery into a second output voltage to power the load.

[0005] In one embodiment, a device for controlling power supply to a load is described. The device may include a power stage that at least includes a first switching converter. The device may also include a power management integrated circuit (PMIC) that at least includes a second switching converter. The switching device in the first switching converter of the power stage may be larger than the switching device in the second switching converter of the PMIC. The PMIC may be configured to convert an input voltage into a first output voltage to supply power to a load operating in a low power mode. The power stage may be configured to convert the input voltage into a second output voltage to supply power to a load operating in a high power mode.

[0006] Other features as well as the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings. In the figures, like reference numerals indicate identical or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is an example diagram of a semiconductor device that can implement voltage regulator control using a scalable power stage in one embodiment.

[0008] Figure 2 is an example diagram showing the influence of the power level required by a load on the operation of voltage regulator control using a scalable power stage in one embodiment.

[0009] Figure 3 is an example diagram showing the influence of load current on the operation of voltage regulator control using a scalable power stage in one embodiment.

[0010] Figure 4 is a flowchart illustrating the process of implementing voltage regulator control using a scalable power stage in one embodiment. DETAILED DESCRIPTION

[0011] In the following description, many specific details such as particular structures, components, materials, dimensions, process steps, and techniques are set forth in order to provide an understanding of the various embodiments of the present application. However, those of ordinary skill in the art will understand that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or process steps have not been described in detail to avoid obscuring the present application.

[0012] Figure 1FIG. 0 is an exemplary diagram of a semiconductor device that can implement voltage regulator control using an expandable power stage in one embodiment. System 100 can be implemented in a semiconductor package including one or more semiconductor devices. System 100 can include a voltage source 101, a load 102, a power management integrated circuit (PMIC) 110, and a power stage 130. System 100 can be part of a computing device (such as a computer, laptop, smartphone, wearable device, tablet device, or other type of computing device). The voltage source 101 can be, for example, a power source internal or external to the computing device including System 100. In one embodiment, the voltage source 101 can be a battery or a battery pack including at least one battery. The load 102 can be, for example, a microprocessor, a single-core processor, a multi-core processor, or other type of processing hardware element in the computing device. System 100 can convert an input voltage Vin to an output voltage Vout, and Vout can be provided to the load 102 to power the load 102.

[0013] The PMIC 110 can at least include a controller 112, a voltage sensing circuit 114, a current sensing circuit 116, drivers 120, 122, and at least include switching converters (such as switching converters 124, 126). The controller 112 can be, for example, a microcontroller including hardware (such as various analog and digital circuit components). The controller 112 can include, for example, a processor, a central processing unit (CPU), a field programmable gate array (FPGA), or any other circuitry configured to control and operate various aspects of the PMIC 110. The voltage sensing circuit 114 can be a circuit configured to sense or measure the voltage output from either the PMIC 110 or the power stage 130 to the load 102. The current sensing circuit 116 can be a circuit configured to sense or measure the current flowing through the switching node SW1, switching node SW2 of the PMIC 110, or the switching node SW3 of the power stage 130. The number of switching converters in the PMIC 110 can be arbitrary, and additional switching converters can be added to accommodate higher current applications.

[0014] Each of the switching converters 124 and 126 may include a corresponding pair of switches implemented by transistors such as various types of field effect transistors (FETs) including metal oxide semiconductor field effect transistors (MOSFETs). The MOSFET pair in the switching converter 124 may be alternately switched to convert the input voltage Vin into a first voltage that may be output at the switching node SW1. The MOSFET pair in the switching converter 126 may be alternately switched to convert the input voltage Vin into a second voltage that may be output at the switching node SW2. The first voltage output at the switching node SW1 and the second voltage output at the switching node SW2 may be combined to form the output voltage Vout. The controller 112 may also include a modulator configured to generate a pulse width modulation (PWM) signal 106. The controller 112 may provide the PWM signal 106 to the drivers 120 and 122. The drivers 120 and 122 may be driver circuits configured to use the PWM signal 106 to generate gate signals. The gate signals generated by the drivers 120 and 122 may be used to drive the gates of the transistor pairs in the switching converters 124 and 126, thereby alternately switching the transistor pairs in the switching converters 124 and 126.

[0015] The power stage 130 may be an external power stage such as a power stage external to the PMIC 110 and / or external to the computing device including the system 100. The power stage 130 may at least include a driver 132 and a switching converter 134. The switching converter 134 may include a pair of switches implemented by transistors such as MOSFETs. The MOSFET pair in the switching converter 134 may be alternately switched to convert the input voltage Vin into a third voltage that may be output as the output voltage Vout at the switching node SW3. The controller 112 may provide the PWM signal 106 to the driver 132, and the driver 132 may be a driver circuit configured to use the PWM signal 106 to generate a gate signal. The gate signal generated by the driver 132 may be used to drive the gates of the transistor pair in the switching converter 134, thereby alternately switching the transistor pairs in the switching converters 124 and 126. The number of switching converters in the power stage 130 may be arbitrary, and additional switching converters may be added to accommodate higher current applications.

[0016] In one aspect, a computing device including system 100 can operate in various operating states or modes, such as an idle mode, a low-power mode, or a high-power mode, depending on the amount of power demanded by load 102. The idle mode can be a mode when load 102 is in an idle state and no power is demanded. The low-power mode can be, for example, a mode when load 102 demands a relatively low amount of power. The high-power mode can be, for example, a mode when load 102 demands a relatively high amount of power. During operation in the idle mode or the low-power mode, load 102 can demand a relatively high level of power and system 100 may need to switch to operation in the high-power mode.

[0017] In Figure 1 In the illustrated embodiment, the transistor pair in switch converter 136 of power stage 130 can be larger than the transistor pairs in switch converters 124 and 126 of PMIC 110. Due to the different sizes, although the same input voltage Vin is supplied to both PMIC 110 and power stage 130 for conversion, the voltage conversions performed by PMIC 110 and power stage 130 can output different output voltages. By way of example, compared with PMIC 110, since the transistor pair in switch converter 134 is larger, power stage 130 can be configured to convert Vin to a higher Vout. If a computing device including system 100 operates in the high-power mode, using only PMIC 110 to convert Vin to Vout may not provide sufficient power to load 102 that demands high power. Further, although PMIC 110 may have lower switching losses due to having smaller devices or transistors in switch converters 124 and 126, operating only PMIC 110 in the high-power mode may require a higher current, which may increase the conduction losses in PMIC 110 because smaller devices have a higher on-resistance (RDSon). If a computing device including system 100 operates in the low-power mode, using only power stage 130 or using both PMIC 110 and power stage 130 to convert Vin to Vout may be inefficient because the larger transistor pair in switch converter 134 can require a relatively large amount of quiescent current to start or switch.

[0018] To allow a computing device including system 100 to operate efficiently in both a low-power mode and a high-power mode, PMIC 110 and power stage 130 may be integrated within the same computing device that includes system 100. Controller 112 may be configured to monitor various parameters and / or operating conditions and use the monitored parameters and / or operating conditions to determine whether load 102 is operating in a low-power mode or a high-power mode. Depending on whether load 102 is operating in a low-power mode or a high-power mode, controller 112 may determine whether to operate PMIC 110, operate power stage 130, or operate both PMIC 110 and power stage 130 to convert Vin to a different output voltage Vout for load 102. In one or more embodiments, the parameters and / or operating conditions that may be monitored by controller 112 may include, but are not limited to: the load current of load 102, output voltage Vout, the ambient temperature of PMIC 110, the known operating power state of system 100, the power demand from load 102, or other parameters and / or operating conditions.

[0019] By integrating both PMIC 110 and power stage 130 within the same computing device and by monitoring the parameters and / or operating conditions of the computing device, controller 112 may determine the appropriate time to use one or more of PMIC 110 and power stage 130 to optimize the efficiency of the computing device. The smaller transistors in switch converters 124 and 126 of PMIC 110 may be used for lower power demands from load 102, thereby reducing switching losses. The larger transistors in switch converter 134 of power stage 130 may be used for higher power demands from load 102 to reduce conduction losses. Further, using one controller (such as controller 112) to control both PMIC 110 and power stage 130 may reduce the bill of materials (BOM) cost when compared to systems that require separate controllers for the PMIC and an external power stage. Additionally, the number of stages (such as switch converters) in PMIC 110 and / or power stage 130 may be configurable, allowing for fine-tuning of the different power levels that may be provided to load 102. In one embodiment, relatively low-cost components may be used for power stage 130 such that the cost of constructing system 100 may be relatively low. Further, controller 112 may perform protection features (such as over-current protection and under-voltage protection) for both PMIC 110 and power stage 130 such that these protection features may be shared and system 100 does not require more than one controller. In embodiments where voltage source 101 is a battery, selecting one or more of PMIC 110 and power stage 130 to power load 102 may improve the efficiency of system 100 and also maintain the battery life of the battery.

[0020] Figure 2 FIG. 0 is an exemplary diagram showing the impact of the power level required by a load on the operation controlled by a voltage regulator using a scalable power stage in one embodiment. Figure 2 The description of can refer to Figure 1 the components shown in Figure 2 In the embodiment shown in FIG. 1, the controller 112 can monitor the power demand from the load 102. The power demand threshold 202 and the monitored power demand can be used by the controller 112 to determine whether to operate the PMIC 110, operate the power stage 130, or operate a combination of the PMIC 110 and the power stage 130 to supply power to the load 102. In one embodiment, the power demand threshold 202 can be programmable and can be stored in the memory device of the PMIC 110. In one embodiment, the voltage sensing circuit 114 can monitor the Vout supplied to the load 102, and the current sensing circuit 116 can monitor the load current of the load 102. The controller 112 can obtain the sensed Vout and the load current from the voltage sensing circuit 114 and the current sensing circuit 116 respectively. The controller can determine the power demand of the load 102 using the sensed Vout and the load current (e.g., the power demand is the product of the sensed Vout and the load current).

[0021] Using Figure 2 the example shown in FIG. 2, before time t1, the power demand from the load 102 can be below the power demand threshold 202, and the controller 112 can operate the PMIC 110 to generate a first Vout (e.g., a lower Vout) to supply power to the load 102 while keeping the power stage 130 deactivated. At time t1, the power demand from the load 102 can exceed the power demand threshold 202, and the controller 112 can 1) operate the power stage 130 to generate a second Vout (e.g., a higher Vout) to supply power to the load 102 while keeping the PMIC 110 deactivated, or 2) operate the PMIC 110 and the power stage 130 simultaneously to generate a third Vout to supply power to the load 102. The second Vout can be greater than the first Vout, and the third Vout can be greater than the second Vout.

[0022] At time t2, the power demand from load 102 can drop below the power demand threshold 202, and the controller 112 can return to operating the PMIC 110 to generate the first Vout, thereby supplying power to the load 102 while keeping the power stage 130 deactivated. At time t3, the power demand from load 102 can exceed the power demand threshold 202 again, and the controller 112 can 1) operate the power stage 130 to generate the second Vout, thereby supplying power to the load 102 while keeping the PMIC 110 deactivated, or 2) operate the PMIC 110 and the power stage 130 simultaneously to generate the third Vout, thereby supplying power to the load 102. Also at time t4, the power demand from load 102 can drop below the power demand threshold 202, and the controller 112 can return to operating the PMIC 110 to generate the first Vout, thereby supplying power to the load 102 while keeping the power stage 130 deactivated.

[0023] Figure 3 is an example diagram showing the effect of load current on the operation of voltage regulator control using a scalable power stage in one embodiment. Figure 3 The description of can refer to Figures 1 to 2 the components shown in Figure 2 In the embodiment shown, the current sensing circuit 116 in the controller 112 can monitor the load current of the load 102. In one embodiment, the memory device of the PMIC 110 can store a mapping between different load currents and different efficiencies (e.g., percentages) of the system 100. In Figure 3 the example shown, the curve 302 represents the mapping of the efficiency of the system 100 to different load currents when the PMIC 110 generates Vout and supplies Vout to the load 102. Also in Figure 3 the example shown, the curve 304 represents the mapping of the efficiency of the system 100 to different load currents when the power stage 130 generates Vout and supplies Vout to the load 102.

[0024] As Figure 3 indicated by the example shown in, as the load current increases, the efficiency shown by both the curve 302 and the curve 304 can increase until a certain load current. For lower load currents (such as load currents less than 6 amperes (A)), the efficiency of using the PMIC 110 can be higher than the efficiency of using the power stage 130. For higher load currents (such as load currents greater than 6 amperes (A)), the efficiency of using the PMIC 110 can be lower than the efficiency of using the power stage 130. In one embodiment, the controller 112 can be configured to use what can be stored as Figure 3The mapping of the digital data represented by the curves 302 and 304 shown determines whether to generate Vout using the PMIC 110, using the power stage 130, or using a combination of the PMIC 110 and the power stage 130. By way of example, if the load current monitored by the current sensing circuit 116 is below a predefined threshold (such as 6 A), then the controller 112 can operate the PMIC 110 to generate a first Vout (e.g., a lower Vout), thereby supplying power to the load 102 while keeping the power stage 130 deactivated. If the load current monitored by the current sensing circuit 116 is above a predefined threshold (such as 6 A), then the controller 112 can 1) operate the power stage 130 to generate a second Vout (e.g., a higher Vout), thereby supplying power to the load 102 while keeping the PMIC 110 deactivated, or 2) operate the PMIC 110 and the power stage 130 simultaneously to generate a third Vout, thereby supplying power to the load 102.

[0025] Figure 4 is a flowchart illustrating a process of implementing voltage regulator control using a scalable power stage in one embodiment. The process may include one or more operations, actions, or functions illustrated by one or more of the blocks such as block 402, block 404, block 406, block 408, block 410, and / or block 412. Although illustrated as discrete blocks, depending on the desired implementation method, various block diagrams may be divided into additional block diagrams, combined into fewer block diagrams, eliminated, executed in a different order, or executed in parallel.

[0026] Figure 4 The description of can refer to Figures 1 to 3 the components shown. The process 400 may be executed by the controller 112 described herein. The process 400 may start at block 402. At block 402, the load 102 may operate in a low power mode, and the controller 112 may operate the PMIC 110 to generate a first Vout (e.g., a lower Vout) and supply the first Vout to the load 102. Also at block 402, the power stage 130 may be deactivated. The process 400 may proceed from block 402 to block 404. At block 404, the controller 112 may monitor the parameters and / or operating conditions of the load 102 to determine whether the load 102 is operating in a low power mode or a high power mode. The parameters and / or operating conditions monitored at block 404 may include, but are not limited to: the load current of the load 102, the output voltage Vout, the ambient temperature of the PMIC 110, the known operating power state of the system 100, the power demand from the load 102, or other parameters and / or operating conditions.

[0027] Process 400 can proceed from block 404 to block 406. At block 406, the controller 112 can determine whether to operate the power stage 130. In one embodiment, the controller 112 (or the current sensing circuit 116) can monitor the load current of the load 102 (see Figure 3 and the corresponding description) to determine whether to operate the power stage 130. By way of example, if the load current of the load 102 results in higher efficiency when using the PMIC 110, then the controller 112 can determine that the load 102 can continue to operate in the low power mode, and the PMIC 110 should continue to generate the first Vout and supply the first Vout to the load 102, and the process 400 can return to block 402. If the load current of the load 102 results in higher efficiency when using the power stage 130, then the controller 112 can determine that the load 102 can operate in the high power mode and the power stage 130 should be activated, and the process 400 can proceed to block 408 or block 410.

[0028] In one embodiment, the controller 112 (or the voltage sensing circuit 114) can monitor the Vout supplied to the load 102. The controller 112 can use the monitored Vout, together with the monitored load current of the load 102, to determine the power required by the load 102 (see Figure 2 and the corresponding description). The controller 112 can determine whether to operate the power stage 130 based on the power required by the load 102. By way of example, if the load 102 requires power lower than the power demand threshold 202 (see Figure 2 ), then the controller 112 can determine that the load 102 can continue to operate in the low power mode and the PMIC 110 should continue to generate the first Vout and supply the first Vout to the load 102, and the process 400 can return to block 402. If the load 102 requires power higher than the power demand threshold 202, then the controller 112 can determine that the load 102 can operate in the high power mode and the power stage 130 should be activated, and the process 400 can proceed to block 408 or block 410.

[0029] In one embodiment, the controller 112 may include at least one temperature sensor configured to measure the ambient temperature of the PMIC 110. The PMIC 110 may also include a memory device configured to store a temperature threshold. The controller 112 may determine whether the ambient temperature of the PMIC 110 is greater than or less than the temperature threshold. In response to the ambient temperature of the PMIC 110 being less than the temperature threshold, the controller 112 may determine that the load 102 may continue to operate in the low power mode and that the PMIC 110 should continue to generate the first Vout and supply the first Vout to the load 102, and process 400 may return to block 402. In response to the ambient temperature of the PMIC 110 being greater than the temperature threshold, the controller 112 may determine that the load 102 may operate in the high power mode, and that the power stage 130 should be activated to reduce the workload of the PMIC 110, and process 400 may proceed to block 408 or block 410.

[0030] In one embodiment, the controller 112 may know the operating power state or mode of the system 100. The operating state of the system 100 may include, for example, an idle mode, a low power mode, a high power mode, or other operating power modes. The idle mode may be a mode when the load 102 is in an idle state and does not demand power. The low power mode may be a mode when, for example, the load 102 demands a relatively low amount of power. The high power mode may be a mode when, for example, the load 102 demands a relatively high amount of power. In response to the system 100 operating in the idle mode or the low power mode, the controller 112 may determine that the PMIC 110 should continue to generate the first Vout and supply the first Vout to the load 102, and process 400 may return to block 402. In response to the system 100 operating in the high power mode, the controller 112 may determine that the power stage 130 should be activated to reduce the workload of the PMIC 110, and process 400 may proceed to block 408 or block 410.

[0031] In one embodiment, block 408 may be an optional block and process 400 may proceed to block 408 to perform a handshake before proceeding to block 410. At block 408, the controller 112 may activate the power stage 130. Activating the power stage 130 at block 408 may cause both the PMIC 110 and the power stage 130 to be activated. Accordingly, the controller 112 may operate both the PMIC 110 and the power stage 130 to generate a third Vout and supply the third Vout to the load 102. The handshake may allow for a seamless transition from operating the PMIC 110 to operating the power stage 130 without interrupting the power supply to the load 102. When process 400 proceeds to the optional block 408 to perform the handshake, the controller 112 may operate both the PMIC 110 and the power stage 130 for a predefined amount of handshake time before proceeding to block 410.

[0032] If the controller 112 does not perform a handshake at the optional box 408, the process 400 can proceed from box 406 to box 410. At box 410, the controller 112 can determine whether to continue operating the PMIC 110 or disable the PMIC 110. In embodiments where a handshake is performed at the optional block diagram 408, the controller 112 can wait for a predefined amount of handshake time to elapse. In response to the predefined amount of handshake time elapsing, the controller 112 can determine that the PMIC 110 can be disabled and proceed to box 412 to disable the PMIC 110.

[0033] In one embodiment, when the load 102 demands a relatively high amount of power, the controller 112 can determine to operate both the PMIC 110 and the power stage 130 to generate a third Vout and supply the third Vout to the load 102. By way of example, referring to Figure 2 , if the power demand of the load 102 exceeds a predefined factor of the power demand threshold 202 (e.g., exceeds the power demand threshold 202 by X%), then the controller 112 can determine to continue operating both the PMIC 110 and the power stage 130 at box 410 and return to box 408 to maintain the activation of both the PMIC 110 and the power stage 130.

[0034] At box 412, the controller 112 can disable the PMIC 110 and operate the power stage 130 to generate a second Vout and provide the second Vout to the load 102. The process 400 can return to box 404 to continue monitoring the parameters and / or operating conditions of the load 102. The second Vout can be greater than the first Vout, and the third Vout can be greater than the second Vout.

[0035] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram may represent a module, segment, or portion of an instruction, which includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the block diagrams may not occur in the order noted in the figures. For example, in fact, depending on the functions involved, two consecutive boxes shown may be executed substantially simultaneously, or sometimes the boxes may be executed in the reverse order. It should also be noted that each box in the block diagrams and / or flowchart illustrations, and combinations of boxes in the block diagrams and / or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0036] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms "comprised" and / or "comprising", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0037] In the following claims, all structural, material, acts, and equivalents of the corresponding structures, materials, acts, and any means-plus-function elements (if any) are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. For purposes of illustration and description, embodiments of the present invention have been presented, but are not intended to be exhaustive or to limit the invention to the disclosed forms. Many modifications and variations are obvious to one of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A system comprising: Power level; as well as A power management integrated circuit PMIC, the PMIC comprising a controller, the controller being configured to: Determining that the load is operating in a low power mode; In response to the load operating in the low power mode, operating the PMIC to provide power to the load; determining that the load is operating in a high power mode; as well as In response to the load operating in the high power mode, at least one of the PMIC and the power stage is operated to provide power to the load. 2 . The system of claim 1 , wherein the controller is configured to operate the PMIC and the power stage to provide power to the load in response to the load operating in the high power mode. 3 . The system of claim 1 , wherein the controller is configured to operate the power stage to provide power to the load in response to the load operating in the high power mode.

4. The system of claim 1, wherein the controller is configured to: In response to the load operating in the high power mode, operating the PMIC and the power stage to provide power to the load; determining that a predefined amount of time has elapsed; and In response to the predefined amount of time elapsing: deactivating the PMIC; and The power stage is operated to provide power to the load.

5. The system of claim 1 , wherein the controller is configured to: In response to a power demand of the load being less than a predefined power demand threshold, determining that the load is operating in the low power mode; and In response to a power demand of the load being greater than a predefined power demand threshold, it is determined that the load is operating in the high power mode.

6. The system of claim 1, wherein the controller is configured to: measuring a load current of the load; determining a first efficiency of the system corresponding to the PMIC and the load current; determining a second efficiency of the system corresponding to the power level and the load current; identifying a higher efficiency between the first efficiency and the second efficiency; in response to the first efficiency being identified as the higher efficiency, determining that the load is operating in the low power mode; as well as In response to the second efficiency being identified as the higher efficiency, it is determined that the load is operating in the high power mode.

7. The system of claim 1, wherein the controller is configured to: In response to an ambient temperature of the PMIC being less than a predefined temperature threshold, determining that the load is operating in the low power mode; and In response to the ambient temperature of the PMIC being greater than a predefined temperature threshold, determining that the load is operating in the high power mode.

8. The system of claim 1, wherein the controller is configured to: determining that the load is in an idle mode; and In response to the load being in the idle mode, operating the PMIC to supply power to the load.

9. A device comprising: Battery; load; Power level; as well as A power management integrated circuit PMIC, the PMIC comprising a controller, the controller being configured to: determining that the load is operating in a low power mode; In response to the load operating in the low power mode, operating the PMIC to convert an input voltage from the battery to a first output voltage to power the load; determining that the load is operating in a high power mode; as well as In response to the load operating in the high power mode, at least one of the PMIC and the power stage is operated to convert the input voltage from the battery to a second output voltage to power the load.

10. The device of claim 9, wherein the controller is configured to, in response to the load operating in the high power mode, operate the PMIC and the power stage to convert the input voltage from the battery to the second output voltage to power the load.

11. The device of claim 9, wherein the controller is configured to, in response to the load operating in the high power mode, operate the power stage to convert the input voltage from the battery to the second output voltage to power the load.

12. The apparatus of claim 9, wherein the controller is configured to: In response to the load operating in the high power mode, operating the PMIC and the power stage to provide power to the load; Determine that a predefined amount of time has elapsed; as well as In response to the predefined amount of time elapsing: deactivating the PMIC; as well as The power stage is operated to convert the input voltage from the battery to the second output voltage to power the load.

13. The apparatus of claim 9, wherein the controller is configured to: In response to a power demand of the load being less than a predefined power demand threshold, determining that the load is operating in the low power mode; and In response to a power demand of the load being greater than a predefined power demand threshold, it is determined that the load is operating in the high power mode.

14. The apparatus of claim 9, wherein the controller is configured to: measuring a load current of the load; determining a first efficiency of the device corresponding to the PMIC and the load current; determining a second efficiency of the device corresponding to the power level and the load current; identifying a higher efficiency between the first efficiency and the second efficiency; in response to the first efficiency being identified as the higher efficiency, determining that the load is operating in the low power mode; as well as In response to the second efficiency being identified as the higher efficiency, it is determined that the load is operating in the high power mode.

15. The apparatus of claim 9, wherein the controller is configured to: In response to an ambient temperature of the PMIC being less than a predefined temperature threshold, determining that the load is operating in the low power mode; and In response to the ambient temperature of the PMIC being greater than a predefined temperature threshold, determining that the load is operating in the high power mode.

16. The apparatus of claim 9, wherein the controller is configured to: determining that the load is in an idle mode; and In response to the load being in the idle mode, operating the PMIC to convert the input voltage from the battery into the first output voltage to power the load.

17. An apparatus comprising: a power stage including at least a first switching converter; as well as A power management integrated circuit PMIC comprises at least a second switching converter, wherein: a switching device in the first switching converter of the power stage is larger than a switching device in the second switching converter of the PMIC; and The PMIC is configured to convert an input voltage to a first output voltage to power a load operating in a low power mode; and The power stage is configured to convert the input voltage to a second output voltage to power a load operating in a high power mode.

18. The device according to claim 17, wherein: The low power mode is defined by a power demand of the load being less than a predefined power demand threshold; The high power mode is defined by the power demand of the load being greater than a predefined power demand threshold.

19. The apparatus of claim 17, wherein: The low power mode is defined by an ambient temperature of the PMIC being less than a predefined temperature threshold; and The high power mode is defined by the ambient temperature of the PMIC being greater than a predefined temperature threshold.

20. The apparatus of claim 17, wherein: The PMIC is configured to convert the input voltage to the first output voltage to power a load operating in an idle mode.

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