Display device and driving method thereof

Abstract

The present application provides a display device and a driving method thereof. The gate driving unit of the display device comprises an input module electrically connected to one of a frame start line, a gate line of an i (positive integer) previous stage and a gate line of an i next stage for controlling a signal of a first node and a signal of a second node, an output module electrically connected to the input module through the first node and the second node, wherein a first output submodule of the output module is used for generating a first gate signal transmitted to a corresponding gate line to turn on a plurality of sub-pixels according to a corresponding first signal, and a second output submodule of the output module controls the signal of the first node according to a second signal, so that the first output submodule generates the first gate signal according to the first signal to reduce the amplitude attenuation of the first gate signal.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to display devices and their driving methods. Background Technology

[0002] During AGO (All Gate On), the display panel resets all sub-pixels by simultaneously scanning all row sub-pixels.

[0003] However, during AGO, since the multi-level gate driving units connected to multiple rows of sub-pixels are all connected to the same signal line to receive and transmit the same signal as multiple gate signals, the load effect of the resistance and capacitance of the signal line is large, resulting in a large attenuation of the amplitude of multiple gate signals. Summary of the Invention

[0004] The present invention provides a display device and a driving method thereof to improve the problem of large amplitude attenuation of multiple gate signals during AGO in existing display panels.

[0005] This invention provides a display device including a plurality of sub-pixels and a gate driving circuit electrically connected to the plurality of sub-pixels. The gate driving circuit includes a plurality of cascaded gate driving units, each gate driving unit comprising:

[0006] The input module is electrically connected to one of the frame start line, the gate line of the first i-th stage, and the gate line of the last i-th stage, and is used to control the signal of the first node and the signal of the second node, where i is a positive integer;

[0007] An output module is electrically connected to the input module through the first node and the second node. The output module includes a first output sub-module, which is electrically connected to the first node and the corresponding first signal line. The first output sub-module is used to generate a first gate signal that is transmitted to the corresponding gate line according to the first signal output by the corresponding first signal line. The first gate signal is used to control the corresponding plurality of sub-pixels to turn on.

[0008] The output module further includes a second output submodule, which is electrically connected to the second signal line and the first node. The second output submodules in the plurality of gate driving units are all electrically connected to the same second signal line to control the signal of the first node according to the second signal output by the second signal line, so that the first output submodule generates the first gate signal according to the first signal.

[0009] This invention also provides a driving method for a display device, the display device including a plurality of sub-pixels and a gate driving circuit electrically connected to the plurality of sub-pixels, the gate driving circuit including a plurality of cascaded gate driving units, the gate driving unit including an input module, a first output sub-module and a second output sub-module, the driving method for the display device including:

[0010] The input module controls the signals of the first node and the second node based on one of the frame start signal, the gate signal of the first i stage, and the gate signal of the last i stage, where i is a positive integer;

[0011] The first output submodule is controlled to generate a first gate signal that is transmitted to the corresponding gate line based on the signal of the first node, the signal of the second node and the first signal. The first gate signal is used to control the corresponding multiple sub-pixels to turn on.

[0012] Multiple second output submodules control the signals of the first node according to the second signal output from the same second signal line, so that the first output submodule generates the first gate signal.

[0013] This invention provides a display device and its driving method. The gate driving unit in the display device includes: an input module electrically connected to a frame start line, one of the gate lines of the preceding i-th stage, and the gate lines of the following i-th stage, used to control the signal of a first node and the signal of a second node, where i is a positive integer; and an output module electrically connected to the input module through the first node and the second node. The output module includes a first output sub-module electrically connected to the first node and a corresponding first signal line. The first output sub-module is used to generate a first gate signal transmitted to the corresponding gate line based on the first signal output from the corresponding first signal line. The first gate signal is used to control the activation of the corresponding plurality of sub-pixels. By configuring the output module to also include a second output sub-module electrically connected to a second signal line and the first node, and the second output sub-modules in the plurality of gate driving units are all electrically connected to the same second signal line, the second signal is no longer directly used to output multiple gate signals but instead controls the signal of the first node so that the first output sub-module generates the first gate signal based on the first signal. Therefore, the attenuation of the amplitude of the first gate signal generated based on the first signal is also smaller, which is beneficial for fully activating multiple rows of sub-pixels simultaneously. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the architecture of a display device provided in an embodiment of the present invention.

[0015] Figures 2 to 5 The circuit diagram of the gate driving unit provided in the embodiment of the present invention.

[0016] Figure 6 , Figure 7 The following are waveforms of "gate signal-time" in the comparative example and embodiment of the present invention, respectively.

[0017] Figure 8 A flowchart of a driving method for a display device provided in an embodiment of the present invention.

[0018] Figure 9 This is a timing diagram of some signals in the gate driving unit provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] In the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In this document, the source and drain of a transistor are not distinguished and can be interchanged. Furthermore, it should be noted that the accompanying drawings only provide structures closely related to the invention, omitting some details less relevant to the invention. The purpose is to simplify the drawings and make the inventive points clear at a glance, not to indicate that the actual device is identical to the attached drawings. Figure 1 It is identical, but this is not a limitation of the actual device.

[0021] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase at various points in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] The present invention provides a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0023] In one embodiment, combined with Figures 1 to 5As shown, the display device 100 includes a plurality of sub-pixels 101 and a gate driving circuit 102 electrically connected to the plurality of sub-pixels 101. The gate driving circuit 102 includes a plurality of cascaded gate driving units 20. Here, the gate driving unit 20 of the Nth stage is described as an example. It includes: an input module 30, electrically connected to one of the frame start line (for transmitting the frame start signal), the gate line of the i-th stage (for transmitting the gate signal GN-i of the i-th stage), and the gate line of the i-th stage (for transmitting the gate signal GN+i of the i-th stage), for controlling the signal of the first node Q1 and the signal of the second node Q2, where i is a positive integer; and an output module 40, electrically connected to the input module 30 through the first node Q1 and the second node Q2. The output module 40 includes a first signal line electrically connected to the first node Q1 and the corresponding first signal line (for transmitting the clock signal CKN of this stage). An output submodule 401 is configured to generate a first gate signal (e.g., a high-potential signal or a low-potential signal of the gate signal GN of the current stage) transmitted to the corresponding gate line based on a first signal output from the corresponding first signal line (i.e., the clock signal CKN of the current stage mentioned above). The first gate signal is used to control the corresponding plurality of sub-pixels 101 to turn on. The output module 40 further includes a second output submodule 402 electrically connected to a second signal line (used to transmit the global second signal Gas1) and the first node Q1. The second output submodules 402 in the plurality of gate driving units 20 are all electrically connected to the same second signal line to control the signal of the first node Q1 based on the second signal Gas1 output from the second signal line, so that the first output submodule 401 generates the first gate signal based on the first signal.

[0024] The display panel 10 in the display device 100 can be a self-emissive display panel or a liquid crystal display panel. In the self-emissive display panel, the image is displayed by the self-emission of the light-emitting elements in the sub-pixels 101. In the liquid crystal display panel, the voltage difference between the pixel electrode and the common electrode in the sub-pixel 101 controls the corresponding liquid crystal molecules to deflect at a corresponding angle, so that the corresponding amount of light emitted by the backlight can be transmitted to display the image. For both the self-emissive display panel and the liquid crystal display panel, "sub-pixel 101 on" can be understood as the corresponding transistor in the sub-pixel 101 being turned on to control the corresponding light-emitting element to emit light, or controlling the voltage difference formed between the corresponding pixel electrode and the common electrode to control the corresponding liquid crystal molecules to transmit light. Conversely, "sub-pixel 101 off" can be understood as the corresponding transistor in the sub-pixel 101 being turned off, causing the light-emitting element to turn off, or causing the voltage difference formed between the pixel electrode and the common electrode to prevent the liquid crystal molecules from transmitting light.

[0025] Specifically, such as Figure 1As shown, the display device 100 may further include a timing controller 201, each gate driving unit 20 electrically connected between the timing controller 201 and a corresponding plurality of sub-pixels 101, for outputting a gate signal Gate transmitted to the corresponding plurality of sub-pixels 101; and at least one source driver 202, each source driver 202 electrically connected between the timing controller 201 and the corresponding plurality of sub-pixels 101, for outputting a data signal Data transmitted to the corresponding plurality of sub-pixels 101. The display device 100 may include an electrically connected display panel 10 and a driving chip 20. The display panel 10 has the aforementioned gate driving circuit 102 and a plurality of sub-pixels 101 disposed on its substrate, and the driving chip 20 may include the timing controller 201 and the source driver 202.

[0026] For ease of description, this example uses multiple sub-pixel 101 arrays arranged in n rows and m columns (n ​​and m are both positive integers).

[0027] The gate drive circuit 102 may include at least n levels of gate drive units, such as Figure 1 As shown, each gate driving unit outputs a corresponding gate signal Gate according to the first control signal provided by the timing controller 201. The n-level gate signals are transmitted to the n rows of sub-pixels 101 through n gate lines (GL1 to GLn). The n gate pulses in the n-level gate signals used to turn on the n rows of sub-pixels 101 can be arranged sequentially on the time axis to turn on multiple rows of sub-pixels 101 in sequence. As can be seen from the above discussion, the gate pulse can be the first gate signal with a higher potential or the second gate signal with a lower potential in the gate signal Gate. For ease of explanation, the former is used as an example in this invention.

[0028] The source driver 202 can generate m data signals Data through m data lines (DL1 to DLm) to output to m columns of sub-pixels 101 respectively according to the second control signal provided by the timing controller 201. Each data signal Data can include n data voltages corresponding to n sub-pixels 101 in the same column. When each row of sub-pixels 101 is turned on, the multiple data lines receive multiple data voltages of multiple sub-pixels 101 located in that row, so that the multiple data voltages act on the multiple sub-pixels 101 in that row to realize the light emission of the multiple sub-pixels 101 in that row. In this way, the light emission of all rows of sub-pixels 101 can be controlled in sequence to present a complete picture.

[0029] Specifically, such as Figures 2 to 5As shown, the input module 30 can control the signal of the first node Q1 and the signal of the second node Q2 based on one of the frame start signal (for the first-stage gate driving unit 20), the gate signal GN-i of the previous i-stage (for the non-first-stage gate driving unit 20), and the gate signal GN+i of the subsequent i-stage. Furthermore, the signals of the first node Q1 and the second node Q2 can be used to control the output module 40, so that the first output sub-module 401 generates a first gate signal (e.g., a high-potential signal of the gate signal GN of the current stage) transmitted to the corresponding gate line according to the corresponding first signal (e.g., the clock signal CKN of the current stage) to control the opening of the corresponding multiple sub-pixels 101.

[0030] It should be noted that the output module 40 in this embodiment also includes a second output sub-module 402 electrically connected to the first node Q1, and the second output sub-modules 402 in the multiple gate driving units 20 are all electrically connected to the same second signal line. Since each gate driving unit 20 is connected to the corresponding multiple sub-pixels 101 through the corresponding gate line, resulting in a large load, if the second signal line directly transmits the second signal Gas1 to multiple gate lines through the second output sub-module 402 to output multiple gate signals respectively, the amplitude of multiple gate signals will be greatly attenuated, and it will be impossible to fully activate multiple rows of sub-pixels 101 simultaneously.

[0031] It is understood that in this embodiment, the second output submodules 402 in the multiple gate driving units 20 are all electrically connected to the same second signal line and are configured to control the signal of the first node Q1 according to the global second signal Gas1, thereby enabling the first output submodule 401 to generate the first gate signal (e.g., the high potential signal of the gate signal GN of this stage) according to the first signal (e.g., the clock signal CKN of this stage). Since the second signal Gas1 is no longer directly used to output multiple gate signals but controls the signal of the first node Q1 so that the first output submodule 401 generates the first gate signal according to the first signal, the second signal Gas1 and the first transistor NT1 no longer require a large driving force. Moreover, compared with the second signal line, each first signal line has fewer gate driving units 20 electrically connected, resulting in less load. Therefore, the attenuation of the amplitude of the first gate signal generated according to the first signal is also smaller, which is beneficial for fully and simultaneously opening multiple rows of sub-pixels 101.

[0032] In some embodiments, such as Figures 2 to 5 As shown, the second output submodule 402 includes: a first transistor NT1, one of the source and drain of the first transistor NT1 and its gate are electrically connected to the second signal line (for transmitting the global second signal Gas1), and the other of the source and drain of the first transistor NT1 is electrically connected to the first node Q1.

[0033] For ease of description later, the second signal Gas1 is applied globally to both the drain and gate of the first transistor NT1. For example Figure 2 and Figure 4 As shown, the source of the first transistor NT1 can be directly electrically connected to the third node Q3 of this stage and indirectly electrically connected to the first node Q1 of this stage. For example... Figure 3 and Figure 5 As shown, the source of the first transistor NT1 can be directly electrically connected to the first node Q1 of this stage and indirectly electrically connected to the third node Q3 of this stage.

[0034] As discussed above, the second signal Gas1 can control the gate potential of the first transistor NT1 in the second output submodule 402 of the multiple gate driving units 20, thereby controlling the first transistor NT1 to transmit the second signal Gas1 to the third node Q3 when it is turned on. This allows the first output submodule 401 to generate the first gate signal based on the first signal, thus avoiding directly outputting the second signal Gas1 as the first gate signal. Furthermore, by shorting the gate and drain of the first transistor NT1, it can be made into a diode structure, reducing the types of signals acting on the first transistor NT1 and simplifying the circuit.

[0035] In some embodiments, such as Figures 2 to 5 As shown, the output module 40 further includes a third output submodule 403 electrically connected to the second node Q2 and the corresponding third signal line (for transmitting the third signal VGL). The third output submodule 403 is used to generate a second gate signal (e.g., a low-potential signal of the gate signal GN of this stage) that is transmitted to the corresponding gate line according to the third signal VGL output by the corresponding third signal line. The second gate signal is used to control the corresponding plurality of sub-pixels 101 to turn off.

[0036] Based on the first output submodule 401 described above, which generates a first gate signal (e.g., a high-potential signal of the gate signal GN of the current level) according to a first signal (i.e., the clock signal CKN of this level) to control the opening of the corresponding multiple sub-pixels 101, this embodiment further sets a third output submodule 403 to generate a second gate signal (e.g., a low-potential signal of the gate signal GN of the current level) according to a corresponding third signal VGL to control the closing of the corresponding multiple sub-pixels 101. Thus, by controlling the first output submodule 401 and the third output submodule 403 to work alternately, the gate line alternately outputs a higher-potential first gate signal and a lower-potential second gate signal to form a complete gate signal GN of the current level, so as to control the opening of the sub-pixels 101 of the corresponding row when the gate signal is the first gate signal in each frame.

[0037] In some embodiments, such as Figure 2 and Figure 3 As shown, the second output submodule 402 further includes: a second transistor NT2, the gate of the second transistor NT2 being electrically connected to the second signal line (for transmitting the global second signal Gas1), and one of the source and drain of the second transistor NT2 being electrically connected to the second node Q2. The second transistor NT2 is used to control the signal of the second node Q2 according to the second signal Gas1. When the second signal Gas1 controls multiple first output submodules 401 to generate the first gate signal (e.g., a high-potential signal of the gate signal GN of this stage), the multiple second transistors NT2 are respectively used to control the signals of the corresponding multiple second nodes Q2 so that the multiple third output submodules 403 do not output the second gate signal (e.g., a low-potential signal of the gate signal GN of this stage).

[0038] For ease of description later, this example uses the second transistor NT2 with its gate loaded with the global second signal Gas1, its source loaded with the global third signal VGL, and its drain electrically connected to the second node Q2 of this stage.

[0039] Understandably, in this embodiment, the second output submodule 402 is configured to also include a second transistor NT2 that controls the signal of the second node Q2 according to the second signal Gas1, so that the second output submodules 402 in the plurality of gate driving units 20 all control the signal of the second node Q2 according to the second signal Gas1, so that when the plurality of first output submodules 401 generate the first gate signal according to the first signal to control the sub-pixels 101 of all rows to be turned on, the second signal Gas1 can control the second transistor NT2 to be turned on to transmit the third signal VGL to the second node Q2, so that the third output submodule 403 does not work, thereby not outputting the second gate signal to avoid affecting the current potential of the gate signal GN of this stage.

[0040] In some embodiments, such as Figures 2 to 5 As shown, the input module 30 includes a third transistor NT3, the gate of which is electrically connected to the first node Q1, and one of the source and drain of the third transistor NT3 is electrically connected to the second node Q2. The third transistor NT3 is used to control the signal of the second node Q2 according to the signal of the first node Q1, so that the third output submodule 403 does not output the second gate signal (e.g., the low potential signal of the gate signal GN of this stage) when the first output submodule 401 generates the first gate signal (e.g., a high potential signal of the gate signal GN of this stage).

[0041] When the second signal Gas1 controls multiple first output submodules 401 to generate the first gate signal, multiple third transistors are respectively used to control the signals of the corresponding multiple second nodes so that the corresponding multiple third output submodules do not output the second gate signal.

[0042] For ease of description later, this example illustrates the following: the gate of the third transistor NT3 is directly electrically connected to the first node Q1 of this stage and indirectly electrically connected to the third node Q3 of this stage; its source is loaded with the global third signal VGL; and its drain is electrically connected to the second node Q2 of this stage.

[0043] Understandably, in this embodiment, the input module 30 is configured to include a third transistor NT3 that controls the signal of the second node Q2 according to the signal of the first node Q1. This not only enables each third transistor NT3 to control the corresponding third output submodule 403 not to output the second gate signal when the input module 30 controls the first output submodule 401 to generate the first gate signal by controlling the signal of the first node Q1, but also enables the multiple third transistors NT3 to control the multiple third output submodules 403 not to output the second gate signal when the second signal Gas1 controls multiple first output submodules 401 to generate the first gate signal. Thus, when multiple gate driving units 20 output the corresponding multiple gate pulses sequentially or multiple gate driving units 20 output the corresponding multiple gate pulses simultaneously, it can prevent the corresponding gate driving unit 20 or multiple gate driving units 20 from not outputting the second gate signal, so as to avoid affecting the current potential of the gate signal GN of this stage.

[0044] In some embodiments, such as Figures 2 to 5 As shown, the input module 30 includes: a first input submodule 301, electrically connected to the forward scan line (for transmitting the forward scan signal U2D), the reverse scan line (for transmitting the reverse scan signal D2U), the first signal line of the first i-th stage (for transmitting the clock signal CKN-i of the first i-th stage), and the first signal line of the last i-th stage (for transmitting the clock signal CKN+i of the last i-th stage), including a fourth transistor NT4 electrically connected to the second node Q2, one of the source and drain of the fourth transistor NT4 being electrically connected to the fourth signal line (for transmitting the global fourth signal Gas3), and the other of the source and drain of the fourth transistor NT4 being electrically connected to the second node Q2; wherein, when the second signal Gas1 controls multiple first output submodules 401 to generate the first gate signal, the multiple fourth transistors NT4 are respectively used to control the signal of the corresponding second node Q2 so that the corresponding multiple third output submodules 403 do not output the second gate signal.

[0045] Comparing the previous discussion of the third transistor NT3, the fourth transistor NT4 in this embodiment is also included in the input module 30. However, its gate can be considered to be controlled by the combined action of the forward scan signal U2D, the reverse scan signal D2U, the clock signal CKN-i of the previous i-stage, and the clock signal CKN+i of the subsequent i-stage, thereby controlling the fourth transistor NT4 to be turned on or off. As discussed above, when the second signal Gas1 controls multiple first output sub-modules 401 to generate the first gate signal, the forward scan signal U2D, the reverse scan signal D2U, the clock signal CKN-i of the previous i-stage, and the clock signal CKN+i of the subsequent i-stage can control the corresponding multiple fourth transistors NT4 to be turned on. It can be considered that at this time, the global fourth signal Gas3 is transmitted to the corresponding multiple second nodes Q2, thereby controlling multiple third output sub-modules 403 not to output the second gate signal, so as to avoid affecting the current potential of the gate signal GN of this stage.

[0046] In some embodiments, such as Figures 2 to 5 As shown, the output module 40 further includes: a fifth transistor NT5, one of the source and drain of the fifth transistor NT5 is electrically connected to the input module 30 through the first node Q1, and the other is electrically connected to the first output submodule 401 through the third node Q3. The gate of the fifth transistor NT5 is electrically connected to the fifth signal line, and the fifth signal VGH transmitted by the fifth signal line is used to turn on the fifth transistor NT5; wherein, the other of the source and drain of the first transistor NT1 is (directly) electrically connected to the first node Q1 and (indirectly) electrically connected to the third node Q3. Figure 3 and Figure 5 As shown), or (directly) electrically connected to the third node Q3, or (indirectly) electrically connected to the first node Q1 (as shown). Figure 2 and Figure 4 (As shown).

[0047] For ease of description later, this example illustrates the fifth transistor NT5, whose gate is electrically connected to the fifth signal line to load the fifth signal VGH, whose source is directly electrically connected to the first node Q1, and whose drain is directly electrically connected to the third node Q3.

[0048] In this embodiment, a fifth transistor NT5, which is normally turned on by the fifth signal VGH (a constant voltage signal), is set between the first node Q1 and the third node Q3. On the one hand, the effective potential of the first node Q1 can be transmitted to the third node Q3 to control the first output submodule 401 to generate and output the first gate signal. On the other hand, the fifth transistor NT5 itself has a certain on-state voltage drop, so it can prevent the transmission of ultra-low or ultra-high potentials of the third node Q3 to the first node Q1, thereby avoiding affecting the working state and lifespan of the device acted upon by the first node Q1.

[0049] Therefore, as Figure 2 and Figure 4 As shown, the source of the first transistor NT1 is directly electrically connected to the third node Q3. When the global second signal Gas1 controls multiple first transistors NT1 to be turned on, the second signal Gas1 is transmitted to the third node Q3 to control multiple first output sub-modules 401 to work, thereby generating and outputting the first gate signal. Furthermore, if the potential of the second signal Gas1 is too high or too low, it will not affect the potential of the first node Q1. Figure 3 and Figure 5 As shown, the source of the first transistor NT1 is directly electrically connected to the first node Q1. When the second signal Gas1 controls multiple first transistors NT1 to be turned on, the second signal Gas1 is transmitted to the first node Q1 and further transmitted to the third node Q3. While controlling multiple first output sub-modules 401 to work and generate and output the first gate signal, it is also beneficial to control the third transistor NT3 to be turned on and the third output sub-module 403 to be turned off, thereby avoiding the third output sub-module 403 from outputting the second gate signal and reducing the impact on the current potential of the gate signal GN of this stage.

[0050] In some embodiments, such as Figures 2 to 5 As shown, the first output submodule 401 includes: a sixth transistor NT6, the gate of the sixth transistor NT6 is electrically connected to the first node (at least including the first node Q1), one of the source and drain of the sixth transistor NT6 is electrically connected to the corresponding first signal line (for transmitting the first signal (i.e., the clock signal CKN of this stage mentioned above)), and the other of the source and drain of the sixth transistor NT6 is electrically connected to the corresponding gate line; wherein, the ratio of the width to the length of the channel of the sixth transistor NT6 is greater than the ratio of the width to the length of the channel of the first transistor NT1.

[0051] The ratio of the channel width to the length of a transistor can affect its current driving capability and switching speed. Specifically, a larger ratio of channel width to length enhances the transistor's current driving capability, which helps improve the circuit's operating speed and response capability, as well as shorten the transistor's switching time and improve the circuit's efficiency.

[0052] As discussed above, the gate of the sixth transistor NT6 is controlled by the signal of the first node Q1. When the signal of the first node Q1 controls the sixth transistor NT6 to be turned on, the clock signal CKN of this stage can be transmitted to the gate line through the sixth transistor NT6 as the first gate signal. The first transistor NT1 is used as the signal to control the first node Q1 to control the sixth transistor NT6 to be turned on or off.

[0053] Understandably, in this embodiment, the ratio of the width to the length of the channel of the sixth transistor NT6 is set to be relatively large, which makes the current driving capability of the sixth transistor NT6 larger, the operating speed and response capability higher, and can quickly turn on to transmit the first gate signal to the gate line, and can improve the reliability of transmitting the first gate signal.

[0054] In some embodiments, combined with Figures 2 to 9 As shown, the first signal (i.e., the clock signal CKN of this stage) includes a first sub-signal with different amplitudes (e.g., one of the high-potential signal and the low-potential signal) and a second sub-signal (e.g., the other of the high-potential signal and the low-potential signal). When the sixth transistor NT6 changes from off to on (e.g., when...), Figure 9 (At the start of the second stage t2 in the process), the first signal changes from the first sub-signal to the second sub-signal.

[0055] Understandably, since the first signal is applied to the source of the sixth transistor NT6, and there is a bootstrap capacitor between the source and gate of the sixth transistor NT6, the moment when the first signal changes from the first sub-signal to the second sub-signal is set to be the same as the moment when the sixth transistor NT6 changes from off to on. On the one hand, when the sixth transistor NT6 is on, the first gate signal output by the sixth transistor NT6 can be used as the second sub-signal in time. On the other hand, when the sixth transistor NT6 is on, the potential jump of the first signal can further increase or decrease the potential of the first node through the effect of the bootstrap capacitor, thereby increasing the conduction degree of the sixth transistor NT6 and further facilitating its output of the second sub-signal as the first gate signal.

[0056] Furthermore, the first input submodule 301 may further include a seventh transistor NT7 and an eighth transistor NT8. The input module 30 may also include a second input submodule 302, a third input submodule 303, an eleventh transistor NT11, a first capacitor C1, and a second capacitor C2. The second input submodule 302 may include a ninth transistor NT9, and the third input submodule 303 may include a tenth transistor NT10. The third output submodule 403 may include a twelfth transistor NT12, and the output module 40 may further include a fourth output submodule 404, which may include a thirteenth transistor NT13. The connection relationships of the transistors and the signals they carry can be found in [reference needed]. Figures 2 to 5 As shown.

[0057] refer to Figure 6 and Figure 7The figures shown are waveforms of "gate signal-time" in the comparative example and embodiment of the present invention, respectively. Based on the above n-row sub-pixels 101, the corresponding n-level gate signals, and the corresponding n-level gate pulses, L1 to Ln here can be schematic diagrams of the waveforms of the first-level gate signal to the nth-level gate signal after aligning their respective gate pulses.

[0058] like Figure 6 As shown in the comparative example, the output terminal (source or drain) of the first transistor NT1 can be considered directly connected to the corresponding gate line. As discussed above, since the second signal Gas1 is directly used to output multiple gate signals, the load on the second signal Gas1 is relatively large. Therefore, the rising and falling edges of the gate pulse in the corresponding gate signal are relatively slow, and its amplitude (e.g., 6.5V) also has a large attenuation. The gate pulse of the first-level gate signal located at the far end of the display panel 10 is attenuated more severely than the gate pulse of the nth-level gate signal located at the near end.

[0059] like Figure 7 As shown in the example, since the second signal Gas1 is no longer directly used to output multiple gate signals, but instead controls the signal of the first node Q1, so that the first output submodule 401 generates the first gate signal according to the first signal, the second signal Gas1 and the first transistor NT1 no longer need a large driving force. Therefore, the rising and falling edges of the gate pulse in the corresponding gate signal are steeper, and the attenuation of its amplitude (e.g., 10V) is also smaller.

[0060] The present invention provides a driving method for a display device, which is applied to the display device described above. The driving method for the display device includes, but is not limited to, the following embodiments and combinations thereof.

[0061] In some embodiments, combined with Figure 8 As shown, the driving method for the display device includes, but is not limited to, the following steps:

[0062] S1, control the input module to control the signal of the first node and the signal of the second node according to the frame start signal, the gate signal of the first i stage and the gate signal of the last i stage, where i is a positive integer;

[0063] As discussed above, for the first-stage gate driving unit 20, the input module 30 controls the signal of the first node Q1 and the signal of the second node Q2 according to the frame start signal and the gate signal GN+i of the next i-th stage; for the non-first-stage gate driving unit 20, the input module 30 controls the signal of the first node Q1 and the signal of the second node Q2 according to the gate signal GN-i of the previous i-th stage and the gate signal GN+i of the next i-th stage.

[0064] S2, control the first output submodule to generate a first gate signal that is transmitted to the corresponding gate line according to the signal of the first node, the signal of the second node and the first signal, the first gate signal is used to control the corresponding multiple sub-pixels to turn on;

[0065] As can be seen from the above discussion, the input module 30 controls the signals of the first node and the second node, and then controls whether the first output sub-module 401 generates a first gate signal (e.g., a high-potential signal of the gate signal GN of the current stage) to be transmitted to the corresponding gate line according to the corresponding first signal (e.g., the clock signal CKN of this stage) in order to control the multiple sub-pixels 101 to be turned on.

[0066] S3, control the second output submodule of the plurality of gate driving units to control the signal of the first node according to the second signal output by the same second signal line, so that the first output submodule generates the first gate signal.

[0067] As discussed above, the global second signal Gas1 can control the signals of the corresponding multiple first nodes by controlling the second output sub-modules in the multiple gate drive units 20, so that the corresponding multiple first output sub-modules 401 generate the first gate signal.

[0068] Therefore, in this embodiment, neither the second signal Gas1 nor the first transistor NT1 requires a large driving force to output the first gate signal. Since each first signal line has fewer gate driving units 20 electrically connected to it compared to the second signal line, resulting in a smaller load, the attenuation of the amplitude of the first gate signal generated according to the first signal is also smaller, which is beneficial for fully and simultaneously opening multiple rows of sub-pixels 101.

[0069] To better explain the principles of the aforementioned display device and its driving method, such as Figure 9 As shown, taking the example that all the above-mentioned transistors are N-type transistors, the present invention will explain the working stage of the Nth gate driving unit 20 in the above-mentioned display device 100 as follows:

[0070] In the scanning phase T1, taking forward scanning as an example, the forward scan signal U2D is at a high potential and the reverse scan signal D2U is at a low potential, so that the seventh transistor NT7 is turned on and the eighth transistor NT8 is turned off. Furthermore, the scanning phase T1 may include, but is not limited to, the following phases:

[0071] In the first stage t1, the clock signal CKN-i of the previous i-stage is at a high potential and the clock signal CKN+i of the next i-stage is at a low potential. Therefore, the clock signal CKN+i of the next i-stage, which is at a low potential, is transmitted to the fourth transistor NT4 to control its cutoff. At the same time, the gate signal GN-i of the previous i-stage is at a high potential and the gate signal GN+i of the next i-stage is at a low potential, so that the ninth transistor NT9 is turned on and the tenth transistor NT10 is turned off. Therefore, the forward scan signal U2D, which is at a high potential, is transmitted to the first node Q1 and the third node Q3, so that the sixth transistor NT6 is turned on to output the current high potential of the clock signal CKN of this stage as the current potential of the gate signal GN of this stage.

[0072] In the second stage t2, the clock signals CKN-i of the previous i-stage and CKN+i of the next i-stage are both at their corresponding low potentials. Therefore, the fourth transistor NT4 remains off. At the same time, the gate signals GN-i of the previous i-stage and GN+i of the next i-stage are both at their corresponding low potentials. Therefore, the ninth transistor NT9 remains on and the tenth transistor NT10 remains off. This allows the ninth transistor NT9 to remain on, which in turn allows the sixth transistor NT6 to be on, outputting the current high potential of the clock signal CKN of this stage as the current potential of the gate signal GN of this stage, which is the first gate signal gn1.

[0073] In the third stage t3, the clock signal CKN-i of the previous i-stage is at a low potential and the clock signal CKN+i of the next i-stage is at a high potential. Therefore, the clock signal CKN+i of the next i-stage with the corresponding high potential is transmitted to the fourth transistor NT4 to control its conduction. Then, the fourth signal Gas3 with the corresponding high potential is transmitted to the second node Q2, so that the twelfth transistor NT12 is turned on to output the third signal VGL as the current potential of the gate signal GN of this stage, that is, the current potential is the second gate signal gn2.

[0074] In the fourth stage t4, compared to the third stage t3, all the transistors mentioned above maintain their previous operating states, so the gate signal GN in this stage remains at its previous potential.

[0075] During the fully open phase T2, both the forward scan signal U2D and the reverse scan signal D2U are at their corresponding high potentials, causing the seventh transistor NT7 and the eighth transistor NT8 to be turned on. In particular, the clock signals of multiple stages (including but not limited to the clock signals CKN-i of the previous i-stage and CKN+i of the next i-stage) are at their corresponding high potentials, so the fourth transistor NT4 of multiple stages is turned on. Therefore, the fourth signal Gas3, which is at its corresponding low potential globally, is transmitted to the second node Q2, causing the twelfth transistor NT12 to be turned off. In particular, the gate signals of multiple stages (including but not limited to the gate signals GN-i of the previous i-stage and GN+i of the next i-stage) are at their corresponding high potentials, so the ninth transistor NT9 and the tenth transistor NT10 of multiple stages are turned on. The first node Q1 and the third node Q3 are at their corresponding high potentials, so the sixth transistor NT6 of multiple stages is turned on to output the current low potential of the clock signal CKN of this stage as the current potential of the gate signal GN of this stage.

[0076] At the same time, the global second signal Gas1, which corresponds to the high potential, controls the first transistor NT1 and the second transistor NT2 of the multi-stage circuit to be turned on, thereby also controlling the third node Q3 to be at the corresponding high potential, thereby stabilizing the conduction state of the sixth transistor NT6, and transmitting the third signal VGL to the second node Q2 to turn off the twelfth transistor NT12.

[0077] During the fully off phase T3, the global sixth signal Gas2 is at a high potential, controlling the thirteenth transistor NT13 of the multi-stage to conduct, so as to transmit the third signal VGL to the gate lines of the multi-stage as the gate signal of the multi-stage.

[0078] In this invention, the global signal can be understood as acting simultaneously on multiple levels of gate driving units 20, rather than being set differently for different gate driving units 20.

[0079] Understandably, in the fully open phase T2 of this invention, the global second signal Gas1 is no longer directly used to output multiple gate signals. Instead, it is controlled by the signals of the first nodes of multiple levels, so that the first output submodules 401 of multiple levels generate and output the first gate signal according to the first signal. This can reduce the attenuation of the amplitude of the first gate signal of multiple levels. At the same time, by setting the forward scan signal U2D, the reverse scan signal D2U, and the clock signals of multiple levels to their corresponding high potentials, the high potential of the first node is further stabilized, and the potential of the second node Q2 is pulled down, thereby reducing the impact on the first gate signal.

[0080] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display device, characterized in that, A gate driving circuit comprising multiple sub-pixels and electrically connected to the multiple sub-pixels, the gate driving circuit comprising multiple cascaded gate driving units, the gate driving unit comprising: The input module is electrically connected to one of the frame start line, the gate line of the first i-th stage, and the gate line of the last i-th stage, and is used to control the signal of the first node and the signal of the second node, where i is a positive integer; An output module is electrically connected to the input module through the first node and the second node. The output module includes a first output sub-module, which is electrically connected to the first node and the corresponding first signal line. The first output sub-module is used to generate a first gate signal that is transmitted to the corresponding gate line according to the first signal output by the corresponding first signal line. The first gate signal is used to control the corresponding plurality of sub-pixels to turn on. The output module further includes a second output submodule, which is electrically connected to the second signal line and the first node. The second output submodules in the plurality of gate driving units are all electrically connected to the same second signal line to control the signal of the first node according to the second signal output by the second signal line, so that the first output submodule generates the first gate signal according to the first signal.

2. The display device according to claim 1, characterized in that, The second output submodule includes: The first transistor has one of its source, one of its drain, and its gate electrically connected to the second signal line, and the other of its source and drain is electrically connected to the first node.

3. The display device according to claim 2, characterized in that, The output module further includes a third output submodule, which is electrically connected to the second node and the corresponding third signal line. The third output submodule is used to generate a second gate signal that is transmitted to the corresponding gate line according to the third signal output by the corresponding third signal line. The second gate signal is used to control the corresponding plurality of sub-pixels to turn off.

4. The display device according to claim 3, characterized in that, The second output submodule also includes: The second transistor has its gate electrically connected to the second signal line, and one of its source and drain electrically connected to the second node. The second transistor is used to control the signal of the second node according to the second signal. When the second signal controls multiple first output submodules to generate the first gate signal, multiple second transistors are respectively used to control the signals of the corresponding multiple second nodes so that the multiple third output submodules do not output the second gate signal.

5. The display device according to claim 3, characterized in that, The input module includes: A third transistor, the gate of which is electrically connected to the first node, and one of the source and drain of which is electrically connected to the second node, is used to control the signal of the second node according to the signal of the first node, so that the third output submodule does not output the second gate signal when the first output submodule generates the first gate signal.

6. The display device according to claim 5, characterized in that, When the second signal controls multiple first output submodules to generate the first gate signal, multiple third transistors are respectively used to control the signals of the corresponding multiple second nodes so that the corresponding multiple third output submodules do not output the second gate signal.

7. The display device according to claim 3, characterized in that, The input module includes: The first input submodule is electrically connected to the forward scan line, the reverse scan line, the first signal line of the first i-th stage, and the first signal line of the last i-th stage. The first input submodule includes a fourth transistor electrically connected to the second node. One of the source and drain of the fourth transistor is electrically connected to the fourth signal line, and the other of the source and drain of the fourth transistor is electrically connected to the second node. When the second signal controls multiple first output submodules to generate the first gate signal, multiple fourth transistors are respectively used to control the signals of the corresponding second nodes so that the corresponding multiple third output submodules do not output the second gate signal.

8. The display device according to any one of claims 2 to 7, characterized in that, The output module also includes: The fifth transistor has one of its source and drain electrically connected to the input module through the first node, and the other electrically connected to the first output sub-module through the third node. The gate of the fifth transistor is electrically connected to the fifth signal line, and the fifth signal transmitted by the fifth signal line is used to turn on the fifth transistor. The source or drain of the first transistor is electrically connected to either the first node or the third node.

9. The display device according to any one of claims 2 to 7, characterized in that, The first output submodule includes: A sixth transistor, wherein the gate of the sixth transistor is electrically connected to the first node, one of the source and drain of the sixth transistor is electrically connected to the corresponding first signal line, and the other of the source and drain of the sixth transistor is electrically connected to the corresponding gate line. The ratio of the width to the length of the channel of the sixth transistor is greater than the ratio of the width to the length of the channel of the first transistor.

10. The display device according to claim 9, characterized in that, The first signal includes a first sub-signal and a second sub-signal with different amplitudes. When the sixth transistor changes from off to on, the first signal changes from the first sub-signal to the second sub-signal.

11. A driving method for a display device, characterized in that, The display device includes multiple sub-pixels and a gate driving circuit electrically connected to the multiple sub-pixels. The gate driving circuit includes multiple cascaded gate driving units. Each gate driving unit includes an input module, a first output sub-module, and a second output sub-module. The driving method of the display device includes: The input module controls the signals of the first node and the second node based on one of the frame start signal, the gate signal of the first i stage, and the gate signal of the last i stage, where i is a positive integer; The first output submodule is controlled to generate a first gate signal that is transmitted to the corresponding gate line based on the signal of the first node, the signal of the second node and the first signal. The first gate signal is used to control the corresponding multiple sub-pixels to turn on. Multiple second output submodules are controlled to control the signal of the first node according to the second signal output from the same second signal line, so that the first output submodule generates the first gate signal.

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