Memory device and operating method of the memory device

Abstract

A memory device and an operating method of the memory device are provided. The memory device includes: a memory block including a plurality of memory cells; a peripheral circuit configured to perform a plurality of read voltage application operations and a plurality of word line setting operations on the memory block; and a control logic configured to control the peripheral circuit to perform a plurality of word line setting operations to set a plurality of word line potentials of the word lines included in the memory block, in which at least one word line setting operation among the plurality of word line setting operations is used to set a word line potential higher than the word line potential set by the other word line setting operations.

Description

Technical Field

[0001] Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a memory device and an operating method of the memory device. Background Art

[0002] Regarding the recent paradigm of the computer environment has shifted to a ubiquitous computing environment where computing systems can be used anytime and anywhere. This has prompted an increasing use of portable electronic devices such as mobile phones, digital cameras, laptop computers, etc. These portable electronic devices typically may include a memory system using a memory device (i.e., a data storage device). The data storage device serves as a main memory device or an auxiliary memory device of the portable electronic device.

[0003] Since there is no mechanical drive component, the data storage device using the memory device has excellent stability and durability, a high information access speed, and low power consumption. In an example of a memory system having these advantages, the data storage device includes a universal serial bus (USB) memory device, a memory card having various interfaces, a solid state drive (SSD), etc.

[0004] Memory devices are roughly classified into volatile memory devices and non-volatile memory devices.

[0005] Compared with volatile memory devices, non-volatile memory devices have relatively slow write and read speeds, but retain the stored data even when the power supply is interrupted. Therefore, non-volatile memory devices are used to store data that needs to be retained regardless of whether the power is supplied. Examples of non-volatile memory include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is classified into NOR type flash memory and NAND type flash memory. Summary of the Invention

[0006] According to an embodiment of the present disclosure, there is provided a memory device including: a storage block including a plurality of memory cells; a peripheral circuit configured to perform a plurality of read voltage application operations and a plurality of word line setting operations on the storage block; and a control logic configured to control the peripheral circuit to perform a plurality of word line setting operations to set a plurality of word line potentials of word lines included in the storage block, wherein at least one of the plurality of word line setting operations is used to set a word line potential higher than the word line potentials set by other word line setting operations.

[0007] According to an embodiment of the present disclosure, there is provided a memory device, which includes: a memory block including a plurality of memory cells; a peripheral circuit configured to alternately perform a plurality of read voltage application operations and a plurality of word line setting operations on the memory block; and a control logic configured to set a first specific word line setting operation, which is performed just before a first specific read voltage application operation using the highest read voltage among the plurality of read voltage application operations, among the plurality of word line setting operations to a word line potential higher than the word line potentials of other word line setting operations, and control the peripheral circuit such that the word lines of the memory block have the set word line potentials.

[0008] According to an embodiment of the present disclosure, there is provided a method of operating a memory device, the method including the steps of: performing a first word line setting operation for controlling a plurality of word lines of a memory block to have a first voltage level; performing a first read voltage application operation on a selected word line; after performing the first read voltage application operation, performing a second word line setting operation for controlling the selected word line to have a second voltage level; performing a second read voltage application operation on the selected word line; after performing the second read voltage application operation, performing a third word line setting operation for controlling the selected word line to have a third voltage level; and performing a third read voltage application operation on the selected word line, wherein a third voltage level of the third word line setting operation, which is performed just before the third read voltage application operation using the highest read voltage among the first read voltage application operation, the second read voltage application operation, and the third read voltage application operation, is higher than each of the first voltage level and the second voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Examples of embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

[0010] In the drawings, for clarity of illustration, the dimensions may be exaggerated. It will be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or there may also be one or more intervening elements. The same reference numerals always denote the same elements.

[0011] Figure 1 is a diagram showing a memory system according to an embodiment of the present disclosure.

[0012] Figure 2 is showing Figure 1 an embodiment of the memory device shown.

[0013] Figure 3 is showing Figure 2 an embodiment of the memory block shown.

[0014] Figure 4It is a diagram showing an embodiment of a memory block having a three-dimensional configuration.

[0015] Figure 5 It is a diagram showing the threshold voltage distribution of a three-level cell according to an embodiment of the present disclosure and the bits of each page corresponding thereto.

[0016] Figure 6 It is a diagram showing a read operation of a memory device according to an embodiment of the present disclosure.

[0017] Figure 7 It is a diagram showing the voltage applied to a word line in a read operation of a memory device according to an embodiment of the present disclosure.

[0018] Figure 8 It is a diagram showing the threshold voltage distribution of a three-level cell according to an embodiment of the present disclosure and the bits of each page corresponding thereto.

[0019] Figure 9 It is a diagram showing a read operation of a memory device according to an embodiment of the present disclosure.

[0020] Figure 10 It is a diagram showing the voltage applied to a word line in a read operation of a memory device according to an embodiment of the present disclosure.

[0021] Figure 11 It is a diagram showing an embodiment of a memory system.

[0022] Figure 12 It is a diagram showing an embodiment of a memory system.

[0023] Figure 13 It is a diagram showing an embodiment of a memory system.

[0024] Figure 14 It is a diagram showing an embodiment of a memory system. Detailed Embodiments

[0025] The specific structural or functional descriptions disclosed herein are merely illustrative and are for describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0026] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical spirit of the present disclosure.

[0027] Various embodiments provide a memory device and an operation method thereof, which can increase the speed of a read operation by shortening the rise time of a read voltage corresponding to a relatively high programming state.

[0028] Figure 1 FIG. is a diagram showing a memory system according to an embodiment of the present disclosure.

[0029] Referring to Figure 1 , the memory system 1000 may include a memory device 1100 that stores data and a storage controller 1200 that controls the memory device 1100 under the control of a host 2000.

[0030] The host 2000 may communicate with the memory system 1000 by using an interface protocol such as Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). Additionally, the interface protocol between the host 2000 and the memory system 1000 is not limited to the above examples and may be one of other interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0031] The storage controller 1200 may control the overall operation of the memory system 1000 and control data exchange between the host 2000 and the memory device 1100. For example, the storage controller 1200 may control the memory device 1100 to program or read data according to a request from the host 2000. In a programming operation, the storage controller 1200 may send a command CMD, an address ADD, and data DATA to be programmed to the memory device 1100. Additionally, in a read operation, the storage controller 1200 may receive the data DATA read from the memory device 1100 and store it for a predetermined duration, and send the stored data DATA to the host 2000. The term "predetermined" used herein with respect to a parameter (e.g., predetermined duration) means that the value of the parameter is determined before using the parameter in a process or algorithm. For some embodiments, the value of the parameter is determined before the start of the process or algorithm. In other embodiments, the value of the parameter is determined during the process or algorithm but before using the parameter in the process or algorithm.

[0032] The memory device 1100 may perform a programming operation, a read operation, or an erase operation under the control of the storage controller 1200.

[0033] In some embodiments, the memory device 1100 may include a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), a Low Power Double Data Rate 4 (LPDDR4) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, a Low Power DDR (LPDDR), a Rambus Dynamic Random Access Memory (RDRAM), or a flash memory.

[0034] Figure 2 is shownFigure 1 Diagram of the memory device shown

[0035] Referring to Figure 2 , the memory device 1100 may include a memory cell array 100 that stores data. The memory device 1100 may include a peripheral circuit 200 configured to perform a programming operation for storing data in the memory cell array 100, a read operation for outputting the stored data, and an erase operation for erasing the stored data. The memory device 1100 may include a control logic 300 that controls the peripheral circuit 200 under the control of a storage controller ( Figure 1 1200 shown). The control logic 300 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 300 may be a control logic circuit operating according to an algorithm and / or a processor executing control logic code.

[0036] The memory device 1100 according to an embodiment of the present disclosure performs a plurality of read voltage application operations corresponding to a plurality of programming states, respectively, in a read operation, and may adjust the potential of a word line to a positive voltage level higher than 0V just before the read voltage application operation corresponding to the highest programming state.

[0037] The memory cell array 100 may include a plurality of memory blocks MB1 to MBk 110 (k is a positive integer). Local lines LL and bit lines BL1 to BLm (m is a positive integer) may be connected to each of the memory blocks MB1 to MBk 110. For example, the local line LL may include a first selection line, a second selection line, and a plurality of word lines arranged between the first selection line and the second selection line. Additionally, the local line LL may include dummy lines arranged between the first selection line and the word lines and between the second selection line and the word lines. The first selection line may be a source selection line, and the second selection line may be a drain selection line. For example, the local line LL may include word lines, a drain selection line, a source selection line, and a source line SL. For example, the local line LL may further include dummy lines. For example, the local line LL may further include pipeline lines. The local line LL may be connected to each of the memory blocks MB1 to MBk 110, and the bit lines BL1 to BLm may be commonly connected to the memory blocks MB1 to MBk 110. The memory blocks MB1 to MBk 110 may be implemented as a two-dimensional or three-dimensional structure. For example, memory cells may be arranged in a direction parallel to the substrate in a memory block 110 having a two-dimensional structure. For example, memory cells may be stacked in a direction perpendicular to the substrate in a memory block 110 having a three-dimensional structure.

[0038] The peripheral circuit 200 can be configured to perform programming operations, read operations, and erase operations on the selected memory block 110 under the control of the control logic 300. For example, the peripheral circuit 200 may include a voltage generation circuit 210, a row decoder 220, a page buffer bank 230, a column decoder 240, an input / output circuit 250, a pass / fail check circuit 260, and a source line driver 270.

[0039] The voltage generation circuit 210 can generate various operation voltages Vop for programming operations, read operations, and erase operations in response to the operation signal OP_CMD. Additionally, the voltage generation circuit 210 can selectively discharge the local line LL in response to the operation signal OP_CMD. For example, the voltage generation circuit 210 can generate a programming voltage, a verification voltage, a read voltage, a pass voltage, a plurality of set voltages, etc. under the control of the control logic 300. The voltage generation circuit 210 can adjust the potential of the word line to a set value after the read voltage application operation under the control of the word line voltage setting component 310 of the control logic 300.

[0040] The row decoder 220 can transfer the operation voltage Vop to the local line LL connected to the selected memory block 110 in response to the row decoder control signal AD_signals. For example, in a programming operation, in response to the row decoder control signal AD_signals, the row decoder 220 can apply the programming voltage generated by the voltage generation circuit 210 to the selected word line among the local lines LL and apply the pass voltage generated by the voltage generation circuit 210 to the unselected word lines. In a read operation, in response to the row decoder control signal AD_signals, the row decoder 220 can sequentially apply the plurality of read voltages generated by the voltage generation circuit 210 to the selected word line among the local lines LL and apply the pass voltage generated by the voltage generation circuit 210 to the unselected word lines.

[0041] The page buffer bank 230 may include a plurality of page buffers PB1 to PBm 231 connected to bit lines BL1 to BLm. The page buffers PB1 to PBm 231 can operate in response to the page buffer control signal PBSIGNALS. For example, in a programming operation, the page buffers PB1 to PBm 231 can temporarily store the data to be programmed for a predetermined duration and control the potential levels of the bit lines BL1 to BLm based on the temporarily stored data to be programmed. Additionally, in a read operation or a programming verification operation, the page buffers PB1 to PBm 231 can sense the voltage or current of the bit lines BL1 to BLm.

[0042] The column decoder 240 may transfer data between the input / output circuit 250 and the page buffer bank 230 in response to a column address CADD. For example, the column decoder 240 may exchange data with the page buffer 231 through data lines DL, or exchange data with the input / output circuit 250 through column lines CL.

[0043] The input / output circuit 250 may transfer a command CMD and an address ADD transmitted from a memory controller ( Figure 1 shown as 1200) to the control logic 300, or exchange data DATA with the column decoder 240.

[0044] In a read operation or a program verification operation, the pass / fail check circuit 260 may generate a reference current in response to an enable bit VRY_BIT<#>, and output a pass signal PASS or a fail signal FAIL by comparing a sense voltage VPB received from the page buffer bank 230 with a reference voltage generated by the reference current. The sense voltage VPB may be a voltage controlled based on the number of memory cells determined to be passed in a program verification operation.

[0045] The source line driver 270 may be connected to memory cells included in the memory cell array 100 through source lines SL, and control the voltage applied to the source lines SL. The source line driver 270 may receive a source line control signal CTRL_SL from the control logic 300, and control the source line voltage applied to the source lines SL based on the source line control signal CTRL_SL.

[0046] The control logic 300 may control the peripheral circuit 200 by outputting operation signals OP_CMD, row decoder control signals AD_signals, page buffer control signals PBSIGNALS, and an enable bit VRY_BIT<#> in response to a command CMD and an address ADD.

[0047] The control logic 300 may control the peripheral circuit 200 to perform a read operation on a selected memory block. For example, the control logic 300 may control the peripheral circuit 200 to perform a read voltage application operation of applying a plurality of read voltages corresponding to a plurality of program states, respectively, in a read operation on the selected memory block. In addition, when a read voltage application operation is completed, the control logic 300 may control the peripheral circuit 200 to perform a word line setting operation of setting the word lines of the selected memory block to a set level before performing the next read voltage application operation. The control logic 300 may control the peripheral circuit 200 such that the potential of the word lines has a positive voltage level higher than 0V in the word line setting operation just before performing the read voltage application operation of the read voltage corresponding to the highest program state among the plurality of read voltages.

[0048] The control logic 300 may include a word line voltage setting component 310. The word line voltage setting component 310 may set the potential of a word line during a word line setting operation between multiple read voltage application operations. The word line voltage setting component 310 may control the peripheral circuit 200 such that the potential of the word line has a positive voltage level higher than 0V during a word line setting operation just before a specific read voltage application operation that executes a read voltage corresponding to the highest programming state among multiple read voltages. Additionally, the word line voltage setting component 310 may control the peripheral circuit 200 such that the potential of the word line becomes 0V during a word line setting operation just before a read voltage application operation other than the specific read voltage application operation.

[0049] Figure 3 is a diagram showing Figure 2 the storage block shown.

[0050] Referring to Figure 3 , in the storage block 110, multiple word lines arranged in parallel with each other may be connected between a first selection line and a second selection line. The first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. For example, the storage block 110 may include multiple strings ST connected between bit lines BL1 to BLm and a source line SL. The bit lines BL1 to BLm may be respectively connected to the strings ST, and the source line SL may be commonly connected to the strings ST. The strings ST may be configured identically to each other. Therefore, as an example, the string ST connected to the first bit line BL1 will be described in detail.

[0051] The string ST may include a source selection transistor SST, multiple memory cells F1 to F16, and a drain selection transistor DST connected in series between the source line SL and the first bit line BL1. At least one source selection transistor SST and at least one drain selection transistor DST may be included in one string ST, and the number of memory cells included in one string ST may be greater than the number of memory cells F1 to F16 shown in the figure.

[0052] The source of the source selection transistor SST can be connected to the source line SL, and the drain of the drain selection transistor DST can be connected to the first bit line BL1. Memory cells F1 to F16 can be connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the source selection transistors SST included in different strings ST can be connected to the source selection line SSL, the gates of the drain selection transistors DST included in different strings ST can be connected to the drain selection line DSL, and the gates of the memory cells F1 to F16 included in different strings ST can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST can be referred to as a physical page PPG. Therefore, physical pages PPG corresponding to the number of the word lines WL1 to WL16 can be included in the memory block 110.

[0053] Figure 4 is a diagram showing an embodiment of a memory block in a three-dimensional configuration.

[0054] Referring to Figure 4 , the memory cell array 100 may include a plurality of memory blocks MB1 to MBk 110. The memory block 110 may include a plurality of strings ST11 to ST1m and ST21 to ST2m. In an embodiment, each of the plurality of strings ST11 to ST1m and ST21 to ST2m may be formed in an "I" shape or a "U" shape. In the first memory block MB1, m strings may be arranged in the row direction (X direction). Although Figure 4 shows a case where two strings are arranged in the column direction (Y direction), this is for convenience of description, and three or more strings may be arranged in the column direction (Y direction).

[0055] Each of the plurality of strings ST11 to ST1m and ST21 to ST2m may include at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain selection transistor DST.

[0056] The source selection transistor SST of each string can be connected between the source line SL and the memory cells MC1 to MCn. The source selection transistors of the strings arranged in the same row can be connected to the same source selection line. The source selection transistors of the strings ST11 to ST1m arranged in the first row can be connected to the first source selection line SSL1. The source selection transistors of the strings ST21 to ST2m arranged in the second row can be connected to the second source selection line SSL2. In another embodiment, the source selection transistors of the strings ST11 to ST1m and ST21 to ST2m can be commonly connected to one source selection line.

[0057] The first memory cell MC1 to the n-th memory cell MCn of each string may be connected in series with each other between a source select transistor SST and a drain select transistor DST. The gates of the first memory cell MC1 to the n-th memory cell MCn may be connected to the first word line WL1 to the n-th word line WLn, respectively.

[0058] In an embodiment, at least one of the first memory cell MC1 to the n-th memory cell MCn may be used as a dummy memory cell. When a dummy memory cell is provided, in an embodiment, the voltage or current of the corresponding string may be stably controlled. Therefore, in an embodiment, the reliability of the data stored in the memory block 110 may be improved.

[0059] The drain select transistor DST of each string may be connected between a bit line and the memory cells MC1 to MCn. The drain select transistors DST of the strings arranged in the row direction may be connected to a drain select line extending in the row direction. The drain select transistors DST of the strings ST11 to ST1m on the first row may be connected to the first drain select line DSL1. The drain select transistors DST of the strings ST21 to ST2m on the second row may be connected to the second drain select line DSL2.

[0060] Figure 5 is a diagram showing the threshold voltage distribution of a triple-level cell according to an embodiment of the present disclosure and the bits of each page corresponding thereto.

[0061] Referring to Figure 5 , this embodiment will be described with reference to the graph of a triple-level cell (TLC). The horizontal axis represents the threshold voltage (e.g., the level of the threshold voltage), and the vertical axis represents the number of memory cells. The TLC may have an erased state E with sequentially increasing threshold voltage distributions and one of the first to seventh programmed states P1, P2, P3, P4, P5, P6, and P7.

[0062] In the TLC, the first read voltage VR1 may be a voltage for distinguishing the erased state E and the first programmed state P1 from each other. The second read voltage VR2 may be a voltage for distinguishing the first programmed state P1 and the second programmed state P2 from each other. The third read voltage VR3 may be a voltage for distinguishing the second programmed state P2 and the third programmed state P3 from each other. The fourth read voltage VR4 may be a voltage for distinguishing the third programmed state P3 and the fourth programmed state P4 from each other. The fifth read voltage VR5 may be a voltage for distinguishing the fourth programmed state P4 and the fifth programmed state P5 from each other. The sixth read voltage VR6 may be a voltage for distinguishing the fifth programmed state P5 and the sixth programmed state P6 from each other. The seventh read voltage VR7 may be a voltage for distinguishing the sixth programmed state P6 and the seventh programmed state P7 from each other.

[0063] Referring to the TLC table, the first logical page bit 1st Page, the second logical page bit 2nd Page, and the third logical page bit 3rd Page according to the cell state are shown. The first logical page bit 1st Page, the second logical page bit 2nd Page, and the third logical page bit 3rd Page may be the least significant bit (LSB), the center significant bit (CSB), and the most significant bit (MSB). In an embodiment, the first logical page bit 1st Page, the second logical page bit 2nd Page, and the third logical page bit 3rd Page may be the least significant bit (LSB), the center significant bit (CSB), and the most significant bit (MSB), respectively. In an embodiment, the first logical page bit 1st Page, the second logical page bit 2nd Page, and the third logical page bit 3rd Page may be the most significant bit (MSB), the center significant bit (CSB), and the least significant bit (LSB), respectively.

[0064] In the read operation of the memory block including the above TLC, a read voltage application operation may be performed for each logical page bit. For example, a first read voltage application operation of applying a first read voltage VR1 and a fifth read voltage VR5 may be performed to read the first logical page bit 1st Page, a second read voltage application operation of applying a second read voltage VR2, a fourth read voltage VR4, and a sixth read voltage VR6 may be performed to read the second logical page bit 2nd Page, and a third read voltage application operation of applying a third read voltage VR3 and a seventh read voltage VR7 may be performed to read the third logical page bit 3rd Page.

[0065] The first read voltage application operation, the second read voltage application operation, and the third read voltage application operation may be performed in sequence.

[0066] Figure 6 FIG. is a diagram illustrating a read operation of a memory device according to an embodiment of the present disclosure.

[0067] Figure 7 FIG. is a diagram illustrating voltages applied to word lines in a read operation of a memory device according to an embodiment of the present disclosure.

[0068] The read operation of the memory device according to an embodiment of the present disclosure will be described below with reference to Figures 2 to 7 description.

[0069] In an embodiment of the present disclosure, as an example, a read operation of a selected word line of a selected memory block (e.g., MB1) including TLC will be described.

[0070] In step S610, the word line voltage setting component 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the first voltage V1. The first voltage V1 can be 0V or a positive voltage higher than 0V.

[0071] The voltage generation circuit 210 generates the first voltage V1 under the control of the word line voltage setting component 310, and the row decoder 220 applies the first voltage V1 to the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1, thereby performing a word line setting operation. That is, within a duration t1, the first voltage V1 is applied to the selected word line Sel WL and the unselected word lines Unsel WLs.

[0072] In step S620, the control logic 300 controls the peripheral circuit 200 to perform a first read voltage application operation for reading the first logic page bit 1st Page among a plurality of logic page bits stored in the memory cells connected to the selected word line Sel WL.

[0073] The first read voltage application operation can be an operation of applying a first read voltage VR1 and a fifth read voltage VR5 to the selected word line Sel WL, which can classify the data value of the first logic page bit 1st Page as 0 or 1. In the first read voltage application operation, the fifth read voltage VR5 having a high potential level selected from the first read voltage VR1 and the fifth read voltage VR5 can be first applied to the selected word line Sel WL, and then the first read voltage VR1 can be applied to the selected word line Sel WL.

[0074] For example, the voltage generation circuit 210 can sequentially generate the fifth read voltage VR5 and the first read voltage VR1 under the control of the control logic 300. The row decoder 220 applies the fifth read voltage VR5 to the selected word line Sel WL of the selected memory block MB1 for a specific time, and then applies the first read voltage VR1 to the selected word line Sel WL of the selected memory block MB1 for a specific time. In addition, the voltage generation circuit 210 generates a pass voltage Vpass. When the fifth read voltage VR5 and the first read voltage VR1 are applied to the selected word line Sel WL, the row decoder 220 applies the pass voltage Vpass to the unselected word lines Unsel WLs. That is, within a duration t2, the fifth read voltage VR5 and the first read voltage VR1 are sequentially applied to the selected word line Sel WL, and the pass voltage Vpass is applied to the unselected word lines Unsel WLs.

[0075] Thereafter, the page buffer group 230 senses the voltage or current of the bit lines BL1 to BLm, thereby storing the data value of the first logic page bit 1st Page of the memory cells connected to the selected word line Sel WL.

[0076] In step S630, the word line voltage setting component 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the second voltage V2. The second voltage V2 may have the same potential as the first voltage V1. For example, the second voltage V2 may be 0V or a positive voltage higher than 0V.

[0077] The voltage generation circuit 210 generates the second voltage V2 under the control of the word line voltage setting component 310, and the row decoder 220 applies the second voltage V2 to the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1, thereby performing a word line setting operation. That is, during the duration t3, the second voltage V2 is applied to the selected word line Sel WL and the unselected word lines Unsel WLs.

[0078] In an embodiment, when the potential of the selected word line Sel WL is higher than the potential of the second voltage V2, the row decoder 220 can discharge the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs to the level of the second voltage V2 without the voltage generation operation of the voltage generation circuit 210.

[0079] In step S640, the control logic 300 controls the peripheral circuit 200 to perform a second read voltage application operation for reading the second logic page bit 2nd Page among a plurality of logic page bits stored in the memory cells connected to the selected word line Sel WL.

[0080] The second read voltage application operation may be an operation of applying the second read voltage VR2, the fourth read voltage VR4, and the sixth read voltage VR6 to the selected word line Sel WL, which can classify the data value of the second logic page bit 2nd Page as 0 or 1. In the second read voltage application operation, the sixth read voltage VR6, the fourth read voltage VR4, and the second read voltage VR2 may be sequentially applied to the selected word line Sel WL in the order of higher potential levels among the second read voltage VR2, the fourth read voltage VR4, and the sixth read voltage VR6.

[0081] For example, the voltage generation circuit 210 can sequentially generate the sixth read voltage VR6, the fourth read voltage VR4, and the second read voltage VR2 under the control of the control logic 300. The row decoder 220 applies the sixth read voltage VR6 to the selected word line Sel WL of the selected memory block MB1 for a specific time, and then applies the fourth read voltage VR4 to the selected word line Sel WL of the selected memory block MB1 for a specific time. Thereafter, the row decoder 220 applies the second read voltage VR2 to the selected word line Sel WL of the selected memory block MB1 for a specific time.

[0082] In addition, the voltage generation circuit 210 generates a pass voltage Vpass. When the sixth read voltage VR6, the fourth read voltage VR4, and the second read voltage VR2 are applied to the selected word line Sel WL, the row decoder 220 applies the pass voltage Vpass to the unselected word lines Unsel WLs. That is, within a duration t4, the sixth read voltage VR6, the fourth read voltage VR4, and the second read voltage VR2 are sequentially applied to the selected word line Sel WL, and the pass voltage Vpass is applied to the unselected word lines Unsel WLs.

[0083] Thereafter, the page buffer group 230 senses the voltages or currents of the bit lines BL1 to BLm, thereby storing the data values of the second logic page bits 2nd Page of the memory cells connected to the selected word line Sel WL.

[0084] In step S650, the word line voltage setting component 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the third voltage V3. The potential of the third voltage V3 may be higher than the potential of each of the first voltage V1 and the second voltage V2. For example, the third voltage V3 may be a positive voltage higher than 0V. In an embodiment, just before the read voltage application operation using the seventh read voltage VR7 corresponding to the seventh programming state P7, which is a relatively high threshold voltage distribution among the multiple programming states P1 to P7, the word line voltage setting component 310 may set the potential of the word line to a positive voltage level higher than 0V. That is, just before the seventh read voltage VR7, which has the highest potential level among the multiple read voltages VR1 to VR7 corresponding to the multiple programming states P1 to P7, is applied to the selected word line Sel WL, the control logic 300 may control the peripheral circuit 200 to adjust the potential of the word line to a positive voltage level higher than 0V. As used herein, performing a first operation just before a second operation means that there is no additional operation between the first operation and the second operation. For example, as Figure 7 shown, the word line setting operation for setting the third voltage V3 is performed just before the read voltage application operation using the seventh read voltage VR7.

[0085] The voltage generation circuit 210 generates the third voltage V3 under the control of the word line voltage setting component 310, and the row decoder 220 applies the third voltage V3 to the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1, thereby performing the word line setting operation. That is, within a duration t5, the third voltage V3 is applied to the selected word line Sel WL and the unselected word lines Unsel WLs.

[0086] In another embodiment, when the potential of the selected word line Sel WL is higher than the potential of the third voltage V3, the row decoder 220 may discharge the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs to the level of the third voltage V3 without the voltage generation operation of the voltage generation circuit 210.

[0087] In step S660, the control logic 300 controls the peripheral circuit 200 to perform a third read voltage application operation for reading the third logic page bit 3rd Page among a plurality of logic page bits stored in the memory cells connected to the selected word line Sel WL.

[0088] The third read voltage application operation may be an operation of applying the third read voltage VR3 and the seventh read voltage VR7 to the selected word line Sel WL, which may classify the data value of the third logic page bit 3rd Page as 0 or 1. In the third read voltage application operation, the seventh read voltage VR7 having a high potential level selected from the third read voltage VR3 and the seventh read voltage VR7 may be first applied to the selected word line Sel WL, and then the third read voltage VR3 may be applied to the selected word line Sel WL.

[0089] For example, the voltage generation circuit 210 may sequentially generate the seventh read voltage VR7 and the third read voltage VR3 under the control of the control logic 300. The row decoder 220 applies the seventh read voltage VR7 to the selected word line Sel WL of the selected memory block MB1 for a specific time, and then applies the third read voltage VR3 to the selected word line Sel WL of the selected memory block MB1 for a specific time. In addition, the voltage generation circuit 210 generates a pass voltage Vpass. When the seventh read voltage VR7 and the third read voltage VR3 are applied to the selected word line Sel WL, the row decoder 220 applies the pass voltage Vpass to the unselected word lines Unsel WLs. That is, within the duration t6, the seventh read voltage VR7 and the third read voltage VR3 are sequentially applied to the selected word line Sel WL, and the pass voltage Vpass is applied to the unselected word lines Unsel WLs.

[0090] Thereafter, the page buffer bank 230 senses the voltages or currents of the bit lines BL1 to BLm, thereby storing the data value of the third logic page bit 3 rd Page of the memory cells connected to the selected word line Sel WL.

[0091] During a duration t6, the voltage generation circuit 210 increases the potential of the word line that has been controlled to a positive voltage level during a duration t5 to the level of a seventh read voltage VR7. In an embodiment of the operation of increasing the potential of the word line from the level of a third voltage V3 having a positive potential to the level of the seventh read voltage VR7, compared with the operation of increasing the potential of the word line from 0V to the level of the seventh read voltage VR7, the operation time is reduced and the power consumption of the voltage generation circuit 210 is also reduced.

[0092] In step S670, the word line voltage setting component 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of a fourth voltage V4. The fourth voltage V4 may have the same potential as the first voltage V1 and the second voltage V2. For example, the fourth voltage V4 may be 0V or a positive voltage higher than 0V. In some embodiments, performing a second operation right after a first operation means that there is no additional operation between the first operation and the second operation. For example, as Figure 7 shown, right after performing a third read voltage application operation on the selected word line Sel WL, a fourth word line setting operation of controlling the selected word line Sel WL to have the fourth voltage V4 is performed.

[0093] The row decoder 220 may discharge the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs to the level of the fourth voltage V4, thereby performing a word line setting operation.

[0094] In the above embodiment of the present disclosure, it is described that the potential of the word line is set to a positive voltage level right before a seventh read voltage having a relatively highest potential among a plurality of read voltages is applied to the selected word line Sel WL. In another embodiment, the potential of the word line may be set to a positive voltage level right before at least one read voltage having a relatively high potential among a plurality of read voltages is applied to the selected word line Sel WL. For example, right before a third read voltage application operation using the seventh read voltage VR7, the potential of the word line may be set to the third voltage V3, and right before a second read voltage application operation using the sixth read voltage VR6, the potential of the word line may be set to a level that is the third voltage V3 or lower than the third voltage V3 and higher than the first voltage V1.

[0095] Figure 8 is a diagram showing the threshold voltage distribution of a three-level cell according to an embodiment of the present disclosure and the bits of each corresponding page.

[0096] Refer to Figure 8, this embodiment will be described with reference to the curve graph of a triple-level cell (TLC). The horizontal axis represents the threshold voltage (e.g., the level of the threshold voltage), and the vertical axis represents the number of memory cells. The TLC can have an erase state E with successively increasing threshold voltage distributions and one of the first to seventh programming states P1, P2, P3, P4, P5, P6, and P7.

[0097] In the TLC, the first read voltage VR1 can be a voltage for distinguishing the erase state E and the first programming state P1 from each other. The second read voltage VR2 can be a voltage for distinguishing the first programming state P1 and the second programming state P2 from each other. The third read voltage VR3 can be a voltage for distinguishing the second programming state P2 and the third programming state P3 from each other. The fourth read voltage VR4 can be a voltage for distinguishing the third programming state P3 and the fourth programming state P4 from each other. The fifth read voltage VR5 can be a voltage for distinguishing the fourth programming state P4 and the fifth programming state P5 from each other. The sixth read voltage VR6 can be a voltage for distinguishing the fifth programming state P5 and the sixth programming state P6 from each other. The seventh read voltage VR7 can be a voltage for distinguishing the sixth programming state P6 and the seventh programming state P7 from each other.

[0098] Referring to the table of the TLC, the first logical page bit 1st Page, the second logical page bit 2nd Page, and the third logical page bit 3rd Page according to the cell state are shown. The first logical page bit 1st Page, the second logical page bit 2nd Page, and the third logical page bit 3rd Page can be the least significant bit (LSB), the middle significant bit (CSB), and the most significant bit (MSB), respectively.

[0099] In the read operation of the memory block including the above-mentioned TLC, the read voltage application operation can be performed for each logical page bit. For example, the first read voltage application operation of applying the fourth read voltage VR4 can be performed to read the third logical page bit 3rd Page. The second read voltage application operation of applying the first read voltage VR1, the third read voltage VR3, and the sixth read voltage VR6 can be performed to read the second logical page bit 2nd Page. Additionally, the third read voltage application operation of applying the second read voltage VR2 and the fifth read voltage VR5 can be performed to read the first logical page bit 1st Page.

[0100] The first read voltage application operation, the second read voltage application operation, and the third read voltage application operation can be performed in sequence.

[0101] Figure 9 It is a diagram showing the read operation of the memory device according to an embodiment of the present disclosure.

[0102] Figure 10It is a diagram showing the voltage applied to a word line in a read operation of a memory device according to an embodiment of the present disclosure.

[0103] The read operation of the memory device according to an embodiment of the present disclosure will be described below with reference to Figures 2 to 4 and Figures 8 to 10 as follows.

[0104] In an embodiment of the present disclosure, as an example, a read operation of a selected word line of a selected memory block (e.g., MB1) including TLC will be described.

[0105] In step S910, the word line voltage setting component 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the first voltage V1. The first voltage V1 can be 0V or a positive voltage higher than 0V.

[0106] The voltage generation circuit 210 generates the first voltage V1 under the control of the word line voltage setting component 310, and the row decoder 220 applies the first voltage V1 to the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1, thereby performing a word line setting operation. That is, within a duration t11, the first voltage V1 is applied to the selected word line Sel WL and the unselected word lines Unsel WLs.

[0107] In step S920, the control logic 300 controls the peripheral circuit 200 to perform a first read voltage application operation for reading the third logic page bit 3rd Page among a plurality of logic page bits stored in the memory cells connected to the selected word line Sel WL.

[0108] The first read voltage application operation can be an operation of applying a fourth read voltage VR4 to the selected word line Sel WL, which can classify the data value of the third logic page bit 3rd Page as 0 or 1.

[0109] For example, the voltage generation circuit 210 can generate the fourth read voltage VR4 under the control of the control logic 300. The row decoder 220 applies the fourth read voltage VR4 to the selected word line Sel WL of the selected memory block MB1 for a specific time. In addition, the voltage generation circuit 210 generates a pass voltage Vpass. When the fourth read voltage VR4 is applied to the selected word line Sel WL, the row decoder 220 applies the pass voltage Vpass to the unselected word lines Unsel WLs. That is, within a duration t12, the fourth read voltage VR4 is applied to the selected word line Sel WL, and the pass voltage Vpass is applied to the unselected word lines Unsel WLs.

[0110] Thereafter, the page buffer group 230 senses the voltages or currents of the bit lines BL1 to BLm, thereby storing the data values of the third logic page bits 3rd Page of the memory cells connected to the selected word line Sel WL.

[0111] In step S930, the word line voltage setting component 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the second voltage V2. The second voltage V2 may have the same potential as the first voltage V1. For example, the second voltage V2 may be 0V or a positive voltage higher than 0V.

[0112] The voltage generation circuit 210 generates the second voltage V2 under the control of the word line voltage setting component 310, and the row decoder 220 applies the second voltage V2 to the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1, thereby performing a word line setting operation. That is, within the duration t13, the second voltage V2 is applied to the selected word line Sel WL and the unselected word lines Unsel WLs.

[0113] In an embodiment, when the potential of the selected word line Sel WL is higher than the potential of the second voltage V2, the row decoder 220 may discharge the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs to the level of the second voltage V2 without the voltage generation operation of the voltage generation circuit 210.

[0114] In step S940, the control logic 300 controls the peripheral circuit 200 to perform a second read voltage application operation for reading the second logic page bits 2nd Page among the multiple logic page bits stored in the memory cells connected to the selected word line Sel WL.

[0115] The second read voltage application operation may be an operation of applying the first read voltage VR1, the third read voltage VR3, and the sixth read voltage VR6 to the selected word line Sel WL, which can classify the data values of the second logic page bits 2nd Page as 0 or 1. In the second read voltage application operation, the sixth read voltage VR6, the third read voltage VR3, and the first read voltage VR1 may be sequentially applied to the selected word line Sel WL in the order of the higher potential levels among the first read voltage VR1, the third read voltage VR3, and the sixth read voltage VR6.

[0116] For example, the voltage generation circuit 210 may sequentially generate a sixth read voltage VR6, a third read voltage VR3, and a first read voltage VR1 under the control of the control logic 300. The row decoder 220 applies the sixth read voltage VR6 to the selected word line Sel WL of the selected memory block MB1 for a specific time, and then applies the third read voltage VR3 to the selected word line Sel WL of the selected memory block MB1 for a specific time. Thereafter, the row decoder 220 applies the first read voltage VR1 to the selected word line Sel WL of the selected memory block MB1 for a specific time.

[0117] In addition, the voltage generation circuit 210 generates a pass voltage Vpass. When the sixth read voltage VR6, the third read voltage VR3, and the first read voltage VR1 are applied to the selected word line Sel WL, the row decoder 220 applies the pass voltage Vpass to the unselected word lines Unsel WLs. That is, within a duration t14, the sixth read voltage VR6, the third read voltage VR3, and the first read voltage VR1 are sequentially applied to the selected word line Sel WL, and the pass voltage Vpass is applied to the unselected word lines Unsel WLs.

[0118] Thereafter, the page buffer group 230 senses the voltage or current of the bit lines BL1 to BLm, thereby storing the data value of the second logic page bit 2nd Page of the memory cells connected to the selected word line Sel WL.

[0119] In step S950, the word line voltage setting component 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of a third voltage V3. The potential of the third voltage V3 may be higher than the potential of each of the first voltage V1 and the second voltage V2. For example, the third voltage V3 may be a positive voltage higher than 0V. In an embodiment, just before the read voltage application operation using the seventh read voltage VR7 corresponding to the seventh programming state P7 which is a relatively high threshold voltage distribution among the plurality of programming states P1 to P7, the word line voltage setting component 310 may set the potential of the word line to a positive voltage level higher than 0V. That is, just before the seventh read voltage VR7 having the highest potential level among the plurality of read voltages VR1 to VR7 corresponding to the plurality of programming states P1 to P7 is applied to the selected word line Sel WL, the control logic 300 may control the peripheral circuit 200 to adjust the potential of the word line to a positive voltage level higher than 0V.

[0120] The voltage generation circuit 210 generates a third voltage V3 under the control of the word line voltage setting component 310, and the row decoder 220 applies the third voltage V3 to the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1, thereby performing a word line setting operation. That is, within a duration t15, the third voltage V3 is applied to the selected word line Sel WL and the unselected word lines Unsel WLs.

[0121] In an embodiment, when the potential of the selected word line Sel WL is higher than the potential of the third voltage V3, the row decoder 220 can discharge the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs to the level of the third voltage V3 without the voltage generation operation of the voltage generation circuit 210.

[0122] In step S960, the control logic 300 controls the peripheral circuit 200 to perform a third read voltage application operation for reading a first logic page bit 1st Page among a plurality of logic page bits stored in a memory cell connected to the selected word line Sel WL.

[0123] The third read voltage application operation may be an operation of applying a second read voltage VR2, a fifth read voltage VR5, and a seventh read voltage VR7 to the selected word line Sel WL, which can classify the data value of the first logic page bit 1st Page as 0 or 1. In the third read voltage application operation, the seventh read voltage VR7 having a high potential level among the second read voltage VR2, the fifth read voltage VR5, and the seventh read voltage VR7 may be first applied to the selected word line Sel WL, and then the fifth read voltage VR5 may be applied to the selected word line Sel WL. The fifth read voltage VR5 may be applied to the selected word line Sel WL, and then the second read voltage VR2 may be applied to the selected word line Sel WL.

[0124] For example, the voltage generation circuit 210 may sequentially generate the seventh read voltage VR7, the fifth read voltage VR5, and the second read voltage VR2 under the control of the control logic 300. The row decoder 220 applies the seventh read voltage VR7 to the selected word line Sel WL of the selected memory block MB1 for a specific time, and then applies the fifth read voltage VR5 to the selected word line Sel WL of the selected memory block MB1 for a specific time. Thereafter, the row decoder 220 applies the second read voltage VR2 to the selected word line Sel WL of the selected memory block MB1 for a specific time.

[0125] In addition, the voltage generation circuit 210 generates a pass voltage Vpass. When the seventh read voltage VR7, the fifth read voltage VR5, and the second read voltage VR2 are applied to the selected word line Sel WL, the row decoder 220 applies the pass voltage Vpass to the unselected word lines Unsel WLs. That is, within a duration t16, the seventh read voltage VR7, the fifth read voltage VR5, and the second read voltage VR2 are sequentially applied to the selected word line Sel WL, and the pass voltage Vpass is applied to the unselected word lines Unsel WLs.

[0126] Thereafter, the page buffer group 230 senses the voltages or currents of the bit lines BL1 to BLm, thereby storing the data values of the first logic page bits 1st Page of the memory cells connected to the selected word line Sel WL.

[0127] Within the duration t16, the voltage generation circuit 210 increases the potential of the word line that was controlled to a positive voltage level within the duration t15 to the level of the seventh read voltage VR7. In an embodiment of the operation of increasing the potential of the word line from the level of the third voltage V3 having a positive potential to the level of the seventh read voltage VR7, compared with the operation of increasing the potential of the word line from 0V to the level of the seventh read voltage VR7, the operation time is reduced and the power consumption of the voltage generation circuit 210 is also reduced.

[0128] In step S970, the word line voltage setting component 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the fourth voltage V4. The fourth voltage V4 may have the same potential as the first voltage V1 and the second voltage V2. For example, the fourth voltage V4 may be 0V or a positive voltage higher than 0V.

[0129] The row decoder 220 may discharge the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs to the level of the fourth voltage V4, thereby performing a word line setting operation.

[0130] In the above embodiments of the present disclosure, it is described that the potential of the word line is set to a positive voltage level before the seventh read voltage having a relatively highest potential among the multiple read voltages is applied to the selected word line Sel WL. In an embodiment, before at least one read voltage having a relatively high potential among the multiple read voltages is applied to the selected word line Sel WL, the potential of the word line may be set to a positive voltage level. For example, before the third read voltage application operation using the seventh read voltage VR7, the potential of the word line may be set to the third voltage V3, and before the second read voltage application operation using the sixth read voltage VR6, the potential of the word line may be set to a level that is the third voltage V3 or lower than the third voltage V3 and higher than the first voltage V1.

[0131] Figure 11 This is a diagram showing an embodiment of a memory system.

[0132] Referring to Figure 11 , the memory system 30000 can be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device. The memory system 30000 may include a memory device 1100 and a storage controller 1200 capable of controlling the operation of the memory device 1100. The storage controller 1200 can control data access operations of the memory device 1100, such as programming operations, erasing operations, read operations, etc., under the control of a processor 3100.

[0133] The data programmed in the memory device 1100 can be output through a display 3200 under the control of the storage controller 1200.

[0134] A radio transceiver 3300 can transmit / receive radio signals through an antenna ANT. For example, the radio transceiver 3300 can change a radio signal received through the antenna ANT into a signal that can be processed by the processor 3100. Therefore, the processor 3100 can process the signal output from the radio transceiver 3300 and send the processed signal to the storage controller 1200 or the display 3200. The storage controller 1200 can send the signal processed by the processor 3100 to the memory device 1100. In addition, the radio transceiver 3300 can change the signal output from the processor 3100 into a radio signal and output the changed radio signal to an external device through the antenna ANT. An input device 3400 is a device capable of inputting a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100, and can be implemented as a pointing device such as a touchpad or a computer mouse, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200 so that the data output from the storage controller 1200, the data output from the radio transceiver 3300, or the data output from the input device 3400 can be output through the display 3200.

[0135] In some embodiments, the storage controller 1200 capable of controlling the operation of the memory device 1100 can be implemented as a part of the processor 3100 or as a chip separate from the processor 3100. In addition, the storage controller 1200 can be implemented as Figure 1 For the example of the storage controller 1200 shown, the memory device 1100 can be implemented as Figure 2 the example of the memory device 1100 shown.

[0136] Figure 12 This is a diagram showing an embodiment of a memory system.

[0137] Reference Figure 12 As shown in Figure 12 , the memory system 40000 can be implemented as a personal computer (PC), a tablet PC, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0138] The memory system 40000 may include a memory device 1100 and a storage controller 1200 capable of controlling data processing operations of the memory device 1100.

[0139] According to the data input through the input device 4200, the processor 4100 may output the data stored in the memory device 1100 through the display 4300. For example, the input device 4200 may be implemented as a pointing device such as a touchpad or a computer mouse, a keypad, or a keyboard.

[0140] The processor 4100 may control the overall operation of the memory system 40000 and control the operation of the storage controller 1200. In some embodiments, the storage controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 4100, or may be implemented as a chip separate from the processor 4100. Additionally, the storage controller 1200 may be implemented as Figure 1 For the example of the storage controller 1200 shown, the memory device 1100 may be implemented as Figure 2 the example of the memory device 1100 shown.

[0141] Figure 13 is a diagram showing an embodiment of the memory system.

[0142] Reference Figure 13 As shown in Figure 13 , the memory system 50000 can be implemented as an image processing device, such as a digital camera, a mobile terminal attached with a digital camera, a smart phone attached with a digital camera, or a tablet PC attached with a digital camera.

[0143] The memory system 50000 may include a memory device 1100 and a storage controller 1200 capable of controlling data processing operations (e.g., programming operations, erasing operations, or read operations) of the memory device 1100.

[0144] The image sensor 5200 of the memory system 50000 may convert an optical image into a digital signal, and the converted digital signal may be sent to the processor 5100 or the storage controller 1200. Under the control of the processor 5100, the converted digital signal may be output through the display 5300 or stored in the memory device 1100 through the storage controller 1200. Additionally, the data stored in the memory device 1100 may be output through the display 5300 under the control of the processor 5100 or the storage controller 1200.

[0145] In some embodiments, a storage controller 1200 that can control the operation of a memory device 1100 may be implemented as part of a processor 5100 or as a chip separate from the processor 5100. Additionally, the storage controller 1200 may be implemented as Figure 1 In the example of the storage controller 1200 shown, the memory device 1100 may be implemented as Figure 2 the example of the memory device 1100 shown.

[0146] Figure 14 FIG. is a diagram showing an embodiment of a memory system.

[0147] Referring to Figure 14 , the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100, a storage controller 1200, and a card interface 7100.

[0148] The storage controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. In some embodiments, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but the present disclosure is not limited thereto. Additionally, the storage controller 1200 may be implemented as Figure 1 In the example of the storage controller 1200 shown, the memory device 1100 may be implemented as Figure 2 the example of the memory device 1100 shown.

[0149] The card interface 7100 may interface data exchange between the host 60000 and the storage controller 1200 according to the protocol of the host 60000. In some embodiments, the card interface 7100 may support a Universal Serial Bus (USB) protocol and an Inter-Chip (IC)-USB protocol. The card interface 7100 may refer to hardware that can support the protocol used by the host 60000, software embedded in the hardware, or a signal transmission scheme.

[0150] When the memory system 70000 is connected to a host interface 6200 of a host 60000 such as a PC, a tablet PC, a digital camera, a digital audio player, a cellular phone, a video game console hardware, or a digital set-top box, the host interface 6200 may perform data communication with the memory device 1100 through the card interface 7100 and the storage controller 1200 under the control of a microprocessor 6100.

[0151] According to an embodiment of the present disclosure, before applying a read voltage corresponding to a relatively high programming state in a read operation, the potential of a word line is set to a positive voltage level, thereby shortening the rise time of the read voltage. Accordingly, the speed of the read operation may be increased, and power consumption may be reduced.

[0152] Although the present disclosure has been shown and described with reference to its specific embodiments, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0153] In the above embodiments, all steps may be selectively performed, or some steps may be omitted. In each embodiment, these steps do not necessarily have to be performed in the order described and may be rearranged. The embodiments disclosed in this specification and the drawings are only examples for facilitating the understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be obvious to those skilled in the art that various modifications can be made based on the technical scope of the present disclosure.

[0154] In addition, embodiments of the present disclosure are described in the drawings and the specification. Although specific terms are used herein, these terms are only for explaining the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and there may be many variations within the spirit and scope of the present disclosure. It should be obvious to those skilled in the art that various modifications can be made based on the technical scope of the present disclosure in addition to the embodiments disclosed herein.

[0155] Cross - reference to related applications

[0156] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0181556, filed with the Korean Intellectual Property Office on December 14, 2023, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: A memory block, the memory block comprising a plurality of memory cells; a peripheral circuit that performs a plurality of read voltage applying operations and a plurality of word line setting operations on the memory block; as well as A control logic controls the peripheral circuit to perform the plurality of word line setting operations to set a plurality of word line potentials of word lines included in the memory block, wherein at least one word line setting operation among the plurality of word line setting operations is used to set a word line potential higher than word line potentials set by other word line setting operations.

2. The memory device according to claim 1, wherein: The multiple memory cells are capable of being in an erased state and multiple programmed states, and the peripheral circuit applies at least one read voltage among multiple read voltages for distinguishing the erased state and the multiple programmed states to a selected word line among the word lines in each of the multiple read voltage application operations.

3. The memory device according to claim 2, wherein: The peripheral circuit: performing any one of the plurality of word line setting operations between the plurality of read voltage applying operations; and The at least one word line setting operation is performed just before a specific read voltage applying operation using at least one highest read voltage among the plurality of read voltage applying operations is performed.

4. The memory device according to claim 2, wherein: Each of the plurality of read voltage applying operations corresponds to a least significant bit, a middle significant bit, and a most significant bit of the memory cell.

5. The memory device according to claim 1, wherein: The peripheral circuit controls the word line to have a first voltage level in the at least one word line setting operation, and controls the word line to have a second voltage level in the other word line setting operations, and Wherein, the first voltage level is a positive voltage level higher than zero volts.

6. The memory device according to claim 5, wherein: The peripheral circuit controls the word line to have the second voltage level before performing a first read voltage applying operation among the plurality of read voltage applying operations.

7. The memory device according to claim 5, wherein: The peripheral circuit controls the word line to have the second voltage level after performing a final read voltage applying operation among the plurality of read voltage applying operations.

8. The memory device according to claim 1, wherein: The control logic includes a word line voltage setting component, and The word line voltage setting component sets the word line potential in each of the plurality of word line setting operations.

9. A memory device, the memory device comprising: A memory block, the memory block comprising a plurality of memory cells; a peripheral circuit that alternately performs a plurality of read voltage applying operations and a plurality of word line setting operations on the memory block; as well as A control logic that sets a first specific word line setting operation among the multiple word line setting operations, which is performed just before a first specific read voltage application operation using a highest read voltage among the multiple read voltage application operations, to a word line potential that is higher than word line potentials of other word line setting operations, and controls the peripheral circuit so that the word line of the storage block has the set word line potential.

10. The memory device according to claim 9, wherein: The control logic sets a second specific word line setting operation among the multiple word line setting operations, which is performed just before a second specific read voltage application operation using a second high read voltage among the multiple read voltage application operations, to a word line potential that is lower than the word line potential of the first specific word line setting operation and higher than the word line potentials of other word line setting operations except the first specific word line setting operation and the second specific word line setting operation.

11. The memory device according to claim 10, wherein: The peripheral circuit controls the word line to have a first voltage level in the first specific word line setting operation, and controls the word line to have a second voltage level in the other word line setting operations except the first specific word line setting operation and the second specific word line setting operation, and Wherein, the first voltage level is a positive voltage level higher than zero volts.

12. The memory device according to claim 11, wherein: The peripheral circuit controls the word line to have a third voltage level in the second specific word line setting operation, and The third voltage level is a positive voltage level higher than zero volt.

13. The memory device according to claim 11, wherein: The peripheral circuit controls the word line to have the second voltage level before performing a first read voltage applying operation among the plurality of read voltage applying operations.

14. The memory device according to claim 11, wherein: The peripheral circuit controls the word line to have the second voltage level after performing a final read voltage applying operation among the plurality of read voltage applying operations.

15. A method of operating a memory device, the method comprising the steps of: performing a first word line setting operation of controlling a plurality of word lines of a memory block to have a first voltage level; performing a first read voltage application operation on the selected word line; After performing the first read voltage applying operation, performing a second word line setting operation of controlling the selected word line to have a second voltage level; performing a second read voltage application operation on the selected word line; After performing the second read voltage applying operation, performing a third word line setting operation of controlling the selected word line to have a third voltage level; as well as performing a third read voltage application operation on the selected word line, wherein the third voltage level of the third word line setting operation performed just before the third read voltage applying operation using the highest read voltage among the first read voltage applying operation, the second read voltage applying operation, and the third read voltage applying operation is higher than each of the first voltage level and the second voltage level.

16. The method according to claim 15, wherein: The third voltage level is above zero volts.

17. The method according to claim 15, wherein: The second voltage level of the second word line setting operation performed just before the second read voltage applying operation using a second high read voltage among the first read voltage applying operation, the second read voltage applying operation, and the third read voltage applying operation is higher than the first voltage level and lower than the third voltage level.

18. The method according to claim 17, wherein: The second voltage level is above zero volts.

19. The method according to claim 15, wherein: The first read voltage applying operation is an operation for reading the least significant bit of the memory cell connected to the selected word line, wherein the second read voltage application operation is an operation for reading an intermediate valid bit of the memory cell, and The third read voltage application operation is an operation for reading the most significant bit of the memory cell.

20. The method according to claim 15, wherein: The first read voltage applying operation is an operation for reading the most significant bit of the memory cell connected to the selected word line, wherein the second read voltage application operation is an operation for reading an intermediate valid bit of the memory cell, and The third read voltage applying operation is an operation for reading the least significant bit of the memory cell.

21. The method according to claim 15, further comprising the steps of: After performing the third read voltage applying operation on the selected word line, performing a fourth word line setting operation of controlling the selected word line to have a fourth voltage level, The fourth voltage level is lower than the third voltage level.

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