Reliability test method for flash memory particles, readable storage medium and computing equipment

Abstract

The embodiment of the invention provides a reliability testing method for flash memory particles, a readable storage medium and computing equipment, the flash memory particles are divided into a plurality of storage blocks, each storage block comprises a plurality of word lines arranged in sequence, and the method performs the following operations for each storage block: erasing data in the storage block; data are written into the storage pages connected with the word lines at intervals of any number of word lines from a starting word line, and the starting word line is a word line which is not selected; reading the data from the storage page connected with the word line in which the data is written and verifying the data; if the error data proportion is larger than or equal to the error bit threshold value, the storage block is marked as a bad block, and if the error data proportion is smaller than the error bit threshold value, the step of erasing the data in the storage block is skipped to be executed. According to the method, the bad block screening capability in the reliability test is improved by changing the data writing mode.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of memory, and more particularly, to a method for reliability testing of flash memory particles, a readable storage medium, and a computing device. Background Art

[0002] Currently, many storage devices, such as solid state drives, UFS devices, etc., use flash memory storage media (especially NAND-type storage media) as the main storage media, and are gradually becoming the mainstream form. Compared with traditional magnetic medium memories, their performance has achieved a qualitative leap.

[0003] At present, during the mass production process of such storage devices, reliability testing is required to ensure the quality of flash memory particles and screen out flash memory particles that cannot meet the factory standards. Reliability testing generally includes the following processes: writing and verification. First, data is written to the flash memory particles, and then the data is verified. By comparing the error bit value obtained from the verification with the set error bit threshold, it is determined whether the storage block is marked as a bad block; high-temperature aging test, which is usually carried out in a high-temperature environment to accelerate the aging process of the flash memory particles and screen out unstable particles. Generally speaking, the set error bit threshold in writing and verification will increase the number of bad blocks screened out, thereby increasing the number of defective products output by the high-temperature aging test and reducing the product first-pass yield. The first-pass yield refers to the ratio of the number of flash memory particles that pass the reliability test to the number of all flash memory particles participating in the reliability test. Flash memory particles need to reach the set first-pass yield during the mass production process to be eligible for shipment.

[0004] During the mass production process, when a batch of flash memory particles cannot reach the set first-pass yield, the set error bit threshold can also be fine-tuned according to the first-pass yield of this batch of flash memory particles, and then the reliability test is carried out again to meet the factory standards. The fundamental reason for such an operation is actually that the current reliability test has poor screening ability for bad blocks with reliability problems, and it is impossible to screen out bad blocks well with just one test. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a method for reliability testing of flash memory particles, a readable storage medium, and a computing device, which strengthen the screening ability of bad blocks in the reliability test and reduce the number of reliability tests to be carried out by strengthening the screening ability of bad blocks.

[0006] According to a first aspect of the embodiments of the present disclosure, a reliability testing method for flash memory particles is provided. The flash memory particles are divided into multiple storage blocks, and each storage block includes multiple word lines arranged in sequence. Each word line is electrically connected to multiple storage pages. The method performs the following operations for each storage block:

[0007] Erase the data in the storage block;

[0008] Starting from the starting word line, write data into the storage page connected by the word line at intervals of any number of word lines, where the starting word line is a word line that has not been selected;

[0009] Read data from the storage page connected by the word line where the data is written and perform data verification; if the proportion of error data is greater than or equal to the error bit threshold, mark the storage block as a bad block, and if the proportion of error data is less than the error bit threshold, jump to the step of erasing the data in the storage block and execute until all the storage pages connected by all the word lines in the storage block have been written to and read from.

[0010] In some embodiments, determine the number of word lines at intervals according to the number of adjacent word lines affected by read interference.

[0011] In some embodiments, writing data into the storage page connected by the word line at intervals of any number of word lines means: writing data into the storage page connected by the word line at intervals of a fixed one word line.

[0012] In some embodiments, compare the number of error bits of all word lines after read interference on a single storage page with the number of error bits of all word lines before read interference on the single storage page to obtain the number of adjacent word lines affected by the read interference.

[0013] In some embodiments, it further includes:

[0014] For the same batch of flash memory particles that have undergone the reliability test method, select several flash memory particles therefrom for high-temperature baking, and perform data verification on the flash memory particles after high-temperature baking; and

[0015] Calculate the throughput rate of this batch of flash memory particles. If the throughput rate is greater than or equal to the set threshold, mark this batch of flash memory particles as ready for shipment. The throughput rate is the ratio of the number of flash memory particles passing data verification to the number of flash memory particles participating in data verification.

[0016] In some embodiments, it further includes: if the throughput rate is less than the set threshold, adjust the error bit threshold, and based on the adjusted error bit threshold, re-perform the read-write and verification operations on this batch of flash memory particles.

[0017] In some embodiments, only for the same batch of flash memory particles composed of storage units with higher storage density, if the throughput rate is less than the set threshold, adjust the error bit threshold, and based on the adjusted error bit threshold, re-perform the read-write and verification operations on this batch of flash memory particles.

[0018] In some embodiments, the flash memory particles are NAND-type flash memory particles.

[0019] According to a second aspect of the embodiments of the present disclosure, there is provided a computer-readable storage medium for storing one or more computer instructions, which, when executed, implement the reliability test method of any one of the above.

[0020] According to a third aspect of the embodiments of the present disclosure, there is provided a computing device including a memory and a processor, where the memory stores one or more computer instructions, and the computer instructions are executed by the processor to implement the reliability test method of any one of the above.

[0021] The reliability test method provided by the embodiments of the present disclosure modifies the read and write operations on the word lines of the storage block in the prior art to perform read and write operations on any number of word lines at intervals, so as to achieve the purpose of improving the bad block screening ability for flash memory particles by changing the data writing method.

[0022] Furthermore, improving the bad block screening ability can help reduce the number of reliability tests performed to meet the outgoing standard during mass production, contribute to improving production efficiency, and at the same time enhance the reliability of mass-produced flash memory particles. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the embodiments of the present disclosure will become clearer. In the drawings:

[0024] Figure 1 is a schematic structural diagram of a test architecture for implementing a reliability test;

[0025] Figure 2A and 2B is a flowchart of a reliability test method provided by an embodiment of the present disclosure.

[0026] Figure 3 is a schematic diagram of data writing and reading operations on any number of word lines at intervals;

[0027] Figure 4 is a flowchart of a writing and verification process in a reliability test of another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The following describes the embodiments of the present disclosure based on examples, but the embodiments of the present disclosure are not limited to these examples. In the following detailed description of the embodiments of the present disclosure, some specific details are described in detail. Those skilled in the art can fully understand the embodiments of the present disclosure without the description of these details. In order to avoid obscuring the essence of the embodiments of the present disclosure, well-known methods, processes, and procedures are not described in detail. Additionally, the drawings are not necessarily drawn to scale.

[0029] The flowcharts and block diagrams in the accompanying drawings illustrate the possible system frameworks, functions, and operations of the systems, methods, and apparatuses of the embodiments of the present disclosure. The boxes in the flowcharts and block diagrams may represent a module, a program segment, or just a piece of code, and the modules, program segments, and code are all executable instructions for implementing the specified logical functions. It should also be noted that the executable instructions for implementing the specified logical functions can be recombined to generate new modules and program segments. Therefore, the boxes in the accompanying drawings and the order of the boxes are only used to better illustrate the processes and steps of the embodiments, and should not be used as a limitation to the invention itself.

[0030] Figure 1 is a schematic structural diagram of a test architecture for implementing a reliability test. As Figure 1 shown, the test architecture 100 includes a platform under test 101, a control terminal 102, and a test terminal 103.

[0031] The platform under test 101 includes a test chamber 1011 and flash memory particles 1012 to be tested. The test chamber 1011 is used to carry the flash memory particles 1012, and operations such as applying high temperature to the flash memory particles 1012, detecting the real-time temperature, and detecting the disk status are performed through the test chamber 1011. At the same time, the status information fed back is received through the test chamber 1011. The platform under test 101 generally also includes a development board, which can integrate a central processing unit, a control chip of the flash memory particles 1012, a memory, and various interfaces. The control chip of the flash memory particles 1012 is electrically connected to the flash memory particles 1012 through an interface circuit, and a basic operating system can be installed in the memory. The test terminal 103 can be a desktop computer, a laptop, an iPad, etc., and the control terminal 102 can be the control terminal of the test chamber 1011.

[0032] The test terminal 103 can send instructions to the platform under test 101 and receive instruction feedback. Generally, the test terminal 103 sends instructions for writing data and reading data to the flash memory particles 1012, for example. The control terminal 102 sends control instructions to the test chamber 1011, such as applying a high-temperature environment to the test chamber 1011 to perform high-temperature baking on the flash memory particles 1012.

[0033] The test terminal 103 can also input the production information of the flash memory particles (for example, the batch number of the flash memory particles, the name of the production company, the model of the main control chip). The test terminal 103 can also obtain one or more test programs adapted to the production information of the flash memory particles, and execute the corresponding test programs according to a pre-designed test plan and test cases. For example, the reliability test method described below can be formed into such a test program.

[0034] The embodiments of the present disclosure provide a reliability test method. As described in the background art, this method includes two parts. The first part is to write to and verify the flash memory particles, as Figure 2AAs shown, the second part conducts a high-temperature aging test on the flash memory particles, as Figure 2B shown.

[0035] As Figure 2A shown, in step S201, the data of the current storage block is erased. The current storage block is one storage block selected from multiple storage blocks of the flash memory particles in the arranged order.

[0036] In step S202, an unselected word line is selected as the starting word line.

[0037] In step S203, data is written to the storage pages of the current word line at an arbitrary number of word lines intervals from the starting word line.

[0038] In step S204, data is read from the storage pages where data is written and verified.

[0039] In step S205, it is determined whether the number of error bits is greater than or equal to the error bit threshold. If so, step S206 is executed; if not, step S202 is executed.

[0040] In step S206, the current block is marked as a bad block.

[0041] In step S207, it is determined whether all word lines have been checked. If so, step S208 is executed; if not, step S202 is executed.

[0042] In step S208, it is determined whether there are still storage blocks not checked. If so, step S209 is executed; if not, step S210 is executed.

[0043] In step S209, jump to the next storage block

[0044] In step S210, the test result is output.

[0045] Next, refer to Figure 3Describe this embodiment in detail. Assume that the current storage block includes word lines from Wl_0 to Wl_12, and each word line is connected to several storage pages. In the first round of operations, Wl_0 is used as the starting word line, and data is first written to the storage pages connected to the word lines at a fixed interval of two word lines, and then data is read from them for verification. That is, data is first written to the storage pages connected to the word lines Wl_0, Wl_3, Wl_6, Wl_9, and Wl_12, and then data is read from them for verification. If the proportion of incorrect data read is greater than or equal to, for example, 5%, the current storage block is marked as a bad block, and the verification jumps to the next storage block. If the proportion of incorrect data read is less than, for example, 5%, the second round of operations continues. In the second round of operations, Wl_1 is used as the starting word line, and data is first written to the storage pages connected to the word lines Wl_1, Wl_4, Wl_7, and Wl_10, and then data is read from them for verification. If the proportion of incorrect data read is greater than or equal to, for example, 5%, the current storage block is marked as a bad block, and the verification jumps to the next storage block. If the proportion of incorrect data read is less than, for example, 5%, the third round of operations continues. And so on.

[0046] Continue to refer to Figure 3 As shown, according to this embodiment, in each round of operations, the storage pages can also be written with data first, then read and verified at different intervals of the number of word lines. For example, in the first round of operations, the interval is 3 word lines, and in the second round of operations, the interval is 2 word lines, and so on; in the same round of operations, the storage pages can also be written with data first, then read and verified at different intervals of the number of word lines. For example, first, the storage pages of the word lines Wl_0 and Wl_2 are written with data first, then read and verified, and then the storage pages of the word line Wl_6 are written with data first, then read and verified, and so on. In addition, considering the characteristics of the flash memory particles, the number of word lines in the interval can also be larger in the middle position of the flash memory particles and smaller in the edge position.

[0047] In the prior art, in the read and write operations of the reliability test method, data is sequentially written into the memory pages connected to each word line, and after completion, the data is read from the memory pages into which the data has been written. Compared with the prior art, in the reliability test of the embodiments of the present disclosure, read and write operations are performed on word lines spaced by any number of word lines. First, performing read and write operations on word lines spaced by any number of word lines can reduce the number of unnecessary read and write operations, and those unstable memory blocks will be screened out in the first or second round of read and write operations; second, performing read and write operations on word lines spaced by any number of word lines can avoid the interference and delay caused by consecutive word line reads and writes; furthermore, when choosing to write data to word lines spaced by any number of word lines, the unselected word lines in the interval are in the erased state because no data is written. Since the word lines above and below the word lines into which data is written are in the erased state without written data, the arrangement of the written states in the memory block belongs to the situation where the data randomization is uneven. For a memory block with poor data retention ability, the charge leakage speed is relatively faster, which will cause more overlapping states in the threshold voltage distribution of the written data positions. Compared with the memory block with good data retention ability, the number of error bits read will be more, thus amplifying the error characteristics of the memory block with poor data retention ability and being screened out. Therefore, the embodiments of the present disclosure improve the bad block screening ability in the reliability test by changing the read and write method.

[0048] In some embodiments, the number of word lines spaced in this embodiment is determined according to the number of adjacent word lines affected by read interference. Specifically, for different batches of flash memory particles, the number of affected adjacent word lines can be determined through a Single Page Read Disturb (SPRD) experiment. Record the number of error bits of all word lines before and after SPRD on the memory block, and obtain the number of adjacent word lines affected by read interference for this batch of flash memory particles through comparison processing. For example, assume that the memory block has a total of n word lines. After filling it with data and performing a read check, obtain the number of error bits of the n word lines in the first round [errorbit_INIT_0, …, errorbit_INIT_(n - 1)]. Then select a fixed word line position (assume it is m) and send multiple read instructions for SPRD operations. After completion, perform a read check on the memory block again to obtain the number of error bits of the n word line positions in the second round [errorbit_SPRD_0, …, errorbit_SPRD_(n - 1)]. Check whether the increase rate of the number of error bits at the word line positions m ± 1 above and below the word line position where SPRD is performed is greater than the set threshold ratio. If it is greater than the threshold ratio, then continue to check the word line positions ±2 above and below until the increase rate of the number of error bits at the word line positions ±i is less than the set threshold. At this point, the number of adjacent word lines affected by read interference can be determined to be i, where i is a positive integer greater than 1.

[0049] Continue to refer to Figure 2BAs shown Figure 2B shows the process of high-temperature aging test performed on flash memory particles after writing and verification.

[0050] In step S211, data verification is performed on some of the flash memory particles that have undergone high-temperature baking. The high-temperature environment can accelerate the physical changes inside the flash memory particles, such as charge leakage and threshold voltage drift. Moreover, after high-temperature baking, the charge loss rate of the storage blocks with poor data retention ability is faster than that of the storage blocks with good data retention ability, thereby simulating the aging effect after long-term use. Therefore, performing data verification on the flash memory particles after high-temperature baking is equivalent to verifying the data retention ability and read / write stability of the flash memory particles after long-term use. Various verification means can be used for data verification. For example, MD5 verification can be used to verify the integrity of the data and detect whether the data has errors or losses due to high temperature. Another example is to verify whether the read performance of the flash memory after high-temperature baking has decreased through a read speed test.

[0051] In step S212, the throughput rate is calculated based on the data verification result output in step S211. The throughput rate is equal to the ratio of the number of flash memory particles that pass the data verification to the number of flash memory particles participating in the data verification.

[0052] In step S213, it is determined whether the throughput rate meets the requirements. If it does, step S214 is executed; if not, step S215 is executed.

[0053] In step S214, product rework adjustment is performed.

[0054] In step S215, the product is released for shipment.

[0055] Steps S214 and S215 refer to: when the throughput rate of a certain batch of flash memory particles fails to meet the requirements, the error bit threshold in Figure 2A is fine-tuned according to the required throughput rate (minimally affecting the product yield rate), and then the implementation example of Figure 2A is executed from the beginning. Generally, after several rounds of adjustment, the flash memory particles of this batch can meet the required throughput rate, and at this time, the flash memory particles of this batch can be released for shipment. However, for flash memory particles composed of storage units with a relatively high storage density (for example, Quad-Level Cell, four-level storage unit), such adjustment often requires multiple rounds of adjustment to meet the set release standard, and usually at the cost of sacrificing the yield rate. Therefore, for the flash memory particles of the same batch composed of storage units with a relatively high storage density, there is no need for adjustment or it is determined whether the flash memory particles of this batch can be released for shipment after only one or two adjustments.

[0056] Figure 4 is the flowchart of the writing and verification process in the reliability test of another embodiment of the present disclosure.

[0057] As Figure 4 shown, in step S401, the data of the current storage block is erased. The current storage block is a storage block sequentially selected from multiple storage blocks of the flash memory particle.

[0058] In step S402, data is only written to the storage pages of the odd-numbered word lines.

[0059] In step S403, the data read from the storage pages of the odd-numbered word lines is verified.

[0060] In step S404, it is determined whether the number of error bits exceeds a set threshold. If so, step S403 is executed; if not, step S411 is executed.

[0061] In step S405, the data of the current storage block is erased.

[0062] In step S406, data is only written to the storage pages of the even-numbered word lines.

[0063] In step S407, the data read from the storage pages of the even-numbered word lines is verified.

[0064] In step S408, it is determined whether the number of error bits exceeds a set threshold. If so, jump to step S411; if not, step S409 is executed.

[0065] In step S409, it is determined whether there is still a storage block not checked. If so, jump to step S410; if not, step S412 is executed.

[0066] In step S410, jump to the next storage block.

[0067] In step S411, the current storage block is marked as a bad block.

[0068] In step S412, the test result is output.

[0069] Continue with Figure 3The present embodiment will be explained by taking [example]. According to this embodiment, first write data to the storage pages connected to the word lines Wl_0, Wl_2, Wl_4, Wl_6, Wl_8, Wl_10, and Wl_12, and then read the data from them for verification. If the proportion of the read error data is greater than or equal to, for example, 5%, the current storage block is marked as a bad block, and the verification jumps to the next storage block. If the proportion of the read error data is less than, for example, 5%, write data to the storage pages connected to the word lines Wl_1, Wl_3, Wl_5, Wl_7, Wl_9, and Wl_11 first, and then read the data from them for verification. If the proportion of the read error data is greater than or equal to, for example, 5%, the current storage block is marked as a bad block. It should be understood that although this embodiment selects the data writing method of odd word lines first and then even word lines, the data writing method of even word lines first and then odd word lines can also be selected. Both embodiments can achieve the desired technical effects.

[0070] Correspondingly, an embodiment of the present disclosure further provides a computer-readable storage medium. The computer-readable storage medium stores one or more computer instructions, and when the one or more computer instructions are executed, the following steps are implemented: Erase the data in the storage block; starting from the start word line, write data into the storage pages connected to the word lines at intervals of any number of word lines, and the start word line is a word line that has not been selected; read the data from the storage pages connected to the word lines where the data is written and verify the data. If the proportion of the error data is greater than or equal to the error bit threshold, mark the storage block as a bad block. If the proportion of the error data is less than the error bit threshold, jump to the step of erasing the data in the storage block and execute until all the storage pages connected to the word lines in the storage block have been written to and read from.

[0071] Correspondingly, an embodiment of the present disclosure further provides a computing device. The computing device includes a processor and a memory. The memory stores one or more computer instructions that can be executed by the processor. When the one or more computer instructions are executed, the following steps are implemented: Erase the data in the storage block; starting from the start word line, write data into the storage pages connected to the word lines at intervals of any number of word lines, and the start word line is a word line that has not been selected; read the data from the storage pages connected to the word lines where the data is written and verify the data. If the proportion of the error data is greater than or equal to the error bit threshold, mark the storage block as a bad block. If the proportion of the error data is less than the error bit threshold, jump to the step of erasing the data in the storage block and execute until all the storage pages connected to the word lines in the storage block have been written to and read from.

[0072] The above are only the preferred embodiments of the present disclosure, and are not intended to limit the present disclosure. For those skilled in the art, various modifications and variations can be made to the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

[0073] As described above, the embodiments in accordance with the present disclosure do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can make good use of the present disclosure and its modifications based on the present disclosure. The present disclosure is only limited by the claims and their full scope and equivalents.

Claims

1. A reliability test method for a flash memory particle, wherein the flash memory particle is divided into a plurality of storage blocks, each storage block includes a plurality of word lines arranged in sequence, each word line is electrically connected to a plurality of storage pages, and the method performs the following operations for each storage block: Erasing data in the storage block; Starting from a start word line, writing data into a storage page connected to the word line at intervals of any number of word lines, wherein the start word line is a word line that has not been selected; Data is read from the storage page connected to the word line where the data is written and the data is verified. If the proportion of erroneous data is greater than or equal to the error bit threshold, the storage block is marked as a bad block. If the proportion of erroneous data is less than the error bit threshold, the step of erasing the data in the storage block is jumped to execute.

2. The reliability testing method according to claim 1, wherein: The number of spaced word lines is determined according to the number of adjacent word lines affected by the read disturbance.

3. The reliability testing method according to claim 1 or 2, wherein: Writing data into the storage page connected to the word line at intervals of any number of word lines is: writing data into the storage page connected to the word line at intervals of a fixed word line.

4. The reliability testing method according to claim 2, wherein: The number of error bits of all word lines after the single storage page read disturbance is compared with the number of error bits of all word lines before the single storage page read disturbance to obtain the number of adjacent word lines affected by the read disturbance.

5. The reliability testing method according to claim 1, further comprising: For the flash memory particles of the same batch that have been subjected to the reliability test method, data verification is performed on a number of flash memory particles that have been selected and have been subjected to high-temperature baking; as well as The pass rate of the flash memory particles in this batch is calculated. If the pass rate is greater than or equal to the set threshold, the flash memory particles in this batch are marked as qualified to be eliminated. The pass rate is the ratio of the number of flash memory particles that pass the data verification to the number of flash memory particles that participate in the data verification.

6. The reliability testing method according to claim 5, further comprising: If the pass rate is less than the set threshold, the error bit threshold is adjusted, and the read, write and verify operations are re-performed on the batch of flash memory particles based on the adjusted error bit threshold.

7. The reliability testing method according to claim 6, wherein: Only for the flash memory particles of the same batch composed of storage units with higher storage density, if the pass rate is less than the set threshold, the error bit threshold is adjusted, and the flash memory particles of the batch are re-read, written and verified based on the adjusted error bit threshold.

8. The reliability testing method according to claim 1, wherein: The flash memory particles are NAND type flash memory particles.

9. A computer-readable storage medium, used for storing one or more computer instructions, wherein when the computer instructions are executed, the reliability testing method according to any one of claims 1 to 8 is implemented.

10. A computing device, comprising a memory and a processor, wherein the memory stores one or more computer instructions, and the computer instructions are executed by the processor to implement the reliability testing method according to any one of claims 1 to 8.

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