Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a redistribution layer; a plurality of through molded vias on the redistribution layer; a photonic integrated circuit on the redistribution layer; a first molding layer on the redistribution layer, on a side surface of the through-molding via, and on a side surface of the photonic integrated circuit; a first semiconductor chip and a second semiconductor chip on the redistribution layer opposite the through molding via; a first glass protruding from the second surface of the redistribution layer and penetrating the redistribution layer; a second molding layer on the redistribution layer, on a side surface of the first semiconductor chip, on a side surface of the second semiconductor chip, and on a side surface of the first glass; and a second glass connected to the optical fiber on the first glass.

Description

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 610,521, filed on December 15, 2023, and U.S. Application No. 18 / 912,098, filed on October 10, 2024, with the United States Patent and Trademark Office, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0002] Example embodiments of the present disclosure relate to semiconductor packages and methods of manufacturing semiconductor packages having a photonic integrated circuit coupled to an optical fiber through a refractive index matching glass. Background Art

[0003] Due to the need for higher computing performance, high bandwidth is required to integrate a larger number of central processing units (CPUs), graphics processing units (GPUs), high bandwidth memories (HBMs), artificial intelligence (AI) chips, etc. in a single semiconductor package.

[0004] For example, compared to copper wires, a photonic transceiver module enables higher bandwidth data transmission and communication by using coherent light, which results in lower loss and attenuation. Photonic transceiver modules have been applied in, for example, data centers and Ethernet communications. However, photonic transceiver modules are typically disposed at the periphery of a semiconductor package, which limits the ability of the photonic transceiver module to be used for data communication between the photonic transceiver module and an integrated circuit (IC) package of a semiconductor chip. Due to the limitations of the photonic transceiver module on packaging and its manufacturing process (which stems from the need for optical fiber integration), the integration of these photonic transceiver modules with semiconductor chips such as CPUs, application specific integrated circuits (ASICs), and memory chips has been difficult.

[0005] To provide a semiconductor package with higher bandwidth and lower latency inter-chip communication with low power consumption and high energy efficiency, on-package integration of a photonic module attached to an optical fiber is required. Summary of the Invention

[0006] One or more embodiments provide a method of manufacturing a semiconductor package having an optical bridge and the manufactured semiconductor package.

[0007] One or more embodiments also provide a method of manufacturing a semiconductor package and the manufactured semiconductor package having a photonic integrated circuit coupled to an optical fiber through a refractive index matching glass.

[0008] One or more embodiments relate to a process by which a packaging method process flow is modified and a refractive index matching glass substrate is used to allow for the embedding of an optical bridge, completion of downstream process steps, and successful optical fiber attachment while maintaining the package structural integrity.

[0009] One or more embodiments relate to lithographically selectively removing a dielectric layer after embedding an optical bridge to expose the optical bridge, directly attaching a refractive index matching glass to a refractive index matching epoxy on top of the optical bridge, completing downstream process steps, and exposing a glass substrate surface by a back grinding operation.

[0010] One or more embodiments provide a scalable package that allows for the integration of electronic integrated circuits (EICs), memories, and photon integrated circuits (PICs) on a package, while enabling relatively high bandwidth communication between these components through redistribution layer-based wiring and embedded optical bridges, allowing for the attachment of optical fibers to the PIC using glass spacers for the purpose of optical coupling in a manner that can be scalable, and allowing for the optical fibers to be coupled to a PIC having a topside grating structure embedded in the redistribution layer.

[0011] According to aspects of one or more embodiments, there is provided a semiconductor package including: a redistribution layer; through molded vias on a first surface of the redistribution layer; a photon integrated circuit on the first surface of the redistribution layer; a first molded layer on the first surface of the redistribution layer, on side surfaces of the through molded vias, and on side surfaces of the photon integrated circuit; a first semiconductor device and a second semiconductor device on a second surface of the redistribution layer opposite the first surface of the redistribution layer; a first glass protruding from the second surface of the redistribution layer and penetrating the redistribution layer from the first surface of the redistribution layer to the second surface; a second molded layer on the second surface of the redistribution layer, on side surfaces of the first semiconductor device, on side surfaces of the second semiconductor device, and on side surfaces of the first glass; and a second glass on the first glass, the second glass being connected to an optical fiber.

[0012] According to another aspect of one or more embodiments, a method of manufacturing a semiconductor package is provided. The method includes: providing a redistribution layer; providing through-molded vias on a first surface of the redistribution layer; providing a photonic integrated circuit on the first surface of the redistribution layer; providing a first molding layer on the first surface of the redistribution layer, on side surfaces of the through-molded vias, and on side surfaces of the photonic integrated circuit; providing a first semiconductor device and a second semiconductor device on a second surface of the redistribution layer opposite the first surface of the redistribution layer; providing a first glass to protrude from the second surface of the redistribution layer and penetrate the redistribution layer from the first surface of the redistribution layer to the second surface; providing a second molding layer on the second surface of the redistribution layer, on side surfaces of the first semiconductor device, on side surfaces of the second semiconductor device, and on side surfaces of the first glass; and providing a second glass on the first glass, the second glass being connected to an optical fiber.

[0013] According to another aspect of one or more embodiments, a semiconductor package is provided. The semiconductor package includes: a redistribution layer including a redistribution insulating layer, a wiring pattern, and vias; through-molded vias on a first surface of the redistribution layer, the through-molded vias being connected to at least one of the wiring pattern and the vias; an under-bump metallization layer on a first surface of the through-molded vias; a photonic integrated circuit on the first surface of the redistribution layer; a first molding layer on the first surface of the redistribution layer, on side surfaces of the through-molded vias, and on side surfaces of the photonic integrated circuit; a first semiconductor device and a second semiconductor device on a second surface of the redistribution layer opposite the first surface of the redistribution layer; a first glass protruding from the second surface of the redistribution layer and penetrating the redistribution layer from the first surface of the redistribution layer to the second surface; a second molding layer on the second surface of the redistribution layer, on side surfaces of the first semiconductor device, on side surfaces of the second semiconductor device, and on side surfaces of the first glass; and a second glass on the first glass, the second glass being connected to an optical fiber. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and / or other aspects, features, and advantages of example embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0015] Figure 1 A semiconductor package according to one or more embodiments is shown.

[0016] In a semiconductor package according to one or more embodiments, Figure 2A A cross-sectional view showing the provision of a photonic IC and through-molded vias is shown. Figure 2B A cross-sectional view showing the provision of a first molding layer and a first refractive index matching glass is shown. Figure 2C A cross-sectional view showing the provision of a redistribution layer is shown. Figure 2DA cross-sectional view showing a trench is provided to expose the first refractive index matching glass. Figure 2E A cross-sectional view showing the redistribution layer is exposed. Figure 2F A cross-sectional view showing the second refractive index matching glass is provided. Figure 2G A cross-sectional view showing the first semiconductor chip and the second semiconductor chip are provided on the redistribution layer. Figure 2H A cross-sectional view showing the second molding layer is provided. Figure 2I A cross-sectional view showing the external connection terminals are provided, and Figure 2J A cross-sectional view showing the third refractive index matching glass and the optical fiber are provided.

[0017] Figure 3 A semiconductor package according to one or more other embodiments is shown.

[0018] In a semiconductor package according to one or more embodiments, Figure 4A A cross-sectional view showing a through-molded via and a photon IC are provided. Figure 4B A cross-sectional view showing the first molding layer is provided. Figure 4C A cross-sectional view showing a under-bump metallization (UBM) layer is provided. Figure 4D A cross-sectional view showing the carrier substrate is removed and the intermediate semiconductor package is flipped. Figure 4E A cross-sectional view showing the photon IC is exposed. Figure 4F A cross-sectional view showing a photoresist layer is provided. Figure 4G A cross-sectional view showing the redistribution layer is provided. Figure 4H A cross-sectional view showing a trench is provided to expose the photon IC. Figure 4I A cross-sectional view showing the second refractive index matching glass, the first semiconductor chip and the second semiconductor chip are provided. Figure 4J A cross-sectional view showing the second molding layer is provided, and Figure 4K A cross-sectional view showing the external terminals are provided.

[0019] Figure 5 A flowchart showing a method of manufacturing a semiconductor package according to one or more embodiments is shown.

[0020] Figure 6 A flowchart showing a method of manufacturing a semiconductor package according to one or more other embodiments is shown.

[0021] Figure 7 A semiconductor package architecture that may include a semiconductor package according to one or more embodiments is shown.

[0022] Figure 8 A schematic block diagram of an electronic system according to one or more embodiments is shown. Detailed Description

[0023] The embodiments described herein are examples or exemplary embodiments, and thus, the present disclosure is not limited thereto and can be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided herein or not provided herein but consistent with the present disclosure. For example, even if a matter described in a particular example or embodiment is not described in a different example or embodiment, unless otherwise mentioned in its description, the matter can be understood to be relevant to or combinable with the different example or embodiment.

[0024] Furthermore, it should be understood that all descriptions of principles, aspects, examples, and embodiments are intended to cover their structural equivalents and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents but also equivalents developed in the future (i.e., all devices invented to perform the same function regardless of their structure).

[0025] It will be understood that when an element, component, layer, pattern, structure, region, etc. of a semiconductor device (hereinafter collectively referred to as "element") is referred to as being "on", "above", "over", "under", "beneath", "below", "connected to", or "coupled to" another element of the semiconductor device, the element can be directly on, above, over, under, beneath, below, directly connected to, or coupled to the other element, or intervening elements may be present. In contrast, when an element of a semiconductor device is referred to as being "directly on", "directly above", "directly over", "directly under", "directly beneath", "directly below", "directly connected to", or "directly coupled to" another element of the semiconductor device, no intervening elements are present. Throughout the present disclosure, the same reference numerals refer to the same elements.

[0026] For ease of description, spatial relative terms such as "on", "above", "over", "on (upper)", "under", "beneath", "below", "lower", "top", and "bottom" may be used herein to describe the relationship of one element to another as shown in the figures. It will be understood that the spatial relative terms are intended to cover different orientations of the semiconductor device in use or operation in addition to the orientation depicted in the figures. For example, if the semiconductor device in the figures is flipped, an element described as being "under" or "beneath" other elements will be oriented "above" the other elements. Thus, the term "under" can cover both above and below orientations. The semiconductor device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are to be interpreted accordingly.

[0027] As used herein, statements such as “at least one of...” following a list of elements modify the entire list of elements, and not individual elements of the list. For example, the statement “at least one of a, b, and c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Herein, when the term “same” is used to compare the sizes of two or more elements, the term may cover sizes that are “substantially the same”.

[0028] It will be understood that although the terms “first”, “second”, “third”, “fourth”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below may be termed a second element without departing from the teachings of this disclosure.

[0029] It will also be understood that even if a particular step or operation of a manufacturing apparatus or structure is described earlier than another step or operation, the step or operation may be performed later than the other step or operation, unless the other step or operation is described as being performed after the step or operation. It will be understood that any one of the components described herein, or any combination of components, may be used to perform one or more of the operations of the flowcharts. Additionally, all operations are exemplary operations and may include various additional steps.

[0030] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments (and intermediate structures). As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments should not be construed as limited to the particular shapes of regions shown herein, but include, for example, shape deviations resulting from manufacturing. For example, an implantation region shown as rectangular will generally have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the present disclosure. Additionally, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0031] For simplicity, general elements of semiconductor devices may or may not be described in detail herein.

[0032] For example, compared with copper wires, a photonic transceiver uses coherent light to achieve relatively high-bandwidth data transmission and communication, which results in lower loss and attenuation. However, the photonic transceiver is mainly disposed on a peripheral region of an integrated circuit (IC) package, which limits the ability of the photonic transceiver for data communication between the transceiver and a host memory chip of the IC package. Due to the limitations of the photonic transceiver on the package and its manufacturing process, the integration of these photonic transceivers with a central processing unit (CPU), an application specific integrated circuit (ASIC), and a memory chip on the IC package has become difficult.

[0033] For higher-bandwidth and lower-latency inter-chip communication at lower power consumption and higher energy efficiency, on-package level integration of a photonic transceiver with an IC package is required.

[0034] For higher-bandwidth communication between a photonic integrated circuit (PIC) on a package and components (such as a CPU, a memory chip, etc.) on an adjacent package, integration of an optical fiber attached to the PIC is required for transmitting laser energy and data into and out of the package.

[0035] Figure 1 A semiconductor package according to one or more embodiments is shown.

[0036] Referring to Figure 1 , the semiconductor package 1 may include a redistribution layer 200, a first semiconductor chip 40 and a second semiconductor chip 50 that may be, for example, a logic chip, a memory chip, etc., a first refractive index matching glass 10, a second refractive index matching glass 30, a photonic integrated circuit (IC) 20, a first molding layer 130, a second molding layer 330, and a plurality of through-molded vias (TMVs) 110.

[0037] Herein, a direction parallel to a main surface (top surface or bottom surface) of the redistribution layer 200 may be referred to as a horizontal direction (X direction and / or Y direction), and a direction perpendicular and orthogonal to the horizontal direction (X direction and / or Y direction) may be referred to as a vertical direction (Z direction).

[0038] The redistribution layer 200 may include a plurality of wiring patterns 210, a plurality of vias 230, and a redistribution insulating layer 220. The redistribution insulating layer 220 may include an insulating material (such as a photoimageable dielectric resin prepared by combining an epoxy resin and a photoinitiator), and may further include a photosensitive polyimide and / or an inorganic filler. The redistribution insulating layer 220 may include one or more redistribution insulating layers.

[0039] A plurality of wiring patterns 210 and a plurality of vias 230 may be provided as conductive patterns to provide electrical connections between the first semiconductor chip 40 and the second semiconductor chip 50 and structures external to the semiconductor package 1. In an example where the redistribution insulating layer 220 includes a plurality of redistribution insulating layers, the conductive patterns may be positioned on at least one of the upper surface and the lower surface of the redistribution insulating layer. The plurality of wiring patterns 210 may be provided to extend in a horizontal direction (X direction and / or Y direction) in the redistribution insulating layer 220. The plurality of vias 230 may penetrate the redistribution insulating layer in a vertical direction (Z direction) to contact and electrically connect to a part of the plurality of wiring patterns 210.

[0040] According to one or more embodiments, at least a part of the plurality of wiring patterns 210 may be integrally provided with a part of the plurality of vias 230. For example, the plurality of wiring patterns 210 and the plurality of vias 230 in contact with the surface of the plurality of wiring patterns 210 may be integrally formed as a single structure.

[0041] According to one or more embodiments, the plurality of vias 230 may have any suitable shape that may facilitate the manufacturing process, such as a tapered shape in which the horizontal width of the plurality of vias 230 decreases in the vertical direction (Z direction) away from the first semiconductor chip 40 and the second semiconductor chip 50.

[0042] The plurality of wiring patterns 210 and vias 230 may include, for example, metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and / or their alloys, but are not limited thereto.

[0043] A plurality of TMVs 110 may be provided on the first surface (bottom surface) of the redistribution layer 200. The plurality of TMVs 110 may include a conductive material, which includes, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and / or their combinations. Here, the first surface and the second surface respectively represent the bottom surface or the lower surface and the top surface or the upper surface.

[0044] The plurality of TMVs 110 may have a first surface and a second surface spaced apart from each other in the vertical direction (Z direction). The plurality of TMVs 110 may at least partially contact the plurality of vias 230 and the wiring patterns 210. For example, the second surface of the TMV 110 may be respectively bonded and connected to the first surface of the plurality of vias 230.

[0045] The TMV 110 may have, for example, a cylindrical shape. The diameter of the TMV 110 in the horizontal direction (X or Y direction) may be constant along the vertical direction (Z direction). In another embodiment, a plurality of TMV 110 may have a conical shape, which has a diameter that varies in the horizontal direction (X or Y direction) along the vertical direction (Z direction) according to manufacturing conditions.

[0046] The first molding layer 130 may be disposed on the first surface of the redistribution layer 200 and surround the side surfaces of the plurality of TMV 110 to seal the semiconductor package 1 and protect the semiconductor package 1 from physical and chemical impacts. The first molding layer 130 may be an epoxy molding compound and may include, for example, an epoxy molding resin having a silicon filler.

[0047] The semiconductor package 1 may further include a plurality of under bump metallization (UBM) layers 120 that are respectively in contact with the first surfaces of the plurality of TMV 110 exposed from the first molding layer 130. The UBM layer 120 may include a copper layer, a nickel layer, and a copper-nickel-tin intermetallic compound layer between the copper layer and the nickel layer. The first surface of the UBM layer 120 may be substantially coplanar with the first surface of the first molding layer 130.

[0048] The plurality of UBM layers 120 may electrically connect and / or physically connect the plurality of TMV 110 to other components of the semiconductor package 1 (such as a plurality of external connection terminals 140 that connect the semiconductor package 1 to components external to the semiconductor package 1 (such as, for example, a printed circuit board (PCB))). In addition, the plurality of UBM layers 120 may prevent the plurality of external connection terminals 140 from being damaged (such as cracked) due to thermal shock between the plurality of external connection terminals 140 and the redistribution layer 200, thereby improving the reliability of the semiconductor package 1. The plurality of UBM layers 120 may include a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and / or a combination thereof.

[0049] The plurality of external connection terminals 140 may be respectively disposed on the first surfaces of the plurality of UBM layers 120. The plurality of external connection terminals 140 may be configured to electrically connect and / or physically connect the redistribution layer 200 and an external device. According to one or more embodiments, the plurality of external connection terminals 140 may include, for example, solder balls, conductive bumps, and flip chip connection structures having a grid array (such as a pin grid array, a ball grid array, and a land grid array). The plurality of external connection terminals 140 may be electrically connected to the plurality of UBM layers 120 and may be electrically connected to an external device (such as a module substrate, a system board, and a printed circuit board).

[0050] The photon IC 20 can be at least laterally surrounded by the first molding layer 130. The first surface of the photon IC 20 can be substantially coplanar with the first surface of the plurality of UBM layers 120 and the first surface of the first molding layer 130. The second surface of the photon IC 20 can contact a part of the plurality of TMVs 110, and a part of the plurality of TMVs 110 is connected to the plurality of wiring patterns 210 included in the redistribution layer 200. The first refractive index matching glass 10 can be disposed on the second surface of the photon IC 20. The second surface of the first refractive index matching glass 10 can be substantially coplanar with the second surface of the first molding layer 130 and the second surface of the plurality of TMVs 110.

[0051] The first semiconductor chip 40 and the second semiconductor chip 50 can be disposed on the second surface of the redistribution layer 200 and are electrically connected to structures external to the semiconductor package 1 through the redistribution layer 200. The plurality of connection pads 41 and the connection structures 42 can be disposed on the first surfaces of the first semiconductor chip 40 and the second semiconductor chip 50. A part of the plurality of connection pads 41 and the connection structures 42 can be disposed between the first surface of the first semiconductor chip 40 and the second surface of the redistribution layer 200 and connect the first semiconductor chip 40 to a part of the wiring patterns 210 in the redistribution layer 200. Similarly, a part of the plurality of connection pads 41 and the connection structures 42 can be disposed between the first surface of the second semiconductor chip 50 and the second surface of the redistribution layer 200 and connect the second semiconductor chip 50 to a part of the wiring patterns 210 in the redistribution layer 200. The first semiconductor chip 40 and the second semiconductor chip 50 can be electrically connected to the redistribution layer 200 through the plurality of connection pads 41 and the plurality of connection structures 42, respectively.

[0052] For example, the first semiconductor chip 40 can be an application specific integrated circuit (ASIC) chip, and the second semiconductor chip 50 can be a high bandwidth memory (HBM) chip. However, the embodiments are not limited thereto. As another example, the first semiconductor chip 40 and the second semiconductor chip 50 can each be a system on chip (SOC), a memory chip (such as a dynamic random access memory (DRAM) chip and a NAND chip), or a logic chip (such as a CPU, a graphics processing unit (GPU), and a field programmable gate array (FPGA) chip), etc.

[0053] The second molding layer 330 can be disposed on the second surface of the redistribution layer 200 and surround the first semiconductor chip 40, the second semiconductor chip 50, the plurality of connection pads 41, and the plurality of connection structures 42 to seal the semiconductor package 1 and protect the semiconductor package 1 from physical shock and chemical shock. The second molding layer 330 can be an epoxy molding compound and can include, for example, an epoxy molding resin.

[0054] The second refractive index matching glass 30 may be disposed between the first semiconductor chip 40 and the second semiconductor chip 50 in the second molding layer 330. The second refractive index matching glass 30 may penetrate the redistribution layer 200 to the height of the second surface of the first refractive index matching glass 10 and may contact the second surface of the first refractive index matching glass 10. The second refractive index matching glass 30 may protrude away from the second surface of the redistribution layer 200 in the vertical direction (Z direction). The second molding layer 330 may surround the side surface of the second refractive index matching glass 30. The second surface of the second refractive index matching glass 30 may be substantially coplanar with the second surface of the first semiconductor chip 40, the second surface of the second semiconductor chip 50, and the second surface of the second molding layer 330.

[0055] The semiconductor package 1 may further include a third refractive index matching glass 32, which is disposed to contact the second surface of the second refractive index matching glass 30 and is connected to the optical fiber 60. For example, the refractive index of the first refractive index matching glass 10, the refractive index of the second refractive index matching glass 30, and the refractive index of the third refractive index matching glass 32 may be the same to prevent light from bending when transmitting from the optical fiber 60 through the third refractive index matching glass 32, the second refractive index matching glass 30, and the first refractive index matching glass 10 to the photon IC 20. Throughout the specification, the term "refractive index matching glass" may be collectively referred to as glass.

[0056] Based on the package-level integration of the photon IC 20 connected to the optical fiber 60 through the first refractive index matching glass 10, the second refractive index matching glass 30, and the third refractive index matching glass 32, the semiconductor package 1 may achieve higher bandwidth and lower latency inter-chip communication with lower power consumption and higher energy efficiency.

[0057] Figures 2A to 2J is a cross-sectional view showing an intermediate semiconductor package after corresponding steps of a method of manufacturing a semiconductor package according to one or more embodiments.

[0058] The semiconductor package manufactured by the method described below may be the same as or corresponding to the semiconductor package 1 shown in Figure 1 Therefore, its repeated description may be omitted herein, and the same reference numerals used in the above description of the semiconductor package 1 may be used hereinafter.

[0059] Refer to Figure 2A, a UBM layer 120 is disposed on the carrier substrate 100. A photon IC 20 is disposed on the carrier substrate 100. A plurality of TMVs 110 are disposed on the second surface of the corresponding UBM layer 120 on the carrier substrate 100 to be adjacent to the photon IC 20. A part of the TMVs 110 is disposed on the second surface of the photon IC 20. A first refractive index matching glass 10 is disposed on the second surface of the photon IC 20 between the TMVs 110 disposed thereon. The second surfaces of the plurality of TMVs 110 and the second surface of the first refractive index matching glass 10 may be substantially coplanar.

[0060] The plurality of TMVs 110 may include a conductive material, which includes, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and / or a combination thereof. The UBM layer 120 may include a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and / or a combination thereof.

[0061] Referring to Figure 2B , a first molding layer 130 may be disposed on the carrier substrate 100 to surround the side surfaces of the plurality of TMVs 110, the side surface of the first refractive index matching glass 10, and the side surface of the photon IC 20. The second surface of the first molding layer 130 may be substantially coplanar with the second surfaces of the plurality of TMVs 110 and the second surface of the first refractive index matching glass 10. For example, the first molding layer 130 may include an epoxy resin with silicon fillers.

[0062] Referring to Figure 2C , a redistribution layer 200 may be disposed on the second surfaces of the plurality of TMVs 110, the second surface of the first molding layer 130, and the second surface of the first refractive index matching glass 10. The redistribution layer 200 may include a plurality of wiring patterns 210, a plurality of vias 230, and a redistribution insulating layer 220 surrounding the wiring patterns 210 and the vias 230. The redistribution insulating layer 220 may include an insulating material (such as a photoimageable dielectric resin), and may also include a photosensitive polyimide and / or an inorganic filler. The redistribution insulating layer 220 may include one or more redistribution insulating layers.

[0063] The plurality of wiring patterns 210 and the plurality of vias 230 may be provided as conductive patterns, and in an example where the redistribution insulating layer 220 includes a plurality of redistribution insulating layers, the conductive patterns may be located on at least one of the first surface and the second surface of the redistribution insulating layer. The plurality of wiring patterns 210 may be provided to extend in the horizontal direction (X direction and / or Y direction) in the redistribution insulating layer 220. The plurality of vias 230 may penetrate the redistribution insulating layer in the vertical direction (Z direction) to contact and electrically connect to a part of the plurality of wiring patterns 210.

[0064] According to one or more embodiments, the plurality of vias 230 may have a tapered shape in which the horizontal width of the plurality of vias 230 decreases in the vertical direction (Z direction) away from the first semiconductor chip 40 and the second semiconductor chip 50.

[0065] The plurality of wiring patterns 210 and the plurality of vias 230 may include, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and / or an alloy thereof, but is not limited thereto.

[0066] Referring to Figure 2D , a resist layer 300 may be applied on the second surface of the redistribution layer 200, and a trench 31 may be wet-etched in the vertical direction (Z direction) to the height of the first refractive index matching glass 10, for example, by a photolithography process, to expose the second surface of the first refractive index matching glass 10.

[0067] Referring to Figure 2E , the resist layer 300 may be removed, for example, by a scum removal process, to expose the second surface of the redistribution layer 200.

[0068] Referring to Figure 2F , a second refractive index matching glass 30 may be disposed in the trench 31 to protrude from the second surface of the redistribution layer 200 in the vertical direction (Z direction). For example, the second surface of the second refractive index matching glass 30 may be formed to be higher than the second surface of the redistribution layer 200 in the vertical direction (Z direction).

[0069] Referring to Figure 2G , the first semiconductor chip 40 and the second semiconductor chip 50 may be disposed on the second surface of the redistribution layer 200. Further, a plurality of connection pads 41 and connection structures 42 may be disposed on the first surface of the first semiconductor chip 40 and the first surface of the second semiconductor chip 50. A part of the plurality of connection pads 41 and connection structures 42 may be disposed between the first surface of the first semiconductor chip 40 and the plurality of wiring patterns 210, and a part of the plurality of connection pads 41 and connection structures 42 connects the first semiconductor chip 40 to the redistribution layer 200. Similarly, a part of the plurality of connection pads 41 and connection structures 42 may be disposed between the first surface of the second semiconductor chip 50 and the plurality of wiring patterns 210, and a part of the plurality of connection pads 41 and connection structures 42 connects the second semiconductor chip 50 to the redistribution layer 200.

[0070] For example, the first semiconductor chip 40 may be an ASIC chip, and the second semiconductor chip 50 may be an HBM chip. However, the embodiments are not limited thereto.

[0071] Referring Figure 2H , a second molding layer 330 may be disposed on the second surface of the redistribution layer 200 and around the first semiconductor chip 40, the second semiconductor chip 50, the plurality of connection pads 41, and the plurality of connection structures 42. The second molding layer 330 may be an epoxy molding compound and may include, for example, an epoxy molding resin having a silicon filler. The second surface of the first semiconductor chip 40, the second surface of the second semiconductor chip 50, and the second surface of the second molding layer 330 may be ground to be substantially coplanar.

[0072] Referring Figure 2I , the carrier substrate 100 may be removed, and the intermediate semiconductor package obtained in the previous step ( Figure 2H ) may be inverted. A plurality of external connection terminals 140 may be disposed on the first surface of the UBM layer 120. The external connection terminals 140 may be configured to electrically and physically connect the redistribution layer 200 and an external device. According to one or more embodiments, the external connection terminals 140 may include, for example, solder balls, conductive bumps, and flip chip connection structures having a grid array (such as a pin grid array, a ball grid array, and an area grid array). The external connection terminals 140 may be electrically connected to the UBM layer 120 and may be electrically connected to an external device (such as a module substrate, a system board, and a printed circuit board).

[0073] See Figure 2J , the intermediate semiconductor package obtained in the previous step ( Figure 2I ) may be inverted, and a third refractive index matching glass 32 attached with an optical fiber 60 may be disposed on the second surface of the second refractive index matching glass 30. Here, the refractive index of the first refractive index matching glass 10, the refractive index of the second refractive index matching glass 30, and the refractive index of the third refractive index matching glass 32 may be the same to prevent light from bending when transmitting from the optical fiber 60 through the third refractive index matching glass 32, the second refractive index matching glass 30, and the first refractive index matching glass 10 to the photon IC 20.

[0074] Figure 3 A semiconductor package according to one or more other embodiments is shown.

[0075] Figure 3 The semiconductor package shown in Figure 1 may include a plurality of structural elements, and these structural elements may be the same as or similar to the structural elements shown in Figure 1 . For ease of description, the same reference numerals as those shown in

[0076] Reference Figure 3 ,the semiconductor package 2 may include a redistribution layer 200, a first semiconductor chip 40, a second semiconductor chip 50, a second refractive index matching glass 30, a photon IC 20, a first molding layer 130, a second molding layer 330, and a plurality of TMVs 110.

[0077] The redistribution layer 200 may include a plurality of wiring patterns 210, a plurality of vias 230, and a redistribution insulating layer 220. The redistribution insulating layer 220 may include an insulating material (such as a photoimageable dielectric resin prepared by combining an epoxy resin and a photoinitiator), and may further include a photosensitive polyimide and / or an inorganic filler. The redistribution insulating layer 220 may include one or more redistribution insulating layers.

[0078] The plurality of wiring patterns 210 and the plurality of vias 230 may be provided as conductive patterns to provide an electrical connection between the first semiconductor chip 40 and the second semiconductor chip 50 and a structure external to the semiconductor package 2. In an example where the redistribution insulating layer 220 includes a plurality of redistribution insulating layers, the conductive patterns may be positioned on at least one of a first surface and a second surface of the redistribution insulating layer. The plurality of wiring patterns 210 may be provided to extend in a horizontal direction (X direction and / or Y direction) in the redistribution insulating layer 220. The plurality of vias 230 may penetrate the redistribution insulating layer in a vertical direction (Z direction) to contact and electrically connect to a part of the plurality of wiring patterns 210.

[0079] According to one or more embodiments, at least a part of the plurality of wiring patterns 210 may be integrally provided with a part of the plurality of vias 230. For example, the plurality of wiring patterns 210 and the plurality of vias 230 in contact with the surface of the plurality of wiring patterns 210 may be integrally formed as a single structure.

[0080] According to one or more embodiments, the plurality of vias 230 may have any suitable shape that may facilitate a manufacturing process, such as a tapered shape in which a horizontal width of the plurality of vias 230 decreases in a vertical direction (Z direction) away from the first semiconductor chip 40 and the second semiconductor chip 50.

[0081] The plurality of wiring patterns 210 and the plurality of vias 230 may include, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and / or their alloys, but is not limited thereto.

[0082] The dielectric layer 160 may be disposed on a first surface of the redistribution layer 200. The dielectric layer 160 may include conductive plates 170 that are electrically connected and / or physically connected to a plurality of vias 230, respectively.

[0083] A plurality of TMVs 110 may be disposed on the first surface of the dielectric layer 160. The plurality of TMVs 110 may include a conductive material, which includes, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and / or combinations thereof.

[0084] The plurality of TMVs 110 may have a first surface and a second surface that are spaced apart from each other in a vertical direction (Z direction). The plurality of TMVs 110 may be at least partially in contact with the plurality of vias 230 and the wiring patterns 210 exposed on the first surface of the redistribution layer 200 through the plurality of conductive plates 170. For example, the second surface of the TMV 110 may be bonded and connected to the first surface of the plurality of conductive plates 170, respectively.

[0085] The TMV 110 may have, for example, a cylindrical shape. The diameter of the TMV 110 in a horizontal direction (X or Y direction) may be constant along the vertical direction (Z direction). In another embodiment, the plurality of TMVs 110 may have a conical shape, and the diameter of the conical shape may vary in the horizontal direction (X or Y direction) along the vertical direction (Z direction) according to manufacturing conditions.

[0086] The first molding layer 130 may be disposed on the first surface of the dielectric layer 160 and surround the side surfaces of the plurality of TMVs 110 to seal the semiconductor package 2 and protect the semiconductor package 2 from physical shock and chemical shock. The first molding layer 130 may be an epoxy molding compound and may include, for example, an epoxy molding resin having a silicon filler.

[0087] The semiconductor package 2 may further include a plurality of UBM layers 120 that are respectively in contact with the first surfaces of the plurality of TMVs 110 exposed from the first molding layer 130. The plurality of UBM layers 120 may electrically connect and / or physically connect the plurality of TMVs 110 to other components of the semiconductor package 2 (such as a plurality of external connection terminals 140 that connect the semiconductor package 2 to components outside the semiconductor package 2 (such as, for example, a printed circuit board (PCB))). In addition, the plurality of UBM layers 120 may prevent the plurality of external connection terminals 140 from being damaged (such as cracking) due to thermal shock between the plurality of external connection terminals 140 and the redistribution layer 200. The plurality of UBM layers 120 may include a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and / or combinations thereof.

[0088] A plurality of external connection terminals 140 may be respectively disposed on a first surface of the plurality of UBM layers 120. The plurality of external connection terminals 140 may be configured to electrically connect and / or physically connect the redistribution layer 200 and an external device. According to one or more embodiments, the plurality of external connection terminals 140 may include, for example, solder balls, conductive bumps, and flip-chip connection structures having a grid array (such as a pin grid array, a ball grid array, and an area grid array). The plurality of external connection terminals 140 may be electrically connected to the plurality of UBM layers 120 and may be electrically connected to an external device (such as a module substrate, a system board, and a printed circuit board).

[0089] The photon IC 20 may be at least laterally surrounded by the first molding layer 130. A first surface of the photon IC 20 may be substantially coplanar with a first surface of the UBM layer 120 and a first surface of the first molding layer 130. In Figure 1 the semiconductor package 1 shown in, a second surface of the photon IC 20 may contact a part of the plurality of TMVs 110, and a part of the plurality of TMVs 110 is connected to the plurality of wiring patterns 210 included in the redistribution layer 200. In Figure 3 the semiconductor package 2 shown in, a second surface of the photon IC 20 may contact the plurality of connection plates 122, and the plurality of connection plates 122 are connected to the plurality of vias 230 included in the redistribution layer 200. A second surface of the photon IC 20 may be substantially coplanar with a second surface of the plurality of TMVs 110 and a second surface of the first molding layer 130.

[0090] The plurality of connection plates 122 may electrically connect the photon IC 20 to the redistribution layer 200 (for example, the plurality of vias 230 in the redistribution layer 200). The plurality of connection plates 122 may be connected to the photon IC 20 through the plurality of connection pads 121 disposed on a second surface of the photon IC 20. A second surface of the connection pad 121 may be coplanar with a second surface of the photon IC 20. The plurality of connection plates 122 may include a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and / or a combination thereof. The plurality of connection plates 122 may be surrounded by the dielectric layer 160.

[0091] The first semiconductor chip 40 and the second semiconductor chip 50 may be disposed on the second surface of the redistribution layer 200 and are electrically connected to a structure outside the semiconductor package 2 through the redistribution layer 200. A plurality of connection pads 41 and connection structures 42 may be disposed on the first surface of the first semiconductor chip 40 and the second semiconductor chip 50. A part of the plurality of connection pads 41 and the plurality of connection structures 42 may be disposed between the second surface of the redistribution layer 200 and the first surface of the first semiconductor chip 40 and connect the first semiconductor chip 40 to a part of the wiring pattern 210 of the redistribution layer 200. Similarly, a part of the plurality of connection pads 41 and the plurality of connection structures 42 may be disposed between the second surface of the redistribution layer 200 and the first surface of the second semiconductor chip 50 and connect the second semiconductor chip 50 to a part of the wiring pattern 210 of the redistribution layer 200. The first semiconductor chip 40 and the second semiconductor chip 50 may be electrically connected to the redistribution layer 200 through the plurality of connection pads 41 and the plurality of connection structures 42, respectively.

[0092] For example, the first semiconductor chip 40 may be an ASIC chip and the second semiconductor chip 50 may be an HBM chip. However, the embodiments are not limited thereto.

[0093] The second molding layer 330 may be disposed on the second surface of the redistribution layer 200 and surround the first semiconductor chip 40, the second semiconductor chip 50, the plurality of connection pads 41, and the plurality of connection structures 42. The second molding layer 330 may be an epoxy molding compound and may include, for example, an epoxy molding resin having a silicon filler.

[0094] The second refractive index matching glass 30 may be disposed in the second molding layer 330 between the first semiconductor chip 40 and the second semiconductor chip 50. The second refractive index matching glass 30 may penetrate the redistribution layer 200 and the dielectric layer 160 to the height of the second surface of the photon IC 20. The first surface of the second refractive index matching glass 30 may contact the second surface of the photon IC 20. The second molding layer 330 may surround the side surface of the second refractive index matching glass 30. The second surface of the second refractive index matching glass 30 may be substantially coplanar with the second surface of the first semiconductor chip 40, the second surface of the second semiconductor chip 50, and the second surface of the second molding layer 330.

[0095] The semiconductor package 2 may further include a third refractive index matching glass 32 disposed on the second surface of the second refractive index matching glass 30 and connected to the optical fiber 60. For example, the refractive index of the second refractive index matching glass 30 and the refractive index of the third refractive index matching glass 32 may be the same to prevent light from bending when transmitted from the optical fiber 60 through the third refractive index matching glass 32 and the second refractive index matching glass 30 to the photon IC 20.

[0096] Based on the superior integration of the package of the photon IC 20 connected to the optical fiber 60 through the second refractive index matching glass 30 and the third refractive index matching glass 32, the semiconductor package 2 can achieve inter-chip communication with higher bandwidth and lower latency with lower power consumption and higher energy efficiency.

[0097] Figure 4A FIGs. 4k are cross-sectional views showing intermediate semiconductor packages after corresponding steps of a method of manufacturing a semiconductor package according to one or more other embodiments.

[0098] The semiconductor package manufactured by the method described below can be the same as or corresponding to the semiconductor package 2 shown in Figure 3 Therefore, its repeated description can be omitted here, and the same reference numerals used in the above description of the semiconductor package 2 can be used hereinafter.

[0099] Referring to Figure 4A , a dielectric layer 160 can be provided on the carrier substrate 100. The dielectric 160 can include a conductive layer 150 and a plurality of conductive plates 170 provided on the first surface of the conductive layer 150. The first surface of the dielectric layer 160 can be substantially coplanar with the first surface of the conductive plates 170. A plurality of TMVs 110 can be provided on the first surface of the dielectric layer 160, and the plurality of TMVs 110 are respectively in contact with the first surface of the conductive plates 170.

[0100] The photon IC 20 is provided on the first surface of the dielectric layer 160 adjacent to the plurality of TMVs 110. A plurality of connection pads 121 can be provided on the second surface of the photon IC 20. The second surface of the connection pads 121 can be coplanar with the second surface of the photon IC 20.

[0101] The plurality of TMVs 110, the plurality of conductive plates 170, and the conductive layer 150 can include a conductive material, which includes, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and / or a combination thereof.

[0102] Referring to Figure 4B , a first molding layer 130 can be provided on the dielectric layer 160 to surround the side surfaces of the plurality of TMVs 110 and the side surfaces of the photon IC 20. The first surface of the first molding layer 130 can be substantially coplanar with the first surface of the plurality of TMVs 110 and the first surface of the photon IC 20. For example, the first molding layer 130 can include an epoxy resin with silicon fillers.

[0103] Referring to Figure 4C, a plurality of UBM layers 120 can be provided on the TMV 110 and the photon IC 20. The plurality of UBM layers 120 can contact a first surface of the plurality of TMVs 110 and a first surface of the photon IC 20. The plurality of UBM layers 120 can include a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and / or a combination thereof.

[0104] Referring to Figure 4D , the carrier substrate 100 can be separated, and the intermediate semiconductor package obtained in the previous step ( Figure 4C ) can be turned upside down and reattached to the carrier substrate 100.

[0105] Here, the carrier substrate 100 can be reattached on the opposite side including a first surface of the first molding layer 130 and a first surface of the UBM layer 120.

[0106] Referring to Figure 4E , the dielectric layer 160 and the conductive layer 150 can be etched by photoimageable dielectric lithography to form trenches 11 and expose a second surface of the photon IC 20 and a second surface of the connection pads 121.

[0107] Through the etching operation in this step, a part of the dielectric layer 160 on the second surface of the conductive layer 150 and the conductive layer 150 can be completely removed, and a part of the other part of the dielectric layer 160 that overlaps with the photon IC 20 can be removed to expose the second surface of the photon IC 20 and the second surface of the connection pads 121.

[0108] Referring to Figure 4F , a photoresist layer 12 including a photoresist material can be formed in the trenches 11. Additionally, a plurality of connection plates 122 can be provided on the second surfaces of the plurality of connection pads 121 by patterning the photoresist layer 12 such that the second surfaces of the plurality of connection plates 122 are substantially coplanar with the second surfaces of the plurality of conductive plates 170 and the second surface of the dielectric layer 160.

[0109] Referring to Figure 4G, the photoresist layer 12 can be removed by, for example, a scum removal process to expose the second surface of the photon IC 20. A redistribution layer 200 can be disposed on the second surface of the dielectric layer 160 in which a plurality of conductive plates 170 are provided and on the second surface of the photon IC 20 to fill the space formed by removing the photoresist layer 12. The redistribution layer 200 can include a plurality of wiring patterns 210, a plurality of vias 230, and a redistribution insulating layer 220 surrounding the wiring patterns 210 and the vias 230. The redistribution insulating layer 220 can include an insulating material (such as a photoimageable dielectric resin), and can also include photosensitive polyimide and / or inorganic fillers. The redistribution insulating layer 220 can include one or more redistribution insulating layers.

[0110] The plurality of wiring patterns 210 and the plurality of vias 230 can be provided as conductive patterns, and in an example where the redistribution insulating layer 220 includes a plurality of redistribution insulating layers, the conductive patterns can be located on at least one of the first surface and the second surface of the redistribution insulating layer. The plurality of wiring patterns 210 can be provided to extend in a horizontal direction (X direction and / or Y direction) in the redistribution insulating layer 220. The plurality of vias 230 can penetrate the redistribution insulating layer in a vertical direction (Z direction) to contact and electrically connect to a part of the plurality of wiring patterns 210. The lowermost via 230 can contact the second surface of the plurality of conductive plates 170 and the second surface of the plurality of connection plates 122.

[0111] According to one or more embodiments, the plurality of vias 230 can have a tapered shape in which the horizontal width of the plurality of vias 230 decreases in a vertical direction (Z direction) away from the first semiconductor chip 40 and the second semiconductor chip 50.

[0112] The plurality of wiring patterns 210 and the plurality of vias 230 can include, for example, metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and / or their alloys, but are not limited thereto.

[0113] Referring to Figure 4H , a trench 31 can be formed in the redistribution layer 200 in a vertical direction (Z direction) to the height of the second surface of the photon IC 20 by a lithography process (such as wet etching) to expose the photon IC 20.

[0114] Referring to Figure 4I, a second refractive index matching glass 30 may be disposed in the trench 31 to contact the second surface of the photon IC 20 and protrude from the second surface of the redistribution layer 200 in the vertical direction (Z direction). For example, the second surface of the second refractive index matching glass 30 may be formed to be higher than the second surface of the redistribution layer 200 in the vertical direction (Z direction).

[0115] A first semiconductor chip 40 and a second semiconductor chip 50 may be disposed on the second surface of the redistribution layer 200, and the first semiconductor chip 40 and the second semiconductor chip 50 are electrically connected to a structure outside the semiconductor package through the redistribution layer 200. A part of the plurality of connection pads 41 and the connection structure 42 may be disposed between the first surface of the first semiconductor chip 40 and the plurality of wiring patterns 210, and a part of the plurality of connection pads 41 and the connection structure 42 connects the first semiconductor chip 40 to the redistribution layer 200. Similarly, a part of the plurality of connection pads 41 and the connection structure 42 may be disposed between the first surface of the second semiconductor chip 50 and the plurality of wiring patterns 210, and a part of the plurality of connection pads 41 and the connection structure 42 connects the second semiconductor chip 50 to the redistribution layer 200.

[0116] For example, the first semiconductor chip 40 may be an application specific integrated circuit (ASIC) chip, and the second semiconductor chip 50 may be a high bandwidth memory (HBM) chip. However, the embodiments are not limited thereto. For example, the first semiconductor chip 40 and the second semiconductor chip 50 may be an SOC, a memory chip (such as a DRAM chip and a NAND chip), or a logic chip (such as a CPU, a GPU, and an FPGA chip), etc.

[0117] Referring to Figure 4J , a second molding layer 330 may be disposed on the second surface of the redistribution layer 200 and around the first semiconductor chip 40, the second semiconductor chip 50, the plurality of connection pads 41, and the plurality of connection structures 42 to seal the semiconductor package and protect the semiconductor package from physical shock and chemical shock. The second molding layer 330 may be an epoxy molding compound and may include, for example, an epoxy molding resin having a silicon filler. The second surface of the first semiconductor chip 40, the second surface of the second semiconductor chip 50, and the second surface of the second molding layer 330 may be ground to be substantially coplanar.

[0118] Referring to Figure 4K, the carrier substrate 100 can be removed. A plurality of external connection terminals 140 can be provided on the first surface of the plurality of UBM layers 120. The plurality of external connection terminals 140 can be configured to electrically and physically connect the redistribution layer 200 and an external device. According to one or more embodiments, the plurality of external connection terminals 140 can include, for example, solder balls, conductive bumps, and flip-chip connection structures having a grid array (such as a pin grid array, a ball grid array, and an area grid array). The plurality of external connection terminals 140 can be electrically connected to the plurality of UBM layers 120 and can be electrically connected to an external device (such as a module substrate, a system board, and a printed circuit board). Additionally, a third refractive index matching glass 32 attached with an optical fiber 60 can be provided on the second surface of the second refractive index matching glass 30. Here, the refractive index of the second refractive index matching glass 30 and the refractive index of the third refractive index matching glass 32 can be the same to prevent light from bending when transmitting from the optical fiber 60 through the third refractive index matching glass 32 and the second refractive index matching glass 30 to the photon IC 20.

[0119] Figure 5 A flowchart of manufacturing a semiconductor package according to one or more embodiments is shown. The semiconductor device manufactured through the flowchart described below can be the same as or corresponding to the semiconductor package 1 shown in Figure 1 the semiconductor package shown in

[0120] In operation S110, a photon IC and a plurality of TMVs are provided on a carrier substrate. A plurality of UBM layers can be provided between the plurality of TMVs and the carrier substrate. A first refractive index matching glass can be provided on the second surface of the photon IC. A first molding layer can be provided on the carrier substrate to surround the side surfaces of the plurality of TMVs and the side surface of the first refractive index matching glass. The second surface of the first molding layer can be substantially coplanar with the second surfaces of the TMVs and the first refractive index matching glass.

[0121] In operation S120, a redistribution layer can be provided on the second surfaces of the plurality of TMVs, the second surface of the first molding layer, and the second surface of the first refractive index matching glass. The redistribution layer can include a redistribution insulating layer in which a plurality of wiring patterns and vias are formed. The redistribution insulating layer can include one or more redistribution insulating layers.

[0122] The plurality of wiring patterns and vias can be provided as conductive patterns, and the conductive patterns can be positioned on at least one of the first surface and the second surface of the redistribution insulating layer among the plurality of redistribution insulating layers. The plurality of wiring patterns can be provided to extend in a horizontal direction (X direction and / or Y direction) in the redistribution insulating layer. The plurality of vias can penetrate the redistribution insulating layer in a vertical direction (Z direction) to contact and electrically connect to a part of the wiring patterns. According to one or more embodiments, the plurality of vias can have a tapered shape.

[0123] In operation S130, a second refractive index matching glass may be disposed in the trenches formed in the redistribution layer, and the second refractive index matching glass protrudes away from the second surface of the redistribution layer in the vertical direction (Z direction). The second refractive index matching glass may contact the first refractive index matching glass.

[0124] In operation S140, a first semiconductor chip and a second semiconductor chip may be disposed on the second surface of the redistribution layer. A plurality of connection pads and a plurality of connection structures may connect the first semiconductor chip and the second semiconductor chip to the redistribution layer. A second molding layer may be disposed on the second surface of the redistribution layer and around the first semiconductor chip, the second semiconductor chip, the plurality of connection pads, and the plurality of connection structures.

[0125] In operation S150, the carrier substrate may be removed to expose the plurality of UBM layers, and a plurality of external connection terminals 140 may be disposed on the plurality of UBM layers to electrically and physically connect the redistribution layer and an external device.

[0126] In operation S160, a third refractive index matching glass connected to an optical fiber may be disposed to contact the second surface of the second refractive index matching glass.

[0127] Figure 6 A flowchart of manufacturing a semiconductor package according to one or more other embodiments is shown. The semiconductor device manufactured by the flowchart described below may be the same as or corresponding to the semiconductor package 2 shown in Figure 3 The semiconductor package shown in

[0128] In operation S210, a dielectric layer may be disposed on a carrier substrate. A conductive layer and a plurality of conductive plates on the conductive layer may be disposed in the dielectric layer. A plurality of TMVs may be disposed on the first surface of the dielectric layer, and the plurality of TMVs respectively contact the first surface of the conductive plates. The photon IC 20 may be disposed on the first surface of the dielectric layer adjacent to the plurality of TMVs. A first molding layer may be disposed on the dielectric layer to surround the side surfaces of the plurality of TMVs and the side surface of the photon IC. The first surface of the first molding layer may be substantially coplanar with the first surface of the TMVs and the first surface of the photon IC.

[0129] In operation S220, a redistribution layer may be disposed on the second surface of the dielectric layer 160 and the second surface of the photon IC 20. The redistribution layer may include a plurality of wiring patterns, a plurality of vias, and a redistribution insulating layer. The redistribution insulating layer may include one or more redistribution insulating layers.

[0130] Multiple wiring patterns and vias can be set as conductive patterns, and the conductive patterns can be positioned on at least one of the first surface and the second surface of a redistribution insulating layer among multiple redistribution insulating layers. The multiple wiring patterns can be set to extend in a horizontal direction (X direction and / or Y direction) in the redistribution insulating layer. The multiple vias can penetrate the redistribution insulating layer in a vertical direction (Z direction) to contact and electrically connect to a part of the wiring patterns. According to one or more embodiments, the multiple vias can have a tapered shape.

[0131] In operation S230, a second refractive index matching glass can be set to penetrate the redistribution layer to contact the second surface of the photon IC and protrude from the second surface of the redistribution layer in a vertical direction (Z direction).

[0132] In operation S240, a first semiconductor chip and a second semiconductor chip can be set on the second surface of the redistribution layer and adjacent to the second refractive index matching glass. Multiple connection pads and multiple connection structures can connect the first semiconductor chip and the second semiconductor chip to the redistribution layer. A second molding layer can be set on the second surface of the redistribution layer and around the first semiconductor chip, the second semiconductor chip, the multiple connection pads, and the multiple connection structures.

[0133] In operation S250, multiple external connection terminals 140 can be set to connect to multiple TMVs. In one embodiment, multiple UBM layers can be set on the photon IC and the multiple TMVs, and the multiple external connection terminals 140 can be set on the multiple UBM layers (e.g., on the first surface of the multiple UBM layers).

[0134] In operation S260, a third refractive index matching glass connected to an optical fiber can be set to contact the second surface of the second refractive index matching glass.

[0135] Figure 7 A semiconductor package architecture that can include a semiconductor package according to one or more embodiments is shown.

[0136] Referring to Figure 7 , a semiconductor package architecture 2000 according to one or more embodiments can include a processor 2200 and a semiconductor device 2300 mounted on a substrate 2100. The processor 2200 and / or the semiconductor device 2300 can include one or more of the semiconductor packages described in the above one or more embodiments.

[0137] Figure 8 A schematic block diagram of an electronic system according to one or more embodiments is shown.

[0138] Referring to Figure 8, an electronic system 3000 according to one or more embodiments may include a microprocessor 3100, a memory 3200, and a user interface 3300 that perform data communication using a bus 3400. The microprocessor 3100 may include a CPU or an application processor (AP). The electronic system 3000 may also include a random access memory (RAM) 3500 that communicates directly with the microprocessor 3100. The microprocessor 3100 and / or the RAM 3500 may be implemented in a single module or package. The user interface 3300 may be used to input data into the electronic system 3000 or output data from the electronic system 3000. For example, the user interface 3300 may include a keyboard, a touchpad, a touch screen, a mouse, a scanner, a voice detector, a liquid crystal display (LCD), a micro light emitting device (LED), an organic light emitting diode (OLED) device, an active matrix light emitting diode (AMOLED) device, a printer, a lighting device, or various other input / output devices, without limitation. The memory 3200 may store the operation code of the microprocessor 3100, the data processed by the microprocessor 3100, or the data received from an external device. The memory 3200 may include a memory controller, a hard disk, or a solid state drive (SSD).

[0139] At least the microprocessor 3100, the memory 3200, and / or the RAM 3500 in the electronic system 3000 may be included in the semiconductor package described in the above embodiments.

[0140] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments.

[0141] Although example embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A semiconductor package, comprising: Redistribution layer; a through-mold via on the first surface of the redistribution layer; a photonic integrated circuit on the first surface of the redistribution layer; a first molding layer on the first surface of the redistribution layer, on the side surfaces of the through-molded vias, and on the side surfaces of the photonic integrated circuit; a first semiconductor chip and a second semiconductor chip on a second surface of the redistribution layer opposite to the first surface of the redistribution layer; a first glass protruding from the second surface of the redistribution layer and penetrating the redistribution layer from the first surface of the redistribution layer to the second surface of the redistribution layer; a second molding layer on the second surface of the redistribution layer, on the side surface of the first semiconductor chip, on the side surface of the second semiconductor chip, and on the side surface of the first glass; as well as A second glass is on the first glass, and the second glass is connected to the optical fiber.

2. The semiconductor package according to claim 1, wherein: The redistribution layer includes: Redistribution insulation layer; wiring pattern; and vias, connected to the wiring pattern, and wherein the through-mold via is connected to at least one of the wiring pattern and the via.

3. The semiconductor package according to claim 1, further comprising: The third glass is between the first glass and the photonic integrated circuit.

4. The semiconductor package according to claim 3, wherein: The first surface of the first glass contacts the second surface of the third glass, and The first surface of the second glass contacts the second surface of the first glass.

5. The semiconductor package according to claim 4, wherein: The refractive index of the first glass, the refractive index of the second glass, and the refractive index of the third glass are the same.

6. The semiconductor package according to claim 1, further comprising: Dielectric layer, between the redistribution layer and the photonic integrated circuit, The first glass contacts the second surface of the photonic integrated circuit, and the second surface of the photonic integrated circuit contacts the first surface of the dielectric layer.

7. The semiconductor package according to claim 6, wherein: The first surface of the second glass contacts the second surface of the first glass.

8. The semiconductor package according to claim 7, wherein: The refractive index of the first glass and the refractive index of the second glass are the same.

9. The semiconductor package according to any one of claims 1 to 8, further comprising: an under bump metallization layer on the first surface of the through molded via; as well as External connection terminals, on the under bump metallization layer.

10. The semiconductor package according to any one of claims 2 to 8, further comprising: a first connection pad and a second connection pad, the first connection pad being between the first semiconductor chip and the redistribution layer, and the second connection pad being between the second semiconductor chip and the redistribution layer; as well as A connection structure is between the first connection pad and the second connection pad and the redistribution layer, the connection structure being connected to at least one of the wiring pattern and the via.

11. The semiconductor package according to any one of claims 1 to 8, wherein: The first semiconductor chip includes an application specific integrated circuit, and the second semiconductor chip includes a high bandwidth memory chip.

12. A method for manufacturing a semiconductor package, the method comprising: Set up the redistribution layer; providing a through-mold via on the first surface of the redistribution layer; Disposing a photonic integrated circuit on the first surface of the redistribution layer; disposing a first molding layer on the first surface of the redistribution layer, on the side surfaces of the through-molded vias, and on the side surfaces of the photonic integrated circuit; disposing a first semiconductor chip and a second semiconductor chip on a second surface of the redistribution layer opposite to the first surface of the redistribution layer; Disposing the first glass to protrude from the second surface of the redistribution layer and penetrate the redistribution layer from the first surface of the redistribution layer to the second surface of the redistribution layer; disposing a second molding layer on the second surface of the redistribution layer, on the side surface of the first semiconductor chip, on the side surface of the second semiconductor chip, and on the side surface of the first glass; as well as A second glass is disposed on the first glass, and the second glass is connected to the optical fiber.

13. The method according to claim 12, wherein: The steps to set up the redistribution layer include: Providing a redistribution insulation layer; Setting a wiring pattern; and Set up vias connected to the wiring pattern, wherein the through-mold via is connected to at least one of the wiring pattern and the via.

14. The method according to claim 12, further comprising: A third glass is provided between the first glass and the photonic integrated circuit. wherein the first surface of the first glass contacts the second surface of the third glass, and The first surface of the second glass contacts the second surface of the first glass.

15. The method according to claim 14, wherein: The refractive index of the first glass, the refractive index of the second glass, and the refractive index of the third glass are the same.

16. The method according to claim 12, further comprising: A dielectric layer is disposed between the redistribution layer and the photonic integrated circuit.

17. The method according to claim 16, wherein: The refractive index of the first glass and the refractive index of the second glass are the same.

18. The method according to any one of claims 12 to 17, further comprising: Disposing an under bump metallization layer on the first surface of the through molded via; as well as External connection terminals are arranged on the under bump metallization layer.

19. The method according to any one of claims 13 to 17, further comprising: Disposing a first connection pad between the first semiconductor chip and the redistribution layer, and disposing a second connection pad between the second semiconductor chip and the redistribution layer; as well as A connection structure is disposed between the first connection pad and the second connection pad and the redistribution layer such that the connection structure is connected to at least one of the wiring pattern and the via.

20. A semiconductor package, comprising: a redistribution layer, including a redistribution insulating layer, a wiring pattern and vias; a through-mold via connected to at least one of the wiring pattern and the via on the first surface of the redistribution layer; an under bump metallization layer on the first surface of the through molded via; a photonic integrated circuit on the first surface of the redistribution layer; a first molding layer on the first surface of the redistribution layer, on the side surfaces of the through-molded vias, and on the side surfaces of the photonic integrated circuit; a first semiconductor chip and a second semiconductor chip on a second surface of the redistribution layer opposite to the first surface of the redistribution layer; a first glass protruding from the second surface of the redistribution layer and penetrating the redistribution layer from the first surface of the redistribution layer to the second surface of the redistribution layer; a second molding layer on the second surface of the redistribution layer, on the side surface of the first semiconductor chip, on the side surface of the second semiconductor chip, and on the side surface of the first glass; as well as A second glass is on the first glass, and the second glass is connected to the optical fiber.

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