Chip packaging structure

Abstract

A chip packaging structure comprises a lead frame, a chip, a plurality of leads, a plurality of first diversion lines and a molding colloid. The chip bearing seat of the lead frame comprises a supporting block and is provided with a first surface and a second surface which are opposite. The supporting block protrudes from the second surface in a direction away from the second surface and has a third surface parallel to the second surface, the supporting block has a first side wall parallel to the first edge of the chip bearing seat and a second side wall parallel to the second edge of the chip bearing seat and connected with the first side wall, and the first edge is perpendicular to the second edge. The chip is arranged on the first surface of the chip bearing seat. The plurality of leads are electrically connected with the chip and the plurality of pins of the lead frame. The plurality of first diversion lines are arranged on the second surface and extend from the side of the first side wall to the side of the second side wall. The molding colloid covers the first surface and the second surface and wraps the chip, the plurality of leads, the plurality of pins and the plurality of first diversion lines. The molding compound covers the first side wall and the second side wall of the support block and exposes the third surface.

Description

Technical Field

[0001] The present invention relates to a chip packaging structure. Background Art

[0002] In the process of packaging a traditional lead frame type molded semiconductor packaging structure, an entire lead frame strip including a plurality of packaging units arranged in a matrix is used as a carrier, and the packaging structure is fabricated batch by batch. As Figure 6 shown, the entire lead frame strip 10 includes a plurality of lead frame units 20. A plurality of chips (not shown) are respectively disposed on corresponding lead frame units 20, and are electrically connected to the pins of the lead frame units by wire bonding or solder balls. Finally, these lead frame units 20 of the entire lead frame strip 10 are covered with a molding compound 30. More specifically, in the bottom of each lead frame unit 20, a half-etching process is usually used to remove part of the metal, so as to form protruding structures such as a support block at the bottom of the chip seat and an external connection end point at the bottom of the pin, making the lead frame have a non-uniform thickness. In this way, when the molding compound 30 is filled, these protruding structures will block the flow of the molding compound 30, resulting in the molding flow rate of the molding compound 30 near the protruding structures being less than that at a position farther away from the protruding structures. Therefore, the air at the back end of the protruding structures may be wrapped by the molding compound 30 with a faster flow rate on both sides before being discharged, forming bubbles 40 (voids). Since the molding flow 50 moves from one side (such as the front section 50a) to the other side (such as the rear section 50b) when the entire lead frame strip 10 is subjected to the molding process, the protruding structures of each lead frame unit 20 passed through impede the flow rate, resulting in a larger flow rate difference accumulating in the rear section 50b, making the lead frame units 20 at that position more likely to have bubbles 40 due to the back wrapping of the molding compound 30. Summary of the Invention

[0003] The present invention provides a chip packaging structure, which can reduce the probability of the back wrapping phenomenon of the molding compound, avoid the generation of bubbles in the molding compound, and thereby improve the product reliability.

[0004] A chip packaging structure of the present invention includes a lead frame, a chip, a plurality of wires, a plurality of first diversion wires, and a molding compound. The lead frame includes a chip carrier and a plurality of pins. The chip carrier includes at least one support block and has opposite first and second surfaces. At least one support block protrudes from the second surface in a direction away from the second surface and has a third surface parallel to the second surface. At least one support block has a first side wall parallel to the first side of the chip carrier and a second side wall parallel to the second side of the chip carrier and connecting the first side wall, wherein the first side is perpendicular to the second side. The chip is disposed on the first surface of the chip carrier. A plurality of wires are electrically connected to the chip and the plurality of pins. A plurality of first diversion wires are disposed on the second surface and extend from beside the first side wall to beside the second side wall. The molding compound covers the first and second surfaces and encapsulates the chip, the plurality of wires, the plurality of pins, and the plurality of first diversion wires. The molding compound covers the first side wall and the second side wall of at least one support block and exposes the third surface.

[0005] In an embodiment of the present invention, the highest point of the plurality of first diversion wires has a first height from the second surface, the third surface of the support block has a second height from the second surface, and the first height is less than the second height.

[0006] In an embodiment of the present invention, the first height is not greater than two-thirds of the second height.

[0007] In an embodiment of the present invention, the plurality of first diversion wires extend obliquely with respect to the first side wall and the second side wall.

[0008] In an embodiment of the present invention, the pins include external connection portions and have opposite fourth and fifth surfaces. The external connection portions protrude from the fifth surface in a direction away from the fifth surface and have a sixth surface parallel to the fifth surface. The external connection portions have a third side wall parallel to the first side of the chip carrier and a fourth side wall parallel to the second side of the chip carrier and connecting the third side wall.

[0009] In an embodiment of the present invention, the chip packaging structure further includes a plurality of second diversion wires disposed on the fifth surface and extending from beside the third side wall to beside the fourth side wall.

[0010] In an embodiment of the present invention, the second side wall beside which the plurality of first diversion wires are disposed and the fourth side wall beside which the plurality of second diversion wires are disposed face the same direction.

[0011] In an embodiment of the present invention, the molding compound covers the fourth and fifth surfaces and encapsulates the plurality of second diversion wires. The molding compound covers the third side wall and the fourth side wall of the external connection portion and exposes the sixth surface.

[0012] In an embodiment of the present invention, the third height from the topmost point of the plurality of second diversion lines to the fifth surface is such that the sixth surface of the external connection portion to the fifth surface has a fourth height, and the third height is less than the fourth height.

[0013] In an embodiment of the present invention, the above-mentioned third height is not greater than two-thirds of the fourth height.

[0014] Based on the above, the present invention at least through the design of arranging the first diversion line beside the support block with a thickness difference at the bottom of the chip carrier, guides the encapsulation colloid at this position to the position where bubbles are likely to occur at the end of the support block. In this way, the encapsulation colloid can have a relatively uniform flow velocity at the bottom of the lead frame, so as to reduce the probability of the back-packing phenomenon, avoid the generation of bubbles in the encapsulation colloid, and thus improve the product reliability.

[0015] To make the above features and advantages of the present invention more obvious and understandable, the following specific embodiments are given and described in detail with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. 15 is a bottom view schematic diagram of a chip packaging structure shown according to an embodiment of the present invention;

[0017] Figure 2 FIG. 19 is a sectional schematic diagram taken along line A-A' of FIG. 15; Figure 1 FIG. 21 is a partial three-dimensional schematic diagram of FIG. 15;

[0018] Figure 3 FIG. 25 is a partial three-dimensional schematic diagram of FIG. 15; Figure 1 FIG. 27 is an enlarged schematic diagram of region R1 of FIG. 15 from another perspective;

[0019] Figure 4 FIG. 31 is a sectional schematic diagram taken along line B-B' of FIG. 15; Figure 3 FIG. 33 is an enlarged schematic diagram of region R1 of FIG. 15 from another perspective;

[0020] Figure 5 FIG. 37 is a sectional schematic diagram taken along line B-B' of FIG. 15; Figure 3 FIG. 39 is a sectional schematic diagram taken along line B-B' of FIG. 15;

[0021] Figure 6 FIG. 43 is a top view schematic diagram of a semiconductor packaging structure of the prior art during the packaging process.

[0022] It should be noted that, according to the standard practice in the industry, various features are not shown to scale. In fact, for the purpose of clear explanation and illustration, the sizes of various features can be arbitrarily enlarged or reduced, and some components can be omitted, such as Figure 1 , Figures 3 to 4 The encapsulation colloid is omitted. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The following detailed description provides numerous specific details to enable a thorough understanding of the present invention. However, those skilled in the art will understand that the present invention can be practiced without these details. In other instances, well-known methods, steps, components, and circuits have not been described in detail so as not to obscure the understanding of the present invention. It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of various embodiments. For the purpose of simplifying the present disclosure, components and configurations are described below in specific examples. Of course, these are merely examples and are not intended to limit the present invention.

[0024] The following disclosure provides many different embodiments or examples for implementing different features of the present application. Specific examples of components and configurations are described below to simplify the disclosure of the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, the following description of forming a first feature on or above a second feature may include embodiments in which the first feature is in direct contact with the second feature; it may also include embodiments in which other features are present between the first feature and the second feature, such that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat the same element symbols and / or letters in different examples. This repetition is for the purpose of simplification and clear expression, and is not used to describe the relationship between different embodiments and / or configurations.

[0025] Figure 1 A bottom view schematic diagram of a chip package structure as shown in an embodiment of the present invention. Figure 2 Along Figure 1 A cross-sectional schematic diagram taken along line A-A' of Figure 3 For Figure 1 A partial perspective schematic diagram of Figure 4 For Figure 3 An enlarged schematic diagram of region R1 of Figure 5 Along Figure 3 A cross-sectional schematic diagram taken along line B-B' of

[0026] Please refer to Figures 1 to 2 , in this embodiment, the chip package structure 100 includes a lead frame 110 having a chip carrier 111 and a plurality of pins 112, a chip 120, and a plurality of wires 130, wherein the chip carrier 111 has opposite first and second surfaces S1 and S2, the chip 120 is disposed on the first surface S1 of the chip carrier 111, and the plurality of wires 130 electrically connect the chip 120 and the plurality of pins 112. In addition, the chip carrier 111 includes at least one support block 113 ( Figure 1Two are schematically shown in the figure), and the support block 113 protrudes from the second surface S2 in a direction away from the second surface S2 and has a third surface S3 parallel to the second surface S2. Here, the protruding support block 113 will form a thickness difference with the surrounding area. Herein, the number of support blocks 113 can be determined according to the actual design requirements, and the present invention is not limited thereto. The support block 113 can be a protruding structure formed at the bottom of the chip carrier 111 by removing some metal materials at the bottom of the lead frame 110 through a semi-etching process.

[0027] Furthermore, the support block 113 has a first side wall 113a parallel to the first side 111a of the chip carrier 111 and a second side wall 113b parallel to the second side 111b of the chip carrier 111 and connecting the first side wall 113a, wherein the first side 111a is perpendicular to the second side 111b, and the first side 111a can be the long side of the chip carrier 111, and the second side 111b can be the short side of the chip carrier 111, but the present invention is not limited thereto.

[0028] In this embodiment, the chip packaging structure 100 further includes a plurality of first lead wires 140 and a molding compound 150, and the plurality of first lead wires 140 are disposed on the second surface S2 and extend from beside the first side wall 113a to beside the second side wall 113b. The first lead wires 140 can be formed on the second surface S2 of the chip carrier 111 in the same way as the lead wires 130 by wire bonding. For example, first form a spherical first solder joint on the second surface S2 beside the first side wall 113a, and then extend it to beside the second side wall 113b and form a fish-tail or crescent-shaped second solder joint on the second surface S2 (as Figure 4 shown), but the present invention is not limited thereto. On the other hand, the molding compound 150 covers the first surface S1 and the second surface S2 and encapsulates the chip 120, the plurality of lead wires 130, the plurality of pins 112 and the plurality of first lead wires 140, wherein the molding compound 150 covers the first side wall 113a and the second side wall 113b of the support block 113 and exposes the third surface S3 ( Figure 3 The slanted part in is the exposed part of the third surface S3 of the support block 113). Accordingly, in this embodiment, through the design of arranging the first lead wires 140 beside the support block 113 with a thickness difference, the molding compound 150 at this place is guided to the position where bubbles are likely to occur. In this way, the molding compound 150 can have a relatively uniform flow rate at the bottom of the lead frame 110, so as to reduce the probability of the back-packaging phenomenon and avoid the generation of bubbles in the molding compound 150, thereby improving the product reliability. It should be noted that although Figure 4 shows four first lead wires 140, the present invention is not limited thereto, and the number of the first lead wires 140 can be determined according to the actual design requirements.

[0029] Please refer to Figure 3 andFigure 4 The topmost point 140t of the first diversion line 140 has a first height 140h to the second surface S2, the third surface S3 of the support block 113 has a second height 113h to the second surface S2, and the first height 140h is less than the second height 113h. For example, the first height 140h may be no greater than two-thirds of the second height 113h. In this way, the first diversion line 140 can be completely encapsulated within the encapsulant 150 to prevent the first diversion line 140 from being exposed outside the encapsulant 150 and having an adverse effect on the external connection and electrical performance of the chip package structure 100.

[0030] In an embodiment, multiple first diversion lines 140 extend obliquely with respect to the first sidewall 113a and the second sidewall 113b. Specifically, the connecting line of the first solder joint to the second solder joint of the first diversion line 140 on the second surface S2 is not parallel or perpendicular to the first sidewall 113a and the second sidewall 113b, but is obliquely arranged. However, the present invention is not limited thereto.

[0031] In this embodiment, as Figure 4 shown, a plurality of first diversion lines 140 extending toward the second sidewall 113b can be provided beside the two opposite first sidewalls 113a of the support block 113. However, the present invention is not limited thereto.

[0032] Please refer to Figure 3 and Figure 5 , the lead 112 has opposite fourth surface S4 and fifth surface S5, and the lead 112 further includes an external connection portion 114 protruding from the fifth surface S5 in a direction away from the fifth surface S5. The external connection portion 114 has a sixth surface S6 parallel to the fifth surface S5, and a thickness difference is formed between the protruding external connection portion 114 and the surrounding area. The external connection portion 114 may be a protruding structure formed at the bottom of the lead 112 by removing a part of the metal material at the bottom of the lead frame 110 through a semi-etching process.

[0033] Furthermore, the external connection portion 114 has a third side wall 114a parallel to the first side 111a of the chip carrier 111 and a fourth side wall 114b parallel to the second side 111b of the chip carrier 111 and connecting the third side wall 114a. In addition, the chip package structure 100 further includes a plurality of second conductive lines 160 disposed on the fifth surface S5 and extending from beside the third side wall 114a to beside the fourth side wall 114b. The second conductive lines 160 can be formed on the fifth surface S5 of the lead 112 in a wire bonding manner similar to the conductive lines 130. For example, a spherical first solder joint is first formed on the fifth surface S5 beside the third side wall 114a, and then extended toward beside the fourth side wall 114b to form a fishtail or crescent-shaped second solder joint on the fifth surface S5, but the present invention is not limited thereto. Accordingly, by the design of disposing the second conductive lines 160 beside the external connection portion 114 having a thickness difference, the encapsulant 150 at this location is guided to the position where bubbles are likely to occur. In this way, the encapsulant 150 can have a relatively uniform flow rate at the bottom of the lead frame 110, so as to reduce the probability of the back-packing phenomenon and avoid the generation of bubbles in the encapsulant 150, thereby improving the product reliability.

[0034] In one embodiment, the highest point 160t of the plurality of second conductive lines 160 has a third height 160h from the fifth surface S5, and the sixth surface S6 of the external connection portion 114 has a fourth height 114h from the fifth surface S5, and the third height 160h is less than the fourth height 114h. For example, the third height 160h is not greater than two-thirds of the fourth height 114h. In this way, the second conductive lines 160 can be completely covered within the encapsulant 150 to prevent the second conductive lines 160 from being exposed outside the encapsulant 150 and having an adverse effect on the external connection and electrical performance of the chip package structure 100.

[0035] In one embodiment, the plurality of second conductive lines 160 extend obliquely with respect to the third side wall 114a and the fourth side wall 114b. Specifically, the connecting line of the first solder joint to the second solder joint of the second conductive lines 160 on the fifth surface S5 is not parallel or perpendicular to the third side wall 114a and the fourth side wall 114b, but is disposed obliquely, but the present invention is not limited thereto.

[0036] In one embodiment, beside the first sidewall 113a, for example, is a semi-etched area at the bottom of the chip carrier 111, and beside the third sidewall 114a, for example, is a semi-etched area at the bottom of the lead 112. After arranging a plurality of first flow guiding lines 140 and / or a plurality of second flow guiding lines 160, the flow rate of the encapsulant 150 in these semi-etched areas can be effectively slowed down, and through the capillary phenomenon, the encapsulant 150 can flow along the plurality of first flow guiding lines 140 and / or the plurality of second flow guiding lines 160 to positions where bubbles are likely to occur (it can flow along the flow direction D of the encapsulant 150 to the ends of the support block 113 and / or the external connection part 114 where the mold flow rate difference is relatively large). One end of the plurality of first flow guiding lines 140 and / or the plurality of second flow guiding lines 160 can be adjacent to the positions where bubbles are likely to occur, but the present invention is not limited thereto.

[0037] In one embodiment, the second sidewall 113b provided with a plurality of first flow guiding lines 140 beside it and the fourth sidewall 114b provided with a plurality of second flow guiding lines 160 beside it face the same direction, and the encapsulant 150 can flow in the aforementioned facing direction. That is to say, this second sidewall 113b and this fourth sidewall 114b are back to the mold flow, but the present invention is not limited thereto.

[0038] Please refer to Figure 5 , in one embodiment, the encapsulant 150 covers the fourth surface S4 and the fifth surface S5 and encapsulates a plurality of second flow guiding lines 160, wherein the encapsulant 150 covers the third sidewall 114a and the fourth sidewall 114b of the external connection part 114 and exposes the sixth surface S6 ( Figure 3 The slanted part in is the part of the sixth surface S6 where the external connection part 114 is exposed), but the present invention is not limited thereto.

[0039] In one embodiment, the bottom surface 150b of the encapsulant 150, the third surface S3, and the sixth surface S6 are coplanar, but the present invention is not limited thereto.

[0040] In one embodiment, the materials of the first flow guiding line 140 and the second flow guiding line 160 can be the same conductive metal material as that of the wire 130, but the present invention is not limited thereto. The first flow guiding line 140 and the second flow guiding line 160 can also use other suitable materials, as long as they have a flow guiding effect, they fall within the protection scope of the present invention.

[0041] It should be noted that the chip packaging structure 100 can be applied to Dual / Quad Flat No-Lead (DFN / QFN) packaging. The above-mentioned support blocks 113 and external connection parts 114 can be protruding structures formed on the bottom of the lead frame by a semi-etching process according to actual design requirements, and their quantity can be set according to needs, which is not limited in the present invention. In addition, the arrangement positions of the plurality of first diversion lines 140 and the plurality of second diversion lines 160 can be selectively arranged in the area where bubbles are likely to form (usually the rear section of the mold flow of the mold encapsulation colloid 150 and at the end of the support block 113 and / or the external connection part 114 in the flow direction D of the mold encapsulation colloid 150) according to the flow direction D of the mold encapsulation colloid 150 and the configuration of the support blocks 113 at the bottom of the chip carrier 111 and the external connection parts 114 at the bottom of the pins 112. Furthermore, as long as the extending directions of the plurality of first diversion lines 140 and / or the plurality of second diversion lines 160 can guide the mold encapsulation colloid 150 to the area where bubbles are likely to form, they all fall within the protection scope of the present invention.

[0042] In summary, the present invention at least through the design of arranging the first diversion line beside the support block with a thickness difference at the bottom of the chip carrier, guides the mold encapsulation colloid at this place to the position where bubbles are likely to occur at the end of the support block. In this way, the mold encapsulation colloid can have a relatively uniform flow velocity at the bottom of the lead frame, so as to reduce the probability of the back-packing phenomenon, avoid the generation of bubbles in the mold encapsulation colloid, and further improve the product reliability.

[0043] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: A lead frame, comprising a chip carrier and a plurality of pins, wherein the chip carrier comprises at least one support block and has a first surface and a second surface opposite to each other, the at least one support block protrudes from the second surface in a direction away from the second surface and has a third surface parallel to the second surface, the at least one support block has a first side wall parallel to a first side of the chip carrier and a second side wall parallel to a second side of the chip carrier and connected to the first side wall, wherein the first side is perpendicular to the second side; A chip, disposed on the first surface of the chip carrier; A plurality of wires electrically connecting the chip and the plurality of pins; A plurality of first guide lines are disposed on the second surface and extend from the first side wall to the second side wall; as well as The molding colloid covers the first surface and the second surface and encapsulates the chip, the plurality of wires, the plurality of pins and the plurality of first guide wires, wherein the molding colloid covers the first side wall and the second side wall of the at least one supporting block and exposes the third surface.

2. The chip packaging structure according to claim 1, characterized in that: A first height is provided from the topmost points of the plurality of first guide lines to the second surface, a second height is provided from the third surface of the support block to the second surface, and the first height is smaller than the second height.

3. The chip packaging structure according to claim 2, characterized in that: The first height is no greater than two-thirds of the second height.

4. The chip packaging structure according to claim 1, characterized in that: The plurality of first guide lines extend obliquely relative to the first side wall and the second side wall.

5. The chip packaging structure according to claim 1, characterized in that: The pin includes an external connection portion and has a fourth surface and a fifth surface relative to each other. The external connection portion protrudes from the fifth surface in a direction away from the fifth surface and has a sixth surface parallel to the fifth surface. The external connection portion has a third side wall parallel to the first edge of the chip carrier and a fourth side wall parallel to the second edge of the chip carrier and connected to the third side wall.

6. The chip packaging structure according to claim 5, characterized in that: It also includes a plurality of second guide lines, which are arranged on the fifth surface and extend from the third side wall to the fourth side wall.

7. The chip packaging structure according to claim 6, characterized in that: The second side wall, beside which the plurality of first guide lines are arranged, and the fourth side wall, beside which the plurality of second guide lines are arranged, face the same direction.

8. The chip packaging structure according to claim 6, characterized in that: The mold encapsulation glue covers the fourth surface and the fifth surface and encapsulates the plurality of second guide lines, wherein the mold encapsulation glue covers the third side wall and the fourth side wall of the external connection portion and exposes the sixth surface.

9. The chip packaging structure according to claim 6, characterized in that: A third height is formed from the apex of the plurality of second guide lines to the fifth surface, a fourth height is formed from the sixth surface of the circumscribed portion to the fifth surface, and the third height is smaller than the fourth height.

10. The chip packaging structure according to claim 9, characterized in that: The third height is no greater than two-thirds of the fourth height.

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