Decoding method for reducing noise influence, decoding circuit and power supply device

Abstract

The invention provides a decoding method for reducing noise influence, a decoding circuit and a power supply device. The decoding method for reducing the noise influence comprises the following steps of: dividing a voltage level of an analog signal to be decoded into a plurality of levels; judging the level of the analog signal to be decoded, and capturing the current level of the analog signal to be decoded to obtain a current level number; when the current level number is greater than a highest level variable, updating the highest level variable; when the current level number is smaller than a lowest level variable, updating the lowest level variable; and when the difference value between the lowest level variable and the highest level variable is greater than a noise allowable difference value, outputting an edge detection pulse, and setting the highest level variable and the lowest level variable as the current level number.

Description

Technical Field

[0001] This application relates to a noise suppression technology, and particularly to a decoding method, a decoding circuit, and a power supply device for reducing the impact of noise. Background Art

[0002] Automatic charging is a popular device at present. The Universal Serial Bus Power Delivery (USB PD) protocol is the most widely used transmission specification. Its main transmission interfaces are not only for charging and discharging through the power bus pin (VBUS pin), but also another related interface signal is on the Channel Configuration pin (CC pin). Since during data transmission (bit rate is about 300K / s), the voltage level of the Channel Configuration pin (CC pin) is approximately around 1.1V. Therefore, if it is interfered by any noise during transmission, it may affect the correct reception of data during information transmission in Universal Serial Bus Power Delivery.

[0003] The Universal Serial Bus Power Delivery protocol includes not only power, but also coordinates the data flow direction, data format, and master-slave relationship between two devices. Through the transmission of the Channel Configuration pin, when converted into a digital signal, its data packet also includes the calculation and comparison of cyclic redundancy check to avoid the use of incorrect packet data caused by noise interference.

[0004] However, if the detection of noise can be enhanced and its occurrence probability can be reduced before the Bi-Phase Marker Coded (BMC) is converted into a digital signal (or for packets using other coding forms). In the usage efficiency of the Universal Serial Bus Power Delivery protocol, the system application will be more stable and the information transmission efficiency will be more optimized. Summary of the Invention

[0005] This application provides a method for reducing the impact of power signal line noise on decoding, a decoding circuit using the same, and a power supply providing / receiving device using the same, so as to enhance the detection of noise and reduce the occurrence probability of noise before converting the carrier into a digital signal.

[0006] An embodiment of the present application provides a decoding method for reducing the influence of noise, which includes: dividing the voltage level of an analog signal to be decoded into multiple levels; judging the level of the analog signal to be decoded, and extracting the current level of the analog signal to be decoded to obtain a current level number; when the current level number is greater than a highest level variable, updating the highest level variable; when the current level number is less than a lowest level variable, updating the lowest level variable; and when the difference between the lowest level variable and the highest level variable is greater than a noise tolerance difference, outputting an edge detection pulse, setting the highest level variable and the lowest level variable to the current level number, and continuously judging the level of the analog signal to be decoded to obtain the current level number.

[0007] An embodiment of the present application provides a decoding circuit, which includes a plurality of comparators, a noise filtering and signal edge detection circuit, and a digital signal information processing circuit. The plurality of comparators include a first end, a second end, and an output end. The first ends of the plurality of comparators receive an analog signal to be decoded, and the second ends of the plurality of comparators are coupled to a corresponding reference voltage level, wherein the plurality of reference voltage levels are all different. The noise filtering and signal edge detection circuit is coupled to the output ends of the comparators, wherein in the noise filtering and signal edge detection circuit, the signals output by the output ends of the plurality of comparators are set to a corresponding level.

[0008] Wherein, the noise filtering and signal edge detection circuit judges the level of the analog signal to be decoded according to the signal output by the output end of the comparator to judge the current level of the analog signal to be decoded to obtain a current level number. Wherein, the noise filtering and signal edge detection circuit internally has a highest level variable and a lowest level variable. When the current level number is greater than a highest level variable, updating the highest level variable to the current level number. When the current level number is less than a lowest level variable, updating the lowest level variable to the current level number. When the difference between the lowest level variable and the highest level variable is greater than a noise tolerance difference, the noise filtering and signal edge detection circuit outputs an edge detection pulse, sets the highest level variable and the lowest level variable to the current level number, and continuously judges the level of the analog signal to be decoded to obtain the current level number. The digital signal information processing circuit is coupled to the output end of the noise filtering and signal edge detection circuit and decodes a decoded signal according to the edge detection pulse.

[0009] A method for reducing the influence of power supply signal line noise on decoding, a decoding circuit using the same, and a power supply providing / receiving device using the same. The analog signal to be decoded is obtained from a channel configuration contact (CC pin) of a universal serial bus port. In a preferred embodiment of the present application, the analog signal to be decoded is modulated according to a bipolar mark code.

[0010] To further understand the technology, means, and effects of the present application, reference may be made to the following detailed description and drawings, so that the purpose, features, and concepts of the present application can be thoroughly and specifically understood. However, the following detailed description and drawings are only for reference and illustration of the implementation manner of the present application, and are not used to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The provided drawings are used to enable those of ordinary skill in the art to which the present application pertains to further understand the present application, and are incorporated into and form a part of the specification of the present application. The drawings show exemplary embodiments of the present application and are used together with the specification of the present application to explain the principles of the present application.

[0012] Figure 1 It is shown as a system block diagram of a power supply providing / receiving device according to a preferred embodiment of the present application.

[0013] Figure 2 It is shown as a circuit diagram of an analog circuit block 104 according to a preferred embodiment of the present application.

[0014] Figure 3 It is shown as an operation flow chart of a noise filtering and signal edge detection circuit 105 when performing the current bit level digital in_level according to a preferred embodiment of the present application.

[0015] Figure 4 It is shown as an operation flow chart of a noise filtering and signal edge detection circuit 105 when performing the highest bit level variable Hi_count and the lowest bit level variable Low_count according to a preferred embodiment of the present application.

[0016] Figure 5 It is shown as an operation waveform diagram of a noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present application.

[0017] Figure 6 It is shown as an operation waveform diagram of a noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present application.

[0018] Figure 7 It is shown as an operation waveform diagram when the first comparator 201, the second comparator 202, and the third comparator 203 encounter noise according to a preferred embodiment of the present application.

[0019] Figure 8 The waveform diagram of the operation of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present application is shown.

[0020] Figure 9 The flowchart of the method for reducing the influence of power supply signal line noise on decoding according to a preferred embodiment of the present application is shown.

[0021] Symbol Explanation

[0022] 101: Universal Serial Bus port;

[0023] 102: Decoding circuit;

[0024] 103: Power supply providing / receiving circuit;

[0025] CCpin: Channel configuration pressure point;

[0026] 104: Analog circuit block;

[0027] 105: Noise filtering and signal edge detection circuit;

[0028] 106: Digital signal information processing circuit;

[0029] Bit_OUT: Decoding signal;

[0030] 201: First comparator;

[0031] 202: Second comparator;

[0032] 203: Third comparator;

[0033] Analog_RCed: Analog signal to be decoded;

[0034] HTH, MTH, LTH: Reference voltage levels;

[0035] Comparator_Slice OUT[2]: Comparison signal output from the output terminal of the first comparator 201;

[0036] Comparator_Slice OUT[1]: Comparison signal output from the output terminal of the second comparator 202;

[0037] Comparator_Slice OUT[0]: Comparison signal output from the output terminal of the third comparator 203;

[0038] Hi_count: Highest order variable;

[0039] Low_count: Lowest order variable;

[0040] in_level: current level number;

[0041] S301 to S308: steps;

[0042] S401 to S407: steps;

[0043] Edge_detected: edge detection pulse output by the noise filtering and signal edge detection circuit 105;

[0044] 701, 702, 703, 704: noise pulses;

[0045] S901 to S905: steps. Detailed implementation

[0046] Now, a demonstration embodiment of the present application will be described in detail, and the demonstration embodiment will be illustrated in the accompanying drawings. Where possible, the same component symbols are used in the drawings and the specification to refer to the same or similar components. Additionally, the practices of the demonstration embodiments are only one of the implementation manners of the design concept of the present application, and the following demonstrations are not used to limit the present application.

[0047] Figure 1 It is a system block diagram of a power supply providing / receiving device according to a preferred embodiment of the present application. Please refer to Figure 1 , in this embodiment, a power supply providing / receiving device based on the Universal Serial Bus (USB) power transfer protocol is taken as an example. This power supply providing / receiving device includes a Universal Serial Bus port 101, a decoding circuit 102, and a power supply providing / receiving circuit 103. The Universal Serial Bus port 101 includes a channel configuration pressure point CCpin. The decoding circuit 102 includes an analog circuit block 104, a noise filtering and signal edge detection circuit 105, and a digital signal information processing circuit 106. The power supply providing / receiving circuit 103 is coupled to the Universal Serial Bus port 101 and the decoding circuit 102, and receives the decoding signal Bit_OUT (packet data bit output) provided by the decoding circuit 102, thereby communicating the power capabilities and requirements with the device coupled to the other end of the Universal Serial Bus port 101. Due to the reception of data, in the Universal Serial Bus power transfer system, in addition to the voltage signal input through the channel configuration pressure point, digital sampling processing is also required to convert it into real digital information data with noise eliminated, facilitating the decoding of the content on the data packet.

[0048] Figure 2 It is a circuit diagram of the analog circuit block 104 according to a preferred embodiment of the present application. Please refer to Figure 2, in this embodiment, the analog circuit block 104 includes a first comparator 201, a second comparator 202, and a third comparator 203. Each of the comparators 201, 202, and 203 includes a first terminal, a second terminal, and an output terminal. The first terminal of each of the comparators 201, 202, and 203 receives the analog signal Analog_RCed to be decoded obtained from the channel configuration pressure point CCpin. The second terminal of each of the comparators 201, 202, and 203 is respectively coupled to a corresponding reference voltage level HTH (High Threshold), MTH (Middle Threshold), and LTH (Low Threshold). The comparison signals output from the output terminals of the comparators 201, 202, and 203 are respectively labeled as Comparator_Slice OUT[2], Comparator_Slice OUT[1], and Comparator_Slice OUT[0] here.

[0049] The noise filtering and signal edge detection circuit 105 is coupled to the output terminals of the comparators 201, 202, and 203. Among them, in the noise filtering and signal edge detection circuit 105, three variables are set, namely the most significant bit variable Hi_count, the least significant bit variable Low_count, and the current bit level number in_level.

[0050] Figure 3 It is a flowchart showing the operation of the noise filtering and signal edge detection circuit 105 for the current bit level number in_level in a preferred embodiment of the present application. Please refer to Figure 3 , in this embodiment, the operation of the noise filtering and signal edge detection circuit 105 for the current bit level number in_level includes the following steps:

[0051] Step S301: Initial reset.

[0052] Step S302: Determine whether the signal Comparator_Slice OUT[2] at the output terminal of the comparator 201 is a logic high voltage. If the determination is yes, go to step S305. If the determination is no, go to step S303.

[0053] Step S303: Determine whether the signal Comparator_Slice OUT[1] at the output terminal of the comparator 202 is a logic high voltage. If the determination is yes, go to step S306. If the determination is no, go to step S304.

[0054] Step S304: Determine whether the signal Comparator_Slice OUT[0] at the output terminal of comparator 203 is a logic high voltage. If the determination is yes, proceed to step S307. If the determination is no, proceed to step S308.

[0055] Step S305: Set the current digit in_level to the three-digit number 011.

[0056] Step S306: Set the current digit in_level to the three-digit number 010.

[0057] Step S307: Set the current digit in_level to the three-digit number 001.

[0058] Step S308: Set the current digit in_level to the three-digit number 000.

[0059] The running time (sampling time) of the above process steps can be designed according to different requirements and will not be elaborated here.

[0060] Figure 4 The operation flowchart of the noise filtering and signal edge detection circuit 105 for the highest digit variable Hi_count and the lowest digit variable Low_count in a preferred embodiment of the present application is shown. Please refer to Figure 4 , the operation of the noise filtering and signal edge detection circuit 105 for the highest digit variable Hi_count and the lowest digit variable Low_count includes the following steps:

[0061] Step S401: Initial reset. Set the highest digit variable Hi_count and the lowest digit variable Low_count to 0.

[0062] Step S402: Input the current digit in_level.

[0063] Step S403: Determine whether the current digit in_level is greater than the highest digit variable Hi_count. If the determination is yes, proceed to step S405.

[0064] Step S404: Determine whether the current digit in_level is less than the lowest digit variable Low_count. If the determination is yes, proceed to step S406.

[0065] Step S405: Set the highest digit variable Hi_count to the current digit in_level. Then, proceed to step S407.

[0066] Step S406: Set the lowest order variable Low_count to the current order digit in_level. Then, proceed to Step S407.

[0067] Step S407: Determine whether the difference between the highest order variable Hi_count and the lowest order variable Low_count is greater than a noise tolerance difference. In this embodiment, the noise tolerance difference is set to 1. When the difference between the highest order variable Hi_count and the lowest order variable Low_count is greater than the noise tolerance difference, trigger the noise filtering and signal edge detection circuit 105 to output an edge detection pulse, and set the highest order variable Hi_count and the lowest order variable Low_count to the current order digit in_level.

[0068] Figure 5 Shown is the operation waveform diagram of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present application. Please refer to Figure 5 , in order for those of ordinary skill in the art to understand the above Figure 3 、 Figure 4 embodiment, here a variable visualization graph is used to mark the changes of the current variables on the graph. It can be seen that at the beginning, when the signal Comparator_Slice OUT[0] at the output end of the comparator 203 changes from a logic low voltage to a logic high voltage, through the Figure 4 process, the highest order variable Hi_count will become 1, the lowest order variable Low_count remains 0, and the current order digit in_level changes from 0 to 1. Next, when the signal Comparator_Slice OUT[1] at the output end of the comparator 202 changes from a logic low voltage to a logic high voltage, through the Figure 4 process, the highest order variable Hi_count will become 2, the lowest order variable Low_count remains 0, and the current order digit in_level changes from 1 to 2. Since Step S407 is triggered here, at this time, the noise filtering and signal edge detection circuit 105 outputs an edge detection pulse, and the highest order variable Hi_count will become 2, the lowest order variable Low_count also changes to 2, and the current order digit in_level becomes 2.

[0069] Next, when the signal Comparator_Slice OUT[2] at the output end of the comparator 203 changes from a logic low voltage to a logic high voltage, through the Figure 4In the process, the highest-order variable Hi_count will become 3, the lowest-order variable Low_count will remain 2, and the current-level digit in_level will change from 2 to 3. Then, when the signal Comparator_Slice OUT[2] at the output terminal of the comparator 203 changes from a logic high voltage to a logic low voltage, via Figure 4 In the process, the highest-order variable Hi_count will remain 3, the lowest-order variable Low_count will remain 2, and the current-level digit in_level will change from 3 to 2. When the signal Comparator_Slice OUT[1] at the output terminal of the comparator 202 changes from a logic high voltage to a logic low voltage, via Figure 4 In the process, the highest-order variable Hi_count will remain 3, the lowest-order variable Low_count will become 1, and the current-level digit in_level will change from 2 to 1. Similarly, at this time, since step S407 is triggered here, at this time, the noise filtering and signal edge detection circuit 105 outputs an edge detection pulse, and the highest-order variable Hi_count will become 1, the lowest-order variable Low_count will also change to 1, and the current-level digit in_level will become 1.

[0070] Next, when the signal Comparator_Slice OUT[0] at the output terminal of the comparator 201 changes from a logic high voltage to a logic low voltage, via Figure 4 In the process, the highest-order variable Hi_count will remain 1, the lowest-order variable Low_count will become 0, and the current-level digit in_level will change from 1 to 0. Then, when the signal Comparator_Slice OUT[0] at the output terminal of the comparator 201 changes from a logic low voltage to a logic high voltage, via Figure 4 In the process, the highest-order variable Hi_count will remain 1, the lowest-order variable Low_count will remain 0, and the current-level digit in_level will change from 0 to 1. The following embodiments can be deduced from the above rules. Therefore, they will not be elaborated here.

[0071] Figure 6 The operation waveform diagram of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present application is shown. Please refer to Figure 6 , where the marked Edge_detected is the edge detection pulse output by the noise filtering and signal edge detection circuit 105. And Bit_OUT is the decoded signal Bit_OUT with the noise eliminated, decoded by the digital signal information processing circuit 106 according to the edge detection pulse output by the noise filtering and signal edge detection circuit 105.

[0072] Figure 7 The operation waveform diagrams of a first comparator 201, a second comparator 202, and a third comparator 203 in a preferred embodiment of the present application when encountering noise are shown. Please refer to Figure 7 , in this embodiment, it can be seen that when the analog signal Analog_RCed to be decoded encounters noise and passes through the reference voltage levels HTH, MTH, and LTH, the comparators 201, 202, and 203 will be triggered and changed, resulting in the comparators 201, 202, and 203 respectively outputting inappropriate noise pulses 701, 702, 703, and 704.

[0073] Figure 8 The operation waveform diagram of the noise filtering and signal edge detection circuit 105 in a preferred embodiment of the present application is shown. Please refer to Figure 8 , in this embodiment, it can be seen that before the time of label 701, since step S407 is triggered, both the highest-order variable Hi_count and the lowest-order variable Low_count are set to 1. Therefore, at the time of label 701, the highest-order variable Hi_count changes to 2, and the lowest-order variable Low_count remains at 1, so the noise filtering and signal edge detection circuit 105 will not be triggered to output an edge detection pulse. By the same token, at the time of label 703, the highest-order variable Hi_count is 1, and the lowest-order variable Low_count remains at 0, so the noise filtering and signal edge detection circuit 105 will not be triggered to output an edge detection pulse. At the time of label 704, the highest-order variable Hi_count is 2, and the lowest-order variable Low_count remains at 2, so the noise filtering and signal edge detection circuit 105 will also not be triggered to output an edge detection pulse.

[0074] In the above embodiments, in order to enable those of ordinary skill in the art to understand the present application, three comparators 201, 202, 203 and three numerical values are used as examples, and the above noise tolerance difference is also simply set to 1. However, those of ordinary skill in the art should understand that after referring to the above embodiments, the more comparators are designed and the more digital designs there are, the larger the noise tolerance difference should be designed, so as to obtain more accurate noise filtering results. In addition, although the above embodiments take the Universal Serial Bus Power Delivery (USBPD) protocol as an example and use the Bi-Phase Marker Coded (BMC) decoding as an example. However, those of ordinary skill in the art should know that other coding methods in other application fields, such as Manchester coding, can also adopt the technology of this case for decoding and filtering noise, so the present application is not limited thereto.

[0075] Figure 9 The figure shows a flowchart of a method for reducing the influence of power supply signal line noise on decoding according to a preferred embodiment of the present application. Please refer to Figure 9 , this method for reducing the influence of power supply signal line noise on decoding includes the following steps:

[0076] Step S901: Divide the voltage level of an analog signal to be decoded into multiple levels. As described in the above Figure 2 embodiment, use multiple comparators to detect the voltage levels of the analog signal to be decoded.

[0077] Step S902: Sequentially assign an arithmetic difference number to the above multiple levels. As described in the above preferred embodiment, use 1, 2, 3 of three digits as examples respectively. Those with ordinary knowledge in the art can also use numbers such as 2, 4, 6. The present application is not limited thereto, and the above numbers can be changed according to the difference between the levels.

[0078] Step S903: Judge the level of the analog signal to be decoded, and extract the current level of the analog signal to be decoded to obtain a current level number. As Figure 3 the method.

[0079] Step S904: When the current level number is greater than a highest level variable, update the highest level variable, and when the current level number is less than a lowest level variable, update the lowest level variable. Such as steps S403 to S406 of the above embodiment.

[0080] Step S905: When the difference between the lowest level variable and the highest level variable is greater than a noise tolerance difference, output an edge detection pulse, and set the highest level variable and the lowest level variable to the current level number, and continuously judge the level of the analog signal to be decoded to obtain the current level number. As in Figure 4 step S407 in the above. After that, the subsequent decoding circuit can decode a decoded signal with noise eliminated according to the time distance between the above edge detection pulses.

[0081] In summary, the embodiments of the present application adopt setting multiple levels, defining the values corresponding to the multiple levels, the current level number, the highest level variable, and the lowest level variable, detecting the times when the analog signal to be decoded reaches the multiple levels respectively, changing the current level number, the highest level variable, and the lowest level variable according to the levels reached by the analog signal to be decoded, and triggering an edge detection pulse and setting the highest level variable and the lowest level variable equal to the current level number when the difference between the highest level variable and the lowest level variable is greater than the noise tolerance difference. Thus, even if the difference between the highest level variable and the lowest level variable changes due to the influence of noise, as long as it is less than the noise tolerance difference, it will not have any impact on the circuit operation.

[0082] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes thereto will be suggested to those skilled in the art and will be included within the spirit and scope of the present application and the scope of the appended claims.

Claims

1. A decoding method for reducing the influence of noise, characterized in that: include: Dividing the voltage level of an analog signal to be decoded into a plurality of levels; Determining the level of the analog signal to be decoded, and capturing the current level of the analog signal to be decoded to obtain a current level number; When the current level number is greater than a highest level variable, updating the highest level variable; When the current level number is less than a lowest level variable, updating the lowest level variable; When the difference between the lowest-level variable and the highest-level variable is greater than a noise tolerance difference, an edge detection pulse is output, and the highest-level variable and the lowest-level variable are set as the current-level digital, and the level of the analog signal to be decoded is continuously determined to obtain the current-level digital; and A decoding signal is generated according to the edge detection pulse.

2. The decoding method for reducing noise influence according to claim 1, characterized in that: The analog signal to be decoded is obtained from a channel configuration voltage point of a universal serial bus port.

3. The decoding method for reducing noise influence according to claim 1, characterized in that: The analog signal to be decoded is modulated according to a bi-phase mark code.

4. A decoding circuit, characterized in that: include: A plurality of comparators, wherein the plurality of comparators include a first terminal, a second terminal and an output terminal, the first terminals of the plurality of comparators receive an analog signal to be decoded, and the second terminals of the plurality of comparators are coupled to a corresponding reference voltage level, wherein the plurality of reference voltage levels are different; a noise filtering and signal edge detection circuit, coupled to the output terminals of the plurality of comparators; The noise filtering and signal edge detection circuit determines the current level of the analog signal to be decoded according to the signal outputted by the output terminal of the comparator to obtain a current level number; The noise filtering and signal edge detection circuit has a highest-order variable and a lowest-order variable inside. Wherein, when the current level number is greater than a highest level variable, the highest level variable is updated to be the current level number; When the current level number is less than a lowest level variable, the lowest level variable is updated to the current level number. When the difference between the lowest-level variable and the highest-level variable is greater than a noise tolerance difference, the noise filtering and signal edge detection circuit outputs an edge detection pulse, sets the highest-level variable and the lowest-level variable as the current-level digital, and continuously determines the level of the analog signal to be decoded to obtain the current-level digital; Wherein, the decoding circuit further includes: A digital signal information processing circuit is coupled to the output end of the noise filter and signal edge detection circuit, and generates a decoding signal according to the edge detection pulse.

5. The decoding circuit according to claim 4, characterized in that: The analog signal to be decoded is obtained from a channel configuration voltage point of a universal serial bus port.

6. The decoding circuit according to claim 4, characterized in that: The analog signal to be decoded is modulated according to a bi-phase mark code, and the digital signal information processing circuit is a bi-phase mark code decoding circuit.

7. A power supply device, characterized in that: include: A universal serial bus port, comprising a channel configuration voltage point, wherein the power supply device is coupled to an external device through the universal serial bus port; A decoding circuit, comprising: A plurality of comparators, wherein the plurality of comparators include a first terminal, a second terminal and an output terminal, the first terminals of the plurality of comparators are coupled to the channel configuration voltage point and receive an analog signal to be decoded through the channel configuration voltage point, and the second terminals of the plurality of comparators are coupled to a corresponding reference voltage level, wherein the plurality of reference voltage levels are different; a noise filtering and signal edge detection circuit, coupled to the output terminals of the plurality of comparators; The noise filtering and signal edge detection circuit determines the current level of the analog signal to be decoded according to the signal outputted by the output terminal of the comparator to obtain a current level number; The noise filtering and signal edge detection circuit has a highest-order variable and a lowest-order variable inside. Wherein, when the current level number is greater than a highest level variable, the highest level variable is updated to be the current level number; When the current level number is less than a lowest level variable, the lowest level variable is updated to the current level number. When the difference between the lowest-level variable and the highest-level variable is greater than a noise tolerance difference, the noise filtering and signal edge detection circuit outputs an edge detection pulse, sets the highest-level variable and the lowest-level variable as the current-level digital, and continuously determines the level of the analog signal to be decoded to obtain the current-level digital; Wherein, the decoding circuit further includes: A digital signal information processing circuit is coupled to the output end of the noise filter and signal edge detection circuit, and decodes a decoding signal according to the time of the edge detection pulse. Wherein, the power supply device further includes: a power supply / receiving circuit, coupled to the universal serial bus port, receiving the decoding signal, The power supply / receiving circuit communicates with the coupled external device according to the decoded signal.

8. The power supply device according to claim 7, characterized in that: The analog signal to be decoded is modulated according to a bi-phase mark code, and the digital signal information processing circuit is a bi-phase mark code decoding circuit.

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