Optical module port signal quality adjusting and testing system, adjusting and testing device, adjusting and testing method and computer equipment

Abstract

The invention relates to the technical field of communication, and provides a signal quality adjusting and testing system, device and method of an optical module port and computer equipment. The debugging and testing device is connected with to-be-tested equipment and computer equipment; the computer equipment configures an equalization parameter for a serializer of an optical module port of the equipment to be tested; after the computer equipment configures equalization parameters for the serializer of the optical module port every time, the debugging and testing device receives a high-speed serial signal, sent by the equipment to be tested, of the serializer, evaluates the quality of the high-speed serial signal, obtains a signal quality testing result and feeds back the signal quality testing result to the computer equipment; and finally, the computer equipment selects a target equalization parameter of the serializer from each signal quality test result. The system can replace a conventional oscilloscope to adjust and test the signal of the optical module port, the debugging process is simple and convenient, the manual participation workload is small, and accidental errors can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular, to a signal quality debugging system, a debugging device, a debugging method, and a computer device for an optical module port. Background Art

[0002] The performance evaluation criteria for the optical module ports of network devices need to follow the protocol corresponding to the optical module type. Taking the optical module as SFP+ or SFP28 as an example, the performance evaluation criteria for the SFP+ and SFP28 ports of network devices follow the protocols SFF-8431 and 25GAUI C2M respectively. The protocol makes specific requirements on the timing and amplitude of signals, including jitter, noise, etc. For each SFP+ / SFP28 port of the network device, it is necessary to adjust its SerDes (High-Speed Serial Signal) equalization parameters to make the signal quality optimal and meet the protocol compliance standard. Adjusting the port SerDes equalization parameters aims to perform spectral shifting and filtering on the signal, perform equalization compensation on the frequency response of the channel, and reduce the influence of channel distortion on the signal during signal transmission.

[0003] The prior art usually uses an oscilloscope to debug and test the SFP+ and SFP28 ports of network devices. Specifically, a compliance test fixture (HCB) that meets the protocol standard is used to access the SFP+ / SFP28 port of the device under test (DUT), and the signal is input into the oscilloscope. The SerDes parameters of the port are configured by the PC, and the oscilloscope tests the port transmission signal in real time. However, using an oscilloscope instrument to debug and test the optical module ports of network devices has problems such as complex topology, expensive oscilloscope instrument, low efficiency, and the need for manual configuration and calibration. As the number of SFP+ / SFP28 ports of network devices increases, the manual test efficiency becomes low.

[0004] It should be noted that the above content is only used to assist in understanding the technical solution of the present invention, and does not represent an admission that the above content is the prior art. Summary of the Invention

[0005] The present invention provides a signal quality debugging system, a debugging device, a debugging method, and a computer device for an optical module port to solve the technical problems of high cost and low efficiency in using an oscilloscope instrument to debug and test the optical module ports of network devices mentioned in the above background art.

[0006] In a first aspect, the present invention provides a signal quality debugging system for an optical module port. The system includes a debugging device and a computer device, and the debugging device is respectively connected to the device under test and the computer device;

[0007] The computer device is configured to configure equalization parameters for the serializer of the optical module port of the device under test;

[0008] The debugging device is used to receive the high-speed serial signal of the serializer sent by the device under test after the computer device configures the equalization parameters for the serializer of the optical module port each time, evaluate the quality of the high-speed serial signal, obtain a signal quality test result, and feedback the signal quality test result to the computer device;

[0009] The computer device is used to select the target equalization parameter of the serializer from each signal quality test result, where the target equalization parameter represents the equalization parameter that enables the signal quality of the optical module port to reach the target performance.

[0010] The beneficial effect of the first aspect of this application is that the debugging device is respectively connected to the device under test and the computer device; the computer device configures the equalization parameter for the serializer of the optical module port of the device under test; after the computer device configures the equalization parameter for the serializer of the optical module port each time, the debugging device receives the high-speed serial signal of the serializer sent by the device under test, evaluates the quality of the high-speed serial signal, obtains a signal quality test result, and feedbacks the signal quality test result to the computer device; finally, the computer device selects the target equalization parameter of the serializer from each signal quality test result. This system can replace a conventional oscilloscope to debug the signal of the optical module port. The debugging process is simple and convenient, with less manual participation and fewer accidental errors.

[0011] In a second aspect, this application also proposes a debugging device, which is configured with a retiming chip, a microcontroller unit, a transceiver unit, and a data interface;

[0012] The microcontroller unit is configured to control the retiming chip to receive the high-speed serial signal and control the retiming chip to analyze the quality of the high-speed serial signal to generate an error rate statistical dot matrix diagram of the high-speed serial signal, so as to obtain a signal quality test result including the error rate statistical dot matrix diagram when the transceiver unit receives the high-speed serial signal of the serializer sent by the device under test.

[0013] In an example, the debugging device is configured with a gold finger interface and a data interface;

[0014] The gold finger interface is used to insert into the optical module port of the device under test;

[0015] The data interface is used to connect to the computer device;

[0016] The microcontroller unit is further configured to convert the signal quality test result into an asynchronous serial digital signal format and send it to the transceiver unit;

[0017] The transceiver unit performs level conversion and / or protocol conversion on the signal quality test result, so that the signal quality test result is converted into a format suitable for transmission through the data interface, and the signal quality test result is transmitted to the computer device.

[0018] In one example, the retiming chip includes:

[0019] An error code statistics unit configured to count the number of error codes in the received high-speed serial signal;

[0020] An error rate analysis unit configured to calculate an error rate based on the number of error codes;

[0021] An error rate statistical dot matrix diagram generation unit configured to generate an error rate statistical dot matrix diagram with sampling points at different positions in the symbol period, where the values of different elements in the error rate statistical dot matrix diagram correspond to the error rates when sampling at different positions in the symbol period.

[0022] The beneficial effect of the second aspect of this application is that the debugging device has a simple structural design, but integrates multiple circuit units, making the debugging function complete. The structural design of the debugging device is consistent with the conventional SFP module form and can be embedded in the device under test. In the embodiments of this application, one end of the gold finger is directly embedded in the port of the device under test, without other fixtures or test wiring, and the other end can be made into various forms of data interfaces (such as RJ45 interface, Type-C interface), without additional test fixtures, with low cost and can be mass-produced.

[0023] In a third aspect, this application also proposes a method for debugging the signal quality of an optical module port. The debugging method is applied to the signal quality debugging system of the optical module port described in the first aspect above. The method includes:

[0024] The computer device configures n equalization parameters for the serializer of the optical module port of the device under test, where n is a positive integer;

[0025] In the case where the computer device configures the equalization parameters for the serializer of the optical module port each time, the debugging device receives the high-speed serial signal of the serializer sent by the device under test; and in the case of receiving the high-speed serial signal each time, evaluates the quality of the high-speed serial signal to obtain the signal quality test result;

[0026] The computer device selects the target equalization parameter of the serializer from the signal quality test results corresponding to the equalization parameters configured by the serializer each time; where the target equalization parameter represents the equalization parameter that enables the signal quality of the optical module port to reach the target performance.

[0027] In one example, when the debugging device receives the high-speed serial signal each time, it evaluates the quality of the high-speed serial signal to obtain the signal quality test result, including:

[0028] When the debugging device receives the high-speed serial signal each time, it analyzes the quality of the high-speed serial signal to generate a bit error rate statistical dot matrix diagram of the high-speed serial signal, and calculates the signal quality index corresponding to the bit error rate statistical dot matrix diagram;

[0029] Taking the signal quality index corresponding to the bit error rate statistical dot matrix diagram as the signal quality test result of the high-speed serial signal; wherein, the signal quality index includes eye width and eye height, the eye width characterizes the jitter information of the high-speed serial signal, and the eye height characterizes the amplitude noise information of the high-speed serial signal.

[0030] In one example, the computer device selects the target equalization parameter of the serializer from the signal quality test results corresponding to the equalization parameters configured by the serializer each time, including:

[0031] The computer device establishes m groups of weight coefficient combinations based on each signal quality test result, and each group of weight coefficient combinations includes an eye width weight coefficient variable and an eye height weight coefficient variable;

[0032] Calculating the candidate scores of the signal quality indexes corresponding to n equalization parameters under the i-th group of weight coefficient combinations respectively, to obtain n candidate scores under the i-th group of weight coefficient combinations;

[0033] Sorting the n candidate scores under the i-th group of weight coefficient combinations, taking the candidate score with the largest value as the largest candidate score in the i-th group of weight coefficient combinations, determining the candidate equalization parameter corresponding to the largest candidate score, and obtaining m candidate equalization parameters; where m is a positive integer;

[0034] Obtaining the bit error rate of each candidate equalization parameter, and selecting the candidate equalization parameter with the smallest bit error rate as the target equalization parameter.

[0035] In one example, the method further includes:

[0036] The computer device sends the target equalization parameter to the device under test, so that the device under test calibrates the optical module port.

[0037] The beneficial effect of the third aspect of this application lies in that: the signal quality debugging method for the optical module port provided by this application can automatically find the optimal target equalization parameters, avoiding the inefficiency and errors of manual debugging required in the conventional sampling oscilloscope method. It can compensate for the loss of high-frequency components during signal transmission, achieve the equalization of high-frequency and low-frequency signals at the receiving end, thereby improving the signal quality and meeting the protocol consistency standard.

[0038] Fourthly, this application also proposes a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the signal quality debugging method for the optical module port as described in the third aspect above.

[0039] Fifthly, this application also proposes a computer program product. The computer program product stores a computer program, and when the computer program is executed by a processor, it implements the signal quality debugging method for the optical module port as described in the third aspect above.

[0040] For the beneficial effects of the fourth and fifth aspects of this application, please refer to the beneficial effects of the first to third aspects above, and will not be elaborated here. Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0042] Figure 1 is the system topology diagram for debugging and testing the optical module port signal of the network device to be measured based on an oscilloscope in the conventional technology;

[0043] Figure 2 is the system topology diagram of the signal quality debugging system for the optical module port provided by the embodiment of this application;

[0044] Figure 3 is the structural schematic diagram of the debugging device provided by the embodiment of this application;

[0045] Figure 4 is the structural block diagram of the retiming chip provided by the embodiment of this application;

[0046] Figure 5 is the flow schematic diagram of the embodiment of the signal quality debugging method for the optical module port provided by this application;

[0047] Figure 6 is the flow schematic diagram of another embodiment of the signal quality debugging method for the optical module port provided by this application;

[0048] Figure 7 It is a block diagram of a computer device provided by an embodiment of the present application.

[0049] The realization of the object of the present invention, functional features and advantages will be further described with reference to the accompanying drawings in conjunction with the embodiments. Specific Embodiments

[0050] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0051] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system architectures and technologies are set forth in order to provide a thorough understanding of the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices and methods are omitted so as not to obscure the description of the present application with unnecessary details.

[0052] It should be understood that when used in the specification of the present application and the appended claims, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations.

[0053] It should also be understood that the term "and / or" used in the specification of the present application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0054] In addition, in the description of the specification of the present application and the appended claims, the terms "first", "second", "third", etc. are only used for differential description and should not be construed as indicating or implying relative importance.

[0055] The reference to "one embodiment" or "some embodiments" etc. described in the specification of the present application means that a specific feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. appearing in different places in this specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in another way.

[0056] It is understandable that one way to debug and test the optical module ports of network devices using an oscilloscope instrument is to use the oscilloscope to detect the signal eye diagram of the SFP+ / SFP28 ports of the network device, determine the optimal equalization parameters of the measured ports, but there are problems such as complex topology, expensive oscilloscope instruments, low efficiency, and the need for manual configuration and calibration. As the number of SFP+ / SFP28 ports of network devices increases, the manual test efficiency becomes low.

[0057] Figure 1 The system test topology diagram for debugging and testing the SFP+ / SFP28 port signals of the network device to be tested based on the oscilloscope is shown. A compliance test fixture (HCB) that meets the protocol standard is used to access the SFP+ / SFP28 ports of the network device to be tested, and the signal is input into the oscilloscope OSC. The SerDes parameters of the port are configured using a PC, and the oscilloscope tests the port transmission signal in real time.

[0058] The test principle of the oscilloscope for the SerDes signal quality is as follows:

[0059] Digital signals will generate jitter during transmission, that is, the time position of the rising edge or falling edge of the signal changes randomly relative to the expected value. The greater the jitter, the worse the signal quality. In the oscilloscope, through a series of sampling and calculation processes, the eye width of the signal is obtained. The size of the eye width can be used to judge the size of the total jitter, and then judge the signal quality. The eye width is defined as:

[0060] Eye_width(BER)=1×UI-TJ(BER)

[0061] Where UI represents a symbol period, and TJ represents the total jitter of the signal. The eye width is not for a single symbol, but the statistical result of a series of data streams.

[0062] The measurement process of the oscilloscope for the eye width and TJ is as follows:

[0063] Sample the rising edge and falling edge of the signal respectively, count the distribution of the sampling points, and obtain the statistical histogram of the jitter deviation of the rising edge and falling edge of each symbol in the data stream relative to the expected value.

[0064] The probability density distribution is obtained by fitting the histogram, and the integral of the probability density function is performed to obtain the cumulative distribution function, which is the bit error rate distribution curve.

[0065] For the bit error rate distribution curve, each bit error rate corresponds to a time window. The size of the time window is defined as the eye width at this bit error rate. After obtaining the eye width, the total jitter TJ can be calculated through the above formula.

[0066] The eye width of the signal eye diagram fluctuates due to jitter, and similarly, the eye height varies due to noise. The measurement method of the eye height is consistent with the above analysis of the eye width. By statistically analyzing the timing jitter and amplitude noise of each symbol in the signal, the oscilloscope can finally determine the total jitter and noise levels, thereby evaluating the signal quality.

[0067] However, when using Figure 1 the oscilloscope shown to detect the signal eye diagram of the SFP+ / SFP28 port of the network device under test and determine the optimal equalization parameters of the measured port, there are problems such as complex topology, expensive oscilloscope instruments, low efficiency, and the need for manual configuration and calibration. As the number of SFP+ / SFP28 ports of network devices increases, the manual test efficiency becomes low. Therefore, an automated debugging device for SFP+ / SFP28 ports is designed and developed to improve the debugging efficiency.

[0068] Aiming at the technical problems of high cost and low efficiency in debugging and testing the optical module ports of network devices using oscilloscope instruments mentioned above, the present invention provides a signal quality debugging system, debugging device, and debugging method for optical module ports. The technical solutions of this application will be described below through specific embodiments.

[0069] Embodiment 1

[0070] Figure 2 This is the topology diagram of the signal quality debugging system for the optical module port of the embodiment of this application. The system includes a debugging device 01 and a computer device 02. The debugging device 01 is respectively connected to the device under test 03 and the computer device 02;

[0071] The computer device 02 is used to configure equalization parameters for the serializer of the optical module port of the device under test 03;

[0072] The debugging device 01 is used to receive the high-speed serial signal sent by the device under test 03 after the computer device configures the equalization parameters for the serializer of the optical module port each time, evaluate the quality of the high-speed serial signal, obtain the signal quality test result, and feedback the signal quality test result to the computer device 02;

[0073] The computer device 02 is used to select the target equalization parameters of the serializer from each signal quality test result, where the target equalization parameters represent the equalization parameters that enable the signal quality of the optical module port to reach the target performance.

[0074] In a specific implementation, the SFP+ / SFP28 port of a network device is used as the optical module port of the device under test 03 implemented in this application; the computer device 02 automatically scans and configures the equalization parameters (including the pre-cursor and post-cursor de-emphasis parameters) of the serializer (SerDes) transmitter of the optical module port by running the computer program stored in its memory. In the case of configuring each set of equalization parameters, the debugging device 01 will act as the receiver of the SerDes signal (i.e., the high-speed serial signal), evaluate the quality of the SerDes signal, and report the signal quality test result to the computer device 02. The computer program on the computer device 02 can analyze the data according to a preset optimization algorithm, select the equalization parameters that enable the signal quality of the optical module port to reach the target performance, so as to realize the automatic calibration of the optical module port.

[0075] In a specific implementation, referring to Figure 3 , the debugging device 01 of this embodiment is configured with a retiming chip 12, a microcontroller unit 13, a transceiver unit 14, and a data interface 16;

[0076] The microcontroller unit 13 is configured to control the retiming chip 12 to receive the high-speed serial signal and control the retiming chip 12 to analyze the quality of the high-speed serial signal to generate an error rate statistical dot matrix diagram of the high-speed serial signal, so as to obtain a signal quality test result including the error rate statistical dot matrix diagram when the transceiver unit 14 receives the high-speed serial signal of the serializer sent by the device under test.

[0077] In addition, the debugging device 01 of this embodiment is further configured with a gold finger interface 11, a data interface 16, and a Supply power unit 16;

[0078] The power unit 16 is responsible for providing power for the entire debugging device 01. It may include a voltage regulator, a power management circuit, etc., to ensure that each component in the module (such as the Retimer chip 12, the microcontroller unit 13, the interface circuit, etc.) can obtain a stable and appropriate voltage and current supply.

[0079] The gold finger interface 11 is used to insert the optical module port of the device under test 03;

[0080] The data interface 16 is used to connect to the computer device 02;

[0081] The microcontroller unit 13 is further configured to convert the signal quality test result into the format of an asynchronous serial digital signal and send it to the transceiver unit 14;

[0082] The transceiver unit 14 is configured to perform level conversion and / or protocol conversion on the signal quality test result, so that the signal quality test result is converted into a format suitable for transmission by the data interface 16, and the signal quality test result is transmitted to the computer device 02.

[0083] The designed shape of the debugging device 01 in this embodiment is similar to that of a conventional standard SFP module. In terms of interfaces, one end is equipped with a gold finger interface 11, which can be directly inserted into the corresponding port of the device under test 03; the other end is configured with a data interface 16, such as an RJ45 or Type-C interface, which is convenient for direct connection to the control computer device. Such a design ensures that the module can be stably integrated into the device and can be easily connected to the (host computer). If a device under test has multiple different optical module ports, multiple debugging devices 01 can be respectively connected to the device under test to calibrate different optical module ports of itself simultaneously, greatly improving the debugging efficiency.

[0084] Furthermore, the retiming chip 12 in this embodiment has an error rate detection function and can generate an error rate statistical dot matrix diagram of the measured signal. The retiming chip 12 specifically includes:

[0085] An error count unit 121, which is configured to count the number of error codes in the received high-speed serial signal; the logic circuit inside the Retimer chip 12 can count the number of error codes in the received data stream, that is, detect the number of error bits appearing in the data stream.

[0086] An error rate analysis unit 122, which is configured to calculate the error rate based on the number of error codes; that is, the Retimer chip 12 can calculate the bit error rate (BER) according to the number of error codes, that is, the ratio of the number of error bits to the total number of transmitted bits.

[0087] An error rate statistical dot matrix diagram generation unit 123, which is configured to generate an error rate statistical dot matrix diagram based on the error rate; that is, the Retimer chip 12 can also generate an error rate statistical dot matrix diagram for further analyzing the signal quality.

[0088] It can be understood that the functions of the error count unit, the error rate analysis unit, and the error rate statistical dot matrix diagram generation unit are all implemented by the hardware logic inside the Retimer chip 12. The Retimer chip 12 evaluates the signal quality through these functional units, and transmits the signal quality test result to the microcontroller unit 13 through the I2C bus. Finally, the microcontroller unit 13 transmits the signal quality test result after format conversion processing to the computer device 02 for further analysis and parameter optimization.

[0089] In a specific implementation, one end of the debugging device 01 of this embodiment is equipped with a gold finger interface 11 for connecting to the SFP+ or SFP28 optical module port of the device under test 03. The debugging device 01 incorporates a Retimer chip 12. The Retimer chip 12 receives the serial data stream from the optical module port of the device under test 03 through its SerDes interface (these "serial data streams" are essentially high-speed serial communication signals, usually data streams transmitted at a rate of 10 Gbps (SFP+) or 25 Gbps (SFP28). These data streams can be communication data between network devices, such as Ethernet frames, Fibre Channel data packets, etc.). The clock recovery circuit built into the retimer chip 12 extracts the clock signal from the received serial data stream (high-speed serial communication signal). After restoring the clock, the Retimer chip 12 retimes the serial data stream (high-speed serial communication signal), that is, regenerates a stable data signal according to the restored clock. The Retimer chip 12 has dedicated logic inside to count the number of bit errors in the data and perform bit error rate analysis.

[0090] The microcontroller unit 13 (Microcontroller Unit; MCU) controls the Retimer chip 12 through the I2C bus to receive SerDes signals (high-speed serial communication signals), perform bit error rate analysis, and generate a bit error rate statistical dot matrix diagram, and then processes the obtained signal quality test results, formats them into a data format suitable for UART or USB transmission, and transmits the signal quality test results to the computer device 02 through the data interface 16 (RJ45 serial port or Type-C interface).

[0091] It can be understood that in the conventional technology, in order to obtain the eye diagram parameters of the SFP+ / SFP28 port of the device under test on an oscilloscope, it is necessary to use a test fixture HCB to connect the device under test to the oscilloscope, configure the eye diagram template and add test items on the oscilloscope, manually configure the port signal transmitter equalization parameters, and only after a period of data signal acquisition can the measurement results be obtained, and the engineer needs to reconfigure the equalization parameters according to the test results and optimize by comparing the results.

[0092] However, the debugging device 01 of this embodiment uses the debugging device 01 to provide a signal test function after accessing the device under test 03 through the debugging device 01, and supports result reporting and automatic parameter configuration. The debugging device 01 of this embodiment has the following technical effects and advantages:

[0093] Effect 1: The quality analysis and debugging effect of the high-speed serial signal of the Serdes serializer is equivalent to that of an oscilloscope;

[0094] Effect 2: The debugging process is simple and convenient, with less manual participation and fewer accidental errors;

[0095] Effect 3: The debugging device 01 in this embodiment has a simple structural design. The structural design of the debugging device 01 is the same as the conventional SFP module form, and it can be embedded in the device under test for testing without additional test fixtures, with low cost and can be mass-produced;

[0096] Effect 4: If a device under test has multiple different optical module ports, a device under test can be respectively connected to multiple debugging devices 01 to calibrate its different optical module ports simultaneously, greatly improving the debugging efficiency.

[0097] Embodiment Two

[0098] Second, referring to Figure 5 , this application embodiment also proposes a method for debugging the signal quality of an optical module port. The debugging method is applied to the signal quality debugging system of the above optical module port, and the method mainly includes steps S10 to S30:

[0099] Step S10, the computer device configures the equalization parameters for the serializer of the optical module port of the device under test n times.

[0100] Step S20, when the computer device configures the equalization parameters for the serializer of the optical module port each time, the debugging device receives the high-speed serial signal of the serializer sent by the device under test; and each time the high-speed serial signal is received, the quality of the high-speed serial signal is evaluated to obtain the signal quality test result;

[0101] In the specific implementation of this embodiment, the computer device can control the device under test to send the high-speed serial signal of the serializer to the debugging device after configuring the equalization parameters of the serializer of the optical module port each time; of course, in other embodiments, the device under test can also be not controlled by the computer device, that is, the device under test actively sends the high-speed serial signal of the serializer to the debugging device;

[0102] The debugging device can analyze the quality of the high-speed serial signal each time the high-speed serial signal is received to generate an error rate statistical dot matrix diagram of the high-speed serial signal, and calculate the corresponding eye width and eye height of the error rate statistical dot matrix diagram;

[0103] Taking the corresponding eye width and eye height of the error rate statistical dot matrix diagram as the signal quality test result of the high-speed serial signal, the eye width represents the jitter information of the high-speed serial signal, and the eye height represents the amplitude noise information of the high-speed serial signal.

[0104] Among them, under one equalization parameter configuration (under the same set of equalization parameters), the debugging device will analyze the error rates of multiple sampling points to generate an error rate statistical dot matrix diagram;

[0105] It should be noted that the principle of the debugging device provided in this embodiment for testing signal quality is different from that of a conventional oscilloscope. A conventional oscilloscope determines the eye width of a signal eye diagram at each bit error rate by statistically analyzing jitter, while the debugging device provided in this embodiment directly counts the bit error rate, obtains the eye width at different bit error rates, and thereby analyzes the magnitude of jitter.

[0106] The specific implementation steps for the debugging device in this embodiment to measure the signal quality indicators (eye width and eye height) at each bit error rate are as follows:

[0107] 1. Data reception and sampling: Figure 4 When the Retimer chip built into the self-developed module of the retiming chip shown receives a series of data streams of the high-speed serial signal, it offsets the sampling points within the symbol period and counts the number of bit errors at each sampling position.

[0108] 2. Construction of the bit error rate statistical dot matrix diagram: Since the number of bit errors directly reflects the bit error rate, this embodiment can construct a dot matrix diagram representing the bit error rate distribution of different sampling points in the horizontal and vertical directions. This dot matrix diagram is actually the statistical manifestation of the eye width and eye height under different bit error rate conditions.

[0109] 3. Calculation of total jitter and total amplitude noise: Subtract the symbol period and modulation amplitude from the eye width and eye height to obtain the total jitter (TJ) and total amplitude noise (TN) at each bit error rate.

[0110] 4. Separation of jitter types: The total jitter (TJ) can be divided into two types: deterministic jitter (DJ) and random jitter (RJ). Given the Gaussian distribution characteristic of RJ, the variance σ of RJ can be obtained by fitting the tail of the jitter curve.

[0111] 5. Signal quality evaluation: By using the different values of the quality factor Q at different bit error rates, the specific values of DJ and RJ can be separated from TJ, thereby achieving a quantifiable and accurate evaluation of the SerDes signal quality.

[0112] Through the above steps, the debugging device can accurately measure the signal quality indicators of the signal at each bit error rate, further separate and analyze the jitter components, and achieve an accurate evaluation of the signal quality.

[0113] Step S30: The computer device selects the target equalization parameter of the serializer from the signal quality test results corresponding to the equalization parameters configured by the serializer each time; wherein, the target equalization parameter represents the equalization parameter that enables the signal quality of the optical module port to reach the target performance.

[0114] It is understandable that "for each set of configured parameters (under the same set of equalization parameters), the debugging device will act as the receiving end of the SerDes signal, evaluate the signal quality, and report the signal quality test result to the computer device", that is, under one equalization parameter configuration, the retiming chip of the debugging device will analyze the bit error rate of multiple sampling points and generate a bit error rate statistical dot matrix diagram.

[0115] It is known that the computer device configures the equalization parameters n times for the serializer of the optical module port of the device under test. Then, the computer device will receive a total of n test results under the n equalization parameter configurations (i.e., n signal quality test results). The computer device will select the optimal SerDes parameters (i.e., the target equalization parameters) from these n test results under the equalization parameter configurations. In the specific implementation of this embodiment, the computer device can determine the target equalization parameters through the following methods as the basis for selection:

[0116] Sub-step S301: The computer device establishes m groups of weight coefficient combinations based on each signal quality test result. Each group of weight coefficient combinations includes an eye width weight coefficient variable and an eye height weight coefficient variable;

[0117] It is understandable that in this embodiment, the total jitter and total amplitude noise of the high-speed serial signal are obtained through the signal quality definition formula to evaluate the signal quality. The signal quality definition formula in this embodiment involves the maximum eye width parameter, the maximum eye height parameter, the eye width weight coefficient, and the eye height weight coefficient;

[0118] In the specific implementation, in this embodiment, by analyzing each equalization parameter pre-cursor and post-cursor, the eye width and eye height of the high-speed serial signal at a specific bit error rate are measured by the debugging device, and the test results shown in the following table are obtained. The values of the eye width and eye height will change with the change of the pre-cursor and post-cursor coefficients, and their change trends are roughly the same because different equalization effects will affect both the signal jitter and the amplitude noise at the same time.

[0119]

[0120] In order to screen out the optimal transmitter equalization parameters, based on a large amount of test data analysis and verification, this embodiment formulates the following processing method: From the above theoretical analysis, both the eye width and the eye height are standards for measuring the quality of high-speed serial signals. The eye width is given an eye width weight coefficient a, the eye height is given an eye height weight coefficient b, and the maximum eye width X MAX and the maximum eye height Y MAX are obtained from the n signal quality test results. Therefore, the signal quality definition formula in this embodiment is expressed by the following formula:

[0121] T n = a·(Xn / X MAX ) + b·(Y n / Y MAX )

[0122] where T n represents the candidate score of the high-speed serial signal corresponding to the equalization parameter of the i-th configuration; a represents the eye-width weight coefficient variable, and b represents the eye-height weight coefficient variable.

[0123] It should be noted that in this embodiment, the eye-width weight coefficient a and the eye-height weight coefficient b involved in the definition formula of the eye width and eye height are not fixed values, but variables that can be adjusted according to different test requirements and application scenarios. That is to say, the computer device will generate the eye-width weight coefficient variable a and the eye-height weight coefficient variable b based on the test results of each signal quality;

[0124] It can be understood that since the eye width fluctuates due to timing jitter and the eye height changes due to amplitude noise, both are crucial for evaluating signal quality. Therefore, a weight coefficient set can be constructed to accurately quantify its impact on signal quality. For example, for the eye-width weight coefficient variable a and the eye-height weight coefficient variable b, (m groups) weight coefficient combinations can be obtained:

[0125] The first group: a1 = 0.4, b1 = 0.6;

[0126] The second group: a2 = 0.5, b2 = 0.5;

[0127] The third group: a3 = 0.6, b3 = 0.4;

[0128] ... (m groups can be extended);

[0129] The eye-width weight coefficient a and the eye-height weight coefficient b can be adjusted according to the requirements of signal quality evaluation. For example, if the signal jitter (affecting the eye width) has a greater impact on signal quality, the value of a can be increased; if the signal noise (affecting the eye height) has a greater impact on signal quality, the value of b can be increased.

[0130] Step S302: Calculate the candidate scores of the signal quality indicators corresponding to n equalization parameters under the i-th group of weight coefficient combinations respectively, and obtain n candidate scores under the i-th group of weight coefficient combinations;

[0131] It can be understood that in this embodiment, each group of weight coefficients will be substituted into the above signal quality definition formula to calculate the candidate scores of the signal quality indicators corresponding to n equalization parameters under the i-th group of weight coefficient combinations respectively.

[0132] Step S303: Sort the n candidate scores under the i-th group of weight coefficient combinations, take the candidate score with the largest value as the maximum candidate score in the i-th group of weight coefficient combinations, determine the candidate equalization parameter corresponding to the maximum candidate score, and obtain m candidate equalization parameters;

[0133] It can be understood that the maximum candidate score in the i-th group of weight coefficient combinations is recorded as T MAX-i , since there are m weight coefficient combinations, a total of m maximum candidate scores are obtained: T MAX-1 、T MAX-2 、T MAX-3 …T MAX-m , and correspondingly m candidate equalization parameters.

[0134] Step S304: Obtain the bit error rate of each candidate equalization parameter, and select the candidate equalization parameter with the smallest bit error rate as the target equalization parameter.

[0135] It can be understood that the bit error rates of the optical module ports of the device under test are calculated respectively under m different candidate equalization parameters, these m bit error rates are obtained and compared, and the candidate equalization parameter with the smallest bit error rate is selected as the target equalization parameter.

[0136] The beneficial effect of this embodiment is that: through the processing methods of the above steps S10 to S30, the optimal target equalization parameter is automatically found, avoiding the inefficiency and errors of manual debugging required by the conventional sampling oscilloscope method.

[0137] Furthermore, in this embodiment, by constructing multiple groups of weight coefficient combinations, the importance of eye width and eye height in signal quality evaluation can be flexibly adjusted according to different test requirements and application scenarios, making the test more flexible; at the same time, through the combination of multiple groups of weight coefficients, the signal quality can be more accurately quantified, ensuring that the selected target equalization parameter can meet the requirements of both eye width and eye height, thus ensuring the optimal signal quality.

[0138] Furthermore, after executing step S30, it further includes: the computer device sends the target equalization parameter to the device under test, so that the device under test calibrates the optical module port. The best SerDes parameter (i.e., the target equalization parameter) selected can compensate for the loss of high-frequency components during signal transmission, achieve the equalization of high-frequency and low-frequency signals at the receiving end, thereby improving the signal quality and meeting the protocol consistency standard.

[0139] Embodiment III

[0140] Figure 7 It is a schematic structural diagram of a computer device provided by an embodiment of the present application. As Figure 7 shown, the computer device 3 of this embodiment includes: at least one processor 31 (Figure 7 Only one processor is shown)、memory 32, and a computer program 33 stored in the memory 32 and executable on the at least one processor 31. When the processor 31 executes the computer program 33, the steps in the method of the second embodiment above are implemented.

[0141] The computer device may include, but is not limited to, a processor 31 and a memory 32. Those skilled in the art can understand that Figure 7 This is merely an example of the computer device 3 and does not constitute a limitation on the computer device 3. It may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, it may also include input / output devices, network access devices, etc.

[0142] The so-called processor 31 may be a central processing unit (CPU), and the processor 31 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0143] In some embodiments, the memory 32 may be an internal storage unit of the computer device 3, such as the hard disk or memory of the computer device 3. In other embodiments, the memory 32 may also be an external storage device of the computer device 3, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the computer device 3. Further, the memory 32 may also include both the internal storage unit and the external storage device of the computer device 3. The memory 32 is used to store an operating system, application programs, a boot loader, data, and other programs, such as the program code of the computer program. The memory 32 may also be used to temporarily store data that has been output or will be output.

[0144] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of the functional units and modules are only for the convenience of mutual distinction and do not limit the protection scope of this application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0145] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the foregoing method embodiments can be implemented.

[0146] The embodiment of the present application provides a computer program product. When the computer program product runs on an electronic device, the electronic device can implement the steps in the foregoing method embodiments when executed.

[0147] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above method embodiments of the present application, a computer program can be used to instruct relevant hardware to complete. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps in the foregoing method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the photographing device / electronic device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal, and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disc, etc. In some jurisdictions, according to legislation and patent practice, the computer-readable medium cannot be an electrical carrier signal and a telecommunication signal.

[0148] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not described in detail or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0149] Those of ordinary skill in the art will realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. A professional technician can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0150] In the embodiments provided in this application, it should be understood that the disclosed device / network device and method can be implemented in other ways. For example, the device / network device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the device or unit can be in electrical, mechanical or other forms.

[0151] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0152] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit the same; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A signal quality adjustment and testing system for an optical module port, characterized in that: The system comprises a debugging device and a computer device, wherein the debugging device is connected to the device to be tested and the computer device respectively; The computer device is used to configure equalization parameters for the serializer of the optical module port of the device under test; The debugging device is used for receiving the high-speed serial signal of the serializer sent by the device under test after the computer device configures the equalization parameters for the serializer of the optical module port each time, evaluating the quality of the high-speed serial signal, obtaining a signal quality test result, and feeding back the signal quality test result to the computer device; The computer device is used to select the target equalization parameter of the serializer from each signal quality test result, wherein the target equalization parameter represents the equalization parameter that makes the signal quality of the optical module port reach the target performance.

2. A debugging device, characterized in that: The debugging device is configured with a retiming chip, a microcontroller unit, a transceiver unit and a data interface; The microcontroller unit is configured to control the retiming chip to receive the high-speed serial signal when the transceiver unit receives the high-speed serial signal of the serializer sent by the device under test, and control the retiming chip to analyze the quality of the high-speed serial signal to generate a bit error rate statistical dot matrix diagram of the high-speed serial signal, and obtain a signal quality test result including the bit error rate statistical dot matrix diagram.

3. The debugging device according to claim 2, characterized in that: The debugging device is equipped with a gold finger interface and a data interface; The gold finger interface is used to insert into the optical module port of the device under test; The data interface is used to connect to the computer device; The microcontroller unit is further configured to convert the signal quality test result into a format of an asynchronous serial digital signal and send it to the transceiver unit; The transceiver unit is configured to perform level conversion and / or protocol conversion on the signal quality test result, so that the signal quality test result is converted into a format suitable for transmission on the data interface, so as to transmit the signal quality test result to the computer device.

4. The debugging device according to claim 2 or 3, characterized in that: The retiming chip comprises: A bit error counting unit, configured to count the number of bit errors in the received high-speed serial signal; a bit error rate analysis unit, configured to calculate a bit error rate based on the number of bit errors; The bit error rate statistical dot matrix generating unit is configured to generate a bit error rate statistical dot matrix of sampling points at different positions in the code element period, wherein the values ​​of different elements in the bit error rate statistical dot matrix correspond to the bit error rates when sampling at different positions in the code element period.

5. A method for adjusting the signal quality of an optical module port, characterized in that: The debugging method is applied to the signal quality debugging system of the optical module port according to claim 1, and the method comprises: The computer device configures n equalization parameters for the serializer of the optical module port of the device under test, where n is a positive integer; The debugging device receives the high-speed serial signal of the serializer sent by the device under test when the computer device configures the equalization parameters for the serializer of the optical module port each time; and evaluates the quality of the high-speed serial signal each time the high-speed serial signal is received to obtain the signal quality test result; The computer device selects the target equalization parameters of the serializer from the signal quality test results corresponding to the equalization parameters configured each time of the serializer; wherein the target equalization parameters represent the equalization parameters that make the signal quality of the optical module port reach the target performance.

6. The debugging method according to claim 5, characterized in that: The debugging device evaluates the quality of the high-speed serial signal each time the high-speed serial signal is received to obtain the signal quality test result, including: The debugging device analyzes the quality of the high-speed serial signal each time the high-speed serial signal is received to generate a bit error rate statistical dot matrix diagram of the high-speed serial signal, and calculates a signal quality index corresponding to the bit error rate statistical dot matrix diagram; The signal quality index corresponding to the bit error rate statistical dot matrix is ​​used as the signal quality test result of the high-speed serial signal; wherein the signal quality index includes an eye width and an eye height, the eye width represents the jitter information of the high-speed serial signal, and the eye height represents the amplitude noise information of the high-speed serial signal.

7. The debugging method according to claim 6, characterized in that: The computer device selects a target equalization parameter of the serializer from the signal quality test results corresponding to the equalization parameters configured each time of the serializer, including: The computer device establishes m groups of weight coefficient combinations based on each signal quality test result, each group of weight coefficient combinations comprising an eye width weight coefficient variable and an eye height weight coefficient variable; Calculate candidate scores of signal quality indicators corresponding to n equalization parameters under the i-th group of weight coefficient combinations, and obtain n candidate scores under the i-th group of weight coefficient combinations; Sorting the n candidate scores under the i-th group of weight coefficient combinations, taking the candidate score with the largest value as the maximum candidate score in the i-th group of weight coefficient combinations, determining the candidate equalization parameter corresponding to the maximum candidate score, and obtaining m candidate equalization parameters; wherein m is a positive integer; The bit error rates of the candidate equalization parameters are obtained, and the candidate equalization parameter with the smallest bit error rate is selected as the target equalization parameter.

8. The debugging method according to any one of claims 5 to 7, characterized in that: The method further comprises: The computer device sends the target equalization parameter to the device under test, so that the device under test calibrates the optical module port.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the signal quality adjustment method of the optical module port according to any one of claims 5 to 8 is implemented.

10. A computer program product, wherein the computer program product stores a computer program, characterized in that: When the computer program is executed by a processor, the signal quality adjustment method of the optical module port according to any one of claims 1 to 8 is implemented.

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