Memory management method and system for switch chip
By dividing the shared memory of the switching chip into multiple independent memory blocks and building corresponding address structures, the problem of switching chips processing multiple high-speed network port data in high-speed networks is solved, and efficient multi-channel parallel reading and writing is achieved, reducing hardware cost and complexity.
Patent Information
- Application Number
- CN202510313330.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2025-06-17
AI Technical Summary
In high-speed networks, it is difficult for switching chips to effectively process data from multiple high-speed network ports, resulting in high storage area read and write bandwidth usage, and pre-allocating fixed buffers is difficult to cope with the randomness of data traffic, increasing hardware cost and complexity.
By dividing the shared memory of the switching chip into multiple independent memory blocks, forming an N×M matrix, and building a two-dimensional array of write addresses and a read address link list, multi-channel parallel reading and writing are realized.
It reduces the requirements for the core processing speed of switching chips, improves the interface speed and switching capacity of high-speed switching chips, realizes high-efficiency data read and write operations in parallel with multiple channels, and reduces hardware costs and implementation difficulty.
Smart Images
Figure CN120166087A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of network technology, and particularly relates to a memory management method and system for a switching chip. Background Art
[0002] With the rapid development of ultra-large-scale cloud computing and data center network technology, the port rate and switching capacity of switching chips in network switches have been significantly improved. For example, the signal interface of a 400GE (Gigabit Ethernet) network (hereinafter referred to as "high-speed network port") has a parallel width of 128 bytes and a parallel rate of more than 400 MHz, which means that the switching chip needs to process more data volume, especially in a high-speed network. However, in the process of using the existing technology, the inventor found that there are at least the following problems in the existing technology:
[0003] The minimum width of an Ethernet packet is only 64 bytes, and the internal logic rate of FPGA (Field Programmable Gate Array) chips and ASIC (Application Specific Integrated Circuit) chips with a process of 40nm to 12nm is usually lower than 800 MHz. This means that when packet data is temporarily stored in the switching chip, due to the very fast data transmission speed of the high-speed network port (such as a 400GE network), one high-speed network port will occupy most of the read-write bandwidth of the storage area in the switching chip, making it extremely difficult for the switching chip to serialize and process data of multiple high-speed network ports by expanding the word width (processing more data each time) or increasing the read-write speed.
[0004] In the existing technology, simultaneous entry and exit of multiple data can be achieved by pre-allocating fixed buffers for each port of the switching chip. However, when the network switch forwards data in a high-speed network, the arrival of packets is random, and the data traffic of different ports of the switching chip cannot be predicted in advance. It is difficult to pre-allocate buffers for each port in advance, and if each port has an independent buffer, the area and cost of the switching chip will increase significantly. Summary of the Invention
[0005] The present invention aims to solve the above technical problems to at least some extent, and provides a memory management method and system for a switching chip.
[0006] To achieve the above object, the present invention adopts the following technical solutions:
[0007] In a first aspect, the present invention provides a memory management method for a switching chip, including:
[0008] S1. Divide the shared memory of the switching chip into multiple independent memory blocks. The multiple memory blocks are organized into an N×M matrix, and each memory block is provided with an independent read / write interface. Here, N is the number of write channels, M is the number of read channels, and both N and M are natural numbers greater than 1.
[0009] S2. Based on the multiple memory blocks, construct an N×M two-dimensional write address array, and each element in the write address two-dimensional array represents the current write address of the memory block queue corresponding to each memory block node in the matrix. At the same time, construct an N×M two-dimensional read address linked list, and each two-dimensional read address linked list contains the storage address and data length of the data packets in the memory block queue corresponding to each memory block node in the matrix, so as to realize multi-channel parallel reading and writing of the switching chip.
[0010] S3. Receive a write data request sent by any write channel, and perform a data writing operation to the write channel corresponding to the write data request according to the write data request.
[0011] The write data request includes the write channel number of the any write channel, the target read channel number, and the write data length. Correspondingly, performing a data writing operation to the write channel corresponding to the write data request includes:
[0012] S301. According to the target read channel number in the write data request, find the current write address of the memory block queue corresponding to the target read channel number in the write address two-dimensional array.
[0013] S302. Determine whether the remaining space of the memory block corresponding to the current write address is sufficient to store the data of the write data length. If so, set the current write address as the current write address of this time, and write the data corresponding to the write data request into the memory block corresponding to the current write address of this time, and then enter step S305. If not, enter step S303.
[0014] S303. Obtain a new free memory block number from the preset set of free memory blocks, and use its starting address as the new write address.
[0015] S304. Set the new write address as the current write address of this time, and write the data corresponding to the write data request into the memory block corresponding to the current write address of this time, and then enter step S305.
[0016] S305. Update the current write address in the write address two-dimensional array, and write the current write address of this time and the write data length into the read address linked list of the corresponding memory block node in the matrix.
[0017] S4. Receive a read data request sent by any read channel, and perform a data read operation on the read channel corresponding to the read data request according to the read data request.
[0018] In a possible design, the cache depth and data width of each memory block are the same.
[0019] In a possible design, at the initial moment, the memory block numbers of each memory block are stored in a preset set of free memory blocks in the form of an array.
[0020] In a possible design, in step S301, after finding the current write address of the memory block queue corresponding to the target read channel number in the two-dimensional write address array, the method further includes:
[0021] Judge whether the current write address is valid. If so, enter step S302; if not, enter step S303.
[0022] In a possible design, after updating the current write address in the two-dimensional write address array, the method further includes:
[0023] S306. Set the initial value greater than 1 for the aging counters of all memory blocks in the memory block queue corresponding to the current write address.
[0024] In a possible design, the read data request includes the read channel number of any read channel; correspondingly, performing a data read operation on the read channel corresponding to the read data request includes:
[0025] S401. According to the read channel number in the read data request, find a specified read address linked list according to the principle of giving priority to the linked list length among N read address linked lists, obtain the current read address and its data length from the head of the specified read address linked list, and perform a data read operation on the current memory block corresponding to the current read address;
[0026] S402. Update the head of the specified read address linked list to the storage address and its data length of the next data packet. If the storage address of the next data packet points to another memory block, recycle the current memory block to the preset set of free memory blocks.
[0027] In a possible design, the method further includes:
[0028] Poll the aging counters of each in-use memory block under the trigger of a timing signal. If the value of the aging counter of any memory block is non-zero, decrement the aging counter of the any memory block by one, and recycle the any memory block to the preset set of free memory blocks when the value of the aging counter of the any memory block decrements to 0.
[0029] In a possible design, the switching chip is applied to a memory chip with switching and forwarding functions by using a memory tube method, and the memory chip is an ASIC chip, an FPGA chip loaded with packet forwarding function logic, or a routing chip.
[0030] In a possible design, the shared memory is a RAM memory in the switching chip.
[0031] In a second aspect, the present invention provides a memory management system for a switching chip, including:
[0032] A memory block division module, configured to divide the shared memory of the switching chip into multiple independent memory blocks. The multiple memory blocks are organized into an N×M matrix, and each memory block is provided with an independent read / write interface; where N is the number of write channels, M is the number of read channels, and both N and M are natural numbers greater than 1.
[0033] An address linked list construction module, communicatively connected to the memory block division module, configured to construct a two-dimensional write address array of N×M based on the multiple memory blocks. Each element in the two-dimensional write address array represents the current write address of the memory block queue corresponding to each memory block node in the matrix. At the same time, construct a two-dimensional read address linked list of N×M, and each two-dimensional read address linked list includes the storage address and data length of the data packet in the memory block queue corresponding to each memory block node in the matrix, so as to achieve multi-channel parallel reading and writing of the switching chip.
[0034] A data read / write module, communicatively connected to the address linked list construction module, configured to receive a write data request sent by any write channel and perform a data writing operation to the write channel corresponding to the write data request according to the write data request; and is further configured to receive a read data request sent by any read channel and perform a data reading operation to the read channel corresponding to the read data request according to the read data request.
[0035] The beneficial effects of the present invention are:
[0036] The present invention discloses a memory management method and system for a switching chip, which realizes multi-channel parallel reading and writing of the switching chip by using a shared memory, has high data processing efficiency, and low hardware cost and complexity. Specifically, in the implementation process of the present invention, first, the shared memory of the switching chip is divided into multiple independent memory blocks, and the multiple memory blocks are organized into an N×M matrix, and each memory block is provided with an independent read-write interface; then, according to the multiple memory blocks, an N×M two-dimensional write address array is constructed, and each element in the two-dimensional write address array represents the current write address of the memory block queue corresponding to each memory block node in the matrix. At the same time, an N×M two-dimensional read address linked list is constructed, and each two-dimensional read address linked list contains the storage address and data length of the data packets in the memory block queue corresponding to each memory block node in the matrix; subsequently, a write data request sent by any write channel is received, and data writing operation is performed on the write channel corresponding to the write data request according to the write data request, or a read data request sent by any read channel is received, and data reading operation is performed on the read channel corresponding to the read data request according to the read data request. Based on this, the present invention reduces the requirement for the core processing speed of the switching chip by setting a shared memory as the buffer of the switching chip. Under the same manufacturing process conditions, the interface speed and switching capacity of the high-speed switching chip can be improved, that is, based on the present invention, high-efficiency data reading and writing operations in parallel with multiple channels can be realized, and at the same time, the chip hardware cost and implementation difficulty are reduced.
[0037] Other beneficial effects of the present invention will be further described in the specific implementation manner. Brief Description of the Drawings
[0038] Figure 1 is a schematic structural diagram of the switching chip in Embodiment 1;
[0039] Figure 2 is a flowchart of the memory management method for the switching chip in Embodiment 1;
[0040] Figure 3 is a block diagram of the memory management system for the switching chip in Embodiment 2. Specific Embodiment
[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the present invention in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the drawings is only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. It should be noted here that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation to the present invention.
[0042] Embodiment 1:
[0043] This embodiment discloses a memory management method for a switching chip, which can be, but is not limited to, executed by a computing module with certain computing resources in the switching chip.
[0044] As Figure 1 and Figure 2 shown, a memory management method for a switching chip can, but is not limited to, include the following steps:
[0045] S1. Divide the shared memory of the switching chip into multiple independent memory blocks. The multiple memory blocks are organized into an N×M matrix, and each memory block is provided with an independent read / write interface, as Figure 1 shown; where N is the number of write channels, M is the number of read channels, and both N and M are natural numbers greater than 1. It should be noted that in this embodiment, the shared memory is divided into multiple memory blocks arranged in N rows and M columns, and each node in the N×M matrix points to a memory block queue of indefinite length.
[0046] In this embodiment, the cache depth and data width of each memory block are the same. It should be noted that based on this setting, it is convenient to number and divide channels for each memory block, so as to facilitate subsequent simultaneous response to multiple write data requests and read data requests, and realize multi-channel parallel reading and writing of the shared memory.
[0047] It should also be noted that in this embodiment, the multiple memory blocks are divided according to the preset shared memory response logic of the switching chip, so that the switching chip can simultaneously respond to the write data requests of N write channels and the read data requests of M read channels.
[0048] In step S1, at the initial moment, the memory block numbers of each memory block are stored in a preset set of free memory blocks in the form of an array. It should be noted that in this embodiment, the set of free memory blocks is used to store the numbers of free memory blocks, and it can provide the numbers of multiple free memory blocks at one time. As the read / write operations proceed, the data in the set of free memory blocks is dynamically read out or written to update the numbers of free memory blocks.
[0049] S2. Based on the multiple memory blocks, construct an N×M two-dimensional write address array, and each element in the two-dimensional write address array represents the current write address of the memory block queue corresponding to each memory block node in the matrix. At the same time, construct an N×M two-dimensional read address linked list, and each two-dimensional read address linked list contains the storage address and data length of the data packets in the memory block queue corresponding to each memory block node in the matrix;
[0050] S3. Receive a write data request sent by any write channel, and perform a data writing operation to the write channel corresponding to the write data request according to the write data request.
[0051] In step S3, the write data request includes the write channel number of any one of the write channels, the target read channel number, and the write data length; correspondingly, in step S3, performing a data writing operation to the write channel corresponding to the write data request according to the write data request includes:
[0052] S301. According to the target read channel number in the write data request, find the current write address of the memory block queue corresponding to the target read channel number in the two-dimensional write address array; determine whether the current write address is valid. If so, proceed to step S302; if not, proceed to step S303. It should be noted that in this embodiment, the validity can be judged by checking the "valid bit" in the current write address. If the current write address is valid, it means that the memory address can be written with data. If it is invalid, it means that the space of the memory block has been occupied or damaged and cannot be used for data writing anymore. Based on the validity judgment process of the current write address, this embodiment can ensure that the memory address to be accessed is legal and valid, preventing system crashes or data damage caused by illegal access.
[0053] S302. Determine whether the remaining space of the memory block corresponding to the current write address is sufficient to store the data of the write data length. If so, set the current write address as the current write address for this time, and write the data corresponding to the write data request into the memory block corresponding to the current write address for this time, and then proceed to step S305. If not, that is, the remaining space of the memory block corresponding to the current write address is not sufficient to store the data of the write data length, proceed to step S303;
[0054] S303. Obtain a new free memory block number from the preset set of free memory blocks, and use its starting address as the new write address;
[0055] S304. Set the new write address as the current write address for this time, and write the data corresponding to the write data request into the memory block corresponding to the current write address for this time, and then proceed to step S305;
[0056] S305. Update the current write address in the two-dimensional write address array, that is, according to the data writing situation for this time, update the current write address in the two-dimensional write address array to the next available memory block address of the current write address for the data written for this time, where the current write address for this time is the current write address in step S302 or the new write address in step S304; and write the current write address for this time and the write data length into the read address linked list of the corresponding memory block node in the matrix.
[0057] After updating the current write address in the two-dimensional write address array, the method further includes:
[0058] S306. Set the aging counters of all memory blocks in the memory block queue corresponding to the current write address to an initial value greater than 1.
[0059] S4. Receive a read data request sent by any read channel, and perform a data read operation on the read channel corresponding to the read data request according to the read data request.
[0060] In step S4, the read data request includes the read channel number of the any read channel; correspondingly, in step S4, performing a data read operation on the read channel corresponding to the read data request according to the read data request includes:
[0061] S401. According to the read channel number in the read data request, find a specified read address linked list according to the principle of giving priority to the linked list length among N read address linked lists, obtain the current read address and its data length from the head of the specified read address linked list, and perform a data read operation on the current memory block corresponding to the current read address. Among them, the principle of giving priority to the linked list length means that the read address linked list with a larger data length is preferentially read.
[0062] S402. Update the head of the specified read address linked list to the storage address and data length of the next data packet. If the storage address of the next data packet points to another memory block, it means that all the data in the current memory block has been read out, then recycle the current memory block to a preset set of free memory blocks
[0063] It should be noted that in this embodiment, during the data reading operation, if the data read is the last data in the corresponding memory block, further check whether the corresponding memory block is the last memory block in its memory block queue. If not, immediately release the memory block to the set of free memory blocks. If so, do not release it temporarily, and perform aging processing and release according to the timing aging logic. Based on this, for a relatively "active" channel, although the current data has been all read out, the memory block of the last address is retained, and there is no need to frequently reallocate memory blocks for this channel. If no data arrives for a long time, aging processing and release are performed according to the timing aging logic.
[0064] It should be understood that steps S3 and S4 in this embodiment are in a parallel execution relationship.
[0065] In this embodiment, the method further includes:
[0066] S5. Poll the aging counters of each in-use memory block upon triggering of the timing signal. If the value of the aging counter of any memory block is non-zero, decrement the aging counter of the said any memory block by one, i.e., perform an operation of decrementing it by 1, and when the value of the aging counter of the said any memory block is decremented to 0, recycle the said any memory block into a preset set of free memory blocks, that is, when the value of the aging counter of the said any memory block is decremented to 0, initiate recycling of the memory block into the set of free memory blocks.
[0067] It should be noted that in this embodiment, in order to optimize the use of memory blocks, each memory block has an aging counter. In the absence of data requests, the memory blocks will gradually age, manifested as the aging counters of the memory blocks decrementing upon triggering of the timing signal until the memory blocks with aging counters of 0 are recycled, thereby releasing memory blocks that have not been used for a long time.
[0068] Specifically, in this embodiment, the memory pipe method of the switching chip is applied to a memory chip with switching and forwarding functions, and the memory chip is an ASIC (Application Specific Integrated Circuit) chip, an FPGA (Field Programmable Gate Array) chip loaded with packet forwarding function logic, or a routing chip. Additionally, in this embodiment, the shared memory is a RAM (Random Access Memory) memory within the switching chip.
[0069] This embodiment realizes multi-channel parallel read and write of the switching chip by using shared memory, with high data processing efficiency, low hardware cost and complexity. Specifically, during the implementation of this embodiment, first, the shared memory of the switching chip is divided into multiple independent memory blocks, and the multiple memory blocks are organized into an N×M matrix, and each memory block is provided with an independent read-write interface; then, according to the multiple memory blocks, an N×M two-dimensional write address array is constructed, and each element in the two-dimensional write address array represents the current write address of the memory block queue corresponding to each memory block node in the matrix. At the same time, an N×M two-dimensional read address linked list is constructed, and each two-dimensional read address linked list contains the storage address and data length of the data packets in the memory block queue corresponding to each memory block node in the matrix; subsequently, a write data request sent by any write channel is received, and data writing operation is performed on the write channel corresponding to the write data request according to the write data request, or a read data request sent by any read channel is received, and data reading operation is performed on the read channel corresponding to the read data request according to the read data request. Based on this, this embodiment reduces the requirement for the core processing speed of the switching chip by setting the shared memory as the buffer of the switching chip. Under the same manufacturing process conditions, the interface speed and switching capacity of the high-speed switching chip can be improved, that is, based on this embodiment, high-efficiency data read and write operations in parallel with multiple channels can be realized, and at the same time, the chip hardware cost and implementation difficulty are reduced.
[0070] Embodiment 2:
[0071] This embodiment discloses a memory management system for a switching chip for implementing the memory management method for the switching chip in Embodiment 1; as Figure 3 shown, the memory management system for the switching chip includes:
[0072] A memory block division module, configured to divide the shared memory of the switching chip into multiple independent memory blocks, and the multiple memory blocks are organized into an N×M matrix, and each memory block is provided with an independent read-write interface; where N is the number of write channels, M is the number of read channels, and both N and M are natural numbers greater than 1;
[0073] An address linked list construction module, communicatively connected to the memory block division module, configured to construct an N×M two-dimensional write address array according to the multiple memory blocks, and each element in the two-dimensional write address array represents the current write address of the memory block queue corresponding to each memory block node in the matrix. At the same time, an N×M two-dimensional read address linked list is constructed, and each two-dimensional read address linked list contains the storage address and data length of the data packets in the memory block queue corresponding to each memory block node in the matrix, so as to realize multi-channel parallel read and write of the switching chip;
[0074] A data reading and writing module, communicatively connected to the address linked list construction module, is configured to receive a write data request sent by any write channel and perform a data writing operation to the write channel corresponding to the write data request according to the write data request; and is further configured to receive a read data request sent by any read channel and perform a data reading operation to the read channel corresponding to the read data request according to the read data request.
[0075] It should be noted that for the working process, working details and technical effects of the memory management system for the switching chip provided in Embodiment 2, reference can be made to Embodiment 1, which will not be elaborated herein.
[0076] Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the present invention can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Optionally, they can be implemented by program codes executable by the computing device, so that they can be stored in a storage device and executed by the computing device, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module to implement. Thus, the present invention is not limited to any specific combination of hardware and software.
[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments or perform equivalent replacements for some of the technical features. And these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A memory management method for a switching chip, characterized in that: include: S1. Divide the shared memory of the switching chip into multiple independent memory blocks, organize the multiple memory blocks into an N×M matrix, and each memory block is provided with an independent read / write interface; wherein N is the number of write channels, M is the number of read channels, and both N and M are natural numbers greater than 1; S2. According to the plurality of memory blocks, an N×M two-dimensional array of write addresses is constructed, and each element in the two-dimensional array of write addresses represents the current write address of the memory block queue corresponding to each memory block node in the matrix, and an N×M two-dimensional read address linked list is constructed at the same time, and each two-dimensional read address linked list contains the storage address and data length of the data packet in the memory block queue corresponding to each memory block node in the matrix, so as to realize multi-channel parallel reading and writing of the switching chip; S3. Receive a write data request issued by any write channel, and perform a data write operation on the write channel corresponding to the write data request according to the write data request; The write data request includes a write channel number of any write channel, a target read channel number, and a write data length; correspondingly, performing a data write operation on a write channel corresponding to the write data request according to the write data request, including: S301. According to the target read channel number in the write data request, find the current write address of the memory block queue corresponding to the target read channel number in the write address two-dimensional array; S302. Determine whether the remaining space of the memory block corresponding to the current write address is sufficient to store data of the write data length. If so, set the current write address as the current write address, and write the data corresponding to the write data request into the memory block corresponding to the current write address, and then proceed to step S305. If not, proceed to step S303. S303. Obtain a new free memory block number from a preset free memory block set, and use its starting address as a new write address; S304. Set the new write address as the current write address, and write the data corresponding to the write data request into the memory block corresponding to the current write address, and then proceed to step S305; S305. Update the current write address in the write address two-dimensional array, and write the current write address and the write data length into the read address linked list of the corresponding memory block node in the matrix; S4. Receive a read data request sent by any read channel, and perform a data read operation on the read channel corresponding to the read data request according to the read data request.
2. A memory management method for a switching chip according to claim 1, characterized in that: The cache depth and data width of each memory block are the same.
3. A memory management method for a switching chip according to claim 1, characterized in that: At the initial moment, the memory block numbers of the memory blocks are stored in a preset free memory block set in an array form.
4. A memory management method for a switching chip according to claim 1, characterized in that: After updating the current write address in the two-dimensional array of write addresses, the method further includes: S306. Set the aging counters of all memory blocks in the memory block queue corresponding to the current write address to an initial value greater than 1.
5. A memory management method for a switching chip according to claim 3, characterized in that: The read data request includes a read channel number of any read channel; Correspondingly, performing a data read operation on a read channel corresponding to the read data request according to the read data request includes: S401. According to the read channel number in the read data request, a designated read address chain list is searched in N read address chain lists according to the chain list length priority principle, the current read address and its data length are obtained from the chain list header of the designated read address chain list, and a data read operation is performed on the current memory block corresponding to the current read address; S402. Update the header of the designated read address linked list to the storage address of the next data packet and its data length. If the storage address of the next data packet points to another memory block, recycle the current memory block into a preset free memory block set.
6. A memory management method for a switching chip according to claim 1, characterized in that: The method further comprises: When triggered by a timing signal, the aging counters of each memory block in use are polled. If the value of the aging counter of any memory block is non-zero, the aging counter of any memory block is reduced by one. When the value of the aging counter of any memory block is reduced to 0, the any memory block is recycled into a preset free memory block set.
7. A memory management method for a switching chip according to claim 1, characterized in that: The memory management method for the switching chip is applied to a memory chip with a switching forwarding function, and the memory chip adopts an ASIC chip, an FPGA chip loaded with message forwarding function logic, or a routing chip.
8. A memory management method for a switching chip according to claim 1, characterized in that: The shared memory is a RAM memory in the switching chip.
9. A memory management system for a switching chip, characterized in that: include: The memory block module is used to divide the shared memory of the switching chip into multiple independent memory blocks, and the multiple memory blocks are organized into an N×M matrix, and each memory block is provided with an independent read and write interface; wherein N is the number of write channels, and M is the number of read channels, and both N and M are natural numbers greater than 1; An address linked list construction module is communicatively connected with the memory block module, and is used to construct an N×M two-dimensional array of write addresses according to a plurality of memory blocks, and each element in the two-dimensional array of write addresses represents the current write address of the memory block queue corresponding to each memory block node in the matrix, and simultaneously construct an N×M two-dimensional read address linked list, and each two-dimensional read address linked list contains the storage address and data length of the data packet in the memory block queue corresponding to each memory block node in the matrix, so as to realize multi-channel parallel reading and writing of the switching chip; A data read-write module is communicatively connected with the address linked list construction module, and is used to receive a write data request issued by any write channel, and perform a data write operation on the write channel corresponding to the write data request according to the write data request; and is also used to receive a read data request issued by any read channel, and perform a data read operation on the read channel corresponding to the read data request according to the read data request.