Vertical field effect transistor structure and method of manufacturing the same
By setting the local threshold voltage curve in the FinMOS and adjusting the dopant gradient in the channel region in the FinMOS and FinFET structures, the problem of local threshold voltage inhomogeneity caused by fin width changes is solved, and the performance and reliability of the equipment are improved.
Patent Information
- Application Number
- CN202411835751.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-15
- Filing Date
- 2024-12-13
- Publication Date
- 2025-06-17
AI Technical Summary
In the existing FinMOS and FinFET structures, changes in the width of the fins cause uneven local threshold voltages in the channel area, affecting the performance and reliability of the equipment.
By setting a predefined local threshold voltage curve in the depth direction of the fin structure, the doping concentration or charge density is adjusted in the channel region using the dopant gradient to ensure that the threshold voltage remains uniform or expected to change in the vertical direction.
Accurate control of local threshold voltage along the depth direction in the fin structure is achieved, improving the performance and reliability of the equipment, especially during the connection process or shutdown process.
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Figure CN120166748A_ABST
Abstract
Description
Field of the Invention
[0001] The present invention relates to a vertical field effect transistor structure and a method for manufacturing a vertical field effect transistor structure. Background Art
[0002] Figures 1a to 1d A schematic cross-sectional view of a conventional FinMOS and associated curves of charge depth, fin width, and threshold voltage Uth are shown. This FinMOS is known to the applicant as internal prior art.
[0003] In Figure 1a The conventional FinMOS schematically shown therein includes a substrate wafer 10 having a first wafer surface 10a and a second wafer surface 10b, with the second wafer surface pointing away from the first wafer surface 10a. The FinMOS has an n-doped silicon carbide layer 12 epitaxially grown on the first wafer surface 10a. On the side of the silicon carbide layer 12 pointing away from the substrate wafer 10, fin structures 14 are structured out of the silicon carbide layer 12, where the fin structures 14 anchored on the silicon carbide layer 12 are (substantially) bar-shaped. For (almost) bar-shaped fin structures 14, a longitudinal direction oriented parallel to the first wafer surface 10a can be respectively defined, in which longitudinal direction the fin structure 14 has its maximum extension scale. Typically, the longitudinal direction of the fin structure 14 is perpendicular to the direction of the silicon carbide layer 12. Each fin structure in the fin structures 14 has an n-doped source region 16 at its end pointing away from the substrate wafer 10. In addition, each fin structure in the fin structures respectively has a p-doped channel region 18, which is adjacent to the corresponding source region 16. Gate electrodes are respectively located between two adjacent fin structures 14, where a gate dielectric 22 electrically insulates the fin structure 14 and the silicon carbide layer 2 from the gate electrode 20. In addition, Figure 1a the conventional FinMOS shown in
[0004] Figure 1b shows the doping in the channel region 18. Typically, the doping or charge density LD in the channel region 18 does not vary in the vertical direction i.e., is constant in the depth direction. In combination with the uniform width of the FB fins in the channel region 18, this results in a uniform local threshold voltage Uth over the entire channel region 18 (i.e., for example, in regions 18.1, 18.2, and 18.3), as Figure 1dAs shown. The threshold voltage (Schwellenwertspannung) or threshold voltage (Threshold-Spannung) Uth describes the following voltage value: at this voltage value, the current just starts to flow through the channel of the FET.
[0005] However, typically, the fin width FB is not uniform or constant, but usually increases vertically from top to bottom in a conventional FinFET according to Figure 2a . This is shown in the curve of the fin width FB of the fin as shown in Figure 2c . Then, the uniform dopant profile in the widened fin channel region 40 of the conventional FinFET (see Figure 2b ) results in a non-uniform local threshold voltage Uth in the vertical direction through the channel region 40, as can be seen in Figure 2d . As the fin width FB of the fin becomes larger and larger, the local threshold voltage Uth or equivalently the depth D is increased locally in the vertical direction, as shown in Figure 2d . Thus, the increasing fin width FB of the fin results in a non-uniform, gradually increasing downward local threshold voltage Uth over the widened fin channel region 40. SUMMARY OF THE INVENTION
[0006] The present invention provides a vertical field effect transistor structure and a method for manufacturing a vertical field effect transistor structure.
[0007] According to a first aspect, the present invention provides a vertical field effect transistor structure having a substrate with a first substrate surface,
[0008] a semiconductor layer located on the first substrate surface, and a plurality of fin structures anchored on a silicon carbide layer are structured from the semiconductor layer on the side facing away from the first substrate surface, wherein source regions are respectively formed at the ends of the fin structures facing away from the substrate; and having
[0009] a plurality of gate electrodes, wherein each of the gate electrodes is located between two adjacent fin structures, and the fin structures and the semiconductor layer are electrically insulated from the gate electrodes by at least one gate dielectric,
[0010] wherein doped channel regions are respectively located on the side of the source regions of the fin structures facing the substrate, and the doping of the doped channel regions is set to provide a predefined local threshold voltage profile along the depth of the respective fin structures.
[0011] According to another aspect, the present invention provides a method for manufacturing a vertical field effect transistor structure, the method having the following steps:
[0012] A semiconductor layer is provided on a first substrate surface of a substrate;
[0013] A plurality of fin structures anchored to the semiconductor layer are structured from the semiconductor layer on a side of the semiconductor layer facing away from the first substrate surface, wherein source regions are respectively formed on ends of the fin structures facing away from the substrate;
[0014] A plurality of gate electrodes are formed, wherein one of the gate electrodes is respectively arranged between two adjacent fin structures, and the fin structures and the semiconductor layer are electrically insulated from the gate electrodes by at least one gate dielectric; and
[0015] The doping of a channel region is set to provide a predefined local threshold voltage profile along the depth of a corresponding fin structure, and the channel regions are respectively located on sides of the source regions of the fin structures facing the substrate.
[0016] Preferred extensions are described below.
[0017] Advantages of the present invention
[0018] The core concept of the present invention is to compensate for or increase the local threshold voltage change caused by the change in the fin width of the fin, so as to achieve a defined local threshold voltage profile along the depth of the corresponding fin structure. A suitable doping profile of the doping concentration or charge density of the channel region is used for the compensation or increase.
[0019] In a preferred embodiment, a doping gradient of the doping of the channel region of the fin structure is generated by ion implantation. Thus, the doping profile in the channel region can be precisely set.
[0020] In a possible embodiment of a vertical field effect transistor structure, the fin width of the fin structure increases with increasing depth. This may be the case due to manufacturing reasons.
[0021] In a possible embodiment of a vertical field effect transistor structure, the semiconductor layer has a silicon carbide layer.
[0022] In a possible embodiment of a vertical field effect transistor structure, the silicon carbide layer is epitaxially grown on the substrate surface of the substrate.
[0023] In a possible embodiment of a vertical field effect transistor structure, the channel region is p-doped.
[0024] In a possible alternative embodiment of a vertical field effect transistor structure, the channel region is n-doped.
[0025] In a possible embodiment of a vertical field effect transistor structure, a predefined local threshold voltage curve has a constant threshold voltage along the depth of the corresponding fin structure.
[0026] In a possible embodiment of a vertical field effect transistor structure, a predefined local threshold voltage curve has a gradually increasing threshold voltage along the depth of the corresponding fin structure. In certain application cases, this can be advantageous during the turn-on or turn-off process of the transistor.
[0027] In a possible embodiment of a vertical field effect transistor structure, a predefined local threshold voltage curve has a gradually decreasing threshold voltage along the depth of the corresponding fin structure. In certain application cases, this can be advantageous during the turn-on or turn-off process of the transistor.
[0028] In a possible embodiment of a vertical field effect transistor structure, the vertical field effect transistor structure includes a source electrode on the side of the fin structure pointing away from the substrate and a drain electrode on a second substrate surface of the substrate pointing away from the first substrate surface.
[0029] Thus, multiple fin structures of the embodiments of the vertical field effect transistor structure described herein are in electrical contact with the (single) source electrode, which results in a minimum on-resistance or turn-on resistance of the vertical field effect transistor structure achieved in this way. Description of the Drawings
[0030] In the following, other features and advantages of the present invention are explained based on the drawings.
[0031] The drawings show:
[0032] Figures 1a - 1d A schematic diagram showing a conventional vertical field effect transistor structure, having associated curves of doping, fin width, and local threshold voltage;
[0033] Figures 2a - 2d A schematic diagram showing another conventional vertical field effect transistor structure, having associated curves of doping, fin width, and local threshold voltage;
[0034] Figures 3a - 3d A schematic diagram showing a possible embodiment of a vertical field effect transistor structure according to the present invention, having associated curves of doping, fin width, and local threshold voltage;
[0035] Figures 4a - 4dSchematic diagram showing another possible embodiment of a vertical field effect transistor structure according to the present invention, having associated curves of doping, fin width, and local threshold voltage;
[0036] Figures 5a - 5d Schematic diagram showing another possible embodiment of a vertical field effect transistor structure according to the present invention, having associated curves of doping, fin width, and local threshold voltage;
[0037] Figures 6a - 6d Schematic diagram showing another possible embodiment of a vertical field effect transistor structure according to the present invention, having associated curves of doping, fin width, and local threshold voltage;
[0038] Figure 7 Flowchart showing a possible embodiment of a method for manufacturing a vertical field effect transistor structure according to the present invention. Detailed implementation mode
[0039] Figure 3a Schematic diagram showing a possible embodiment of a vertical field effect transistor structure.
[0040] In Figure 3a The vertically oriented field effect transistor structure schematically reproduced has a substrate 30 having a first substrate surface 30a and a second substrate surface 30b, the second substrate surface pointing away from the first substrate surface 30a. Preferably, the substrate 30 is an n-doped substrate 30, in particular a highly n-doped substrate 30. Preferably, the substrate 30 is an (n-doped / highly n-doped) silicon carbide substrate 30.
[0041] On the first substrate surface 30a, a semiconductor layer 32, in particular a silicon carbide layer, is epitaxially grown such that the semiconductor layer 32 contacts the first substrate surface 30a of the substrate 30. The first substrate surface 30a may be inclined at an angle between 2° and 7° with respect to the (0001) crystal plane of the silicon carbide substrate 30 along the direction of the silicon carbide substrate 30. This ensures fewer crystal defect structures in the semiconductor layer 32, in particular the silicon carbide layer 32, which is epitaxially grown on the first substrate surface 30a.
[0042] The epitaxially grown silicon carbide layer 32 forms the drift region of the vertical field effect transistor structure. Thus, the silicon carbide layer 32 is preferably n-doped, in particular weakly n-doped. On the side of the silicon carbide layer 32 facing away from the first substrate surface 30a, a plurality of recesses 34 can be structured into the silicon carbide layer 32 such that a plurality of fin structures 36 anchored to the silicon carbide layer 32 are structured out of the silicon carbide layer 32. The minimum width of the recesses 34 oriented parallel to the first substrate surface 30a is at least a factor of 2, preferably at least a factor of 5, greater than the maximum width of the fin structures 36 oriented parallel to the first substrate surface 30a. Constructing the fin structures 36 as "narrow" fin structures 36 results in a high channel density and a minimum on-resistance or turn-on resistance of the thus constructed vertical field effect transistor structure. Preferably, for the fin structures 36, a longitudinal direction oriented parallel to the first substrate surface 30a can be respectively defined, in which longitudinal direction the fin structures 36 have their maximum extension scale. In particular, the longitudinal direction of the fin structures 36 can be perpendicular to the direction of the silicon carbide layer 32. Preferably, on each end of the fin structures 36 facing away from the substrate 30, an n-doped source region 38 is respectively constructed. The respective n-doped source regions 38 of the fin structures 36 can in particular be strongly n-doped source regions 38. In Figures 3a - 3d the illustrated embodiment, the p-doped channel regions 40 are respectively located on the side of the n-doped source regions 38 of the fin structures 36 facing the substrate 30.
[0043] Figure 3a The vertical field effect transistor structure also has a plurality of gate electrodes 42, although only one of the gate electrodes 42 is reproduced in the figure. Each of the gate electrodes 42 is located between two adjacent fin structures 36. At least one gate dielectric 44 is formed and / or deposited on the vertical field effect transistor structure such that the fin structures 14 and the silicon carbide layer 32 are electrically insulated from the gate electrodes 42 by means of at least one gate dielectric 44. If present, in particular the n-doped source regions 38 and / or the p-doped channel regions 40 can be electrically insulated from the adjacent gate electrodes 42 by means of at least one gate dielectric 44.
[0044] In Figure 3a the illustrated embodiment, the FiFET has a source electrode 46 on the side of the fin structures 30 facing away from the substrate 30 and / or a drain electrode 48 on the second substrate surface 30b of the substrate 30 facing away from the first substrate surface 30a.
[0045] In a FinFET according to the present invention, doped channel regions 40 are respectively located on sides of source regions 38 of fin structures 36 that are oriented toward substrate 30. The doping of channel regions 40 is set to provide a predefined local threshold voltage profile in a vertical direction along a depth D of the respective fin structures 36.
[0046] Figures 3a - 3d Fig. 4 shows a first embodiment of a FinFET according to the present invention, which has associated curves. In Figures 3a - 3d the embodiment shown in Fig. 4, the fin width FB of the fins increases as the depth D (English: Depth) increases, as Figure 3c shown in Fig. 4. In the embodiment shown in Fig. 3, the channel regions 40 are p-doped. The doping charge density LD of this doping is schematically shown in Figure 3b Fig. 4. In order to provide a local threshold voltage profile with a constant threshold voltage Uth in the vertical direction (see Figure 3d Fig. 4), the doping of channel regions 40 is implemented to gradually decrease, as can be seen in Figure 3b Fig. 4. Channel regions 40 are implemented to have a gradually decreasing p-doping as the depth D increases. The wider the fin is in channel region 40, the smaller the p-doping within channel region 40 of that fin. With an appropriately selected dopant profile, it is possible to achieve that the two effects partially or completely compensate each other, and thus the resulting curve of the threshold voltage Uth on the fin extends uniformly or constantly in the vertical direction or along depth D, as Figure 3d shown in Fig. 4. In the embodiment shown in Figures 3a to 3d Fig. 4, the charge density of p-type charge carriers is changed in such a way that this charge density equalizes the threshold voltage change caused by the changed fin width FB. In one possible implementation, the dopant gradient can be generated in a simple manner by means of ion implantation.
[0047] In addition to a local threshold voltage Uth that is uniform or remains unchanged in the vertical direction, i.e., a constant threshold voltage Uth in the vertical direction (as Figure 3d shown in Fig. 4), a controlled change of the threshold voltage Uth over the height of the fin can also be advantageous, for example, for the turn-on process or turn-off process of the transistor. However, the controllability of the threshold voltage Uth is limited due to fin width changes caused by the fin manufacturing process. By appropriately selecting the doping gradient in channel regions 40, in a FinFET according to the present invention, the threshold voltage Uth can be locally and precisely set.
[0048] In the embodiment of the FinFET shown in Fig. 4, a higher change of the threshold voltage Uth over the fin height or depth D is achieved, as Figure 4dAs shown herein. Here, the p-type charge density LD is selected to gradually increase in the vertical direction as the depth D increases (as shown in Figure 4b ), so as to further improve or enhance the effect of the local threshold voltage increase caused by the increase in the fin width FB (see Figure 4c ), (see Figure 4d ).
[0049] In addition to the gradually increasing or decreasing or constant local threshold voltage Uth, by appropriately selecting the dopant profile or the charge density LD of the dopant, a combination consisting of increasing / decreasing and constant threshold voltages Uth can also be achieved within the fin.
[0050] The same mechanism can also be used in FinFETs without p-doping in the channel region. A FinFET with an unchanged n-doping profile having a constant charge density LD as shown in Figure 5b —as shown in Figure 5a —has a spatially deeper and wider region of the fin (see Figure 5c ) together with a smaller local threshold voltage Uth, as shown in Figure 5d .
[0051] If there is no p-doping in the channel region 40, then in the case of an increase in the fin width FB, the n-doping or the charge density LD can also be changed (see Figure 6b ), such that in a possible embodiment of the FinFET according to the invention (as shown in Figure 6a ), a locally uniform or constant threshold voltage Uth in the vertical direction is achieved, as shown in Figure 6d .
[0052] In addition to silicon carbide (SiC), the processing method according to the invention can also be applied in similar structural elements based on other power semiconductors, especially GaN, gallium oxide, aluminum nitride or diamond.
[0053] Figure 7 A flowchart for manufacturing a vertical field-effect transistor according to another aspect of the invention is shown. The manufacturing method according to the invention includes a plurality of main steps S, as shown for these main steps in Figure 7 .
[0054] In a first step S1, a semiconductor layer 32 is provided on a first substrate surface 30a of a substrate 30.
[0055] In a possible embodiment, the semiconductor layer 32 has silicon carbide (SiC), which is epitaxially grown on the first substrate surface 30a of the substrate 30.
[0056] In a further step S2, a plurality of fin structures 36 anchored to the semiconductor layer 32 are structured out of the semiconductor layer 32 on the side facing away from the first substrate surface 30a, wherein source regions 38 are respectively formed on the ends of the fin structures 36 facing away from the substrate 30.
[0057] For example, strip-shaped initial structures can be structured out of the semiconductor layer 32 by means of an anisotropic trench process. Alternatively or additionally, the etching method can include thermal oxidation of at least the strip-shaped initial structures and a subsequent etching process for etching the oxidized semiconductor layer 32.
[0058] In a further step S3, a plurality of gate electrodes 42 are formed, wherein one of the gate electrodes 42 is respectively arranged between two adjacent fin structures 36. The fin structures 36 and the semiconductor layer 32 are electrically insulated from the gate electrodes 42 by means of at least one formed gate dielectric 44.
[0059] After forming the fin structures 36, a plurality of gate electrodes 42 can be formed, wherein one of each of the gate electrodes 42 is arranged between two adjacent fin structures 36. Before forming the plurality of gate electrodes 42, at least one gate dielectric 44 is also deposited and / or formed such that the fin structures 36 and the silicon carbide layer 32 are electrically insulated from the gate electrodes 42 by means of at least one gate dielectric 44.
[0060] In a further step S4, the doping of the channel regions 40 is set to provide a predefined local threshold voltage profile along the depth D of the respective fin structures 36, and the channel regions are respectively located on the side of the source regions 38 of the fin structures 36 facing the substrate 30.
[0061] In a preferred embodiment, a doping gradient of the channel regions 40 is generated by means of ion implantation.
[0062] Optionally, a source electrode 46 can also be formed on the side of the fin structure 30 facing away from the substrate 30 and / or a drain electrode 48 can be formed on the second substrate surface 30b of the substrate 30 facing away from the first substrate surface 30a.
[0063] Thus, the fin structures 36 can be in electrical contact with a single source electrode 46. Preferably, the vertical field effect transistor structure further includes a drain electrode 48 fastened to the second substrate surface 30b. In a possible embodiment, the vertical field effect transistor structure can furthermore have a p-doped shielding region, which, however, is not reproduced pictorially in FIGS. 3 to 6 for the sake of clarity.
[0064] The vertical field effect transistor structure reproduced graphically in FIGS. 3 to 6 can be used, for example, as a traction inverter, in particular as a traction inverter in an electric drive train in an EV / HEV, or as an inverter. The vertical field effect transistor structure can be used in a plurality of devices, for example in domestic appliances, in particular in washing machines. It should be noted that the usability of the vertical field effect transistor structure is not limited to a specific field of use.
Claims
1. A vertical field effect transistor structure, the vertical field effect transistor structure having: A substrate (30) having a first substrate surface (30a); A semiconductor layer (32) located on the first substrate surface (30a), a plurality of fin structures (36) anchored on the semiconductor layer (32) being structured out of the semiconductor layer (32) on a side of the semiconductor layer (32) pointing away from the first substrate surface (30a), wherein: A source region (38) is formed at each end of the fin structure (36) pointing away from the substrate (30); and A plurality of gate electrodes (42), wherein each of the gate electrodes (42) is located between two adjacent fin structures (36), and the fin structure (36) and the semiconductor layer (32) are electrically insulated from the gate electrode (42) by at least one gate dielectric (44); It is characterized in that Doped channel regions (40) are respectively located on the side of the source region (38) of the fin structure (36) oriented toward the substrate (30), and the doping of the doped channel regions is set to provide a predefined local threshold voltage curve along the depth (D) of the corresponding fin structure (36).
2. The vertical field effect transistor structure according to claim 1, wherein: The fin width (FB) of the fin structure (36) increases with the increase of the depth (D).
3. The vertical field effect transistor structure according to claim 1 or 2, wherein: The semiconductor layer (32) includes a silicon carbide layer.
4. The vertical field effect transistor structure according to claim 3, wherein: The silicon carbide layer is epitaxially grown on a substrate surface (30a) of the substrate (30).
5. A vertical field effect transistor structure according to any one of the preceding claims, wherein: The channel region (40) is p-doped.
6. A vertical field effect transistor structure according to any one of the preceding claims, wherein: The channel region (40) is n-doped.
7. A vertical field effect transistor structure according to any one of the preceding claims, wherein: The predefined local threshold voltage profile has a constant threshold voltage (Uth) along a depth (D) of the corresponding fin structure (36).
8. The vertical field effect transistor structure according to any one of claims 1 to 6, wherein: The predefined local threshold voltage profile has a gradually increasing threshold voltage (Uth) along a depth (D) of the corresponding fin structure (36).
9. The vertical field effect transistor structure according to any one of claims 1 to 6, wherein: The predefined local threshold voltage profile has a gradually decreasing threshold voltage (Uth) along a depth (D) of the corresponding fin structure (36).
10. A vertical field effect transistor structure according to any one of the preceding claims, wherein: The vertical field effect transistor structure comprises a source electrode (46) on a side of the fin structure (36) pointing away from the substrate (30) and a drain electrode (48) on a second substrate surface (30b) of the substrate (30) pointing away from the first substrate surface (30a).
11. A method for manufacturing a vertical field effect transistor structure, the method comprising the following steps: Providing (S1) a semiconductor layer (32) on a first substrate surface (30a) of a substrate (30); A plurality of fin structures (36) anchored to the semiconductor layer (32) are structured (S2) out of the semiconductor layer (32) on a side of the semiconductor layer (32) pointing away from the first substrate surface (30a), wherein: forming a source region (38) at each end of the fin structure (36) pointing away from the substrate (30); forming (S3) a plurality of gate electrodes (42), wherein one of the gate electrodes (42) is arranged between two adjacent fin structures (36), and the fin structure (36) and the semiconductor layer (32) are electrically insulated from the gate electrode (42) by means of at least one gate dielectric (44); The doping of a channel region (40) is set (S4) to provide a predefined local threshold voltage curve along the depth (D) of the corresponding fin structure (36), wherein the channel region is respectively located on the side of the source region (38) of the fin structure (36) oriented toward the substrate (30).
12. The method according to claim 11, wherein: The doping of the channel region (40) is produced with the aid of ion implantation.
13. The method according to claim 11 or 12, wherein: The semiconductor layer (32) comprises silicon carbide which is epitaxially grown on a first substrate surface (30a) of the substrate (30).
14. The method according to any one of claims 11 to 13, wherein: The channel region (40) is p-doped.
15. The method according to any one of claims 11 to 13, wherein: The channel region (40) is n-doped.