Display panel and display device

Abstract

The invention relates to a display panel and a display device, and relates to the technical field of display. The display panel comprises a pixel circuit, a light-emitting element and a signal line, the signal line comprises a grid reset signal line, an anode reset signal line and a power supply signal line; the grid reset signal lines comprise first grid reset signal lines extending in the first direction and second grid reset signal lines extending in the second direction; the first gate reset signal line comprises a plurality of first sub-segments extending along a first direction; the first direction intersects with the second direction; the anode reset signal line comprises a first anode reset signal line extending along a first direction and a second anode reset signal line extending along a second direction; wherein the first anode reset signal line comprises a plurality of second sub-segments extending along the first direction; the power signal lines include first power signal lines extending in a first direction and arranged in a second direction. The display uniformity can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the continuous development of display technologies, display products are gradually moving towards high resolution. However, the higher the resolution, the more compressed the design space becomes, making it impossible to fully consider the grid design of some signal lines, resulting in poor display uniformity of display products. Summary of the Invention

[0003] The present application provides a display panel and a display device, which can implement the grid design of gate reset signal lines and anode reset signal lines, helping to improve display uniformity.

[0004] In a first aspect, an embodiment of the present application provides a display panel, including: a pixel circuit, a light-emitting element, and signal lines;

[0005] The pixel circuit includes a driving transistor, a gate reset transistor, and an anode reset transistor; the signal lines include a gate reset signal line, an anode reset signal line, and a power supply signal line; a first pole of the gate reset transistor is electrically connected to the gate reset signal line, a second pole of the gate reset transistor is electrically connected to a gate of the driving transistor, a first pole of the anode reset transistor is electrically connected to the anode reset signal line, a second pole of the anode reset transistor is electrically connected to a first electrode of the light-emitting element, and a second electrode of the light-emitting element is electrically connected to the power supply signal line; wherein,

[0006] The gate reset signal line includes a first gate reset signal line extending along a first direction and a second gate reset signal line extending along a second direction; wherein, the first gate reset signal line includes a plurality of first sub-segments extending along the first direction, and the first sub-segments are electrically connected to the second gate reset signal line; the first direction intersects with the second direction;

[0007] The anode reset signal line includes a first anode reset signal line extending along the first direction and a second anode reset signal line extending along the second direction; wherein, the first anode reset signal line includes a plurality of second sub-segments extending along the first direction, and the second sub-segments are electrically connected to the second anode reset signal line;

[0008] The power supply signal line includes first power supply signal lines extending along the first direction and arranged along the second direction.

[0009] In a second aspect, an embodiment of the present application further provides a display device, which includes the display panel provided above.

[0010] The display panel and the display device provided by the embodiments of the present application, by setting the gate reset signal line to include a first gate reset signal line and a second gate reset signal line extending in different directions, and setting the first gate reset signal to include a plurality of first sub-segments extending in the first direction and disconnected, and a second gate reset signal line extending in the second direction and connected, and electrically connecting the first sub-segments to the second gate reset signal line, not only realizes the layout design of the gate reset signal line, but also realizes the grid design of the gate reset signal line, which helps to improve the distribution uniformity of the gate reset signal line, thereby improving the uniformity of the gate reset signal in the display panel and helping to improve the display effect of the display panel; in addition, by setting the anode reset signal line to include a first anode reset signal line and a second anode reset signal line extending in different directions, and setting the first anode reset signal to include a plurality of second sub-segments extending in the first direction and disconnected, and a second anode reset signal line extending in the second direction and connected, and electrically connecting the second sub-segments to the second anode reset signal line, not only realizes the layout design of the anode reset signal line, but also realizes the grid design of the anode reset signal line, which helps to improve the distribution uniformity of the anode reset signal line, thereby improving the uniformity of the gate reset signal in the display panel and helping to improve the display effect of the display panel; furthermore, by setting the power supply signal line to include a first power supply signal line extending in the first direction and arranged in the second direction, the layout design of the power supply signal line is realized, providing support for the display panel to realize the display function; thus, the layout design of the gate reset signal line, the anode reset signal line and the power supply signal line is realized, and the grid design of the gate reset signal line and the anode reset signal line is also realized, which helps to improve the wiring uniformity in the display panel, thereby helping to improve the signal uniformity of the display panel and further helping to improve the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 FIG. is a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0012] Figure 2 FIG. is a schematic structural diagram of another display panel provided by an embodiment of the present application;

[0013] Figure 3 FIG. is a schematic structural diagram of a pixel circuit and a light-emitting element provided by an embodiment of the present application;

[0014] Figure 4 FIG. is a schematic layout diagram of a display panel provided by an embodiment of the present application;

[0015] Figure 5 FIG. is a schematic layout diagram of a first active layer provided by an embodiment of the present application;

[0016] Figure 6Schematic diagram of the layout structure of a first conductive layer provided by an embodiment of the present application;

[0017] Figure 7 Schematic diagram of the layout structure of a second conductive layer provided by an embodiment of the present application;

[0018] Figure 8 Schematic diagram of the layout structure of a third conductive layer provided by an embodiment of the present application;

[0019] Figure 9 Schematic diagram of the layout structure of another display panel provided by an embodiment of the present application;

[0020] Figure 10 Schematic diagram of the layout structure of yet another display panel provided by an embodiment of the present application;

[0021] Figure 11 Schematic diagram of the layout structure of another first active layer provided by an embodiment of the present application;

[0022] Figure 12 Schematic diagram of the layout structure of another first conductive layer provided by an embodiment of the present application;

[0023] Figure 13 Schematic diagram of the layout structure of another second conductive layer provided by an embodiment of the present application;

[0024] Figure 14 Schematic diagram of the layout structure of another third conductive layer provided by an embodiment of the present application;

[0025] Figure 15 Schematic diagram of the layout structure of still another display panel provided by an embodiment of the present application;

[0026] Figure 16 Schematic diagram of the cross-sectional structure of a display panel provided by an embodiment of the present application;

[0027] Figure 17 Schematic diagram of the structure of yet another display panel provided by an embodiment of the present application;

[0028] Figure 18 Schematic diagram of the structure of still another display panel provided by an embodiment of the present application;

[0029] Figure 19 Schematic diagram of the layout structure of another display panel provided by an embodiment of the present application;

[0030] Figure 20 Schematic diagram of the layout structure of yet another display panel provided by an embodiment of the present application;

[0031] Figure 21 Schematic diagram of the structure of a display device provided by an embodiment of the present application.

[0032] Description of Reference Numerals

[0033] 1. Display panel; 2. Display device; 100. Pixel circuit; 101. First sub-pixel; 102. Second sub-pixel; 103. Third sub-pixel; 011. Buffer layer; 012. First active layer; 013. First gate insulating layer; 014. First conductive layer; 015. Interlayer dielectric layer; 016. Second conductive layer; 017. Second gate insulating layer; 018. Second active layer; 019. Third gate insulating layer; 020. Second gate metal layer; 021. Passivation layer; 022. Third conductive layer; 023. First auxiliary planarization layer; 024. Fourth conductive layer; 025. Second auxiliary planarization layer; 026. Second auxiliary metal layer; 027. Planarization layer; 028. Reflective electrode layer; 029. Light-emitting material layer; 030. Counter electrode layer; 031. Encapsulation layer; 41. First connection part; 42. Second connection part. Detailed Embodiment

[0034] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application in this specification are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0036] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be intermediate elements. Further, when a layer is referred to as being "under" another layer, it can be directly below or there can be one or more intermediate elements. It can also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there can also be one or more intermediate elements.

[0037] In the case of using "comprising", "having", and "including" as described herein, unless a clear limiting term such as "only", "consisting of", etc. is used, another component can also be added. Unless otherwise mentioned, terms in the singular form can include the plural form and should not be construed as having a quantity of one.

[0038] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0039] It should also be understood that when interpreting an element, although not explicitly described, the element is interpreted as including an error range, which should be within the acceptable deviation range of a specific value determined by those skilled in the art. For example, "about", "approximately" or "substantially" may mean within one or more standard deviations, which is not defined herein.

[0040] In addition, in the specification, the phrase "schematic diagram of planar distribution" refers to the drawing when observing the target part from above, and the phrase "schematic cross-sectional view" refers to the drawing when observing the cross-section intercepted by vertically cutting the target part from the side.

[0041] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the various elements are only drawn by way of example in the drawings and not necessarily to the true scale.

[0042] As described in the background art section, there is a problem of poor uniformity in the display panels in the related art. It can be understood that the display panel may include signal lines, and the signal lines may include gate reset signal lines, anode reset signal lines, and power signal lines. In some display panels, due to the limited space of the display panel, when laying out the gate reset signal lines, anode reset signal lines, and power signal lines, it is impossible to achieve a grid design for the gate reset signal lines and anode reset signal lines, resulting in poor uniformity of the display panel. Therefore, there is a problem of non-uniformity in the display panel.

[0043] Based on the above technical problems, the inventors have found through research that by re-layoutting the signal lines in the display panel, the phenomenon of uneven display can be improved under limited space. Based on this, the inventors have further developed the technical solution of the embodiment of the present application. Specifically, the display panel provided by the embodiment of the present application includes a pixel circuit, a light-emitting element, and signal lines; wherein, the pixel circuit includes a driving transistor, a gate reset transistor, and an anode reset transistor; the signal lines include a gate reset signal line, an anode reset signal line, and a power supply signal line; a first pole of the gate reset transistor is electrically connected to the gate reset signal line, a second pole of the gate reset transistor is electrically connected to the gate of the driving transistor, a first pole of the anode reset transistor is electrically connected to the anode reset signal line, a second pole of the anode reset transistor is electrically connected to a first electrode of the light-emitting element, and a second electrode of the light-emitting element is electrically connected to the power supply signal line; the gate reset signal line includes a first gate reset signal line extending in a first direction and a second gate reset signal line extending in a second direction; wherein, the first gate reset signal line includes a plurality of first sub-segments extending in the first direction, and the first sub-segments are electrically connected to the second gate reset signal line; the first direction intersects with the second direction; the anode reset signal line includes a first anode reset signal line extending in the first direction and a second anode reset signal line extending in the second direction; wherein, the first anode reset signal line includes a plurality of second sub-segments extending in the first direction, and the second sub-segments are electrically connected to the second anode reset signal line; the power supply signal line includes a first power supply signal line extending in the first direction and arranged in the second direction. In this way, a reasonable layout of the gate reset signal line, the anode reset signal line, and the power supply signal line is achieved, and a grid design of the gate reset signal line and the anode reset signal line is also achieved. Thereby, the display uniformity is improved.

[0044] The above is the core idea of the present application. Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0045] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present application. Figure 2 It is a schematic structural diagram of another display panel provided by an embodiment of the present application. Figure 3 It is a schematic structural diagram of a pixel circuit and a light-emitting element provided by an embodiment of the present application. As shown in Figures 1 to 3 The display panel 1 provided by the embodiment of the present application includes a pixel circuit 100, a light-emitting element D, and signal lines.

[0046] Among them, the signal lines include a gate reset signal line Vref1, an anode reset signal line Vref2, and a power supply signal line PVEE.

[0047] The gate reset signal line Vref1 includes a first gate reset signal line Vref11 extending in a first direction and a second gate reset signal line Vref12 extending in a second direction. Among them, the display panel 1 may include a plurality of first gate reset signal lines Vref11, and the plurality of first gate reset signal lines Vref11 may be arranged in the second direction; the display panel 1 may include a plurality of second gate reset signal lines Vref12, and the plurality of second gate reset signal lines Vref12 may be arranged in the first direction. The gate reset signal line Vref1, including the first gate reset signal line Vref11 and the second gate reset signal line Vref12, is respectively configured to provide a gate reset signal to the pixel circuit 100.

[0048] Among them, the first gate reset signal line Vref11 includes a plurality of first sub-segments Vref110 extending in the first direction. The first sub-segment Vref110 is electrically connected to the second gate reset signal line Vref12. The first sub-segment Vref110 may be electrically connected to at least one second gate reset signal line Vref12. The plurality of first sub-segments Vref110 of the first gate reset signal line Vref11 may be arranged at intervals. That is, the first gate reset signal line Vref11 may be disconnected in the first direction and includes a plurality of discontinuous first sub-segments Vref110; the second gate reset signal line Vref12 may be continuous in the second direction.

[0049] The anode reset signal line Vref2 includes a first anode reset signal line Vref21 extending in a first direction and a second anode reset signal line Vref22 extending in a second direction. Among them, the display panel 1 may include a plurality of first anode reset signal lines Vref21, and the plurality of first anode reset signal lines Vref21 may be arranged in the second direction; the display panel 1 may include a plurality of second anode reset signal lines Vref22, and the plurality of second anode reset signal lines Vref22 may be arranged in the first direction. The anode reset signal line Vref2, including the first anode reset signal line Vref21 and the second anode reset signal line Vref22, is respectively configured to provide an anode reset signal to the pixel circuit 100.

[0050] Among them, the first anode reset signal line Vref21 includes a plurality of second sub-segments Vref210 extending in the first direction. The second sub-segments Vref210 are electrically connected to the second anode reset signal line Vref22. The second sub-segments Vref210 can be electrically connected to at least one second anode reset signal line Vref22. The plurality of second sub-segments Vref210 of the first anode reset signal line Vref21 can be arranged at intervals. That is to say, the first anode reset signal line Vref21 can be disconnected along the first direction and includes a plurality of discontinuous second sub-segments Vref210; the second anode reset signal line Vref22 can be continuous along the second direction.

[0051] The power supply signal line PVEE includes a first power supply signal line PVEE1 extending in the first direction. The power supply signal line PVEE can include a plurality of first power supply signal lines PVEE1, and the plurality of first power supply signal lines PVEE1 can be arranged in the second direction. The power supply signal line PVEE, including the first power supply signal line PVEE1, is configured to provide a first power supply signal to the light-emitting element D.

[0052] Among them, the first direction intersects the second direction. In some embodiments, the first direction is perpendicular to the second direction; for example, in Figure 1 and Figure 2 in the shown display panel 1, the first direction is the Y-axis direction and the second direction is the X-axis direction. In some embodiments, the first direction intersects the second direction and is not perpendicular.

[0053] The display panel 1 can include a plurality of pixel circuits 100 and a plurality of light-emitting elements D. Among them, the plurality of pixel circuits 100 can be arranged in an array, and the plurality of light-emitting elements D can be arranged in an array. The pixel circuit 100 is configured to drive the light-emitting element D to emit light for display and control the light-emitting brightness of the light-emitting element D. The pixel circuit 100 can include a plurality of transistors, and the plurality of transistors can include a driving transistor M0, a gate reset transistor M1, and an anode reset transistor M2.

[0054] The first pole of the gate reset transistor M1 is electrically connected to the gate reset signal line Vref1. The first pole of the gate reset transistor M1 can be electrically connected to the first gate reset signal line Vref11 and the second gate reset signal line Vref12 respectively. Among them, the gate reset signal line Vref1, including the first gate reset signal line Vref11 and the second gate reset signal line Vref12, can be respectively configured to provide a gate reset signal to the first pole of the gate reset transistor M1. The second pole of the gate reset transistor M1 is electrically connected to the first node N1 and the gate of the driving transistor M0 respectively.

[0055] Among them, the signal line may further include a first scan signal line Scan1. The gate of the gate reset transistor M1 may be electrically connected to the first scan signal line Scan1, and the first scan signal line Scan1 may be configured to provide a first scan signal to the gate of the gate reset transistor M1. The gate reset transistor M1 may transmit a gate reset signal to the gate of the driving transistor M0 in response to the enabling level of the first scan signal to reset the gate of the driving transistor M0.

[0056] Among them, the number of the gate reset transistors M1 may be one or more. Exemplarily, the gate reset transistor M1 includes a first gate reset transistor and a second gate reset transistor. Among them, the gates of the first gate reset transistor and the second gate reset transistor are respectively electrically connected to the first scan signal line Scan1. The first pole of the first gate reset transistor is electrically connected to the gate reset signal line Vref1. The second pole of the first gate reset transistor is respectively electrically connected to the fourth node N4 and the first pole of the second gate reset transistor. The second pole of the second gate reset transistor is respectively electrically connected to the first node N1 and the gate of the driving transistor M0.

[0057] The first pole of the anode reset transistor M2 is electrically connected to the anode reset signal line Vref2. The first pole of the anode reset transistor M2 may be respectively electrically connected to a first anode reset signal line Vref21 and a second anode reset signal line Vref22. The second pole of the anode reset transistor M2 may be respectively electrically connected to the sixth node N6 and the first electrode of the light-emitting element D. Among them, the anode reset signal line Vref2, including the first anode reset signal line Vref21 and the second anode reset signal line Vref22, may be respectively configured to provide an anode reset signal to the first electrode of the light-emitting element D.

[0058] Among them, the signal line may further include a second scan signal line Scan2. The gate of the anode reset transistor M2 may be connected to the second scan signal line Scan2, and the second scan signal line Scan2 may be configured to provide a received second scan signal to the gate of the anode reset transistor M2. The anode reset transistor M2 may transmit an anode reset signal to the first electrode of the light-emitting element D in response to the enabling level of the second scan signal to reset the first electrode of the light-emitting element D. The number of the anode reset transistors M2 may be one.

[0059] The second electrode of the light-emitting element D is electrically connected to the power supply signal line PVEE. Among them, the power supply signal line PVEE may be configured to provide a first power supply signal to the second electrode of the light-emitting element D. Among them, the first electrode of the light-emitting element D may be an anode, and the second electrode may be a cathode. In this regard, the power supply signal line PVEE may provide a first power supply signal to the cathode of the light-emitting element D.

[0060] The display panel 1 provided by the embodiment of the present application, by setting the gate reset signal line Vref1 to include a first gate reset signal line Vref11 and a second gate reset signal line Vref12 extending in different directions, and setting the first gate reset signal to include a plurality of first sub-segments Vref110 extending in a first direction and disconnected, and a second gate reset signal line Vref12 extending in a second direction and connected, and electrically connecting the first sub-segments Vref110 to the second gate reset signal line Vref12, not only realizes the layout design of the gate reset signal line Vref1, but also realizes the grid design of the gate reset signal line Vref1, which helps to improve the distribution uniformity of the gate reset signal line Vref1, thereby improving the uniformity of the gate reset signal in the display panel 1, and helps to improve the display effect of the display panel 1; In addition, by setting the anode reset signal line Vref2 to include a first anode reset signal line Vref21 and a second anode reset signal line Vref22 extending in different directions, and setting the first anode reset signal to include a plurality of second sub-segments Vref210 extending in a first direction and disconnected, and a second anode reset signal line Vref22 extending in a second direction and connected, and electrically connecting the second sub-segments Vref210 to the second anode reset signal line Vref22, not only realizes the layout design of the anode reset signal line Vref2, but also realizes the grid design of the anode reset signal line Vref2, which helps to improve the distribution uniformity of the anode reset signal line Vref2, thereby improving the uniformity of the gate reset signal in the display panel 1, and helps to improve the display effect of the display panel 1; In addition, by setting the power supply signal line PVEE to include a first power supply signal line PVEE1 extending in a first direction and arranged in a second direction, the layout design of the power supply signal line PVEE is realized, which provides support for the display panel 1 to realize the display function; In this way, the layout design of the gate reset signal line Vref1, the anode reset signal line Vref2 and the power supply signal line PVEE is realized, and the grid design of the gate reset signal line Vref1 and the anode reset signal line Vref2 is also realized, which helps to improve the wiring uniformity in the display panel 1, thereby helping to improve the signal uniformity of the display panel 1, and further helping to improve the display effect.

[0061] Please continue to refer to Figure 1 and Figure 2 In some embodiments, the display panel 1 includes a display area AA. Among them, the display area AA includes a first gate reset signal line Vref11, a first anode reset signal line Vref21, a first power supply signal line PVEE1, a second gate reset signal line Vref12 and a second anode reset signal line Vref22.

[0062] Among them, along the second direction, the second gate reset signal line Vref12 and the second anode reset signal line Vref22 respectively penetrate through the display area AA of the display panel 1. Among them, the lengths of the second gate reset signal line Vref12 and the second anode reset signal line Vref22 may be the same or different. Exemplarily, along the second direction, the lengths of the second gate reset signal line Vref12 and the second anode reset signal line Vref22 are respectively greater than or equal to the total width of the pixel circuit 100. Another exemplarily, along the second direction, the lengths of the second gate reset signal line Vref12 and the second anode reset signal line Vref22 are respectively greater than or equal to the width of the display area AA. In this way, by setting the second gate reset signal line Vref12 and the second anode reset signal line Vref22 extending along the second direction as an overall structure that penetrates through the display area AA, the distribution uniformity of the second gate reset signal line Vref12 in the display panel 1 can be improved, and the distribution uniformity of the second anode reset signal line Vref22 in the display panel 1 can be improved, thereby improving the wiring uniformity in the display panel 1, which is beneficial to improving the overall signal consistency of the display panel 1 and improving the display effect.

[0063] Along the first direction, the first power supply signal line PVEE1 penetrates through the display area AA of the display panel 1. Exemplarily, along the first direction, the length of the first power supply signal line PVEE1 is greater than or equal to the total length of the pixel circuit 100. Another exemplarily, along the first direction, the length of the first power supply signal line PVEE1 is greater than or equal to the width of the display area AA. In this way, by setting the first power supply signal line PVEE1 extending along the first direction as an overall structure that penetrates through the display area AA, the distribution uniformity of the first power supply signal line PVEE1 in the display panel 1 can be improved, thereby improving the wiring uniformity in the display panel 1, which is beneficial to improving the overall signal consistency of the display panel 1 and improving the display effect.

[0064] Along the first direction and the second direction, the first sub-segment Vref110 and the second sub-segment Vref210 are alternately arranged. That is, along the first direction, the first sub-segment Vref110 and the second sub-segment Vref210 are alternately arranged. Along the second direction, the first sub-segment Vref110 and the second sub-segment Vref210 are alternately arranged. Among them, the first sub-segment Vref110 and the second sub-segment Vref210 can be alternately arranged according to a certain quantity ratio; for example, they are alternately arranged in sequence with one first sub-segment Vref110 and one second sub-segment Vref210, and the quantity ratio can be 1:1; or, they are alternately arranged in sequence with two first sub-segments Vref110 and one second sub-segment Vref210, and the quantity ratio can be 2:1; or, they are alternately arranged according to other quantity ratios, which are not limited here. With such an arrangement, the distribution uniformity of the first sub-segment Vref110 in the display panel 1 can be improved, and the distribution uniformity of the second sub-segment Vref210 in the display panel 1 can be improved, thereby improving the distribution uniformity of the first gate reset signal line Vref11 and the first anode reset signal line Vref21 in the display panel 1 respectively, and further improving the wiring uniformity in the display panel 1, which is beneficial to improving the overall signal consistency of the display panel 1 and improving the display effect.

[0065] Please continue to refer to Figure 1 and Figure 2 , in some embodiments, along the second direction, a first power supply signal line PVEE1 is included between any adjacent first sub-segment Vref110 and second sub-segment Vref210. That is, along the second direction, a first power supply signal line PVEE1 is spaced between any adjacent first sub-segment Vref110 and second sub-segment Vref210.

[0066] Exemplarily, along the second direction, the first sub-segment Vref110, the first power supply signal line PVEE1, and the second sub-segment Vref210 are arranged in sequence; and / or, the second sub-segment Vref210, the first power supply signal line PVEE1, and the first sub-segment Vref110 are arranged in sequence.

[0067] With such an arrangement, a first power supply signal line PVEE1 is spaced between the first sub-segment Vref110 and the second sub-segment Vref210. While improving the wiring uniformity of the first sub-segment Vref110 and the wiring uniformity of the second sub-segment Vref210, the distance between the first sub-segment Vref110 and the second sub-segment Vref210 is increased, reducing the mutual influence between the two, which is beneficial to improving the distribution consistency of the gate reset signal in the display panel 1 and the distribution consistency of the anode reset signal in the display panel 1, and is beneficial to improving the display effect.

[0068] Please continue to refer to Figure 1 andFigure 2 In some embodiments, the second gate reset signal line Vref12 and the second anode reset signal line Vref22 are alternately arranged in the first direction.

[0069] Among them, the second gate reset signal line Vref12 and the second anode reset signal line Vref22 can be alternately arranged according to a certain quantity ratio; for example, they can be alternately arranged in sequence as one second gate reset signal line Vref12 and one second anode reset signal line Vref22, and the quantity ratio can be 1:1; or, they can be alternately arranged in sequence as two second gate reset signal lines Vref12 and one second anode reset signal line Vref22, and the quantity ratio can be 2:1; or, they can be alternately arranged according to other quantity ratios, which is not limited herein.

[0070] With such an arrangement, the distribution uniformity of the second gate reset signal line Vref12 in the display panel 1 can be improved, and the distribution uniformity of the second anode reset signal line Vref22 in the display panel 1 can be improved, thereby improving the wiring uniformity in the display panel 1, which is beneficial to improving the overall signal consistency of the display panel 1 and enhancing the display effect.

[0071] Figures 4 to 15 It is a schematic layout structure diagram of a display panel 1 and its internal film layers provided by an embodiment of the present application. Combining Figures 1 to 15 As shown, in some embodiments, the first sub-segment Vref110 and the second gate reset signal line Vref12 overlap in the third direction.

[0072] The first sub-segment Vref110 can overlap with at least one second gate reset signal line Vref12 in the third direction. For example, the first sub-segment Vref110 can overlap with one second gate reset signal line Vref12 in the third direction; or, the first sub-segment Vref110 can overlap with two second gate reset signal lines Vref12 in the third direction; or, the first sub-segment Vref110 can overlap with three or more second gate reset signal lines Vref12 in the third direction, which is not limited herein.

[0073] In each embodiment of the present application, the third direction is perpendicular to the plane where the first direction and the second direction are located. Among them, the third direction can be the thickness direction of the display panel 1. The overlap can be understood as having an overlap in the positive projection in the third direction.

[0074] Among them, a plurality of first sub-segments Vref110 arranged along the second direction have the same overlapping second gate reset signal lines Vref12. Exemplarily, a plurality of first sub-segments Vref110 arranged along the second direction and having the same center point in the second direction have the same overlapping second gate reset signal lines Vref12. For example, a plurality of first sub-segments Vref110 arranged along the second direction and having the same center point in the second direction may overlap with the same second gate reset signal line Vref12, or may overlap with the same multiple second gate reset signal lines Vref12, which is not limited herein.

[0075] Taking Figure 9 and Figure 15 the shown display panel 1 as an example, the pixel circuits 100 in the display panel 1 are arranged in an array, and the second direction is the row direction of the pixel circuits 100; among them, a plurality of first sub-segments Vref110 arranged along the second direction and having the same center point in the second direction, that is, a plurality of first sub-segments Vref110 arranged in the same row, have the same overlapping second gate reset signal lines Vref12. With such a setting, it is beneficial to reduce the planar occupation area of the first sub-segments Vref110 and the second gate reset signal lines Vref12 in the display panel 1, thereby being beneficial to reducing the planar occupation area of the first gate reset signal lines Vref11 and the second gate reset signal lines Vref12 in the display panel 1, and further being beneficial to reducing the planar occupation area of the gate reset signal lines Vref1 in the display panel 1, being beneficial to increasing the spatial density of the signal lines, improving the pixel density, and further improving the display effect.

[0076] A plurality of first sub-segments Vref110 arranged along the first direction have different overlapping second gate reset signal lines Vref12. Exemplarily, a plurality of first sub-segments Vref110 arranged along the first direction have completely different overlapping second gate reset signal lines Vref12. For example, a plurality of first sub-segments Vref110 arranged along the first direction respectively overlap with a second gate reset signal line Vref12, and the second gate reset signal lines Vref12 with which each first sub-segment Vref110 overlaps are different.

[0077] Another exemplarily, a plurality of first sub-segments Vref110 arranged along the first direction have partially different overlapping second gate reset signal lines Vref12. For example, a plurality of first sub-segments Vref110 arranged along the first direction respectively overlap with two second gate reset signal lines Vref12; and among adjacent two first sub-segments Vref110, one overlapping second gate reset signal line Vref12 is the same, and the remaining second gate reset signal lines Vref12 are different.

[0078] Such a setting facilitates the realization of the electrical connection between the first sub-segment Vref110 arranged in the first direction and the second gate reset signal line Vref12, thereby facilitating the reduction of the wiring length between the first sub-segment Vref110 and the second gate reset signal line Vref12, increasing the space density of the signal lines, enhancing the pixel density, and further improving the display effect.

[0079] Please continue to refer to Figures 1 to 15 As shown, in some embodiments, the second sub-segment Vref210 and the second anode reset signal line Vref22 overlap in the third direction.

[0080] The second sub-segment Vref210 may overlap with at least one second anode reset signal line Vref22 in the third direction. For example, the second sub-segment Vref210 may overlap with one second anode reset signal line Vref22 in the third direction; or, the second sub-segment Vref210 may overlap with two second anode reset signal lines Vref22 in the third direction; or, the second sub-segment Vref210 may overlap with three or more second anode reset signal lines Vref22 in the third direction, which is not limited herein.

[0081] Among them, for the multiple second sub-segments Vref210 arranged in the second direction, the overlapping second anode reset signal lines Vref22 are the same. Exemplarily, for the multiple second sub-segments Vref210 arranged in the second direction and having the same center point in the second direction, the overlapping second anode reset signal lines Vref22 are the same. For example, for the multiple second sub-segments Vref210 arranged in the second direction and having the same center point in the second direction, they may overlap with the same second anode reset signal line Vref22, or may overlap with the same multiple second anode reset signal lines Vref22, which is not limited herein.

[0082] Taking Figure 9 and Figure 15 the shown display panel 1 as an example, the pixel circuits 100 in the display panel 1 are arranged in an array, and the second direction is the row direction of the pixel circuits 100; among them, for the multiple second sub-segments Vref210 arranged in the second direction and having the same center point in the second direction, that is, the multiple second sub-segments Vref210 arranged in the same row, the overlapping second anode reset signal lines Vref22 are the same.

[0083] With such a setting, it is beneficial to reduce the planar occupation area of the second sub-segment Vref210 and the second anode reset signal line Vref22 in the display panel 1, thereby facilitating the reduction of the planar occupation area of the first anode reset signal line Vref21 and the second anode reset signal line Vref22 in the display panel 1. Furthermore, it is conducive to reducing the planar occupation area of the anode reset signal line Vref2 in the display panel 1, increasing the spatial density of the signal lines, improving the pixel density, and thus enhancing the display effect.

[0084] The multiple second sub-segments Vref210 arranged along the first direction are different from the overlapping second anode reset signal lines Vref22. Exemplarily, the multiple second sub-segments Vref210 arranged along the first direction are completely different from the overlapping second anode reset signal lines Vref22. For example, the multiple second sub-segments Vref210 arranged along the first direction respectively overlap with one second anode reset signal line Vref22, and the second anode reset signal lines Vref22 with which each second sub-segment Vref210 overlaps are different.

[0085] In another exemplary case, the multiple second sub-segments Vref210 arranged along the first direction are partially different from the overlapping second anode reset signal lines Vref22. For example, the multiple second sub-segments Vref210 arranged along the first direction respectively overlap with two second anode reset signal lines Vref22; and among adjacent two second sub-segments Vref210, one second anode reset signal line Vref22 with which they overlap is the same, and the remaining second anode reset signal lines Vref22 are different.

[0086] With such a setting, it is beneficial to achieve the electrical connection between the second sub-segments Vref210 arranged along the first direction and the second anode reset signal lines Vref22, thereby facilitating the reduction of the wiring length between the second sub-segments Vref210 and the second anode reset signal lines Vref22, increasing the spatial density of the signal lines, improving the pixel density, and thus enhancing the display effect.

[0087] Please continue to refer to Figure 2 、 Figures 10 to 15 , in some embodiments, the power supply signal line PVEE further includes a second power supply signal line PVEE2 that extends along the second direction and is arranged along the first direction. The display panel 1 may include multiple second power supply signal lines PVEE2, and the multiple second power supply signal lines PVEE2 are arranged at intervals in sequence along the first direction. The second power supply signal line PVEE2 is electrically connected to the first power supply signal line PVEE1. The second power supply signal line PVEE2 can provide a first power supply signal for the second electrode of the light-emitting element D.

[0088] Thus, the power supply signal line PVEE includes both a first power supply signal line PVEE1 extending in the first direction and a second power supply signal line PVEE2 extending in the second direction. The second power supply signal line PVEE2 and the first power supply signal line PVEE1 form a grid structure, which helps to improve the wiring uniformity of the power supply signal line PVEE in the display panel 1, thereby improving the signal uniformity of the first power supply signal in the display panel 1, and further improving the display effect.

[0089] It should be noted that in the case where the layout space is sufficient, such as when the pixel size is large, the power supply signal line PVEE can be configured as the first power supply signal line PVEE1 and the second power supply signal line PVEE2. While realizing the grid design of the gate reset signal line Vref1 and the anode reset signal line Vref2, it is also possible to realize the grid layout design of the power supply signal line PVEE, which can further improve the wiring uniformity of the display panel 1 and improve the display effect. In the case where the layout space is limited, such as when the pixel size is small, the power supply signal line PVEE can be configured as the first power supply signal line PVEE1 to realize the grid design of the gate reset signal line Vref1 and the anode reset signal line Vref2 in a limited space, and to realize the layout design of the power supply signal line PVEE, so as to provide three different signals for the display panel 1 respectively, reduce the number of signal lines, thereby reducing the occupied area of the signal lines, which helps to achieve a narrow border.

[0090] The second power supply signal line PVEE2 is located in the display area AA. Among them, along the second direction, the second power supply signal line PVEE2 penetrates the display area AA of the display panel 1. Exemplarily, along the second direction, the length of the second power supply signal line PVEE2 is greater than or equal to the total width of the pixel circuit 100. Another example is that along the second direction, the length of the second power supply signal line PVEE2 is greater than or equal to the width of the display area AA. Thus, setting the second power supply signal line PVEE2 as an overall structure penetrating the display area AA along the second direction helps to improve the distribution uniformity of the second power supply signal line PVEE2 in the display panel 1, thereby helping to improve the distribution uniformity of the power supply signal line PVEE in the display panel 1, and further helping to improve the uniformity of the display panel 1 and improve the display effect.

[0091] Please continue to refer to Figure 2 、 Figures 10 to 15, in some embodiments, the display panel 1 further includes a plurality of signal line groups arranged in a first direction. The number of signal line groups can be set according to the specific requirements of the display panel 1, which is not limited herein. Each signal line group includes a second gate reset signal line Vref12, a second anode reset signal line Vref22, and a second power supply signal line PVEE2. Exemplarily, in the same signal line group, the second gate reset signal line Vref12, the second anode reset signal line Vref22, and the second power supply signal line PVEE2 are arranged in sequence in the first direction. In another example, the second anode reset signal line Vref22, the second gate reset signal line Vref12, and the second power supply signal line PVEE2 are arranged in sequence in the first direction. It should be noted that in the same signal line group, the second gate reset signal line Vref12, the second anode reset signal line Vref22, and the second power supply signal line PVEE2 can be freely arranged in the first direction according to requirements. Here, all are exemplary descriptions and not overly limited. In this way, taking a second gate reset signal line Vref12, a second anode reset signal line Vref22, and a second power supply signal line PVEE2 as a signal line group and arranging multiple signal line groups in the first direction helps to improve the distribution uniformity of the second gate reset signal, the second anode reset signal line Vref22, and the second power supply signal line PVEE2 in the display panel 1 respectively, thereby improving the overall signal uniformity of the display panel 1 and further improving the display effect.

[0092] Please continue to refer to Figure 2 , Figure 10 and Figure 15 , in some embodiments, the first sub-segment Vref110 overlaps with the second power supply signal line PVEE2 in a third direction. The first sub-segment Vref110 can overlap with at least one second power supply signal line PVEE2 in the third direction. For example, the first sub-segment Vref110 can overlap with one second power supply signal line PVEE2 in the third direction; or, the first sub-segment Vref110 can overlap with two second power supply signal lines PVEE2 in the third direction; or, the first sub-segment Vref110 can overlap with three or more second power supply signal lines PVEE2 in the third direction, which is not limited herein.

[0093] A plurality of first sub-segments Vref110 arranged along a second direction have the same overlapping second power supply signal line PVEE2. Exemplarily, a plurality of first sub-segments Vref110 arranged along the second direction and having the same center point in the second direction have the same overlapping second power supply signal line PVEE2. For example, a plurality of first sub-segments Vref110 arranged along the second direction and having the same center point in the second direction may overlap with the same second power supply signal line PVEE2, or may overlap with the same plurality of second anode reset signal lines Vref22, which is not limited herein. Taking Figure 2 、 Figure 10 and Figure 15 the shown display panel 1 as an example, the pixel circuits 100 in the display panel 1 are arranged in an array, and the second direction is the row direction of the pixel circuits 100; among them, a plurality of first sub-segments Vref110 arranged along the second direction and having the same center point in the second direction, that is, a plurality of first sub-segments Vref110 arranged in the same row, have the same overlapping second power supply signal line PVEE2.

[0094] A plurality of first sub-segments Vref110 arranged along a first direction have different overlapping second power supply signal lines PVEE2. Exemplarily, a plurality of first sub-segments Vref110 arranged along the first direction have completely different overlapping second power supply signal lines PVEE2. For example, a plurality of first sub-segments Vref110 arranged along the first direction respectively overlap with a second power supply signal line PVEE2, and the overlapping second power supply signal lines PVEE2 of each first sub-segment Vref110 are different. Another exemplarily, a plurality of first sub-segments Vref110 arranged along the first direction have partially different overlapping second power supply signal lines PVEE2. For example, a plurality of first sub-segments Vref110 arranged along the first direction respectively overlap with two second power supply signal lines PVEE2; and among adjacent two first sub-segments Vref110, one overlapping second power supply signal line PVEE2 is the same, and the remaining second power supply signal lines PVEE2 are different.

[0095] In the above embodiments, the first sub-segment Vref110 and the second power supply signal line PVEE2 overlap in a third direction; a plurality of first sub-segments Vref110 arranged along the second direction have the same overlapping second power supply signal line PVEE2; a plurality of first sub-segments Vref110 arranged along the first direction have different overlapping second power supply signal lines PVEE2; with such a setting, it is beneficial to reduce the planar occupation area of the first sub-segment Vref110 and the second power supply signal line PVEE2 in the display panel 1, thereby being beneficial to reducing the planar occupation area of the gate reset signal line Vref1 and the power supply signal line PVEE in the display panel 1, and further being beneficial to increasing the spatial density of the signal lines, improving the pixel density, and further improving the display effect.

[0096] Please continue to refer toFigure 2 , Figure 10 and Figure 15 , in some embodiments, the second sub-segment Vref210 overlaps with the second power supply signal line PVEE2 in the third direction. The second sub-segment Vref210 may overlap with at least one second power supply signal line PVEE2 in the third direction. For example, the second sub-segment Vref210 may overlap with one second power supply signal line PVEE2 in the third direction; or, the second sub-segment Vref210 may overlap with two second power supply signal lines PVEE2 in the third direction; or, the second sub-segment Vref210 may overlap with three or more second power supply signal lines PVEE2 in the third direction, which is not limited herein.

[0097] For multiple second sub-segments Vref210 arranged along the second direction, the overlapping second power supply signal lines PVEE2 are the same. Exemplarily, for multiple second sub-segments Vref210 arranged along the second direction and having the same center point in the second direction, the overlapping second power supply signal lines PVEE2 are the same. For example, for multiple second sub-segments Vref210 arranged along the second direction and having the same center point in the second direction, they may overlap with the same second power supply signal line PVEE2, or may overlap with the same multiple second power supply signal lines PVEE2, which is not limited herein. Taking Figure 2 , Figure 10 and Figure 15 shown display panel 1 as an example, the pixel circuits 100 in the display panel 1 are arranged in an array, and the second direction is the row direction of the pixel circuits 100; among them, for multiple second sub-segments Vref210 arranged along the second direction and having the same center point in the second direction, that is, multiple second sub-segments Vref210 arranged in the same row, the overlapping second power supply signal lines PVEE2 are the same.

[0098] For multiple second sub-segments Vref210 arranged along the first direction, the overlapping second power supply signal lines PVEE2 are different. Exemplarily, for multiple second sub-segments Vref210 arranged along the first direction, the overlapping second power supply signal lines PVEE2 are completely different. For example, for multiple second sub-segments Vref210 arranged along the first direction, each overlaps with one second power supply signal line PVEE2, and the second power supply signal lines PVEE2 overlapped by each second sub-segment Vref210 are different. Another exemplarily, for multiple second sub-segments Vref210 arranged along the first direction, the overlapping second power supply signal lines PVEE2 are partially different. For example, for multiple second sub-segments Vref210 arranged along the first direction, each overlaps with two second power supply signal lines PVEE2; and among adjacent two second sub-segments Vref210, one overlapping second power supply signal line PVEE2 is the same, and the remaining second power supply signal lines PVEE2 are different.

[0099] In the embodiments of the present application, the second sub-segment Vref210 overlaps with the second power supply signal line PVEE2 in the third direction; for multiple second sub-segments Vref210 arranged along the second direction, the overlapping second power supply signal line PVEE2 is the same; for multiple second sub-segments Vref210 arranged along the first direction, the overlapping second power supply signal line PVEE2 is different; with such an arrangement, it is beneficial to reduce the planar occupation area of the second sub-segment Vref210 and the second power supply signal line PVEE2 in the display panel 1, thereby being beneficial to reducing the planar occupation area of the anode reset signal line Vref2 and the power supply signal line PVEE in the display panel 1, and further being beneficial to increasing the spatial density of the signal lines, improving the pixel density, and further improving the display effect.

[0100] Please continue to refer to Figure 1 and Figure 2 , in some embodiments, the pixel circuits 100 in the display panel 1 are arranged in an array. Exemplarily, as Figure 1 and Figure 2 shown, the column direction of the pixel circuit 100 is the first direction, and the row direction of the pixel circuit 100 is the second direction.

[0101] Along the first direction, in the same column of pixel circuits 100, the number of pixel circuits 100 is N10; the number of the first sub-segments Vref110 corresponding to this column of pixel circuits 100 is N11, and the number of the second sub-segments Vref210 is N12. Among them, N10 ≥ N11 + N12, that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is greater than or equal to the total number of the corresponding first sub-segments Vref110 and second sub-segments Vref210. Among them, N10, N11, and N12 are all positive integers, then N10 > N11, and N10 > N12; that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is greater than the number of the corresponding first sub-segments Vref110, and the number of pixel circuits 100 in the same column of pixel circuits 100 is greater than the number of the corresponding second sub-segments Vref210.

[0102] In the same column of pixel circuits 100, at least some of the pixel circuits 100 are correspondingly provided with at least one first sub-segment Vref110 and at least one second sub-segment Vref210. Exemplarily, N10 = N11 + N12; that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is equal to the total number of the corresponding first sub-segments Vref110 and second sub-segments Vref210; for example, in the same column of pixel circuits 100, some of the pixel circuits 100 are respectively correspondingly provided with one first sub-segment Vref110, and the remaining pixel circuits 100 are respectively correspondingly provided with one second sub-segment Vref210.

[0103] Exemplarily, N10 = N11 + N12, and N11 = N12; that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is equal to the total number of the corresponding first sub-segment Vref110 and the second sub-segment Vref210, and the number of the first sub-segment Vref110 is the same as the number of the second sub-segment Vref210. Exemplarily, in the same column of pixel circuits 100, the first sub-segment Vref110 and the second sub-segment Vref210 are alternately arranged. Among them, in any two adjacent pixel circuits 100, one pixel circuit 100 is correspondingly provided with a first sub-segment Vref110, and the other pixel circuit 100 is correspondingly provided with a second sub-segment Vref210. With such an arrangement, the distribution uniformity of the first sub-segment Vref110 is relatively good, and the distribution uniformity of the second sub-segment Vref210 is relatively good, which is beneficial to improving the signal uniformity and the display effect.

[0104] In another example, N10 > N11 + N12; for example, in the same column of pixel circuits 100, for some pixel circuits 100, the first sub-segment Vref110 can be set, or the second sub-segment Vref210 can be set; for the remaining pixel circuits 100, neither the first sub-segment Vref110 nor the second sub-segment Vref210 is set, and for the remaining pixel circuits 100, signal lines for transmitting other signals can be arranged. With such an arrangement, while improving the display effect, the requirement of arranging signal lines with different functions in a limited film layer can be taken into account.

[0105] In the embodiments of the present application, the first sub-segment Vref110 corresponding to the pixel circuit 100 can be understood as that there is an overlap between the pixel circuit 100 and the first sub-segment Vref110 in the third direction; the second sub-segment Vref210 corresponding to the pixel circuit 100 can be understood as that there is an overlap between the pixel circuit 100 and the second sub-segment Vref210 in the third direction.

[0106] Please continue to refer to Figure 1 and Figure 2 , in some embodiments, along the second direction, in the same row of pixel circuits 100, the number of pixel circuits 100 is N20, the number of the first gate reset signal lines Vref11 corresponding to the pixel circuits 100 in this row is N21, the number of the first anode reset signal lines Vref21 is N22, and the number of the first power supply signal lines PVEE1 is N23. Among them, N20 ≥ N21, N20 ≥ N22, N20 ≥ N23, and N20, N21, N22, and N23 are all positive integers.

[0107] Exemplarily, N20 > N21, N20 > N22, N20 > N23; that is, the number of pixel circuits 100 in the same row of pixel circuits 100 is greater than the corresponding first gate reset signal line Vref11, the number of pixel circuits 100 in the same row of pixel circuits 100 is equal to the number of the corresponding first anode reset signal line Vref21, and the number of pixel circuits 100 in the same row of pixel circuits 100 is equal to the number of the corresponding first power supply signal line PVEE1.

[0108] For example, in each row of pixel circuits 100, some pixel circuits 100 are correspondingly provided with the first gate reset signal line Vref11; the remaining pixel circuits 100 are not provided with the first gate reset signal line Vref11, and the first anode reset signal line Vref21 and / or the first power supply signal line PVEE1 can be arranged. Also, in each row of pixel circuits 100, some pixel circuits 100 are correspondingly provided with the first anode reset signal line Vref21; the remaining pixel circuits 100 are not provided with the first anode reset signal line Vref21, and the first gate reset signal line Vref11 and / or the first power supply signal line PVEE1 can be arranged. Again, in each row of pixel circuits 100, some pixel circuits 100 are correspondingly provided with the first power supply signal line PVEE1; the remaining pixel circuits 100 are not provided with the first power supply signal line PVEE1, and the first gate reset signal line Vref11 and / or the first anode reset signal line Vref21 can be arranged.

[0109] With such a setting, the distribution uniformity of the first gate reset signal line Vref11 is relatively good, the distribution uniformity of the first anode reset signal line Vref21 is relatively good, and the distribution uniformity of the first power supply signal line PVEE1 is relatively good, which is beneficial to improving the signal uniformity, enhancing the display effect, and also taking into account the requirement of arranging different functional signal lines within a limited film layer.

[0110] Please continue to refer to Figure 1 and Figure 2 , in some embodiments, N21 = N22 = N23, N20 ≥ N21 + N23; that is, N20 > N21 = N22 = N23. That is to say, the number of the first gate reset signal line Vref11, the number of the first anode reset signal line Vref21, and the number of the first power supply signal line PVEE1 are the same, and the number of pixel circuits 100 in the same row of pixel circuits 100 is greater than the number of the corresponding first gate reset signal line Vref11.

[0111] Exemplarily, N20 = N21 + N23; for example, in any two adjacent columns of pixel circuits 100, one column of pixel circuits 100 is correspondingly provided with a first gate reset signal line Vref11 and a first anode reset signal line Vref21, and the other column of pixel circuits 100 is correspondingly provided with a first power supply signal line PVEE1; wherein, for one column of pixel circuits 100 provided with a first gate reset signal line Vref11 and a first anode reset signal line Vref21, a first sub-segment Vref110 of the first gate reset signal line Vref11 and a second sub-segment Vref210 of the first anode reset signal line Vref21 can be arranged alternately along a first direction. In any two adjacent pixel circuits 100, one pixel circuit 100 is correspondingly provided with a first sub-segment Vref110, and the other pixel circuit 100 is correspondingly provided with a second sub-segment Vref210.

[0112] In another exemplary case, it may further include some columns of pixel circuits 100 that are neither provided with the first gate reset signal line Vref11 nor the first anode reset signal line Vref21, and are not provided with the first power supply signal line PVEE1, that is, N20 > N21 + N23. For these columns of pixel circuits 100, signal lines for transmitting other signals can be arranged. With such an arrangement, while improving the display effect, it can also meet the requirement of arranging signal lines with different functions within a limited film layer.

[0113] Please continue to refer to Figure 1 and Figure 2 , in some embodiments, along the first direction, in the same column of pixel circuits 100, the number of pixel circuits 100 is N30, the number of second gate reset signal lines Vref12 corresponding to this column of pixel circuits 100 is N31, and the number of second anode reset signal lines Vref22 is N32; wherein, N30 ≥ N31, N30 ≥ N32, and N30, N31, and N32 are all positive integers.

[0114] Exemplarily, N30 = N31 = N32; that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is equal to the corresponding second gate reset signal line Vref12, and the number of pixel circuits 100 in the same column of pixel circuits 100 is equal to the number of the corresponding second anode reset signal line Vref22. Among them, the number of pixel circuits 100 in the same column of pixel circuits 100 can be understood as the number of rows of the pixel circuits 100. That is, the number of rows of the pixel circuits 100 is equal to the number of the second gate reset signal lines Vref12, and the number of rows of the pixel circuits 100 is equal to the number of the second anode reset signal lines Vref22. Exemplarily, for each row of pixel circuits 100, a second gate reset signal line Vref12 and a second anode reset signal line Vref22 are respectively provided. With such a setting, the distribution uniformity of the second gate reset signal line Vref12 is relatively good, and the distribution uniformity of the second anode reset signal line Vref22 is relatively good, which is beneficial to improving the signal uniformity and the display effect.

[0115] In another example, N30 > N31, N30 > N32; that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is greater than the corresponding second gate reset signal line Vref12, and the number of pixel circuits 100 in the same column of pixel circuits 100 is greater than the number of the corresponding second anode reset signal line Vref22; or, it can be understood that the number of rows of the pixel circuits 100 is greater than the number of the second gate reset signal lines Vref12, and the number of rows of the pixel circuits 100 is greater than the number of the second anode reset signal lines Vref22. Exemplarily, for some rows of pixel circuits 100, a second gate reset signal line Vref12 and a second anode reset signal line Vref22 are respectively provided; for the remaining rows of pixel circuits 100, neither the second gate reset signal line Vref12 nor the second anode reset signal line Vref22 is provided, and signal lines for transmitting other signals can be arranged. With such a setting, not only the display effect can be improved, but also the requirement of arranging signal lines with different functions in a limited film layer can be taken into account.

[0116] Please continue to refer to Figure 1 and Figure 2 , in some embodiments, the power supply signal line PVEE includes a first power supply signal line PVEE1 and a second power supply signal line PVEE2 that extends along the second direction and is arranged along the first direction. The first power supply signal line PVEE1 and the second power supply signal line PVEE2 can be referred to the foregoing introduction and will not be elaborated here. Among them, the number of the second power supply signal lines PVEE2 is N33, N30 ≥ N33, and N33 are all positive integers.

[0117] Exemplarily, N30 = N33; that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is equal to the corresponding second power supply signal line PVEE2; or, it can be understood that the number of rows of pixel circuits 100 is equal to the number of second power supply signal lines PVEE2. Exemplarily, for each row of pixel circuits 100, a second power supply signal line PVEE2 is respectively provided. With such a setting, the distribution uniformity of the second power supply signal line PVEE2 is relatively good, which is beneficial to improving the signal uniformity and enhancing the display effect.

[0118] In another example, N30 > N33; for example, for some pixel circuits 100, a second power supply signal line PVEE2 is respectively provided; for the remaining pixel circuits 100, no second power supply signal line PVEE2 is provided, and signal lines for transmitting other signals can be arranged. With such a setting, not only can the display effect be improved, but also the requirement of arranging signal lines with different functions in a limited film layer can be taken into account.

[0119] Please continue to refer to Figure 2 , in some embodiments, N31 = N32 = N33; that is, the number of second gate reset signal lines Vref12, the number of second anode reset signal lines Vref22, and the number of second power supply signal lines PVEE2 are the same.

[0120] Exemplarily, N30 = N31 = N32 = N33; that is, the number of pixel circuits 100 in the same column of pixel circuits 100, the number of second gate reset signal lines Vref12, the number of second anode reset signal lines Vref22, and the number of second power supply signal lines PVEE2 are the same. Exemplarily, for each row of pixel circuits 100, a second gate reset signal line Vref12, a second anode reset signal line Vref22, and a second power supply signal line PVEE2 are respectively provided. With such a setting, the distribution uniformity of the second gate reset signal line Vref12 is relatively good, the distribution uniformity of the second anode reset signal line Vref22 is relatively good, and the distribution uniformity of the second power supply signal line PVEE2 is relatively good, which is beneficial to improving the signal uniformity and enhancing the display effect.

[0121] Another exemplary case is N30 > N31 = N32 = N33; that is, the number of second gate reset signal lines Vref12, the number of second anode reset signal lines Vref22, and the number of second power supply signal lines PVEE2 are the same, and the number of pixel circuits 100 in the same column of pixel circuits 100 is greater than the number of second gate reset signal lines Vref12. Exemplarily, in the same column of pixel circuits 100, some pixel circuits 100 are respectively provided with one second gate reset signal line Vref12, one second anode reset signal line Vref22, and one second power supply signal line PVEE2. With such a setting, the distribution uniformity of the second gate reset signal line Vref12 is relatively good, the distribution uniformity of the second anode reset signal line Vref22 is relatively good, and the distribution uniformity of the second power supply signal line PVEE2 is relatively good, which is beneficial to improving the signal uniformity and enhancing the display effect.

[0122] Please continue to refer to Figure 1 and Figure 2 , in some embodiments, the display panel 1 includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103 with different emission colors. Among them, the sub-pixel may include a pixel circuit 100 and a light-emitting element D. Different color sub-pixels can be distinguished based on the different emission colors of different light-emitting elements D. Exemplarily, the light-emitting element D includes an anode, a light-emitting material layer, and a cathode, and the light-emitting element D can emit different color lights based on the different properties of the light-emitting material layer.

[0123] Please continue to refer to Figure 1 and Figure 2 , in some embodiments, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are respectively one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel and are different from each other. With such a setting, the display panel 1 can achieve full-color display. Exemplarily, the first sub-pixel 101 can be a red sub-pixel R, the second sub-pixel 102 can be a blue sub-pixel B, and the color of the third sub-pixel 103 is a green sub-pixel G. In some other embodiments, the first color, the second color, and the third color may also be other colors, which are not limited herein.

[0124] A plurality of first sub-pixels 101 and second sub-pixels 102 form a first virtual quadrilateral. The center of the first sub-pixel 101 is located at the first vertex of the first virtual quadrilateral, and the center of the second sub-pixel 102 is located at the second vertex of the first virtual quadrilateral. The first vertex and the second vertex are alternately arranged at intervals, and the third sub-pixel 103 is located inside the first virtual quadrilateral; a plurality of third sub-pixels 103 form a second virtual quadrilateral, and the centers of the plurality of third sub-pixels 103 are located at the vertices of the second virtual quadrilateral, and the first sub-pixel 101 or the second sub-pixel 102 is located inside the second virtual quadrilateral. Thus, a windmill arrangement is formed, which can achieve a good display effect while being energy-efficient.

[0125] Wherein, the first power signal line PVEE1 overlaps at least with the pixel circuit 100 of the third sub-pixel 103; the first sub-segment Vref110 overlaps at least with the pixel circuit 100 of the first sub-pixel 101, and the second sub-segment Vref210 overlaps at least with the pixel circuit 100 of the second sub-pixel 102; or, the first sub-segment Vref110 overlaps at least with the pixel circuit 100 of the second sub-pixel 102, and the second sub-segment Vref210 overlaps at least with the pixel circuit 100 of the first sub-pixel 101.

[0126] Exemplarily, the first power signal line PVEE1 overlaps at least with the pixel circuit 100 of the green sub-pixel, the first sub-segment Vref110 overlaps at least with the pixel circuit 100 of the red sub-pixel, and the second sub-segment Vref210 overlaps at least with the pixel circuit 100 of the blue sub-pixel. In another example, the first power signal line PVEE1 overlaps at least with the pixel circuit 100 of the green sub-pixel, the first sub-segment Vref110 overlaps at least with the pixel circuit 100 of the blue sub-pixel, and the second sub-segment Vref210 overlaps at least with the pixel circuit 100 of the red sub-pixel.

[0127] In the embodiments of the present application, the third sub-pixels 103 (such as green sub-pixels) can be arranged in a pure color column along the first direction; the first sub-pixels 101 and the second sub-pixels 102 (such as red sub-pixels and blue sub-pixels) can be alternately arranged at intervals along the first direction to form a mixed color column. Correspondingly, the continuously extending first power signal line PVEE1 can overlap with the pixel circuits 100 of the sub-pixels in the pure color column; the first sub-segment Vref110 and the second sub-segment Vref210 arranged at intervals and extending in segments can overlap with the pixel circuits 100 of the sub-pixels in the mixed color column, and the first sub-segment Vref110 and the second sub-segment Vref210 respectively overlap with the pixel circuits 100 of sub-pixels of different colors. With such an arrangement, the signal lines can be arranged according to the arrangement rule of the sub-pixels, reducing the difficulty of arranging the signal lines. It should be noted that in some other embodiments, the corresponding relationship between the arrangement of the signal lines and the arrangement of the sub-pixels can also be other relationships, which are not limited herein.

[0128] Figure 16 This is a schematic cross-sectional structure diagram of a display panel 1 provided by an embodiment of the present application. In some embodiments, the display panel 1 may include a substrate 010, a buffer layer 011, a first active layer 012, a first gate insulating layer 013, a first conductive layer 014, an interlayer dielectric layer 015, a second conductive layer 016, a second gate insulating layer 017, a second active layer 018, a third gate insulating layer 019, a second gate metal layer 020, a passivation layer 021, a third conductive layer 022, a first auxiliary planarization layer 023, a fourth conductive layer 024, a second auxiliary planarization layer 025, a second auxiliary metal layer 026, a planarization layer 027, a reflective electrode layer 028, a light-emitting material layer 029, a counter electrode layer 030, and a packaging layer 031, which are stacked in sequence. Among them, the first conductive layer 014 may be denoted as M1; the second conductive layer 016 may be denoted as MC; the third conductive layer 022 may be denoted as M2; and the fourth conductive layer 24 may be denoted as M3.

[0129] The substrate 010 is configured to support the film layers disposed thereon. The substrate 010 may include a rigid substrate 010, such as glass or a silicon wafer, and may also include a flexible substrate, such as thin glass, stainless steel, polyimide, etc., which is not limited herein. The buffer layer 011 is configured to planarize and passivate the substrate 010 to facilitate the smooth deposition of subsequent functional film layers and avoid the influence of the components in the substrate 010 on the performance of subsequent film layers.

[0130] Both the first active layer 012 and the second active layer 018 are semiconductor layers; exemplarily, the first active layer 012 may be a silicon semiconductor layer, such as a polysilicon (poly-Si) semiconductor layer; the second active layer 018 may be an oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) semiconductor layer.

[0131] The first conductive layer 014, the second conductive layer 016, the second gate metal layer 020, the third conductive layer 022, the fourth conductive layer 024, and the second auxiliary metal layer 026 may all be metal layers, and through patterning, pixel circuits 100, signal lines, and other conductor structures in the display panel 1 are formed. The passivation layer 021 is configured to optimize the electrical performance of the conductor structures it covers.

[0132] The reflective electrode layer 028 may be a composite film layer, such as an indium tin oxide (ITO) / silver (Ag) / ITO layer, and the counter electrode layer 030 may be a relatively thin metal composite layer, such as a magnesium (Mg) / silver (Ag) layer, to improve the light transmittance and facilitate the emission of light generated by the light-emitting material layer 029 in the light-emitting element D. The light-emitting material layer 029 is configured to emit light with a target brightness and a target color based on the photoelectric effect in response to the signals provided by the reflective electrode layer 028 and the counter electrode layer 030 under the drive of the pixel circuit 100, so that the display panel 1 presents a target picture.

[0133] The first gate insulating layer 013, the interlayer dielectric layer 015, the second gate insulating layer 017, the third gate insulating layer 019, and the passivation layer 021 are generally inorganic insulating layers. The first auxiliary planarization layer 023, the second auxiliary planarization layer 025, and the planarization layer 027 are generally organic insulating layers. Through the via holes in the layers, via electrical connection of the corresponding conductor structures can be achieved to form the devices in the pixel circuit 100. The encapsulation layer 031 may include an inorganic layer-organic layer-inorganic layer, thereby realizing the encapsulation function.

[0134] It should be noted that the number and stacking order of the above-mentioned film layers are only for illustration, and the position or order of the film layers can be increased, deleted, or adjusted based on actual needs; the materials of the above-mentioned film layers can also be other materials known to those skilled in the art and can be set based on the requirements of the display panel 1, which is not limited herein.

[0135] Please continue to refer to Figures 1 to 16 , in some embodiments, the first gate reset signal line Vref11 and the second gate reset signal line Vref12 are arranged in different layers. Among them, the first gate reset signal line Vref11 and the second gate reset signal line Vref12 are two signal lines with different extending directions that constitute the gate reset signal line Vref1. These two signal lines with different extending directions are arranged in different layers, that is, the first gate reset signal line Vref11 and the second gate reset signal line Vref12 are respectively located in different film layers, which is beneficial to reducing the layout difficulty of the signal lines. Exemplarily, the first gate reset signal line Vref11 can be located in the third conductive layer 022, and the second gate reset signal line Vref12 can be located in the second conductive layer 016. In another example, the first gate reset signal line Vref11 and the second gate reset signal line Vref12 can also be arranged in other two different conductive layers. For example, the first gate reset signal line Vref11 is located in the second conductive layer 016, and the second gate reset signal line Vref12 is located in the third conductive layer 022, which is not limited herein.

[0136] Please continue to refer to Figures 1 to 16, in some embodiments, the first anode reset signal line Vref21 and the second anode reset signal line Vref22 are arranged on different layers. The first anode reset signal line Vref21 and the second anode reset signal line Vref22 are two signal lines with different extending directions that constitute the anode reset signal line Vref2. These two signal lines with different extending directions are arranged on different layers, that is, the first anode reset signal line Vref21 and the second anode reset signal line Vref22 are respectively located in different film layers, which is beneficial to reducing the difficulty of arranging the signal lines. Exemplarily, the first anode reset signal line Vref21 can be located in the third conductive layer 022, and the second anode reset signal line Vref22 can be located in the second conductive layer 016. In another example, the first anode reset signal line Vref21 and the second anode reset signal line Vref22 can also be arranged in two other different conductive layers. For example, the first anode reset signal line Vref21 is located in the second conductive layer 016, and the second anode reset signal line Vref22 is located in the third conductive layer 022, which is not limited herein.

[0137] Please continue to refer to Figures 1 to 16 , in some embodiments, the first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power supply signal line PVEE1 are arranged on the same layer. Among them, the first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power supply signal line PVEE1 are electrically insulated from each other. The second gate reset signal line Vref12 and the second anode reset signal line Vref22 are arranged on the same layer. Among them, the second gate reset signal line Vref12 and the second anode reset signal line Vref22 are electrically insulated from each other. With such an arrangement, it is beneficial to reduce the total number of conductive layers occupied by the gate reset signal line Vref1, the anode reset signal line Vref2, and the power supply signal line PVEE, which is beneficial to realizing the thinning design of the display panel 1; at the same time, by forming at least two different signal lines in the same film layer, it is beneficial to improve the utilization rate of the film layer and the uniformity of film layer wiring, thereby improving the electrical performance uniformity of the display panel 1 and being beneficial to improving the display effect.

[0138] Please continue to refer to Figures 1 to 16, in some embodiments, the display panel 1 further includes a substrate 010, a first conductive layer 014, a second conductive layer 016, a third conductive layer 022, and a fourth conductive layer 24 that are sequentially stacked. Among them, the first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power supply signal line PVEE1 are respectively located in the third conductive layer 022, and the second gate reset signal line Vref12 and the second anode reset signal line Vref22 are respectively located in the second conductive layer 016. In some other embodiments, the first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power supply signal line PVEE1 are respectively located in the second conductive layer 016, and the second gate reset signal line Vref12 and the second anode reset signal line Vref22 are respectively located in the third conductive layer 022. With such an arrangement, by respectively disposing the first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power supply signal line PVEE1 in the third conductive layer 022, and respectively disposing the second gate reset signal line Vref12 and the second anode reset signal line Vref22 in the second conductive layer 016, signal lines extending in the same direction are included in the same conductive layer, and signal lines extending in different directions are located in different conductive layers. While reducing the difficulty of routing layout within the same conductive layer, the film layer occupation is reduced, which is conducive to realizing the thin and light design of the display panel 1.

[0139] Please continue to refer to Figures 1 to 16 , in some embodiments, the first power supply signal line PVEE1 and the second power supply signal line PVEE2 are disposed in different layers. Among them, the first power supply signal line PVEE1 and the second power supply signal line PVEE2 are two signal lines with different extending directions that constitute the power supply signal line PVEE. These two signal lines with different extending directions are disposed in different layers, that is, the first power supply signal line PVEE1 and the second power supply signal line PVEE2 are respectively located in different film layers, which is beneficial to reducing the difficulty of routing the signal lines.

[0140] Please continue to refer to Figures 1 to 16, in some embodiments, the first power supply signal line PVEE1 is disposed on the same layer as the first gate reset signal line Vref11 and the first anode reset signal line Vref21 respectively. Among them, the first power supply signal line PVEE1, the first gate reset signal line Vref11, and the first anode reset signal line Vref21 are electrically insulated from each other. The second power supply signal line PVEE2 is disposed on the same layer as the second gate reset signal line Vref12 and the second anode reset signal line Vref22 respectively. The second power supply signal line PVEE2, the second gate reset signal line Vref12, and the second anode reset signal line Vref22 are electrically insulated from each other. With such a setting, it is beneficial to reduce the total number of conductive layers occupied by the gate reset signal line Vref1, the anode reset signal line Vref2, and the power supply signal line PVEE, which is beneficial to realizing the thinning design of the display panel 1; at the same time, by forming three different signal lines in the same film layer, it is beneficial to improve the utilization rate of the film layer, improve the uniformity of film layer wiring, thereby improving the electrical performance uniformity of the display panel 1, and is beneficial to improving the display effect.

[0141] Please continue to refer to Figures 1 to 16 , in some embodiments, the display panel 1 further includes a substrate 010, a first conductive layer 014, a second conductive layer 016, a third conductive layer 022, and a fourth conductive layer 24 that are sequentially stacked. Among them, the first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power supply signal line PVEE1 are respectively located in the third conductive layer 022; the second gate reset signal line Vref12, the second anode reset signal line Vref22, and the second power supply signal line PVEE2 are respectively located in the second conductive layer 016. In some other embodiments, the first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power supply signal line PVEE1 are respectively located in the second conductive layer 016, and the second gate reset signal line Vref12, the second anode reset signal line Vref22, and the second power supply signal line PVEE2 are respectively located in the third conductive layer 022. With such a setting, the signal lines extending in the same direction are included in the same conductive layer, and the signal lines extending in different directions are located in different conductive layers, which reduces the difficulty of routing layout in the same conductive layer and reduces the film layer occupation, and is beneficial to realizing the thinning design of the display panel 1.

[0142] Please continue to refer to Figures 4 to 16, in some embodiments, the display panel 1 further includes a first connection portion 41. Among them, the first sub-segment Vref110 is electrically connected to the second gate reset signal line Vref12 through the first connection portion 41. Exemplarily, the first connection portion 41 may be a via hole, and the first connection portion 41 may be located at the overlapping position of the first sub-segment Vref110 and the second gate reset signal line Vref12 in the third direction. In this way, by providing the first connection portion 41, the electrical connection between the first sub-segment Vref110 and the second gate reset signal line Vref12 can be realized. In some other embodiments, the first connection portion 41 may also have other shapes, which are not limited herein.

[0143] Please continue to refer to Figures 4 to 16 , in some embodiments, the display panel 1 further includes a second connection portion 42. Among them, the second sub-segment Vref210 is electrically connected to the second anode reset signal line Vref22 through the second connection portion 42. Exemplarily, the second connection portion 42 may be a via hole, and the second connection portion 42 may be located at the overlapping position of the second sub-segment Vref210 and the second anode reset signal line Vref22 in the third direction. In this way, by providing the second connection portion 42, the electrical connection between the second sub-segment Vref210 and the second anode reset signal line Vref22 can be realized. In some other embodiments, the second connection portion 42 may also have other shapes, which are not limited herein.

[0144] Figure 17 is a schematic structural diagram of a display panel 1 provided by an embodiment of the present application. Figure 18 is another schematic structural diagram of a display panel 1 provided by an embodiment of the present application. Combining Figure 17 and Figure 18 , in some embodiments, the display panel 1 includes a display area AA and a non-display area NA, and the non-display area NA is located on the periphery of the display area AA. Among them, the display area AA is used to display a picture, and may further include sub-pixels arranged in an array. The sub-pixels include a pixel driving circuit and a light-emitting element D to realize active light emission control, and further realize picture display. The non-display area NA may at least partially surround the display area AA. For example, the non-display area NA may be arranged in at least part of the space on at least one side of the display area AA, and may be used to arrange peripheral circuits and traces to transmit display signals such as driving signals and power supply signals to the display area AA. Among them, the non-display area NA is not used to display a picture, and may also be called a border area. The smaller the proportion of the non-display area NA in the planar area of the display panel 1, the higher the proportion of the display area AA, and the easier it is to realize a narrow-border full-screen display.

[0145] Among them, the display panel 1 further includes a third power supply signal line PVEE3 located in the non-display area NA. The first power supply signal line PVEE1 is electrically connected to the driver chip (Driver IC) through the third power supply signal line PVEE3. Among them, the driver chip can be used to generate a first power supply signal, and the third power supply signal line PVEE3 can transmit the first power supply signal from the driver chip to provide the first power supply signal for the first electrode of the light-emitting element D. Exemplarily, the third power supply signal line PVEE3 can be a block-shaped or linear structure. Thus, by arranging the third power supply signal line PVEE3 in the non-display area NA, the first power supply signal generated by the driver chip can be received through the third power supply signal line PVEE3 and transmitted to the first electrode of the light-emitting element D through the first power supply signal line PVEE1, thereby realizing the transmission of the first power supply signal from the driver chip to the first electrode of the light-emitting element D, which is beneficial to improving the display uniformity of the display panel 1 and thus beneficial to improving the display effect.

[0146] Figure 19 This is a schematic layout structure diagram of a display panel 1 provided by an embodiment of the present application. Figure 20 This is a schematic layout structure diagram of a display panel 1 provided by an embodiment of the present application. Combining Figures 17 to 20 As shown, in some embodiments, the third power supply signal line PVEE3 includes an electrically connected third sub-segment PVEE31 and a fourth sub-segment PVEE32. The third sub-segment PVEE31 and the fourth sub-segment PVEE32 are respectively located in the non-display areas NA on opposite sides of the display area AA. For example, the third sub-segment PVEE31 and the fourth sub-segment PVEE32 are respectively located in the non-display areas NA on opposite sides of the display area AA along the first direction. Among them, the third sub-segment PVEE31 is arranged close to the driver chip, and the fourth sub-segment PVEE32 is arranged far from the driver chip. Taking Figure 17 and Figure 18 the shown display panel 1 as an example, the driver chip is located on the lower side of the display area AA. Among them, the third sub-segment PVEE31 is located in the non-display area NA close to the lower side of the display area AA, and the fourth sub-segment PVEE32 is located in the non-display area NA close to the upper side of the display area AA. In some other embodiments, the driver chip, the third sub-segment PVEE31, and the fourth sub-segment PVEE32 can be located in the non-display area NA near other positions of the display area AA, which is not limited herein.

[0147] Among them, the first end of the first power supply signal line PVEE1 is electrically connected to the third sub-segment PVEE31. The second end of the first power supply signal line PVEE1 is electrically connected to the fourth sub-segment PVEE32. Exemplarily, the first power supply signal line PVEE1 overlaps with the third sub-segment PVEE31, and the first power supply signal line PVEE1 can be electrically connected to the third sub-segment PVEE31 through a third connection part such as a via hole; the first power supply signal line PVEE1 overlaps with the fourth sub-segment PVEE32, and the first power supply signal line PVEE1 can be electrically connected to the fourth sub-segment PVEE32 through a fourth connection part such as a via hole. In this way, the electrical connection between the first power supply signal line PVEE1 and the third power supply signal line PVEE3 can be realized, so as to realize the transmission of the first power supply signal from the driving chip to the first electrode of the light-emitting element D, which is beneficial to improving the display uniformity of the display panel 1 and thus beneficial to improving the display effect.

[0148] Please continue to refer to Figures 16 to 20 , in some embodiments, the third sub-segment PVEE31 and the fourth sub-segment PVEE32 are arranged in different layers. Among them, the third sub-segment PVEE31 and the fourth sub-segment PVEE32 are two signal lines with different extending directions constituting the third power supply signal line PVEE3, and the third sub-segment PVEE31 and the fourth sub-segment PVEE32 are respectively located in different film layers, which is beneficial to reducing the layout difficulty of the signal lines.

[0149] Exemplarily, the display panel 1 further includes a substrate 010, a first conductive layer 014, a second conductive layer 016, a third conductive layer 022, and a fourth conductive layer 24 that are sequentially stacked; among them, the third sub-segment PVEE31 is located in the third conductive layer 022, and the fourth sub-segment PVEE32 is located in the fourth conductive layer 024. In some other embodiments, the third sub-segment PVEE31 and the fourth sub-segment PVEE32 can be located in other conductive layers of the display panel 1. For example, the third sub-segment PVEE31 can be located in the fourth conductive layer 024, and the fourth sub-segment PVEE32 can be located in the third conductive layer 022, which is not limited herein.

[0150] The third sub-segment PVEE31 is arranged in the same layer as the first power supply signal line PVEE1. With such an arrangement, the first power supply signal line PVEE1 can be directly electrically connected to the third sub-segment PVEE31, so as to realize the electrical connection with the driving chip, which is beneficial to reducing the total number of conductive layers occupied by the third sub-segment PVEE31 and the first power supply signal line PVEE1, that is, reducing the number of power supply signal lines PVEE, which is beneficial to realizing the thin and light design of the display panel 1, beneficial to improving the utilization rate of the film layer, improving the uniformity of film layer wiring, and thus improving the electrical performance uniformity of the display panel 1, which is beneficial to improving the display effect.

[0151] Exemplarily, the third sub-segment PVEE31 and the first power supply signal line PVEE1 are respectively located in the second conductive layer 016M2. In some other embodiments, the third sub-segment PVEE31 and the first power supply signal line PVEE1 may be located in other conductive layers of the display panel 1, which are not limited herein.

[0152] Please continue to refer to Figure 3 , in some embodiments, the pixel circuit 100 may further include a data writing transistor M3, a first light-emitting control transistor M4, a second light-emitting control transistor M5, a threshold compensation transistor M6, and a capacitor Cst. Among them, the gate of the data writing transistor M3 may be electrically connected to the second scan signal line Scan2, and the first pole of the data writing transistor M3 may be electrically connected to the second node N2, the first pole of the driving transistor M0, and the second pole of the first light-emitting control transistor M4 respectively. The signal line may further include a data signal line. Among them, the second pole of the data writing transistor M3 may be electrically connected to the data signal line, and the data signal line may be configured to provide a data signal to the second pole of the data writing transistor M3. The data writing transistor M3 may transmit the data signal to the first pole of the driving transistor M0 in response to the enabling level of the second scan signal.

[0153] The signal line may further include a light-emitting control signal line Emit. Among them, the gates of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 may be electrically connected to the light-emitting control signal line Emit respectively, and the light-emitting control signal line Emit may be configured to provide a light-emitting control signal to the gates of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 respectively. The signal line may further include a fourth power supply signal line PVDD. Among them, the first pole of the first light-emitting control transistor M4 may be electrically connected to the first end of the capacitor Cst and the fourth power supply signal line PVDD respectively, and the fourth power supply signal line PVDD may be configured to provide a second power supply signal to the first pole of the first light-emitting control transistor M4. The first pole of the second light-emitting control transistor M5 is electrically connected to the third node N3, the second pole of the driving transistor M0, and the second pole of the threshold compensation transistor M6 respectively. The second pole of the second light-emitting control transistor M5 is electrically connected to the second pole of the anode reset transistor M2 and the first electrode of the light-emitting element D respectively. The first light-emitting control transistor M4 and the second light-emitting control transistor M5 may control the light-emitting element D to emit light in response to the enabling level of the light-emitting control signal respectively. Among them, the second power supply signal is different from the first power supply signal.

[0154] The gate of the threshold compensation transistor M6 can be electrically connected to the second scan signal line Scan2, and the second scan signal line Scan2 can also be configured to provide a second scan signal to the gate of the threshold compensation transistor M6. The first pole of the threshold compensation transistor M6 is electrically connected to the first node N1, the second pole of the gate reset transistor M1, the gate of the driving transistor M0, and the second end of the capacitor Cst respectively. The threshold compensation transistor M6 can compensate the threshold voltage of the driving transistor M0 in response to the enabling level of the third scan signal.

[0155] Among them, the number of the threshold compensation transistors M6 can be one or more. Exemplarily, the threshold compensation transistor M6 includes a first threshold compensation transistor and a second threshold compensation transistor. Among them, the gates of the first threshold compensation transistor and the second threshold compensation transistor are electrically connected to the second scan signal line Scan2 respectively. The first pole of the first threshold compensation transistor is electrically connected to the first node N1. The second pole of the first threshold compensation transistor is electrically connected to the fifth node N5 and the first pole of the second threshold compensation transistor respectively. The second pole of the second threshold compensation transistor is electrically connected to the third node N3.

[0156] The pixel circuit 100 can include P-type transistors. Alternatively, the pixel circuit 100 can include P-type transistors and N-type transistors. Among them, each transistor in the pixel circuit 100 can be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOS) or a Thin Film Transistor (TFT). Exemplarily, each transistor in the pixel circuit 100 can be a P-type transistor. For example, it can be a PMOS or a PTFT. In another example, the gate reset transistor M1 and the threshold compensation transistor M6 in the pixel circuit 100 can both be N-type transistors. For example, they can be NMOS or NTFT; the driving transistor M0, the anode reset transistor M2, the data writing transistor M3, the first light control transistor M4, and the second light control transistor M5 can all be P-type transistors. For example, they can be PMOS or PTFT.

[0157] The pixel circuit 100 may include low temperature poly-silicon (LTPS) transistors. Alternatively, the pixel circuit 100 may include low temperature poly-silicon transistors and oxide transistors; for example, the oxide may be indium gallium zinc oxide (IGZO). Exemplarily, each transistor in the pixel circuit 100 may be a low temperature poly-silicon transistor. In another embodiment, the gate reset transistor M1 and the threshold compensation transistor M6 in the pixel circuit 100 may both be oxide transistors, and the driving transistor M0, the anode reset transistor M2, the data writing transistor M3, the first light-emitting control transistor M4, and the second light-emitting control transistor M5 may all be low temperature poly-silicon transistors.

[0158] It should be noted that the pixel circuit 100 may be the 7T1C structure provided above, where "T" represents a transistor and "C" represents the capacitor Cst. The pixel circuit 100 may also be any other suitable structure, such as 8T1C, 9T1C, 7T2C, etc., which will not be specifically limited herein.

[0159] Based on the same inventive concept, an embodiment of the present application also provides a display device. Figure 21 The following is a schematic structural diagram of the display device 2 provided by the embodiment of the present application, as Figure 21 shown. The display device 2 includes the display panel 1 in any of the above embodiments. Exemplarily, as Figure 21 shown, the display device 2 includes the display panel 1. Therefore, the display device 2 also has the beneficial effects of the display panel 1 in the above embodiments. The same parts can be understood by referring to the explanation of the display panel 1 above, and will not be repeated hereinafter.

[0160] The display device 2 provided by the embodiment of the present application may be Figure 21 the mobile phone shown in the figure, or any electronic product with a display function, including but not limited to the following categories: television sets, laptop computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, vehicle-mounted displays, industrial control devices, medical display screens, touch interaction terminals, etc. The embodiment of the present application does not make special limitations on this.

[0161] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combinations of these technical features do not conflict, they should all be considered as the scope recorded in this specification.

[0162] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A display panel, characterized in that: include: Pixel circuits, light-emitting elements and signal lines; The pixel circuit includes a driving transistor, a gate reset transistor and an anode reset transistor; the signal line includes a gate reset signal line, an anode reset signal line and a power signal line; the first electrode of the gate reset transistor is electrically connected to the gate reset signal line, the second electrode of the gate reset transistor is electrically connected to the gate of the driving transistor, the first electrode of the anode reset transistor is electrically connected to the anode reset signal line, the second electrode of the anode reset transistor is electrically connected to the first electrode of the light emitting element, and the second electrode of the light emitting element is electrically connected to the power signal line; wherein, The gate reset signal line includes a first gate reset signal line extending along a first direction, and a second gate reset signal line extending along a second direction; wherein the first gate reset signal line includes a plurality of first sub-segments extending along the first direction, and the first sub-segments are electrically connected to the second gate reset signal line; the first direction intersects with the second direction; The anode reset signal line includes a first anode reset signal line extending along a first direction, and a second anode reset signal line extending along a second direction; wherein the first anode reset signal line includes a plurality of second sub-segments extending along the first direction, and the second sub-segments are electrically connected to the second anode reset signal line; The power signal lines include first power signal lines extending along a first direction and arranged along a second direction.

2. The display panel according to claim 1, characterized in that: Along the second direction, the second anode reset signal line and the second gate reset signal line respectively pass through the display area of ​​the display panel; Along the first direction, the first power signal line runs through the display area of ​​the display panel; Along the first direction and the second direction, the first sub-segments and the second sub-segments are alternately arranged.

3. The display panel according to claim 2, characterized in that: Along the second direction, a first power signal line is included between any adjacent first sub-segments and second sub-segments.

4. The display panel according to claim 1, characterized in that: The second gate reset signal lines and the second anode reset signal lines are alternately arranged along the first direction.

5. The display panel according to claim 1, characterized in that: The first sub-segment overlaps with the second gate reset signal line in a third direction; wherein the third direction is perpendicular to the plane where the first direction and the second direction are located; wherein, The plurality of first sub-segments arranged along the second direction have the same overlapping second gate reset signal lines; The plurality of first sub-segments arranged along the first direction have different overlapping second gate reset signal lines.

6. The display panel according to claim 1, characterized in that: The second sub-segment overlaps with the second anode reset signal line in a third direction; wherein the third direction is perpendicular to the plane where the first direction and the second direction are located; wherein, The second anode reset signal lines overlapped by the plurality of second sub-segments arranged along the second direction are the same; The second sub-segments arranged along the first direction have different overlapping second anode reset signal lines.

7. The display panel according to claim 1, characterized in that: The power signal line further includes a second power signal line extending along the second direction and arranged along the first direction, and the first power signal line is electrically connected to the second power signal line; Along the second direction, the second power signal line passes through the display area of ​​the display panel.

8. The display panel according to claim 7, characterized in that: The display panel further includes a plurality of signal line groups arranged along the first direction, and the signal line groups include a second gate reset signal line, a second anode reset signal line, and a second second power supply signal line.

9. The display panel according to claim 7, characterized in that: The first sub-segment and the second sub-segment overlap with the second power signal line in a third direction respectively; wherein the third direction is perpendicular to the plane where the first direction and the second direction are located; wherein, The second power signal lines overlapped by the plurality of first sub-segments arranged along the second direction are the same; the second power signal lines overlapped by the plurality of first sub-segments arranged along the first direction are different; The second power signal lines overlapped by the plurality of second sub-segments arranged along the second direction are the same; the second power signal lines overlapped by the plurality of second sub-segments arranged along the first direction are different.

10. The display panel according to claim 1, characterized in that: Along the first direction, in the same column of pixel circuits, the number of the pixel circuits is N10; the number of the first sub-segments corresponding to the pixel circuits in the column is N11, and the number of the second sub-segments is N12; wherein N10≥N11+N12, and N10, N11 and N12 are all positive integers.

11. The display panel according to claim 1, characterized in that: Along the second direction, in the same row of pixel circuits, the number of the pixel circuits is N20, the number of the first gate reset signal lines corresponding to the pixel circuits in the row is N21, the number of the first anode reset signal lines is N22, and the number of the first power supply signal lines is N23; wherein, N20≥N21, N20≥N22, N20≥N23, and N20, N21, N22 and N23 are all positive integers.

12. The display panel according to claim 11, characterized in that: N21=N22=N23, N20≥N21+N23.

13. The display panel according to claim 1, characterized in that: Along the first direction, in the same column of pixel circuits, the number of the pixel circuits is N30, the number of the second gate reset signal lines corresponding to the pixel circuits in the column is N31, and the number of the second anode reset signal lines is N32; wherein, N30≥N31, N30≥N32, and N30, N31 and N32 are all positive integers.

14. The display panel according to claim 13, characterized in that: The power signal lines include the first power signal lines and second power signal lines extending along the second direction and arranged along the first direction, wherein the number of the second power signal lines is N33, N30≥N33, and N33 is a positive integer.

15. The display panel according to claim 14, characterized in that: N31=N32=N33.

16. The display panel according to any one of claims 1 to 15, characterized in that: The display panel includes a first sub-pixel, a second sub-pixel and a third sub-pixel, each emitting different colors; The first sub-pixel and the second sub-pixel form a first virtual quadrilateral, the center of the first sub-pixel is located at a first vertex of the first virtual quadrilateral, the center of the second sub-pixel is located at a second vertex of the first virtual quadrilateral, the first vertices and the second vertices are alternately arranged, and the third sub-pixel is located inside the first virtual quadrilateral; The third sub-pixels form a second virtual quadrilateral, the centers of the third sub-pixels are located at vertices of the second virtual quadrilateral, and the first sub-pixel or the second sub-pixel is located inside the second virtual quadrilateral; Among them, the first power signal line overlaps with at least the pixel circuit of the third sub-pixel; the first sub-segment overlaps with at least the pixel circuit of the first sub-pixel, and the second sub-segment overlaps with at least the pixel circuit of the second sub-pixel; or, the first sub-segment overlaps with at least the pixel circuit of the second sub-pixel, and the second sub-segment overlaps with at least the pixel circuit of the first sub-pixel.

17. The display panel according to claim 16, characterized in that: The first sub-pixel, the second sub-pixel and the third sub-pixel are respectively one of a red sub-pixel, a green sub-pixel and a blue sub-pixel and are different from each other.

18. The display panel according to any one of claims 1 to 15, characterized in that: The first gate reset signal line and the second gate reset signal line are arranged in different layers; The first anode reset signal line and the second anode reset signal line are arranged in different layers.

19. The display panel according to claim 18, characterized in that: The first gate reset signal line, the first anode reset signal line and the first power supply signal line are arranged on the same layer; The second gate reset signal line and the second anode reset signal line are arranged in the same layer.

20. The display panel according to claim 19, characterized in that: The display panel further includes a substrate, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are stacked in sequence; in; The first gate reset signal line, the first anode reset signal line and the first power signal line are respectively located in the third conductive layer; the second gate reset signal line and the second anode reset signal line are respectively located in the second conductive layer.

21. The display panel according to any one of claims 7 to 9, characterized in that: The first power signal line and the second power signal line are arranged in different layers.

22. The display panel according to claim 21, characterized in that: The first power signal line is disposed on the same layer as the first gate reset signal line and the first anode reset signal line; the second power signal line is disposed on the same layer as the second gate reset signal line and the second anode reset signal line.

23. The display panel according to claim 22, characterized in that: The display panel further includes a substrate, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are stacked in sequence; in; The first gate reset signal line, the first anode reset signal line and the first power signal line are respectively located in the third conductive layer; the second gate reset signal line, the second anode reset signal line and the second power signal line are respectively located in the second conductive layer.

24. The display panel according to any one of claims 1 to 15, characterized in that: The display panel further includes a first connection portion and a second connection portion, wherein the first sub-segment is electrically connected to the second gate reset signal line through the first connection portion, and the second sub-segment is electrically connected to the second anode reset signal line through the second connection portion.

25. The display panel according to any one of claims 1 to 15, characterized in that: The display panel includes a display area and a non-display area, wherein the non-display area is located around the display area; wherein The display panel further includes a third power signal line located in the non-display area, and the first power signal line is electrically connected to the driving chip through the third power signal line.

26. The display panel according to claim 25, characterized in that: The third power signal line includes a third sub-segment and a fourth sub-segment that are electrically connected, the third sub-segment and the fourth sub-segment are respectively located in the non-display area at two opposite sides of the display area, the third sub-segment is arranged close to the driver chip, and the fourth sub-segment is arranged far from the driver chip; wherein, A first end of the first power signal line is electrically connected to the third sub-segment, and a second end of the first power signal line is electrically connected to the fourth sub-segment.

27. The display panel according to claim 26, characterized in that: The third sub-segment and the fourth sub-segment are arranged in different layers; the third sub-segment and the first power signal line are arranged in the same layer.

28. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 27.

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