Display apparatus and method of manufacturing same

Abstract

A display apparatus and a method of manufacturing the same are provided. The display device includes: a first sub-pixel electrode; a spacer including a first opening overlapping the first sub-pixel electrode, where the spacer surrounds the first sub-pixel electrode; a first intermediate layer disposed in the first opening of the spacer and overlapping the first sub-pixel electrode; and a first counter electrode disposed on the first intermediate layer, in which the spacer includes a structure in which an insulating layer, a light absorbing layer, and a bank layer are stacked in this order.

Description

[0001] Cross - reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10 - 2023 - 0176773, filed with the Korean Intellectual Property Office on December 7, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] One or more embodiments relate to the structure of a display device and a method of manufacturing a display device. Background art

[0004] A display device visually displays data. The display device may include a substrate divided into a display area and a peripheral area. The display area typically includes scan lines, data lines, and a plurality of sub - pixels. Each sub - pixel may include a thin - film transistor and a pixel electrode electrically connected to the thin - film transistor. Additionally, an electrode opposite the pixel electrode may be provided in the display area, where the counter electrode is common to all sub - pixels. The peripheral area may include various wirings configured to transfer electrical signals to the display area, a scan driver, a data driver, a controller, a pad portion, etc.

[0005] Display devices are used in a variety of applications, and attempts have been made to design display devices with improved quality. Summary of the invention

[0006] One or more embodiments disclosed herein include a display device having improved resolution and capable of achieving excellent image quality. However, this technical objective is merely an example, and the present disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows and in part will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0008] According to one or more embodiments, a display device includes: a first sub - pixel electrode; an isolation layer including a first opening overlapping the first sub - pixel electrode, wherein, in a plan view, the isolation layer surrounds the first sub - pixel electrode; a first intermediate layer disposed in the first opening of the isolation layer and overlapping the first sub - pixel electrode; and a first counter electrode disposed on the first intermediate layer, wherein the isolation layer includes a structure in which an insulating layer, a light - absorbing layer, and a bank layer are sequentially stacked therein.

[0009] The insulating layer may cover a side surface of the first intermediate layer.

[0010] The insulating layer may cover an edge of the first sub - pixel electrode and contact the first counter electrode.

[0011] The light absorption layer may cover the upper surface of the insulating layer.

[0012] The angle formed by the side surface of the first intermediate layer with respect to the bottom surface of the first intermediate layer may be from about 50° to about 90°.

[0013] The display device may further include: a second sub-pixel electrode adjacent to the first sub-pixel electrode; a second intermediate layer disposed in the second opening of the spacer and overlapping the second sub-pixel electrode; and a second pair of electrodes that may be disposed on the second intermediate layer.

[0014] The first pair of electrodes and the second pair of electrodes may be provided integrally.

[0015] The insulating layer and the light absorption layer may extend from a region overlapping the side surface of the first intermediate layer to a region overlapping the side surface of the second intermediate layer.

[0016] The bank layer may be disposed on the light absorption layer and may fill the step difference formed by the first intermediate layer and the second intermediate layer.

[0017] The light absorption layer may include tantalum molybdenum oxide (MTO) or molybdenum oxide (MoO x )).

[0018] The light absorption layer may have a thickness of about to about .

[0019] The light absorption layer may include silicon carbide (SiC).

[0020] The insulating layer and the bank layer may include different materials from each other.

[0021] The insulating layer may include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), and silicon oxynitride (SiO x N y ).

[0022] The bank layer may include at least one of hexamethyldisiloxane (HMDSO) and an acrylic monomer.

[0023] According to one or more embodiments, a method of manufacturing a display device includes: forming a first sub-pixel electrode and a second sub-pixel electrode adjacent to the first sub-pixel electrode; forming a first intermediate layer on the first sub-pixel electrode and a second intermediate layer on the second sub-pixel electrode; forming a spacer between the first intermediate layer and the second intermediate layer; and forming a first pair of electrodes on the first intermediate layer and a second pair of electrodes on the second intermediate layer, wherein forming the spacer includes: forming an insulating layer covering an edge of the first sub-pixel electrode and an edge of the second sub-pixel electrode; forming a light absorption layer on the insulating layer; and forming a bank layer on the light absorption layer.

[0024] The method may further include: forming a first protective layer on the first intermediate layer and a second protective layer on the second intermediate layer between forming the first intermediate layer and the second intermediate layer and forming the spacer.

[0025] Forming the spacer may include: depositing the insulating layer to cover from an upper surface of the first protective layer through side surfaces of the first intermediate layer and the second intermediate layer to an upper surface of the second protective layer; and depositing the light absorption layer on an upper surface of the insulating layer to overlap with the upper surface of the first protective layer, side surfaces of the first intermediate layer, side surfaces of the second intermediate layer, and the upper surface of the second protective layer.

[0026] Forming the spacer may include: forming a photoresist on the light absorption layer between the first intermediate layer and the second intermediate layer; etching portions of the insulating layer that do not overlap with the photoresist and portions of the light absorption layer that do not overlap with the photoresist; and removing the photoresist.

[0027] The bank layer may be disposed on the light absorption layer and formed to fill a step difference between the first intermediate layer and the second intermediate layer.

[0028] The method may further include: removing the first protective layer and the second protective layer between forming the spacer and forming the first pair of electrodes and the second pair of electrodes.

[0029] The first pair of electrodes and the second pair of electrodes may be integrally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0031] Figure 1 is a schematic perspective view of a display device according to an embodiment of the present disclosure.

[0032] Figure 2A and Figure 2B are schematic equivalent circuit diagrams of a light-emitting diode corresponding to one of a plurality of sub-pixels of a display device and a sub-pixel circuit electrically connected to the corresponding light-emitting diode according to various embodiments of the present disclosure.

[0033] Figure 3 is a schematic plan view of a part of a display device according to an embodiment of the present disclosure.

[0034] Figure 4 is a schematic cross-sectional view of a part of a display device according to an embodiment of the present disclosure.

[0035] Figure 5 is a cross-sectional view of a stacked structure of light-emitting diodes according to an embodiment of the present disclosure.

[0036] Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D 、 Figure 6E 、 Figure 6F and Figure 6G are schematic cross-sectional views showing structures formed during a process of manufacturing a display device according to an embodiment of the present disclosure. Detailed Description of the Embodiments

[0037] Embodiments are described in detail below with examples illustrated in the accompanying drawings. In this regard, embodiments according to the present disclosure may have different forms and should not be construed as limited to the detailed description set forth herein. Therefore, only exemplary embodiments are described below to explain aspects of the present disclosure.

[0038] Hereinafter, embodiments will be described with reference to the accompanying drawings, where like reference numerals always refer to like elements and repeated descriptions thereof may be omitted.

[0039] As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items. Throughout the present disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variants thereof.

[0040] Although terms such as “first” and “second” may be used to describe various components, such components are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another.

[0041] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0042] It will be understood that as used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated feature or component, but do not preclude the addition of one or more other features or components.

[0043] It will also be understood that a layer, region or element referred to as being "on" another layer, region or element can be directly or indirectly on the other layer, region or element. That is, for example, there can be intervening layers, regions or elements.

[0044] For ease of illustration or depiction, the dimensions of elements in the drawings can be exaggerated or reduced. As an example, the dimensions and thicknesses of each element shown in the drawings can be arbitrarily represented and thus, the present disclosure is not necessarily limited thereto.

[0045] Unless otherwise explicitly stated, embodiments described herein as having a specific process order can be performed in an order different from the described order. As an example, two consecutively described processes can be performed simultaneously or in the reverse order.

[0046] A layer, region or element described herein as being "connected" to another layer, region or element can be "directly connected" to the other layer, region or element or can be "indirectly connected" to the other layer, region or element with one or more other layers, regions or elements therebetween. For example, a layer, region or element referred to herein as being "electrically connected" to another layer, region or element can be "directly electrically connected" to the other layer, region or element or can be "indirectly electrically connected" to the other layer, region or element with one or more other layers, regions or elements disposed therebetween.

[0047] Figure 1 is a schematic perspective view of a display device according to an embodiment of the present disclosure.

[0048] Reference Figure 1 , the display device 1 can include a display area DA and a non-display area NDA outside the display area DA. The display area DA can display an image using first sub-pixels P1, second sub-pixels P2 and third sub-pixels P3 provided in the display area DA. The non-display area NDA is outside the display area DA and does not display an image. The non-display area NDA can completely surround the display area DA. The non-display area NDA can include drivers and the like configured to supply an electrical signal or power to the display area DA. The non-display area NDA can also include pads, which are areas to which an electronic component or a printed circuit board can be electrically connected.

[0049] Figure 1An embodiment is shown in which the display area DA is a polygon (e.g., a quadrilateral) having a length in the x direction that is less than its length in the y direction. Alternatively, in another embodiment, the display area DA of the display device 1 may be a polygon (e.g., a quadrilateral), where the length of the polygon (e.g., a quadrilateral) in the y direction is less than the length of the polygon (e.g., a quadrilateral) in the x direction. More generally, the embodiments are not limited to making the display area DA approximately quadrilateral. As another embodiment, the display area DA may have various shapes, such as an N-sided polygon (where N is a natural number of 3 or greater), a circle, or an ellipse. In addition, although Figure 1 the display area DA is shown having a shape in which each corner of the display area DA includes a vertex where a straight line meets a straight line, in other embodiments, the display area DA may have rounded corners.

[0050] The display device 1 can be used in various products including televisions, notebook computers, monitors, billboards, Internet of Things (IoT) devices, and portable electronic devices including mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic notepads, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs). Additionally, the display device 1 can be used in wearable devices including smartwatches, wrist phones, glasses-type displays, and head-mounted displays (HMDs). Additionally, in some embodiments, the display device 1 can be employed in a display screen in an instrument panel for an automobile, a central instrument panel for an automobile, a central information display (CID) provided on a dashboard, an in-vehicle mirror display replacing a side mirror of an automobile, and a display for an entertainment system for a passenger in a rear seat of an automobile provided on the rear side of a front seat.

[0051] Figure 2A and Figure 2B are schematic equivalent circuit diagrams of a light-emitting diode corresponding to one of a plurality of sub-pixels of a display device and a sub-pixel circuit electrically connected to the corresponding light-emitting diode.

[0052] Referring to Figure 2A , the light-emitting diode ED can be electrically connected to the sub-pixel circuit PC, and the sub-pixel circuit PC can include a first transistor T1, a second transistor T2, and a storage capacitor Cst. A sub-pixel electrode (e.g., an anode) of the light-emitting diode ED can be electrically connected to the first transistor T1, and a counter electrode (e.g., a cathode) of the light-emitting diode ED can be electrically connected to the auxiliary line VSL, and a voltage corresponding to the common voltage ELVSS can be received through the auxiliary line VSL.

[0053] When a data signal Dm is input through a data line DL, a second transistor T2 is configured to transfer the data signal Dm to a first transistor T1 in accordance with a scan signal Sgw input through a scan line GW.

[0054] A storage capacitor Cst may be connected to the second transistor T2 and a driving voltage line PL, and may be configured to store a voltage corresponding to a difference between a voltage from the second transistor T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0055] The first transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and may be configured to control a driving current I in accordance with the voltage stored in the storage capacitor Cst d . The driving current I d flows from the driving voltage line PL to a light-emitting diode ED. The light-emitting diode ED may be configured to emit light having a preset luminance corresponding to the driving current I d .

[0056] Although Figure 2A the illustrated example embodiment shows a sub-pixel circuit PC including two transistors and one storage capacitor, the embodiment is not limited thereto. For example, Figure 2B an embodiment is illustrated in which the sub-pixel circuit PC includes seven transistors and two capacitors.

[0057] Referring Figure 2B , the sub-pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a storage capacitor Cst, and a boosting capacitor Cbt. (In another embodiment similar to the embodiment of Figure 2B , the sub-pixel circuit PC may not include the boosting capacitor Cbt.) Figure 2B The pixel circuit PC of

[0058] is connected to a sub-pixel electrode (e.g., an anode) of the light-emitting diode ED. Specifically, the first transistor T1 may be electrically connected to the sub-pixel electrode of the light-emitting diode ED through the sixth transistor T6, and a counter electrode (e.g., a cathode) of the light-emitting diode ED may be electrically connected to an auxiliary line VSL, and may receive a voltage corresponding to a common voltage ELVSS through the auxiliary line VSL.Some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be n-channel metal-oxide-semiconductor (NMOS) field-effect transistors (n-channel MOSFETs, i.e., NMOSFETs), and the remaining transistors may be p-channel metal-oxide-semiconductor (PMOS) field-effect transistors (p-channel MOSFETs, i.e., PMOSFETs). In Figure 2B the illustrated embodiment, the third transistor T3 and the fourth transistor T4 may be n-channel MOSFETs, and the remaining transistors may be p-channel MOSFETs. As an example, the third transistor T3 and the fourth transistor T4 may be n-channel MOSFETs including an oxide-based semiconductor material, and the remaining transistors may be p-channel MOSFETs including a silicon-based semiconductor material. In another embodiment, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be n-channel MOSFETs, and the remaining transistors may be p-channel MOSFETs.

[0059] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the storage capacitor Cst, and the boost capacitor Cbt may be connected to signal lines. The signal lines may include an emission control line EM, a compensation gate line GC, a first initialization gate line GI1, a second initialization gate line GI2, and a data line DL. The sub-pixel circuit PC may be electrically connected to one or more voltage lines, e.g., a driving voltage line PL, a first initialization voltage line VL1, and a second initialization voltage line VL2.

[0060] The first transistor T1 may be a driving transistor. The gate electrode of the first transistor T1 may be connected to the storage capacitor Cst, the first electrode of the first transistor T1 may be electrically connected to the driving voltage line PL through the fifth transistor T5, and the second electrode of the first transistor T1 may be electrically connected to the first electrode (e.g., anode) of the light-emitting diode ED through the sixth transistor T6. One of the first electrode and the second electrode of the first transistor T1 may be a source electrode, and the other may be a drain electrode. The first transistor T1 may be configured to supply a driving current I d to the light-emitting diode ED.

[0061] The second transistor T2 may be a switching transistor. The gate electrode of the second transistor T2 is connected to the scan line GW, the first electrode of the second transistor T2 is connected to the data line DL, and the second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1 and is electrically connected to the driving voltage line PL through the fifth transistor T5. One of the first electrode and the second electrode of the second transistor T2 may be a source electrode, and the other may be a drain electrode. The second transistor T2 may be turned on according to the scan signal Sgw transmitted through the scan line GW, and may perform a switching operation of transmitting the data signal Dm from the data line DL to the first electrode of the first transistor T1.

[0062] The third transistor T3 may be a compensation transistor configured to compensate for the threshold voltage of the first transistor T1. The gate electrode of the third transistor T3 is connected to the compensation gate line GC. The first electrode of the third transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst and the gate electrode of the first transistor T1 through the node connection line 166. The first electrode of the third transistor T3 may also be connected to the fourth transistor T4. The second electrode of the third transistor T3 is connected to the second electrode of the first transistor T1 and is electrically connected to the first electrode (e.g., anode) of the light emitting diode ED through the sixth transistor T6. One of the first electrode and the second electrode of the third transistor T3 may be a source electrode, and the other may be a drain electrode.

[0063] The third transistor T3 is turned on according to the compensation signal Sgc transmitted through the compensation gate line GC, and when turned on, the third transistor T3 diode-connects the first transistor T1 by electrically connecting the gate electrode and the second electrode (e.g., drain electrode) of the first transistor T1.

[0064] The fourth transistor T4 may be a first initialization transistor configured to initialize the gate electrode of the first transistor T1. The gate electrode of the fourth transistor T4 is connected to the first initialization gate line GI1. The first electrode of the fourth transistor T4 is connected to the first initialization voltage line VL1. The second electrode of the fourth transistor T4 may be connected to the lower electrode CE1 of the storage capacitor Cst, the first electrode of the third transistor T3, and the gate electrode of the first transistor T1. One of the first electrode and the second electrode of the fourth transistor T4 may be a source electrode, and the other may be a drain electrode. The fourth transistor T4 may be turned on according to the first initialization signal Sgi1 transmitted through the first initialization gate line GI1, and may perform an initialization operation of initializing the voltage of the gate electrode of the first transistor T1 by transmitting the first initialization voltage Vint to the gate electrode of the first transistor T1.

[0065] The fifth transistor T5 may be an operation control transistor. The gate electrode of the fifth transistor T5 is connected to the emission control line EM, the first electrode of the fifth transistor T5 is connected to the driving voltage line PL, and the second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1 and the second electrode of the second transistor T2. One of the first electrode and the second electrode of the fifth transistor T5 may be a source electrode, and the other may be a drain electrode.

[0066] The sixth transistor T6 may be an emission control transistor. The gate electrode of the sixth transistor T6 is connected to the emission control line EM, the first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1 and the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the second electrode of the seventh transistor T7 and the first electrode (e.g., anode) of the light-emitting diode ED. One of the first electrode and the second electrode of the sixth transistor T6 may be a source electrode, and the other may be a drain electrode.

[0067] The fifth transistor T5 and the sixth transistor T6 may be simultaneously turned on according to the emission control signal Sem transmitted through the emission control line EM. When the fifth transistor T5 and the sixth transistor T6 are turned on, the driving voltage ELVDD is transmitted to the light-emitting diode ED, and the driving current I d flows through the light-emitting diode ED.

[0068] The seventh transistor T7 may be a second initialization transistor configured to initialize the first electrode (e.g., anode) of the light-emitting diode ED. The gate electrode of the seventh transistor T7 is connected to the second initialization gate line GI2. The first electrode of the seventh transistor T7 is connected to the second initialization voltage line VL2. The second electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6 and the first electrode (e.g., anode) of the light-emitting diode ED. The seventh transistor T7 may be turned on according to the second initialization signal Sgi2 transmitted through the second initialization gate line GI2, and the seventh transistor may be configured to initialize the first electrode of the light-emitting diode ED by transmitting the second initialization voltage Vaint from the second initialization voltage line VL2 to the first electrode (e.g., anode) of the light-emitting diode ED.

[0069] In an embodiment, the second initialization voltage line VL2 may be the next scan line. As an example, the seventh transistor T7 connected to the sub-pixel circuit PC and disposed in the i-th row (i is a natural number) of the second initialization gate line GI2 may correspond to the scan line GW of the sub-pixel circuit PC disposed in the i + 1-th row. In another embodiment, the second initialization voltage line VL2 may be the emission control line EM. As an example, the emission control line EM may be electrically connected to the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0070] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2. The lower electrode CE1 of the storage capacitor Cst is connected to the gate electrode of the first transistor T1, and the upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL. The storage capacitor Cst can be configured to store a charge corresponding to the difference between the voltage of the gate electrode of the first transistor T1 and the driving voltage ELVDD.

[0071] The boosting capacitor Cbt includes a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 can be connected to the scanning line GW and the gate electrode of the second transistor T2, and the fourth electrode CE4 can be connected to the node connection line 166 and the first electrode of the third transistor T3. When the scanning signal Sgw supplied to the scanning line GW is a cut-off voltage, the boosting capacitor Cbt can boost the voltage of the first node N1. When the voltage of the first node N1 is boosted, the first transistor T1 can cause the driving current I d to be completely cut off, such that the light-emitting diode ED can clearly express a black gradation.

[0072] The first node N1 can be a region where the gate electrode of the first transistor T1, the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the fourth electrode CE4 of the boosting capacitor Cbt are connected to each other.

[0073] In Figure 2B the embodiment, the third transistor T3 and the fourth transistor T4 are n-channel MOSFETs, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are p-channel MOSFETs. The first transistor T1 that directly affects the brightness of the display device 1 of the display image can be configured to include a semiconductor layer containing polysilicon having high reliability, and thus, a high-resolution display device can be achieved by this configuration.

[0074] Although Figure 2B the embodiment provides an example of the sub-pixel circuit PC in which some transistors are NMOSFETs and the remaining transistors are PMOSFETs, the embodiment is not limited thereto. In another embodiment, the sub-pixel circuit PC includes three transistors, and all of the three transistors can be NMOSFETs. However, various modifications can be made.

[0075] Figure 3 is a schematic plan view of a part of a display device according to an embodiment of the present disclosure. Specifically, Figure 3 is Figure 1 an enlarged schematic plan view of an embodiment of the region A in the display area DA of the display device 1 shown in

[0076] Refer to Figure 3, multiple sub-pixels can be disposed in a display area DA of a display device 1. The multiple sub-pixels can include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 can be sub-pixels configured to emit lights of different colors. As an example, the first sub-pixel P1 can be a pixel configured to emit red light, the second sub-pixel P2 can be a pixel configured to emit blue light, and the third sub-pixel P3 can be a pixel configured to emit green light. The red light can be light in a wavelength band of approximately 580 nm to approximately 780 nm, the blue light can be light in a wavelength band of approximately 400 nm to approximately 495 nm, and the green light can be light in a wavelength band of approximately 495 nm to approximately 580 nm.

[0077] Each of the multiple sub-pixels can include an organic light-emitting diode, and the organic light-emitting diode can include a sub-pixel electrode, a counter electrode, and an intermediate layer between the sub-pixel electrode and the counter electrode. Accordingly, the first sub-pixel P1 can include a first sub-pixel electrode 1210, the second sub-pixel P2 can include a second sub-pixel electrode 2210, and the third sub-pixel P3 can include a third sub-pixel electrode 3210. The first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210 can be separated from each other in a plane. In this specification, "in a plane" refers to a plane viewed from a direction perpendicular to a substrate 100 (see Figure 4 ). That is, "A and B are separated from each other in a plane" means "when viewed from a direction perpendicular to the substrate 100, A and B are separated or detached from each other".

[0078] The spacer SP can surround each of the multiple sub-pixels. That is, the spacer SP can surround the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210. Although described in more detail with reference to Figure 4 , the spacer SP can include a structure in which an insulating layer 115, a light absorption layer 117, and a bank layer 119 are sequentially stacked, and the insulating layer 115 of the spacer SP can cover an edge or a periphery of each of the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210. Specifically, the spacer SP can include a plurality of openings in which organic light-emitting diodes of sub-pixels can be disposed. As an example, the spacer SP can include a first opening OP1 overlapping with the first sub-pixel electrode 1210, a second opening OP2 overlapping with the second sub-pixel electrode 2210, and a third opening OP3 overlapping with the third sub-pixel electrode 3210. Although in Figure 3Although not shown in the figure, an emission layer configured to emit light may be separately disposed inside the first opening OP1, the second opening OP2, and the third opening OP3 of the spacer SP, and a counter electrode may be disposed on the emission layer. As described above, a stacked structure including a sub-pixel electrode, an emission layer, and a counter electrode may form an organic light-emitting diode. That is, one opening of the spacer SP may correspond to one organic light-emitting diode and define an emission region.

[0079] When viewed in a direction perpendicular to the substrate 100 (e.g., the z-axis direction) (see Figure 4 ), each of the first opening OP1, the second opening OP2, and the third opening OP3 may have a polygonal shape. Although each of the first opening OP1, the second opening OP2, and the third opening OP3 has a quadrilateral shape in the plan view shown in Figure 3 , the embodiments are not limited thereto. As an example, each of the first opening OP1, the second opening OP2, and the third opening OP3 may have a circular shape or an oval shape in the plan view.

[0080] Figure 4 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure, and Figure 5 is a cross-sectional view of a stacked structure of a light-emitting diode according to an embodiment of the present disclosure.

[0081] Referring to Figure 4 , the display device 1 may include a first sub-pixel region PA1, a second sub-pixel region PA2, and a third sub-pixel region PA3, and include a non-sub-pixel region NPA between adjacent sub-pixel regions. The planar shape of the display device 1 may be the same as the planar shape of the substrate 100. Therefore, when the display device 1 includes the first sub-pixel region PA1, the second sub-pixel region PA2, the third sub-pixel region PA3, and the non-sub-pixel region NPA, the substrate 100 may similarly include the first sub-pixel region PA1, the second sub-pixel region PA2, the third sub-pixel region PA3, and the non-sub-pixel region NPA.

[0082] The sub-pixel circuit PC of the display device 1 may be formed on the substrate 100. The sub-pixel circuit PC may include a first sub-pixel circuit PC1 of the first sub-pixel P1, a second sub-pixel circuit PC2 of the second sub-pixel P2, and a third sub-pixel circuit PC3 of the first sub-pixel P3. Each of the first sub-pixel circuit PC1, the second sub-pixel circuit PC2, and the third sub-pixel circuit PC3 may include the same structure. Each of the first sub-pixel circuit PC1, the second sub-pixel circuit PC2, and the third sub-pixel circuit PC3 may include one or more transistors and a storage capacitor Cst such as those described above with reference to Figure 2A and Figure 2B . Figure 4shows an embodiment in which each of a first sub-pixel circuit PC1, a second sub-pixel circuit PC2, and a third sub-pixel circuit PC3 includes a first transistor T1, a sixth transistor T6, and a storage capacitor Cst that can be connected to operate as described above with reference to Figure 2B the embodiments described.

[0083] The substrate 100 may include glass or a polymer resin. The substrate 100 may have a structure in which a base layer and an inorganic barrier layer are stacked, where the base layer includes a polymer resin. The polymer resin may include polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate, triacetyl cellulose (TAC), cellulose acetate propionate (CAP), etc.

[0084] The buffer layer 101 may be disposed on the upper surface of the substrate 100. The buffer layer 101 may prevent impurities from infiltrating into the overlying semiconductor layer of the transistor. The buffer layer 101 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and may include a single-layer structure or a multi-layer structure including the above inorganic insulating materials.

[0085] The first transistor T1 may include a semiconductor layer A1 and a gate electrode G1, where the semiconductor layer A1 is on the buffer layer 101, and the gate electrode G1 overlaps with the channel region of the first semiconductor layer A1. The semiconductor layer A1 may include a silicon-based semiconductor material, for example, polysilicon. The semiconductor layer A1 may include a channel region, a first region, and a second region, and the first region and the second region are respectively on opposite sides of the channel region. The first region and the second region may be regions including impurities at a concentration higher than the concentration of impurities in the channel region. One of the first region and the second region may correspond to the source region, and the other may correspond to the drain region.

[0086] The sixth transistor T6 may include a semiconductor layer A6 and a gate electrode G6, where the semiconductor layer A6 is on the buffer layer 101, and the gate electrode G6 overlaps with the channel region in the semiconductor layer A6. The semiconductor layer A6 may include a silicon-based semiconductor material, for example, polysilicon. The semiconductor layer A6 may include a channel region, a first region, and a second region, and the first region and the second region are respectively on opposite sides of the channel region. The first region and the second region may be regions including impurities at a concentration higher than the concentration of impurities in the channel region. One of the first region and the second region may correspond to the source region, and the other may correspond to the drain region.

[0087] The gate electrodes G1 and G6 may include a conductive material (e.g., one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti)), and may have a single-layer structure or a multi-layer structure including the above materials. The first gate insulating layer 103 may be disposed under the gate electrodes G1 and G6, wherein the first gate insulating layer 103 is for electrical insulation between the semiconductor layer A1 and the gate electrode G1 and between the semiconductor layer A6 and the gate electrode G6. The first gate insulating layer 103 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and may include a single-layer structure or a multi-layer structure of the above inorganic insulating materials.

[0088] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 that overlap each other. In an embodiment, the lower electrode CE1 of the storage capacitor Cst may include the gate electrode G1, or the gate electrode G1 may include the lower electrode CE1 of the storage capacitor Cst. As an example, the gate electrode G1 and the lower electrode CE1 of the storage capacitor Cst may be integral.

[0089] The first interlayer insulating layer 105 may be disposed between the lower electrode CE1 and the upper electrode CE2 of the storage capacitor Cst. The first interlayer insulating layer 105 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and the first interlayer insulating layer 105 may include a single-layer structure or a multi-layer structure including the above inorganic insulating materials.

[0090] The upper electrode CE2 of the storage capacitor Cst may include a conductive material of a low-resistance material such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and the upper electrode CE2 may have a single-layer structure or a multi-layer structure including the above materials.

[0091] The second interlayer insulating layer 107 may be on the upper electrode CE2 and the first interlayer insulating layer 105. The source electrode S1 and the drain electrode D1 may be disposed on the second interlayer insulating layer 107, and the source electrode S1 and the drain electrode D1 are electrically connected to the semiconductor layer A1 of the first transistor T1. The source electrode S6 and the drain electrode D6 may also be disposed on the second interlayer insulating layer 107, and the source electrode S6 and the drain electrode D6 are electrically connected to the semiconductor layer A6 of the sixth transistor T6. The source electrode S1 and the source electrode S6, and the drain electrode D1 and the drain electrode D6 may include aluminum (Al), copper (Cu), titanium (Ti), and / or another conductive material, and may include a single-layer structure or a multi-layer structure of the above materials.

[0092] The first organic insulating layer 109 may be disposed on the sub-pixel circuit PC. The first organic insulating layer 109 may include an organic insulating material such as acrolein group, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0093] The connection metal CM may be disposed on the first organic insulating layer 109. The connection metal CM may include aluminum (Al), copper (Cu), and / or titanium (Ti), and may include a single-layer structure or a multi-layer structure including the above materials.

[0094] The second organic insulating layer 111 may be disposed between the connection metal CM and the sub-pixel electrode 210. The second organic insulating layer 111 may include an organic insulating material such as acrolein group, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). According to Figure 4 the embodiment shown in, the sub-pixel circuit PC is electrically connected to the sub-pixel electrode 210 through the connection metal CM. Alternatively, the connection metal CM may be omitted, and an organic insulating layer may be located between the sub-pixel circuit PC and the sub-pixel electrode 210. In some other alternative embodiments, three or more organic insulating layers may be located between the sub-pixel circuit PC and the sub-pixel electrode 210, and the sub-pixel circuit PC may be electrically connected to the sub-pixel electrode 210 through a plurality of connection metals.

[0095] The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may respectively include a first light-emitting diode ED1, a second light-emitting diode ED2, and a third light-emitting diode ED3. The first light-emitting diode ED1, the second light-emitting diode ED2, and the third light-emitting diode ED3 respectively electrically connected to the first sub-pixel circuit PC1, the second sub-pixel circuit PC2, and the third sub-pixel circuit PC3 may each have a stacked structure of a sub-pixel electrode 210, an intermediate layer 220, and a counter electrode 230.

[0096] As an example, the first light-emitting diode ED1 may include a first sub-pixel electrode 1210, a first intermediate layer 1220, and a first counter electrode 1230. The first sub-pixel electrode 1210 may be electrically connected to the first sub-pixel circuit PC1. The second light-emitting diode ED2 may include a second sub-pixel electrode 2210, a second intermediate layer 2220, and a second counter electrode 2230. The second sub-pixel electrode 2210 may be electrically connected to the second sub-pixel circuit PC2. The third light-emitting diode ED3 may include a third sub-pixel electrode 3210, a third intermediate layer 3220, and a third counter electrode 3230. The third sub-pixel electrode 3210 may be electrically connected to the third sub-pixel circuit PC3.

[0097] In Figure 4In the example shown, the first pair of electrodes 1230, the second pair of electrodes 2230, and the third pair of electrodes 3230 may be part of an integrated layer or region represented by the counter electrode 230. In other words, the counter electrode 230 may include the first pair of electrodes 1230, the second pair of electrodes 2230, and the third pair of electrodes 3230, and the first pair of electrodes 1230, the second pair of electrodes 2230, and the third pair of electrodes 3230 may be electrically connected to each other.

[0098] The sub-pixel electrode 210 is sometimes used herein to generically refer to any one of the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210. Each sub-pixel electrode 210 may be formed on the second organic insulating layer 111. Each sub-pixel electrode 210 may be a (semi)transparent electrode or a reflective electrode. In the case where the sub-pixel electrode 210 includes a (semi)transparent electrode, the sub-pixel electrode 210 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In the case where the sub-pixel electrode 210 includes a reflective electrode, the sub-pixel electrode 210 may include a reflective layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof, and a layer on the reflective layer, the layer including ITO, IZO, ZnO, or In2O3. In an embodiment, the sub-pixel electrode 210 may have a structure including an ITO layer, an Ag layer, and an ITO layer stacked in sequence. Each sub-pixel electrode 210 may be electrically connected to a corresponding connection metal CM through a contact hole extending through the second organic insulating layer 111.

[0099] The first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210 may each include an inner portion and an outer portion surrounding the inner portion. In this specification, the "outer portion (or adjacent portion)" of the sub-pixel electrode 210 refers to a part of the sub-pixel electrode 210 that includes the edge of the sub-pixel electrode 210, and the "inner portion of the sub-pixel electrode 210" refers to another part of the sub-pixel electrode 210 surrounded by the outer portion (or adjacent portion).

[0100] The intermediate layer 220 may be disposed on each sub-pixel electrode 210. The intermediate layer 220 may be disposed on the inner portion of each sub-pixel electrode 210. The intermediate layer 220 may include a first intermediate layer 1220, a second intermediate layer 2220, and a third intermediate layer 3220. Among them, the first intermediate layer 1220 is in the first sub-pixel P1, the second intermediate layer 2220 is in the second sub-pixel P2, and the third intermediate layer 3220 is in the third sub-pixel P3. The first intermediate layer 1220 may be configured to overlap and contact the first sub-pixel electrode 1210, the second intermediate layer 2220 may be configured to overlap and contact the second sub-pixel electrode 2210, and the third intermediate layer 3220 may be configured to overlap and contact the third sub-pixel electrode 3210.

[0101] The intermediate layer 220 may include Figure 5 the emission layer 222 as shown in. The intermediate layer 220 may include a common layer disposed between the sub-pixel electrode 210 and the emission layer 222 and between the emission layer 222 and the counter electrode 230. Hereinafter, the common layer disposed between the sub-pixel electrode 210 and the emission layer 222 is referred to as the first common layer 221, and the common layer disposed between the emission layer 222 and the counter electrode 230 is referred to as the second common layer 223.

[0102] The emission layer 222 may include a polymer organic material or a low molecular weight organic material that emits light of a preset color (red, green, or blue). In another embodiment, the emission layer 222 may include an inorganic material or quantum dots and include a first emission layer, a second emission layer, and a third emission layer. Here, the first emission layer of the first intermediate layer 1220, the second emission layer of the second intermediate layer 2220, and the third emission layer of the third intermediate layer 3220 may be configured to emit light of different colors.

[0103] The first common layer 221 may include a hole transport layer (HTL) and a hole injection layer (HIL). The second common layer 223 may include an electron transport layer (ETL) and an electron injection layer (EIL). Both the first common layer 221 and the second common layer 223 may include organic materials.

[0104] The intermediate layer 220 may have a single stacked structure including a single emission layer 222, or in some other alternative embodiments, the intermediate layer 220 may have a tandem structure as a multi-stacked structure including multiple emission layers. In the case where the intermediate layer 220 has a tandem structure, a charge generation layer CGL may be disposed between the multiple stacked members.

[0105] The intermediate layer 220 may be formed using a photolithographic patterning process. As an example, to form the first intermediate layer 1220, a first material layer including a material identical to that of the first intermediate layer 1220 may be deposited over the entire surface of the substrate 100, and then a photoresist may be formed on the first material layer to overlap with the first sub-pixel electrode 1210. Then, the first intermediate layer 1220 may be patterned and formed by etching a portion of the first material layer using the photoresist as a mask. The same or a similar process may be repeated to pattern the layer of the second material and the layer of the third material to form the second intermediate layer 2220 and the third intermediate layer 3220 on the second sub-pixel electrode 2210 and the third sub-pixel electrode 3210, respectively. In this case, the etching process may include a dry etching process, and the intermediate layer 220 may be the portion remaining after the etching process. Additionally, the photoresist disposed on the intermediate layer 220 may be removed by an ashing process.

[0106] Since the intermediate layer 220 in the display device 1 according to the embodiment is formed by the photolithographic patterning process described above, the sub-pixels may be small and closely spaced to provide an ultra-high resolution image. Specifically, when the intermediate layer 220 is formed by the photolithographic patterning process, a fine metal mask (FMM) for patterning the intermediate layer 220 may not be required. Instead, patterning using a fine metal mask may require a specific length or greater spacing between adjacent sub-pixels, which may limit the minimum spacing between sub-pixels and thus limit the resolution of the displayed image. The display device 1 according to the embodiment may be configured to pattern the intermediate layer 220 using a photoresist without a fine metal mask, such that the spacing between adjacent sub-pixels may be significantly reduced, and thus an ultra-high resolution image may be provided.

[0107] The edge or side surface of the intermediate layer 220 formed using the photolithographic patterning process may have a shape close to vertical. Alternatively, the side surface of the intermediate layer 220 may have a forwardly tapered shape. That is, the width of the bottom surface of the intermediate layer 220 may be similar to the width of the upper surface of the intermediate layer 220, or may be slightly wider than the width of the upper surface of the intermediate layer 220. In other words, the cross-section of the intermediate layer 220 may have a rectangular or trapezoidal shape. The angle formed by the side surface of the intermediate layer 220 with respect to the bottom surface of the intermediate layer 220 may be from about 50° to about 90°.

[0108] Refer again to Figure 4, the spacer SP may overlap with the sub-pixel electrode 210. The spacer SP may be specifically disposed on each sub-pixel electrode 210 to cover the outer portion of the sub-pixel electrode 210. As an example, the spacer SP may overlap with the outer portion of the sub-pixel electrode 210 and be in direct contact with the upper surface of the second organic insulating layer 111 where the sub-pixel electrode 210 does not exist. The spacer SP may cover the side surface of each sub-pixel electrode 210.

[0109] The spacer SP may be arranged to surround the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3. Specifically, the spacer SP may include a first opening OP1 overlapping with the first sub-pixel electrode 1210, a second opening OP2 overlapping with the second sub-pixel electrode 2210, and a third opening OP3 overlapping with the third sub-pixel electrode 3210. As an example, the first intermediate layer 1220 may be disposed in the first opening OP1, the second intermediate layer 2220 may be disposed in the second opening OP2, and the third intermediate layer 3220 may be disposed in the third opening OP3. In other words, the spacer SP may be disposed in the non-sub-pixel region NPA between the first sub-pixel P1 and the second sub-pixel P2 or in the non-sub-pixel region NPA between the second sub-pixel P2 and the third sub-pixel P3. Here, the non-sub-pixel region NPA may represent the region of the display area DA other than the emission regions of the first light-emitting diode ED1, the second light-emitting diode ED2, and the third light-emitting diode ED3.

[0110] The spacer SP may have a structure in which an insulating layer 115, a light-absorbing layer 117, and a bank layer 119 are sequentially stacked. First, the insulating layer 115 is disposed in the lowermost part of the three-layer structure of the spacer SP and may be used to insulate the sub-pixel electrode 210 from the counter electrode 230. For this purpose, the insulating layer 115 may not only cover the outer portion of the sub-pixel electrode 210 but also cover the side surface of the intermediate layer 220 and be in contact with the counter electrode 230. That is, in the non-sub-pixel region NPA, the insulating layer 115 may extend from the sub-pixel electrode 210 through the intermediate layer 220 to the counter electrode 230.

[0111] In addition, the insulating layer 115 may be disposed between the first sub-pixel P1 and the second sub-pixel P2 to define the region of the sub-pixel and may separate adjacent light-emitting diodes so that adjacent light-emitting diodes are independently driven. For this purpose, the insulating layer 115 may extend from the side surface of the first intermediate layer 1220 to the side surface of the second intermediate layer 2220. As an example, the insulating layer 115 may overlap with the side surface of the intermediate layer 220 and the outer portion of the sub-pixel electrode 210 and be in direct contact with the upper surface of the second organic insulating layer 111 where the sub-pixel electrode 210 does not exist. The insulating layer 115 may cover the side surface of each of the plurality of sub-pixel electrodes 210.

[0112] The insulating layer 115 may include an inorganic insulating material. During the process of manufacturing the display device 1 using an organic insulating material in the insulating layer 115, using an inorganic insulating material in the insulating layer 115 can prevent or reduce the deterioration of the quality of the light-emitting diodes that might otherwise be caused by the gas emitted from the organic insulating layer. The insulating layer 115 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y ). In an embodiment, the insulating layer 115 may have a thickness of approximately to approximately .

[0113] The light absorption layer 117 included in the three-layer structure of the spacer SP may be disposed on the insulating layer 115. The light absorption layer 117 may cover the upper surface of the insulating layer 115. Thus, similar to the insulating layer 115, the light absorption layer 117 may overlap with the side surface of the intermediate layer 220. As an example, the light absorption layer 117 on the insulating layer 115 may overlap with the side surface of the first intermediate layer 1220 and extend to also overlap with the side surface of the second intermediate layer 2220.

[0114] In an embodiment, the light absorption layer 117 may include a light absorption material such as molybdenum tantalum oxide (MTO) or molybdenum oxide (MoO x ). In another embodiment, the light absorption layer 117 may include a light absorption material such as silicon carbide (SiC). The light absorption layer 117 may have a thickness of approximately to approximately . The transmittance of the light absorption layer 117 including the light absorption material may be 10% or less. As an example, the transmittance of the light absorption layer 117 may be approximately 1%. That is, the light emitted from the side surfaces of the first light-emitting diode ED1, the second light-emitting diode ED2, and the third light-emitting diode ED3 and incident on the spacer SP can be mostly absorbed by the light absorption layer 117.

[0115] Since the light absorption layer 117 includes a light absorption material, even if the first light-emitting diode ED1, the second light-emitting diode ED2, and the third light-emitting diode ED3 are closely spaced apart for displaying an ultra-high resolution image, the display device 1 according to the embodiment can also be configured to improve the color purity of light emitted from each of the regions of the first light-emitting diode ED1, the second light-emitting diode ED2, and the third light-emitting diode ED3. As described above, in the case where the intermediate layer 220 is formed using a photolithography patterning process, an ultra-high resolution image can be achieved. However, when the setting interval of a plurality of sub-pixels is reduced to achieve an ultra-high resolution image in a display device lacking the light absorption layer 117, light emitted from one of the plurality of sub-pixels may be totally reflected and incident on an adjacent sub-pixel, resulting in a decrease in color purity. In contrast, in the display device 1 according to the embodiment, since the spacer SP includes the light absorption layer 117, light that can propagate between adjacent sub-pixels can be blocked, and thus, the color purity of light emitted from each of the plurality of sub-pixels can be improved.

[0116] The three-layer structure of the spacer SP may further include a bank layer 119 disposed on the light absorption layer 117. Specifically, the bank layer 119 may be formed to cover the upper surface of the light absorption layer 117 and fill the step difference formed by the intermediate layer 220. As an example, in the case where the intermediate layer 220 is patterned by a photolithography patterning process, a step difference may occur between the non-sub-pixel region NPA and the first sub-pixel region PA1, the second sub-pixel region PA2, and the third sub-pixel region PA3. A large step difference increases the risk of disconnection in a layer deposited later. Thus, the bank layer 119 may be disposed in the non-sub-pixel region NPA to planarize the upper surface of the structure.

[0117] The bank layer 119 may include a material different from that of the insulating layer 115. In an embodiment, the bank layer 119 may include an organic material such as hexamethyldisiloxane (HMDSO) or polyimide (PI). However, the embodiment is not limited thereto, and the bank layer 119 may include an organic material such as an acrylic monomer or benzocyclobutene (BCB).

[0118] The counter electrode 230 may be disposed on the intermediate layer 220 and the spacer SP. As described above, a stacked structure including one of the sub-pixel electrode 210, the intermediate layer 220, and the counter electrode 230 corresponds to a light-emitting diode. The counter electrode 230 may include a first counter electrode 1230, a second counter electrode 2230, and a third counter electrode 3230. Among them, the first counter electrode 1230 is in the first sub-pixel P1, the second counter electrode 2230 is in the second sub-pixel P2, and the third counter electrode 3230 is in the third sub-pixel P3. The first counter electrode 1230 may be disposed on the first intermediate layer 1220, the second counter electrode 2230 may be disposed on the second intermediate layer 2220, and the third counter electrode 3230 may be disposed on the third intermediate layer 3220.

[0119] The first counter electrode 1230, the second counter electrode 2230, and the third counter electrode 3230 may be integrally provided within the counter electrode 230. The counter electrode 230 may be formed on the entire surface of the substrate 100 and cover the entire surface of the substrate 100. That is, the counter electrode 230 may also be disposed on the spacer SP provided in the non-sub-pixel region NPA. Since the spacer SP fills the step difference caused by the intermediate layer 220 and flattens the upper surface of the structure on which the counter electrode 230 is formed, the counter electrode 230 can overcome the step difference and extend without breaking.

[0120] The counter electrode 230 may include a conductive material having a low work function. As an example, the counter electrode 230 may include a (semi) transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode 230 may further include a transparent conductive layer on the (semi) transparent layer, and the transparent conductive layer includes ITO, IZO, ZnO, or In2O3.

[0121] The capping layer 240 may be on the counter electrode 230. The capping layer 400 may improve the external light-emitting efficiency of the first light-emitting diode ED1, the second light-emitting diode ED2, and the third light-emitting diode ED3 based on the principle of constructive interference. The capping layer 240 may be an organic capping layer including an organic material, an inorganic capping layer including an inorganic material, or a composite capping layer including an organic material and an inorganic material. In an embodiment, the capping layer 240 may include a transparent conductive oxide (TCO) such as indium zinc oxide (IZO) or indium tin oxide (ITO). However, in an embodiment, the capping layer 240 may be omitted.

[0122] An encapsulation layer (not shown) may be disposed on the first light-emitting diode ED1, the second light-emitting diode ED2, and the third light-emitting diode ED3. The encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The inorganic encapsulation layer may include at least one inorganic substance among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride, and the organic encapsulation layer may include a polymer-based material.

[0123] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F and Figure 6G are schematic cross-sectional views showing structures formed during a process of manufacturing a display device according to an embodiment of the present disclosure.

[0124] First, referring to Figure 6A , as described above, the display device 1 (see Figure 4 ) may include a first sub-pixel region PA1, a second sub-pixel region PA2, and a third sub-pixel region PA3, and a non-sub-pixel region NPA between adjacent sub-pixel regions. First sub-pixel circuits PC1, second sub-pixel circuits PC2, and third sub-pixel circuits PC3 may be formed on the substrate 100 corresponding to the respective sub-pixel regions. The first sub-pixel circuit PC1, the second sub-pixel circuit PC2, and the third sub-pixel circuit PC3 may each include transistors and a storage capacitor Cst as described above with reference to Figure 2A and Figure 2B . In the embodiment shown in Figure 6A , the first sub-pixel circuit PC1, the second sub-pixel circuit PC2, and the third sub-pixel circuit PC3 each have the same structure as the first sub-pixel circuit PC1, the second sub-pixel circuit PC2, and the third sub-pixel circuit PC3 described with reference to Figure 4 , and the specific structure may be the same as the specific structure described above.

[0125] The first organic insulating layer 109 and the second organic insulating layer 111 may cover the sub-pixel circuit PC, and the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210 may be formed on the second organic insulating layer 111. The first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210 may be respectively connected to a connection metal CM disposed between the first organic insulating layer 109 and the second organic insulating layer 111, and are respectively electrically connected to the first sub-pixel circuit PC1, the second sub-pixel circuit PC2, and the third sub-pixel circuit PC3. Specifically, the first sub-pixel electrode 1210 may be in the first sub-pixel region PA1 and connected to the first sub-pixel circuit PC1 through the connection metal CM, the second sub-pixel electrode 2210 may be in the second sub-pixel region PA2 and connected to the second sub-pixel circuit PC2 through the connection metal CM, and the third sub-pixel electrode 3210 may be in the third sub-pixel region PA3 and connected to the third sub-pixel circuit PC3 through the connection metal CM.

[0126] The intermediate layer 220 may be formed on each sub-pixel electrode 210. The intermediate layer 220 may include a first intermediate layer 1220, a second intermediate layer 2220, and a third intermediate layer 3220, wherein the first intermediate layer 1220 overlaps with the first sub-pixel electrode 1210, the second intermediate layer 2220 overlaps with the second sub-pixel electrode 2210, and the third intermediate layer 3220 overlaps with the third sub-pixel electrode 3210. As described above with reference to Figure 5 what has been described, the intermediate layer 220 may have a multi-layer structure including a first common layer 221, an emission layer 222, and a second common layer 223.

[0127] The protective layer 300 may be formed on the intermediate layer 220. The protective layer 300 may include a first protective layer 1300, a second protective layer 2300, and a third protective layer 3300, wherein the first protective layer 1300 is formed on the first intermediate layer 1220, the second protective layer 2300 is formed on the second intermediate layer 2220, and the third protective layer 3300 is formed on the third intermediate layer 3220. The protective layer 300 may be arranged to prevent damage to the intermediate layer 220, wherein damage may occur during subsequent processes of forming the spacer SP (see Figure 4 ).

[0128] In an embodiment, the protective layer 300 may include a metal and include a single layer or multiple layers. As an example, the protective layer 300 may include zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), molybdenum (Mo), copper (Cu), or an alloy thereof. However, the embodiment is not limited thereto, and the protective layer 300 may include various metal materials. In an embodiment, the protective layer 300 may have about to about The thickness.

[0129] As described above, the lithographic patterning process can form the intermediate layer 220 and the protective layer 300. First, to form the first intermediate layer 1220, a first material layer including a material the same as that of the first intermediate layer 1220 can be deposited over the entire surface of the substrate 100, and a first protective material layer including a material the same as that of the first protective layer 1300 can be deposited on the first material layer. Then, a photoresist can be formed on the first material layer and the first protective material layer to overlap with the first sub-pixel electrode 1210. The first intermediate layer 1220 and the first protective layer 1300 can be formed by etching a part of the first material layer and a part of the first protective material layer using the photoresist as a mask. The same or similar lithographic patterning process can form the second intermediate layer 2220 and the second protective layer 2300, and the third intermediate layer 3220 and the third protective layer 3300.

[0130] Next, referring to Figure 6B , the insulating layer 115 and the light absorption layer 117 included in the spacer SP (see Figure 4 ) can be formed on the structure shown in Figure 6A . The insulating layer 115 can be disposed on the structure shown in Figure 6A and deposited over the entire surface of the substrate 100. Similarly, the light absorption layer 117 can be disposed on the insulating layer 115 and deposited over the entire surface of the substrate 100. The materials included in the insulating layer 115 and the light absorption layer 117 can be the same as the materials described above with reference to Figure 4 .

[0131] Next, referring to Figure 6C , a photoresist PR can be formed on the structure shown in Figure 6B . The photoresist PR can be disposed on the light absorption layer 117 and provided in the non-sub-pixel area NPA. In other words, the photoresist PR can be formed in the area where the first intermediate layer 1220, the second intermediate layer 2220, and the third intermediate layer 3220 are not provided. That is, the photoresist PR can be formed to surround each of the first intermediate layer 1220, the second intermediate layer 2220, and the third intermediate layer 3220 in a plan view, and can include openings overlapping with the first intermediate layer 1220, the second intermediate layer 2220, and the third intermediate layer 3220.

[0132] Next, referring to Figure 6D, a portion of the insulating layer 115 and a portion of the light absorbing layer 117 may be removed using the photoresist PR as a mask. As an example, a portion of the insulating layer 115 and a portion of the light absorbing layer 117 may be removed by a dry etching process through an opening in the photoresist PR. The etching process may be performed until the upper surface of the protective layer 300 is exposed. In addition, since the etching process is performed over the entire area of ​​the substrate 100, a portion of the photoresist PR may be removed in the manner described above. Figure 6D The portions of the insulating layer 115 and the light absorbing layer 117 shown in FIG. 1 are removed during the etching process for removing the portions of the insulating layer 115 and the light absorbing layer 117 .

[0133] The insulating layer 115 and the light absorbing layer 117 disposed under the photoresist PR may remain to form a spacer SP (see Figure 4 ) portion. The insulating layer 115 may cover the side surface of the intermediate layer 220 and extend to cover the edge of the sub-pixel electrode 210. The light absorbing layer 117 may be arranged on the insulating layer 115 and may extend to overlap with the adjacent intermediate layer 220. As an example, the insulating layer 115 may extend from the side surface of the first intermediate layer 1220 to the side surface of the second intermediate layer 2220 through the outer portion of the first sub-pixel electrode 1210, the upper surface of the second organic insulating layer 111, and the outer portion of the second sub-pixel electrode 2210. The light absorbing layer 117 may overlap with the side surface of the first intermediate layer 1220 and extend to also overlap with the side surface of the second intermediate layer 2220.

[0134] Next, refer to Figure 6E , the photoresist PR may be removed, and the bank layer 119 may be formed in the region from which the photoresist PR has been removed. The photoresist PR may be removed by an ashing process. The bank layer 119 may be formed on the light absorbing layer 117 in the non-sub-pixel area NPA. Specifically, the bank layer 119 may be deposited to fill the step difference formed by the intermediate layer 220. In other words, the bank layer 119 may be configured to Figure 6E The material included in the bank layer 119 may be similar to that in the reference Figure 4 The spacer SP thus formed may include Figure 6E The three-layer structure of the insulating layer 115, the light absorbing layer 117 and the bank layer 119 is shown in FIG.

[0135] Next, refer to Figure 6F , the protective layer 300 can be from Figure 6EIt is removed from the structure shown. Since the protective layer 300 includes a metallic material, the protective layer 300 can be removed by a wet etching process that selectively etches the metal. The etchant used in the wet etching process for removing the protective layer 300 may not damage the intermediate layer 220. As an example, the etchant used in the etching process for the protective layer 400 may include potassium oxide or tetramethylammonium hydroxide, but the embodiments are not limited thereto.

[0136] Next, referring to Figure 6G , the counter electrode 230 and the capping layer 240 may be formed on the structure shown in Figure 6F . The structure shown in Figure 6F may be thermally cured by a baking process before the counter electrode 230 and the capping layer 240 can be deposited. The baking process may be performed by applying heat of about 100 °C for about 1 hour.

[0137] Each of the counter electrode 230 and the capping layer 240 may be deposited over the entire surface of the substrate 100. The counter electrode 230 may be deposited by a thermal deposition process, and the capping layer 240 may be deposited by a sputtering process. Since the spacer SP fills the step difference caused by the intermediate layer 220, each of the counter electrode 230 and the capping layer 240 may be provided integrally without discontinuity. The materials included in the counter electrode 230 and the capping layer 240 may be the same as the materials described with reference to Figure 4 .

[0138] The display device according to an embodiment may be configured to implement an ultra-high resolution image and emit light having high purity of color. However, this effect is an example, and the scope of the present disclosure is not limited by this effect.

[0139] The embodiments described herein should be considered only in an illustrative sense and not for purposes of limitation. The description of the features or aspects in each embodiment should generally be considered available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, comprising: a first sub-pixel electrode; a spacer, the spacer comprising a first opening overlapping the first sub-pixel electrode, wherein in a plan view, the spacer surrounds the first sub-pixel electrode; a first intermediate layer disposed in the first opening of the spacer and overlapping the first sub-pixel electrode; and a first pair of electrodes, the first pair of electrodes being arranged on the first intermediate layer, The spacer includes a structure in which an insulating layer, a light absorbing layer and a bank layer are stacked in sequence.

2. The display device according to claim 1, wherein: The insulating layer covers side surfaces of the first intermediate layer.

3. The display device according to claim 2, wherein: The insulating layer covers an edge of the first sub-pixel electrode and contacts the first pair of electrodes.

4. The display device according to claim 2, wherein: The light absorbing layer covers an upper surface of the insulating layer.

5. The display device according to claim 1, wherein: An angle formed by a side surface of the first intermediate layer with respect to a bottom surface of the first intermediate layer is 50° to 90°.

6. The display device according to claim 1, further comprising: a second sub-pixel electrode, the second sub-pixel electrode being adjacent to the first sub-pixel electrode; a second intermediate layer disposed in the second opening of the spacer and overlapping the second sub-pixel electrode; as well as A second pair of electrodes is disposed on the second intermediate layer.

7. The display device according to claim 6, wherein: The first pair of electrodes and the second pair of electrodes are integrally provided.

8. The display device according to claim 6, wherein: The insulating layer and the light absorbing layer extend from a region overlapping with a side surface of the first intermediate layer to a region overlapping with a side surface of the second intermediate layer.

9. The display device according to claim 8, wherein: The bank layer is disposed on the light absorbing layer and fills a step difference formed by the first intermediate layer and the second intermediate layer.

10. The display device according to claim 1, wherein: The light absorbing layer includes molybdenum tantalum oxide or molybdenum oxide.

11. The display device according to claim 10, wherein: The light absorbing layer has to Thickness.

12. The display device according to claim 1, wherein: The light absorbing layer includes silicon carbide.

13. The display device according to claim 1, wherein: The insulating layer and the bank layer include materials different from each other.

14. The display device according to claim 13, wherein: The insulating layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

15. The display device according to claim 13, wherein: The bank layer includes at least one of hexamethyldisiloxane and an acrylic monomer.

16. A method for manufacturing a display device, the method comprising: forming a first sub-pixel electrode and a second sub-pixel electrode adjacent to the first sub-pixel electrode; forming a first intermediate layer on the first sub-pixel electrode, and forming a second intermediate layer on the second sub-pixel electrode; forming a spacer between the first intermediate layer and the second intermediate layer; as well as forming a first pair of electrodes on the first intermediate layer, and forming a second pair of electrodes on the second intermediate layer, Wherein, forming the spacer comprises: forming an insulating layer covering an edge of the first sub-pixel electrode and an edge of the second sub-pixel electrode; forming a light absorbing layer on the insulating layer; and A bank layer is formed on the light absorbing layer.

17. The method for manufacturing a display device according to claim 16, further comprising: Between forming the first and second intermediate layers and forming the spacer, a first protective layer is formed on the first intermediate layer, and a second protective layer is formed on the second intermediate layer.

18. The method for manufacturing a display device according to claim 17, wherein: Forming the spacer includes: depositing the insulating layer to cover from the upper surface of the first protective layer through the side surface of the first intermediate layer and the side surface of the second intermediate layer to the upper surface of the second protective layer; and The light absorbing layer is deposited on an upper surface of the insulating layer to overlap with the upper surface of the first protective layer, the side surface of the first intermediate layer, the side surface of the second intermediate layer, and the upper surface of the second protective layer.

19. The method for manufacturing a display device according to claim 18, wherein: Forming the spacer further comprises: forming a photoresist on the light absorbing layer between the first intermediate layer and the second intermediate layer; etching a portion of the insulating layer that does not overlap with the photoresist and a portion of the light absorbing layer that does not overlap with the photoresist; and The photoresist is removed.

20. The method for manufacturing a display device according to claim 19, wherein: The bank layer is disposed on the light absorbing layer, and is formed to fill a step difference between the first intermediate layer and the second intermediate layer.

21. The method for manufacturing a display device according to claim 17, further comprising: The first protective layer and the second protective layer are removed between forming the spacer and forming the first pair of electrodes and the second pair of electrodes.

22. The method for manufacturing a display device according to claim 16, wherein: The first pair of electrodes and the second pair of electrodes are integrally formed.

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