Display device having crack protection region

Abstract

The display device comprises a display panel. The display panel includes a substrate, a circuit layer disposed on the substrate, and an element layer disposed on the circuit layer. The main area of the substrate includes a display area in which the emission area is arranged and a non-display area disposed around the display area. The display area includes a front display area and a peripheral display area disposed around the front display area and having a curved shape. The substrate includes a first support layer, a barrier layer disposed on a portion of the first support layer, and a second support layer covering the barrier layer. The substrate further includes a crack protection region in contact with at least a portion of the edge of the substrate. In the crack protection region, the second support layer is in contact with the first support layer.

Description

[0001] Cross - reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10 - 2023 - 0182525, filed with the Korean Intellectual Property Office on December 15, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a display device having a crack - protected region. Background art

[0004] With the development of multimedia technology, the demand for display devices has been continuously increasing. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0005] The display device may be a flat - panel display device such as a liquid - crystal display device, a field - emission display device, or a light - emitting display device. For example, the light - emitting display device may include an organic light - emitting display device including organic light - emitting elements, an inorganic light - emitting display device including inorganic light - emitting elements such as inorganic semiconductors, and a micro - light - emitting display device including micro - light - emitting elements.

[0006] The organic light - emitting display device displays an image using self - emitting elements, and thus may have relatively good performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle compared to other display devices.

[0007] However, the organic light - emitting display device is prone to cracking. The thinness of the organic light - emitting display device makes it more vulnerable to damage from impact, bending, or pressure, which can cause cracks. Therefore, there is a need for an organic light - emitting display device that is more resistant to cracking. Summary of the invention

[0008] When the display area of the display surface of the display device is very wide, the light - emitting area of the display device is also very wide, which is more aesthetically pleasing and more compatible with various electronic devices. The width of the non - display area of the display surface can be reduced to increase the width of the display area. However, since some signal lines and circuit elements need to be disposed in the non - display area, there are limitations on how much the width of the non - display area can be reduced. In addition, reducing the width of the non - display area may make the display device more prone to cracking.

[0009] At least one embodiment of the present disclosure provides a display device in which, by transforming the edge of the display area into a curved shape, the width of the non - display area viewed in the front direction facing the display surface can be reduced.

[0010] According to aspects of the present disclosure, a display device is provided. The display device includes a display panel that emits light for displaying an image. The display panel includes a substrate, a circuit layer disposed on the substrate, and an element layer disposed on the circuit layer. A main region of the substrate includes a display region in which emission regions are arranged and a non-display region disposed around the display region. The display region includes a front display region and a peripheral display region disposed around the front display region and having a curved shape. The substrate includes a first support layer, a barrier layer disposed on a part of the first support layer, and a second support layer covering the barrier layer. The substrate further includes a crack protection region that contacts at least a part of an edge of the substrate. In the crack protection region, the second support layer contacts the first support layer.

[0011] The front display region may include a first side and a second side that extend in a first direction and face each other, and a third side and a fourth side that extend in a second direction intersecting the first direction and face each other. The peripheral display region may include: a first side region, a second side region, a third side region, and a fourth side region, respectively contacting the first side, the second side, the third side, and the fourth side of the front display region; a first corner region, contacting a vertex where the first side and the third side meet and disposed between the first side region and the third side region; a second corner region, contacting a vertex where the second side and the third side meet and disposed between the second side region and the third side region; a third corner region, contacting a vertex where the second side and the fourth side meet and disposed between the second side region and the fourth side region; and a fourth corner region, contacting a vertex where the first side and the fourth side meet and disposed between the first side region and the fourth side region.

[0012] The barrier layer may overlap with the display region of the main region.

[0013] The element layer may include light-emitting elements respectively disposed in the emission regions. The circuit layer includes: an emission pixel driver, disposed in the display region in the first direction and the second direction and electrically connected to the light-emitting elements respectively; a gate line, extending in the first direction and transmitting a gate signal to the emission pixel driver; and a gate driver, disposed in a gate circuit region of at least one side facing the display region in the first direction among the non-display regions, and providing the gate signal to the gate line. The barrier layer may extend to the non-display region to further overlap with the gate circuit region.

[0014] The display panel may further include a sealing layer disposed on the element layer and at least one dam portion disposed in a dam region of the non-display region surrounding the display region and spaced apart from the display region. The barrier layer may extend to the non-display region to further overlap with the dam region. The crack protection region may be disposed between the dam region and the edge of the substrate.

[0015] The edges of the main region include: a fifth side and a sixth side, extending in a first direction and facing each other; a seventh side and an eighth side, extending in a second direction intersecting the first direction and facing each other; a first corner where the fifth side and the seventh side meet; a second corner where the sixth side and the seventh side meet; a third corner where the sixth side and the eighth side meet; and a fourth corner where the fifth side and the eighth side meet. The crack protection region contacts at least one of the first corner, the second corner, the third corner, and the fourth corner among the edges of the main region.

[0016] The substrate may further include a sub-region protruding from at least a part of the fifth side. The crack protection region may further contact the seventh side, the sixth side, and the eighth side among the edges of the main region. The crack protection region may further contact a part of the fifth side of the edge of the main region other than the part of the main region in contact with the sub-region.

[0017] The sub-region may include a curved region connected to the main region and a pad region connected to the curved region. The crack protection region may include the curved region.

[0018] The crack protection region may further contact a part of the edge of the sub-region other than the part of the sub-region connected to the main region.

[0019] Each of the first support layer and the second support layer may include an organic insulating material. The barrier layer may include an inorganic insulating material.

[0020] The circuit layer may further include: a first semiconductor layer disposed on the substrate; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer disposed on the second gate insulating layer; an interlayer insulating layer disposed on the second gate insulating layer and the second gate conductive layer; a first source / drain conductive layer disposed on the interlayer insulating layer; a first planarization layer covering the first source / drain conductive layer; a second source / drain conductive layer disposed on the first planarization layer; and a second planarization layer covering the second source / drain conductive layer.

[0021] The circuit layer may further include: an auxiliary interlayer insulating layer covering the second gate conductive layer; a second semiconductor layer disposed on the auxiliary interlayer insulating layer; a third gate insulating layer covering the second semiconductor layer; and a third gate conductive layer disposed on the third gate insulating layer and covered by the interlayer insulating layer.

[0022] The display device may further include a bracket supporting the display panel and a cover window disposed on the display panel and coupled to the bracket. The peripheral display region may have a shape curved toward the bracket.

[0023] According to aspects of the present disclosure, a display device is provided. The display device includes: a display panel configured to emit light for displaying an image; a bracket configured to support the display panel; and a cover window disposed on the display panel and coupled to the bracket. The display panel includes a substrate, a circuit layer disposed on the substrate, and an element layer disposed on the circuit layer. A main region of the substrate includes a display region in which emission regions are arranged and a non-display region disposed around the display region. The display region includes a front display region and a peripheral display region disposed around the front display region and having a shape curved toward the bracket. The substrate includes: a first support layer; a barrier layer disposed on a part of the first support layer and including a material different from that of the first support layer; and a second support layer covering the barrier layer and including the same material as the first support layer. The substrate further includes a crack protection region in contact with at least a part of an edge of the substrate. In the crack protection region, the second support layer is in contact with the first support layer.

[0024] The front display region may include a first side and a second side extending in a first direction and facing each other, and a third side and a fourth side extending in a second direction intersecting the first direction and facing each other. The peripheral display region may include: a first side region, a second side region, a third side region, and a fourth side region respectively in contact with the first side, the second side, the third side, and the fourth side of the front display region; a first corner region in contact with a vertex where the first side and the third side meet and disposed between the first side region and the third side region; a second corner region in contact with a vertex where the second side and the third side meet and disposed between the second side region and the third side region; a third corner region in contact with a vertex where the second side and the fourth side meet and disposed between the second side region and the fourth side region; and a fourth corner region in contact with a vertex where the first side and the fourth side meet and disposed between the first side region and the fourth side region.

[0025] The barrier layer may overlap with the display region of the main region.

[0026] The element layer may include light-emitting elements respectively disposed in the emission regions. The circuit layer may include: an emission pixel driver arranged in the first direction and the second direction in the display region and electrically connected to the light-emitting elements respectively; a gate line extending in the first direction and transmitting a gate signal to the emission pixel driver; and a gate driver disposed in a gate circuit region of at least one side facing the display region in the first direction among the non-display regions and supplying the gate signal to the gate line. The barrier layer may extend to the non-display region to further overlap with the gate circuit region.

[0027] The display panel may further include a sealing layer disposed on the element layer and at least one dam portion disposed in a dam region of a non-display region surrounding the display region and spaced apart from the display region. The edge of the main region may include: a fifth side and a sixth side extending in a first direction and facing each other; a seventh side and an eighth side extending in a second direction crossing the first direction and facing each other; a first corner where the fifth side and the seventh side meet; a second corner where the sixth side and the seventh side meet; a third corner where the sixth side and the eighth side meet; and a fourth corner where the fifth side and the eighth side meet. The crack protection region may be in contact with the first corner, the second corner, the third corner, and the fourth corner among the edges of the main region, and is disposed between the dam region and the edge of the substrate. The barrier layer may extend to the non-display region to further overlap with the dam region.

[0028] The substrate may further include a sub-region protruding from a part of the fifth side. The crack protection region may also be in contact with the seventh side, the sixth side, and the eighth side among the edges of the main region. The crack protection region may also be in contact with a part of the fifth side of the edge of the main region except for the part of the main region in contact with the sub-region.

[0029] The crack protection region may also be in contact with a part of the edge of the sub-region except for the part of the sub-region adjacent to the main region.

[0030] A display device according to an embodiment may include a display panel for emitting light for displaying an image, and a main region of a substrate of the display panel may include a display region in which an emission region is disposed and a non-display region disposed around the display region. The display region may include a front display region and a peripheral display region disposed around the front display region and having a curved shape.

[0031] According to an embodiment, the peripheral display region may include: a first side region, a second side region, a third side region, and a fourth side region, respectively in contact with a first side, a second side, a third side, and a fourth side of the front display region; and a first corner region, a second corner region, a third corner region, and a fourth corner region, in contact with a vertex where any two of the first side, the second side, the third side, and the fourth side of the front display region meet.

[0032] As described above, the display region according to an embodiment includes a peripheral display region having a curved shape, and thus, the non-display region connected to the peripheral display region may have a curved shape together with the peripheral display region. That is, when viewed in the front direction facing the display surface, the width of the non-display region having a curved shape may be smaller than the width of the non-display region in a non-curved state. Therefore, the width of the display region of the display surface of the display device viewed in the front direction can be increased, and thus, the aesthetics and compatibility of the display device can be increased.

[0033] According to an embodiment, a substrate of a display panel may include a first support layer, a barrier layer disposed on a part of the first support layer, and a second support layer covering the barrier layer.

[0034] According to an embodiment, the substrate may include a crack protection region in contact with at least a part of an edge of the substrate.

[0035] According to an embodiment, in the crack protection region, the barrier layer may be removed such that the second support layer contacts the first support layer.

[0036] As described above, the barrier layer may be removed from at least a part of the edge of the substrate, and thus, in the process of separating the substrate from a mother substrate and the process of modifying a peripheral display region into a curved shape, only a part of the barrier layer may be exposed. Accordingly, cracks in the barrier layer may be reduced and prevented. As a result, substrate separation defects in which the first support layer and the second support layer are separated due to cracks in the barrier layer may be prevented.

[0037] Accordingly, the lifespan and quality reliability of the display device may be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other aspects and features of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0039] Figure 1 is a perspective view showing a display device according to an embodiment;

[0040] Figure 2 is a cross-sectional view taken along line A-A' of Figure 1 ;

[0041] Figure 3 is a plan view showing a display panel of Figure 2 ;

[0042] Figure 4 is a layout view showing part C of Figure 3 ;

[0043] Figure 5 is a cross-sectional view of the display panel taken along line B-B' of Figure 1 ;

[0044] Figure 6 is a layout view showing a touch sensor layer of Figure 5 according to an embodiment;

[0045] Figure 7 is a detailed plan view showing part D of Figure 6 ;

[0046] Figure 8is an equivalent circuit diagram of a light-emitting pixel driver according to an embodiment; Figure 4 ;

[0047] Figure 9 is a cross-sectional view taken along line E-E' of an embodiment according to Figure 8 ; Figure 7 ;

[0048] Figure 10 is an equivalent circuit diagram of a light-emitting pixel driver according to an embodiment; Figure 4 ;

[0049] Figure 11 is a cross-sectional view taken along line E-E' of an embodiment according to Figure 10 ; Figure 7 ;

[0050] Figure 12 is a plan view of a display panel according to an embodiment;

[0051] Figure 13 is a cross-sectional view of the display panel taken along line F-F'; and Figure 12 ;

[0052] Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 19 are plan views of a display panel according to an embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0053] The features and methods for implementing the present disclosure can be more easily understood by referring to the following detailed description of exemplary embodiments and the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete, and will convey the concept of the present disclosure to those skilled in the art.

[0054] It will be understood that when an element or layer is referred to as being "on" another element or layer, the element or layer can be directly on the other element or layer, or on an intervening element or layer. Throughout the specification, the same reference numerals denote the same elements. The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings for describing the embodiments are merely examples, and the present disclosure is not limited to the details shown.

[0055] The features of the various embodiments of the present disclosure can be partially or completely coupled or combined with each other, and can be interoperated and driven in various technical ways. The embodiments can be implemented independently of each other, or can be implemented together in a mutually dependent relationship.

[0056] In the following, specific embodiments will be described with reference to the accompanying drawings.

[0057] Figure 1 is a perspective view showing a display device according to an embodiment. Figure 2 is a cross-sectional view taken along line A-A' of Figure 1 .

[0058] Referring to Figure 1 , the display device 10 according to an embodiment is a device that displays moving images or still images and can be used as a display screen for various products (such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs)).

[0059] Alternatively, the display device 10 according to an embodiment can be applied to a central information display (CID) provided on an instrument panel, a center console, or a dashboard of a vehicle, an in-vehicle mirror display replacing a side mirror of the vehicle, or a display provided on the rear surface of a front seat for entertainment of a rear seat of the vehicle.

[0060] Referring to Figure 2 , the display device 10 according to an embodiment includes a display panel 100 that emits light for displaying an image.

[0061] In addition, the display device 10 according to an embodiment further includes a bracket 200 that supports the display panel 100 and a cover window 300 that is provided on the display panel 100 and coupled to the bracket 200.

[0062] The display panel 100 may be a light-emitting display panel including light-emitting elements. For example, the display panel 100 may be an organic light-emitting display panel using an organic light-emitting diode including an organic light-emitting layer, a micro light-emitting diode (LED) display panel using a micro light-emitting diode, a quantum dot light-emitting diode display panel using a quantum dot light-emitting layer including quantum dots, or an inorganic light-emitting display panel using an inorganic light-emitting element including an inorganic semiconductor. In the following, the display panel 100 being an organic light-emitting display panel will be mainly described.

[0063] The bracket 200 may include a rigid insulating material to prevent the display panel 100 from deforming, reduce external physical impact on the display panel 100, and reduce electrical impact on the display panel 100. However, this is merely an example, as the bracket 200 may be changed to include different materials.

[0064] The cover window 300 may include a light-transmissive material. The cover window 300 may be made of an inorganic material such as glass, or an organic material such as a plastic or polymer material. The cover window 300 may be fixed to the bracket 200 by an adhesive material 400 provided at its edge. The cover window 300 may also be attached to the display panel 100 by a transparent adhesive member such as an optically clear adhesive (OCA) film or an optically clear resin (OCR). The display surface of the display panel 100 may be protected from electrical shock and physical shock caused by the cover window 300.

[0065] As Figure 1 shown, according to an embodiment, the display panel 100 includes a display area DA that emits light and a non-display area NDA disposed around the display area DA.

[0066] The display area DA may include a front display area FSA having a flat shape and a peripheral display area PSA disposed around the front display area FSA and having a curved shape.

[0067] The front display area FSA may include a first side SD1 and a second side SD2 that extend in a first direction DR1 and face each other (also referred to as "facing each other"), and a third side SD3 and a fourth side SD4 that extend in a second direction DR2, connect the first side SD1 and the second side SD2 to each other, and face each other.

[0068] As an example, the first side SD1 and the second side SD2 may be shorter than the third side SD3 and the fourth side SD4. That is, the front display area FSA may have a quadrilateral shape in a plan view.

[0069] As another example, the corners where each of the first side SD1 and the second side SD2 meets each of the third side SD3 and the fourth side SD4 may be formed as arcs or vertices having a right-angled shape.

[0070] However, the shape of the front display area FSA according to an embodiment is not limited to Figure 1 the quadrilateral shape shown, and may also be a circular shape, an oval shape, or a polygonal shape other than the quadrilateral shape.

[0071] The peripheral display area PSA may include a first side area SS1 in contact with the first side SD1 of the front display area FSA, a second side area SS2 in contact with the second side SD2 of the front display area FSA, a third side area SS3 in contact with the third side SD3 of the front display area FSA, and a fourth side area SS4 in contact with the fourth side SD4 of the front display area FSA.

[0072] In addition, the peripheral display area PSA may further include a first corner area CS1, a second corner area CS2, a third corner area CS3, and a fourth corner area CS4. The first corner area CS1 is in contact with the vertex connecting the first side SD1 and the third side SD3 to each other, and is disposed between the first side area SS1 and the third side area SS3. The second corner area CS2 is in contact with the vertex connecting the second side SD2 and the third side SD3 to each other, and is disposed between the second side area SS2 and the third side area SS3. The third corner area CS3 is in contact with the vertex connecting the second side SD2 and the fourth side SD4 to each other, and is disposed between the second side area SS2 and the fourth side area SS4. The fourth corner area CS4 is in contact with the vertex connecting the first side SD1 and the fourth side SD4 to each other, and is disposed between the first side area SS1 and the fourth side area SS4.

[0073] The first side area SS1 may have a shape extending from the first side SD1 and curving toward the bracket 200 with a predetermined first curvature.

[0074] The second side area SS2 may have a shape extending from the second side SD2 and curving toward the bracket 200 with a second curvature. The second curvature may be within the same range as the range of the first curvature.

[0075] The third side area SS3 may have a shape extending from the third side SD3 and curving toward the bracket 200 with a predetermined third curvature. The third curvature may be within the same or a similar range as the range of the first curvature or the second curvature, but is not limited thereto. For example, the first curvature to the third curvature may fall within a similar numerical range.

[0076] The fourth side area SS4 may have a shape extending from the fourth side SD4 and curving toward the bracket 200 with a fourth curvature. The fourth curvature may be within the same range as the range of the third curvature. For example, the third curvature and the fourth curvature may fall within a similar numerical range.

[0077] The first corner area CS1 may be disposed between the other side of the first side area SS1 and one side of the third side area SS3.

[0078] The first corner area CS1 may be a bi-curvature area curved with the first curvature of the first side area SS1 and the third curvature of the third side area SS3.

[0079] The second corner area CS2 may be disposed between the other side of the second side area SS2 and the other side of the third side area SS3.

[0080] The second corner area CS2 may be a bi-curvature area curved with the second curvature of the second side area SS2 and the third curvature of the third side area SS3.

[0081] The third corner region CS3 may be provided between one side of the second side region SS2 and the other side of the fourth side region SS4.

[0082] The third corner region CS3 may be a bi-curved region curved with a second curvature of the second side region SS2 and a fourth curvature of the fourth side region SS4.

[0083] The fourth corner region CS4 may be provided between one side of the first side region SS1 and one side of the fourth side region SS4.

[0084] The fourth corner region CS4 may be a bi-curved region curved with a first curvature of the first side region SS1 and a fourth curvature of the fourth side region SS4.

[0085] That is, since each of the first corner region CS1, the second corner region CS2, the third corner region CS3, and the fourth corner region CS4 is a bi-curved region affected by two different curvatures, higher bending stresses may be applied to these corner regions compared to the first side region SS1, the second side region SS2, the third side region SS3, and the fourth side region SS4.

[0086] Therefore, cracks caused by relatively high bending stresses may occur more frequently in the first corner region CS1, the second corner region CS2, the third corner region CS3, the fourth corner region CS4, and portions of the non-display region NDA adjacent to the first corner region CS1, the second corner region CS2, the third corner region CS3, and the fourth corner region CS4.

[0087] As described above, according to the embodiment, the display region DA not only includes the front display region FSA having a flat shape, but also includes the peripheral display region PSA having a shape curved toward the bracket 200.

[0088] The non-display region NDA is provided around the display region DA and may thus be connected to the outer side of the peripheral display region PSA.

[0089] That is, the non-display region NDA connected to the peripheral display region PSA having a curved shape may have a curved shape together with the peripheral display region PSA having a curved shape.

[0090] As Figure 2 shown, the display device 10 may include a display region DA that emits light of the display panel 100 and a non-display region NDA that is provided around the display region DA and does not emit light.

[0091] The display region DA of the display panel 100 may have a peripheral display region PSA at its edge (see Figure 1) a shape that bends towards the bracket 200. Therefore, since the peripheral display area PSA has a curved shape, the non-display area NDA of the display device 10 can be provided on the side surface of the display device 10.

[0092] In addition, each of the bracket 200 and the cover window 300 can have a shape in which its edge is curved like the display panel 100.

[0093] Therefore, when viewed in the front direction of the light facing the front display area FSA of the display device 10 (see Figure 1 ), for example, in the direction opposite to the third direction DR3), the width W of the non-display area NDA having a curved shape in the display device 10 can be smaller than the width L of the non-display area NDA in the non-curved state.

[0094] Therefore, as the width W of the non-display area NDA in the display surface of the display device 10 viewed in the front direction decreases, the ratio of the display area DA of the display surface can increase, and thus, the aesthetics and compatibility of the display device 10 can be increased.

[0095] Figure 3 is a plan view of the display panel showing Figure 2 . Figure 4 is a layout view of part C showing Figure 3 .

[0096] Referring to Figure 3 , the display panel 100 of the display device 10 according to an embodiment includes a substrate 110.

[0097] The substrate 110 may include a main area MA corresponding to the display surface and a sub-area SBA protruding from one side of the main area MA.

[0098] The main area MA may include a display area DA that emits light and a non-display area NDA that is provided around the display area DA and does not emit light.

[0099] Referring to Figure 4 , the emission areas EA that emit light of each color and brightness to display an image may be arranged in the display area DA.

[0100] The display area DA may further include a non-emission area provided in the interval between the emission areas EA.

[0101] The emission area EA may have a rhombus shape in a plan view or a rectangular shape in a plan view. However, this is merely an example, and according to an embodiment, the shape of the emission area EA in a plan view is not limited to Figure 4The shape shown in []. That is, the emission area EA may have a polygonal shape such as a quadrilateral shape, a pentagon shape, or a hexagon shape in a plan view, or may have a circular shape or an elliptical shape including a curved edge in a plan view.

[0102] The emission area EA may include a first emission area EA1 that emits light of a first color in a predetermined wavelength band, a second emission area EA2 that emits light of a second color in a wavelength band lower than that of the first color, and a third emission area EA3 that emits light of a third color in a wavelength band lower than that of the second color.

[0103] As an example, the first color may be red corresponding to a wavelength band of approximately 600 nanometers (nm) to 750 nm. The second color may be green corresponding to a wavelength band of approximately 480 nm to 560 nm. The third color may be blue corresponding to a wavelength band of approximately 370 nm to 460 nm.

[0104] The first emission area EA1 and the third emission area EA3 may be alternately arranged in at least one of a first direction DR1 and a second direction DR2.

[0105] The second emission area EA2 may be arranged side by side in at least one of a first direction DR1 and a second direction DR2.

[0106] In addition, the second emission area EA2 may be adjacent or neighboring to the first emission area EA1 and the third emission area EA3 in diagonal directions DR4 and DR5 that intersect the first direction DR1 and the second direction DR2.

[0107] Pixels PX that display each brightness and color may be provided by the first emission area EA1, the second emission area EA2, and the third emission area EA3 that are adjacent to each other among such emission areas EA.

[0108] In other words, the pixel PX may be a basic unit of various colors including white that is displayed at a predetermined brightness.

[0109] Each of the pixels PX may include at least one first emission area EA1, at least one second emission area EA2, and at least one third emission area EA3 that are adjacent to each other. Therefore, each of the pixels PX may display various colors by mixing the light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 that are adjacent to each other.

[0110] As Figure 3 shown in [], the display area DA of the substrate 110 of the display panel 100 according to an embodiment includes a front display area FSA provided at the center and a peripheral display area PSA provided around the front display area FSA.

[0111] The front display area FSA can maintain a flat shape on a plane defined by a first direction DR1 and a second direction DR2.

[0112] The front display area FSA can include a first side SD1 and a second side SD2 that extend in the first direction DR1 and face each other, and a third side SD3 and a fourth side SD4 that extend in the second direction DR2, connect the first side SD1 and the second side SD2 to each other, and face each other.

[0113] The peripheral display area PSA can be provided between the front display area FSA and the non-display area NDA. The peripheral display area PSA can have an annular shape surrounding the front display area FSA.

[0114] As Figure 1 and Figure 2 shown, the peripheral display area PSA can be transformed into a curved shape.

[0115] As Figure 3 shown, the peripheral display area PSA can include: a first side area SS1, a second side area SS2, a third side area SS3, and a fourth side area SS4, which are in contact with the first side SD1, the second side SD2, the third side SD3, and the fourth side SD4 of the front display area FSA respectively; a first corner area CS1, which is in contact with the vertex connecting the first side SD1 and the third side SD3 and is provided between the first side area SS1 and the third side area SS3; a second corner area CS2, which is in contact with the vertex connecting the second side SD2 and the third side SD3 and is provided between the second side area SS2 and the third side area SS3; a third corner area CS3, which is in contact with the vertex connecting the second side SD2 and the fourth side SD4 and is provided between the second side area SS2 and the fourth side area SS4; and a fourth corner area CS4, which is in contact with the vertex connecting the first side SD1 and the fourth side SD4 and is provided between the first side area SS1 and the fourth side area SS4.

[0116] The non-display area NDA can be provided at the edge of the main area MA and can have an annular shape surrounding the display area DA.

[0117] The non-display area NDA can include a dam area DMA that surrounds the display area DA and is spaced apart from the display area DA. At least one dam portion DM1 and DM2 (see Figure 13 ) having an annular shape surrounding the display area DA can be arranged in the dam area DMA.

[0118] The sub-area SBA can face the first side SD1 of the front display area FSA. The sub-area SBA can be adjacent to the first side SD1.

[0119] The sub-region SBA may include a bent region BA transformed into a bent shape and a pad region PDA connected to the bent region BA.

[0120] When the main region MA has a shape similar to that of the front display region FSA, the edge of the main region MA may include four sides SD5, SD6, SD7, and SD8 and four corners VT1, VT2, VT3, and VT4 that connect two sides extending in different directions to each other.

[0121] That is to say, the edge of the main region MA may include a fifth side SD5 and a sixth side SD6 that extend in a first direction DR1 and face each other (also referred to as "opposite each other") and a seventh side SD7 and an eighth side SD8 that extend in a second direction DR2, connect between the fifth side SD5 and the sixth side SD6, and face each other.

[0122] For example, compared with the seventh side SD7 and the eighth side SD8, the fifth side SD5 and the sixth side SD6 may have a shorter length. That is to say, the main region MA may have a quadrilateral shape in a plan view.

[0123] In another example, the corners VT1, VT2, VT3, and VT4 where each of the fifth side SD5 and the sixth side SD6 meets each of the seventh side SD7 and the eighth side SD8 may be formed as arcs or vertices having a right-angle shape.

[0124] However, the shape of the main region MA according to the embodiment in a plan view is not limited to Figure 3 the quadrilateral shape shown in, and may also be a circular shape, an oval shape, or a polygonal shape other than the quadrilateral shape.

[0125] Figure 5 is a cross-sectional view of the display panel taken along the line B - B'. Figure 1 of the display panel.

[0126] Referring to Figure 5 , the display panel 100 of the display device 10 according to the embodiment includes a substrate 110, a circuit layer 120 provided on the substrate 110, and an element layer 130 provided on the circuit layer 120.

[0127] The substrate 110 may include a main region MA and a sub-region SBA.

[0128] The main region MA may include a display region DA and a non-display region NDA provided around the display region DA.

[0129] The display region DA may include a front display region FSA and a peripheral display region PSA provided around the front display region FSA and having a curved shape.

[0130] The edge of the front display area FSA may include a first side SD1 and a second side SD2 that face each other in the second direction DR2.

[0131] The peripheral display area PSA may include a first side area SS1 disposed between the first side SD1 of the front display area FSA and the non-display area NDA, and a second side area SS2 disposed between the second side SD2 of the front display area FSA and the non-display area NDA.

[0132] In addition, as Figure 3 shown, the edge of the front display area FSA may further include a third side SD3 and a fourth side SD4 that face each other in the first direction DR1.

[0133] The peripheral display area PSA may include a third side area SS3 disposed between the third side SD3 of the front display area FSA and the non-display area NDA, and a fourth side area SS4 disposed between the fourth side SD4 of the front display area FSA and the non-display area NDA.

[0134] In addition, the peripheral display area PSA may further include a first corner area CS1 that contacts the vertex connecting the first side SD1 and the third side SD3 and is disposed between the first side area SS1 and the third side area SS3, a second corner area CS2 that contacts the vertex connecting the second side SD2 and the third side SD3 and is disposed between the second side area SS2 and the third side area SS3, a third corner area CS3 that contacts the vertex connecting the second side SD2 and the fourth side SD4 and is disposed between the second side area SS2 and the fourth side area SS4, and a fourth corner area CS4 that contacts the vertex connecting the first side SD1 and the fourth side SD4 and is disposed between the first side area SS1 and the fourth side area SS4.

[0135] According to an embodiment, the display device 10 may further include a display driving circuit 500 implemented as an integrated circuit (IC) chip and mounted in a pad area PDA of a sub-region SBA of the substrate 110.

[0136] The display driving circuit 500 may provide a data signal Vdata (see Figure 8 and Figure 10 ) to the data lines DL of the circuit layer 120 (see Figure 8 and Figure 10 ).

[0137] According to an embodiment, the display device 10 may further include a circuit board bonded to a pad area PDA of a sub-region SBA of the substrate 110. The circuit board may be bonded to pads SPD (see Figure 6 ) provided in the sub-region SBA of the substrate 110 using a low-resistance and high-reliability material such as an anisotropic conductive film or a self-assembled anisotropic conductive paste (SAP).

[0138] As Figure 4 shown, the emission area EA may be arranged in the display area DA.

[0139] The circuit layer 120 (see Figure 5 ) may include emission pixel drivers EPD arranged side by side in a first direction DR1 and a second direction DR2.

[0140] As Figure 5 shown, the element layer 130 may include light-emitting elements LE respectively provided in the emission area EA (see Figure 8 , Figure 9 , Figure 10 and Figure 11 ).

[0141] The emission pixel drivers EPD of the circuit layer 120 (see Figure 4 , Figure 8 , Figure 9 , Figure 10 and Figure 11 ) may be electrically connected to the light-emitting elements LE of the element layer 130 (see Figure 8 , Figure 9 , Figure 10 and Figure 11 ).

[0142] According to an embodiment, the display panel 100 further includes a sealing layer 140 provided on the element layer 130 and a touch sensor layer 150 provided on the sealing layer 140.

[0143] The sealing layer 140 may be provided on the element layer 130 and may have a structure in which two or more inorganic films and at least one organic film are alternately stacked.

[0144] The touch sensor layer 150 may include touch electrodes for detecting signals that change according to the touch of a person or an object to sense the point where the touch of a person or an object has occurred in the main area MA.

[0145] According to an embodiment, the display panel 100 further includes a polarization layer 160 provided on the touch sensor layer 150 (see Figure 9 ).

[0146] The polarization layer 160 can prevent the deterioration of image visibility due to external light reflection by blocking external light reflected from the touch sensor layer 150, the sealing layer 140, the element layer 130, the circuit layer 120, and the interfaces between these layers.

[0147] Figure 6 is a layout diagram of a Figure 5 touch sensor layer according to an embodiment. Figure 7 is a diagram showing Figure 6 a detailed plan view of part D of

[0148] Figure 6 and Figure 7 show a capacitive touch sensor layer 150. In this case, the display device 10 may further include a touch driving circuit for sensing a touch based on whether a change in capacitance has occurred. The touch driving circuit may be mounted on the pad area PDA of the substrate 110 or on a circuit board. However, Figure 6 and Figure 7 are merely examples for explanation, and the touch sensor layer 150 according to the embodiment is not limited to Figure 6 and Figure 7 those shown in

[0149] For ease of explanation, Figure 6 only some of the components of the touch sensor layer 150 are shown.

[0150] Referring to Figure 6 , the touch sensor layer 150 may be disposed on the main area MA of the substrate 110. The touch sensor layer 150 may include a touch sensing area TSA for sensing a user's touch and a touch peripheral area TPA disposed around the touch sensing area TSA.

[0151] The touch sensing area TSA may be wider than the display area DA and may be similar to the display area DA. Therefore, the touch peripheral area TPA, which is the peripheral area of the touch sensing area TSA, may be similar to the non-display area NDA, which is the peripheral area of the display area DA.

[0152] As an example, the touch sensing area TSA may overlap with the edges of the display area DA and the non-display area NDA that are in contact with the display area DA. In this case, the touch peripheral area TPA may overlap with the remaining portion of the non-display area NDA that does not correspond to the touch sensing area TSA.

[0153] The touch sensor layer 150 may include sensor electrodes SE and dummy electrodes DE arranged in a matrix in the touch sensing area TSA and generating mutual capacitance, and sensor lines disposed in the touch peripheral area TPA.

[0154] The sensor electrode SE may include a touch driving electrode TE to which a touch driving signal is applied and a receiving electrode RE for sensing a voltage charged in a mutual capacitance manner with the touch driving electrode TE.

[0155] The sensor lines may include a first driving line TL1, a second driving line TL2, and a sensing line RL.

[0156] Each of the first driving line TL1 and the second driving line TL2 may be electrically connected to two or more touch driving electrodes TE that are connected to each other in the second direction DR2 among the touch driving electrodes TE.

[0157] The first driving line TL1 may extend from an edge at one side of the touch sensing area TSA adjacent to the sub-area SBA and extend in the first direction DR1 to reach the sub-area SBA.

[0158] The second driving line TL2 may extend from an edge at the other side of the touch sensing area TSA spaced apart from the sub-area SBA and extend in the first direction DR1, and be arranged parallel to the edge at one side of the touch sensing area TSA and extend in the second direction DR2 to reach the sub-area SBA.

[0159] The sensing line RL may be electrically connected to two or more receiving electrodes RE that are connected to each other in the first direction DR1 among the receiving electrodes RE.

[0160] The receiving electrodes RE may be arranged side by side in the first direction DR1. The receiving electrodes RE adjacent to each other in the first direction DR1 may be electrically connected to each other through a protruding portion in the first direction DR1.

[0161] The touch driving electrodes TE may be arranged side by side in the second direction DR2. The touch driving electrodes TE adjacent to each other in the second direction DR2 may be electrically connected to each other through a bridging electrode BE in the second direction DR2 (see Figure 7 ).

[0162] Each of the touch driving electrodes TE and the receiving electrodes RE may have a shape surrounding a dummy electrode DE provided at its center.

[0163] Each of the dummy electrodes DE may be spaced apart from the touch driving electrodes TE and the receiving electrodes RE surrounding each of the dummy electrodes DE. In an embodiment, the dummy electrodes DE are maintained in a floating state.

[0164] Although Figure 6The touch driving electrodes TE, the receiving electrodes RE, and the dummy electrodes DE have each been shown to have a rhombus shape in a plan view, but embodiments of the present disclosure are not limited thereto. As an example, the shape of each of the touch driving electrodes TE, the receiving electrodes RE, and the dummy electrodes DE in a plan view may be a circular shape, an elliptical shape, a quadrilateral shape other than a rhombus shape, or a polygonal shape other than a quadrilateral.

[0165] According to an embodiment, the display panel 100 includes pads SPD that are disposed in a pad region PDA of a sub-region SBA of the substrate 110 and are connected to a circuit board.

[0166] As an example, the display driving circuit 500 may be mounted in the pad region PDA.

[0167] The pad region PDA may include a display pad region DPDA adjacent to the display driving circuit 500 and a first touch pad region TPDA1 and a second touch pad region TPDA2 that are respectively disposed on both sides of the display pad region DPDA.

[0168] The pads SPD may include display signal pads DPD disposed in the display pad region DPDA and a first touch pad TPD1 and a second touch pad TPD2 that are respectively disposed in the first touch pad region TPDA1 and the second touch pad region TPDA2.

[0169] The display signal pads DPD may be electrically connected to the circuit layer 120 or the display driving circuit 500.

[0170] The first touch pad TPD1 may be electrically connected to a first driving line TL1 and a second driving line TL2.

[0171] The second touch pad TPD2 may be electrically connected to a sensing line RL.

[0172] Reference Figure 7 , the touch sensor layer 150 may further include bridging electrodes BE that electrically connect touch driving electrodes TE adjacent to each other in a second direction DR2.

[0173] The bridging electrodes BE may be electrically connected to the touch driving electrodes TE through touch electrode connection holes TCNT.

[0174] Touch driving electrodes TE adjacent to each other in the second direction DR2 may be electrically connected to each other through two or more bridging electrodes BE. In this way, the reliability of the electrical connection between the touch driving electrodes TE can be improved.

[0175] Although Figure 7Two bridging electrodes BE that are parallel to each other have been shown to be disposed between touch driving electrodes TE that are adjacent to each other in a second direction DR2, but embodiments of the present disclosure are not limited thereto.

[0176] Although Figure 7 a bridging electrode BE having a shape including a single bend has been shown, the shape of the bridging electrode BE is not limited thereto.

[0177] In an embodiment, the touch driving electrode TE and the receiving electrode RE are spaced apart from each other.

[0178] The bridging electrode BE may be disposed at a conductive layer different from the touch driving electrode TE and the receiving electrode RE.

[0179] Each of the touch driving electrode TE, the receiving electrode RE, and the bridging electrode BE may have a shape of a grid pattern or a mesh structure in a plan view. The dummy electrode DE may also have a shape of a grid pattern or a mesh structure in a plan view. In this way, the width of the emission region EA overlapping with the touch driving electrode TE, the receiving electrode RE, the dummy electrode DE, and the bridging electrode BE can be reduced. Therefore, a reduction in the luminous efficiency of the emission region EA caused by the touch driving electrode TE, the receiving electrode RE, the dummy electrode DE, and the bridging electrode BE can be alleviated.

[0180] Figure 8 is a schematic diagram showing an Figure 4 emission pixel driver according to an embodiment.

[0181] Referring to Figure 8 , the emission pixel driver EPD of the circuit layer 120 can be electrically connected between a first power line VDL that transmits a first power supply ELVDD (for example, a first power supply voltage) and a light emitting element LE of the element layer 130. One of the light emitting elements LE in the element layer 130 can be electrically connected between one of the emission pixel drivers EPD in the emission pixel driver EPD of the circuit layer 120 and a second power line VSL that transmits a second power supply ELVSS (for example, a second power supply voltage or a ground voltage).

[0182] That is, the anode electrode of the light emitting element LE can be electrically connected to the emission pixel driver EPD, and the second power supply ELVSS having a voltage level lower than that of the first power supply ELVDD can be applied to the cathode electrode of the light emitting element LE through the second power line VSL.

[0183] The capacitor Cel connected in parallel to the light emitting element LE represents the parasitic capacitance between the anode electrode and the cathode electrode.

[0184] The circuit layer 120 may include a first power line VDL that transmits a first power supply ELVDD, a gate initialization voltage line VGIL that transmits a gate initialization voltage VGINT, and an anode initialization voltage line VAIL that transmits an anode initialization voltage VAINT.

[0185] The circuit layer 120 may further include a scan write line GWL that transmits a scan write signal GW, a scan initialization line GIL that transmits a scan initialization signal GI, a transmission control line ECL that transmits a transmission control signal EC, and a gate control line GCL that transmits a gate control signal GC.

[0186] Meanwhile, since the scan write line GWL, the scan initialization line GIL, the transmission control line ECL, and the gate control line GCL are electrically connected to the gate electrodes of the second transistor T2 to the seventh transistor T7, hereinafter, they may be collectively referred to as the gate line GL.

[0187] One emission pixel driver EPD of the circuit layer 120 may include a first transistor T1 that generates a driving current for driving a light-emitting element LE, two or more transistors T2 to T7 electrically connected to the first transistor T1, and at least one capacitor (for example, a first capacitor PC1).

[0188] The first transistor T1 may be electrically connected between a first node N1 and a second node N2. The first node N1 is electrically connected to a first electrode (for example, a source electrode) of the first transistor T1.

[0189] The second node N2 is electrically connected to a second electrode (for example, a drain electrode) of the first transistor T1.

[0190] The first node N1 may be electrically connected to the first power line VDL through a fifth transistor T5.

[0191] The second node N2 may be electrically connected to the anode electrode of the light-emitting element LE through a sixth transistor T6.

[0192] The first capacitor PC1 may be electrically connected between the first power line VDL and a third node N3. The third node N3 is electrically connected to the gate electrode of the first transistor T1.

[0193] That is to say, the gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through the first capacitor PC1.

[0194] Therefore, the potential of the gate electrode of the first transistor T1 may be maintained as the voltage charged in the first capacitor PC1.

[0195] The second transistor T2 may be electrically connected between the data line DL and the first node N1.

[0196] The second transistor T2 can be electrically connected between the first electrode of the first transistor T1 and the data line DL.

[0197] That is to say, the first electrode of the first transistor T1 can be electrically connected to the data line DL through the second transistor T2.

[0198] The second transistor T2 can be turned on by the scan write signal GW of the scan write line GWL. For example, the gate electrode of the second transistor T2 can receive the scan write signal GW.

[0199] The fifth transistor T5 can be electrically connected between the first node N1 and the first power supply line VDL.

[0200] The sixth transistor T6 can be electrically connected between the second node N2 and the fourth node N4. The fourth node N4 is electrically connected to the anode electrode of the light-emitting element LE.

[0201] That is to say, the fifth transistor T5 can be electrically connected between the first electrode of the first transistor T1 and the first power supply line VDL.

[0202] The sixth transistor T6 can be electrically connected between the second electrode of the first transistor T1 and the anode electrode of the light-emitting element LE.

[0203] The fifth transistor T5 and the sixth transistor T6 can be turned on by the emission control signal EC of the emission control line ECL. For example, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 can receive the emission control signal EC.

[0204] When the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2, the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 can be the voltage difference between the first power supply ELVDD and the data signal Vdata.

[0205] In this case, when the voltage difference (i.e., the gate-source voltage difference) between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 is greater than or equal to the threshold voltage, the first transistor T1 is turned on, so that a drain-source current corresponding to the data signal Vdata of the first transistor T1 can be generated.

[0206] Subsequently, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first power supply line VDL for transmitting the first power supply ELVDD, the first transistor T1, the light-emitting element LE, and the second power supply line VSL for transmitting the second power supply ELVSS can be connected in series with each other. Therefore, the drain-source current corresponding to the data signal Vdata of the first transistor T1 can be provided as the drive current of the light-emitting element LE.

[0207] Therefore, the light-emitting element LE can emit light with a luminance corresponding to the data signal Vdata.

[0208] The third transistor T3 can be electrically connected between the second node N2 and the third node N3. That is to say, the third transistor T3 can be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0209] The third transistor T3 can include a plurality of sub-transistors connected in series with each other. As an example, the third transistor T3 can include a first sub-transistor T31 and a second sub-transistor T32.

[0210] The first electrode of the first sub-transistor T31 can be connected to the gate electrode of the first transistor T1, the second electrode of the first sub-transistor T31 can be connected to the first electrode of the second sub-transistor T32, and the second electrode of the second sub-transistor T32 can be connected to the second electrode of the first transistor T1.

[0211] In this way, it is possible to prevent the potential of the gate electrode of the first transistor T1 from changing due to the leakage current caused by the non-conducting third transistor T3.

[0212] The first sub-transistor T31 and the second sub-transistor T32 can be turned on by the scan write signal GW of the scan write line GWL. For example, the gate terminals of the first sub-transistor T31 and the second sub-transistor T32 can receive the scan write signal GW.

[0213] When the first sub-transistor T31 and the second sub-transistor T32 are turned on, the voltage difference between the second node N2 and the third node N3 can be initialized.

[0214] The fourth transistor T4 can be electrically connected between the gate initialization voltage line VGIL and the third node N3. That is to say, the fourth transistor T4 can be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL.

[0215] The fourth transistor T4 can include a plurality of sub-transistors connected in series with each other. As an example, the fourth transistor T4 can include a third sub-transistor T41 and a fourth sub-transistor T42.

[0216] The first electrode of the third sub-transistor T41 can be connected to the gate electrode of the first transistor T1, the second electrode of the third sub-transistor T41 can be connected to the first electrode of the fourth sub-transistor T42, and the second electrode of the fourth sub-transistor T42 can be connected to the gate initialization voltage line VGIL.

[0217] In this way, it is possible to prevent the potential of the gate electrode of the first transistor T1 from changing due to the leakage current caused by the non-conducting fourth transistor T4.

[0218] The third sub-transistor T41 and the fourth sub-transistor T42 can be turned on by a scan initialization signal GI of a scan initialization line GIL. For example, the gate terminals of the third sub-transistor T41 and the fourth sub-transistor T42 can receive the scan initialization signal GI.

[0219] When the third sub-transistor T41 and the fourth sub-transistor T42 are turned on, the potential of the third node N3 can be initialized to a gate initialization voltage VGINT.

[0220] The seventh transistor T7 can be electrically connected between a fourth node N4 and an anode initialization voltage line VAIL. That is to say, the seventh transistor T7 can be electrically connected between the anode electrode of the light-emitting element LE and the anode initialization voltage line VAIL.

[0221] The seventh transistor T7 can be turned on by a gate control signal GC of a gate control line GCL. For example, the gate terminal of the seventh transistor T7 can receive the gate control signal GC.

[0222] Through the turned-on seventh transistor T7, the potential of the fourth node N4 can be initialized to an anode initialization voltage VAINT.

[0223] As Figure 8 shown, according to an embodiment, the first transistor T1 to the seventh transistor T7 can be implemented as P-type metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0224] Figure 9 is a cross-sectional view taken along Figure 8 the line E-E' according to an embodiment of Figure 7 .

[0225] Referring to Figure 9 , according to an embodiment, the display panel 100 of the display device 10 includes a substrate 110, a circuit layer 120 provided on the substrate 110, and an element layer 130 provided on the circuit layer 120.

[0226] The display panel 100 of the display device 10 according to an embodiment further includes a sealing layer 140 provided on the element layer 130, a touch sensor layer 150 provided on the sealing layer 140, and a polarization layer 160 provided on the touch sensor layer 150.

[0227] According to an embodiment, the substrate 110 includes a first support layer 111, a barrier layer 112 provided on the first support layer 111, and a second support layer 113 provided on the barrier layer 112.

[0228] Each of the first support layer 111 and the second support layer 113 may include an organic insulating material that can be easily provided with a thickness sufficient to buffer external impurities or prevent external impurities from entering, or is an organic insulating material that can be easily provided with a thickness sufficient to buffer external impurities or prevent external impurities from entering. As an example, each of the first support layer 111 and the second support layer 113 may include polyimide (PI). In an embodiment, the support layers 111 and 113 include only PI.

[0229] The barrier layer 112 may include an inorganic insulating material different from the first support layer 111 and the second support layer 113 to prevent oxygen or moisture from penetrating into the substrate 110. In an embodiment, the barrier layer 112 includes only an inorganic insulating material.

[0230] The circuit layer 120 may include a first semiconductor layer disposed on the substrate 110, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, a second gate conductive layer disposed on the second gate insulating layer 123, an interlayer insulating layer 124 disposed on the second gate conductive layer, a first source / drain conductive layer disposed on the interlayer insulating layer 124, a first planarization layer 125 covering the first source / drain conductive layer, a second source / drain conductive layer disposed on the first planarization layer 125, and a second planarization layer 126 covering the second source / drain conductive layer.

[0231] According to an embodiment, the interlayer insulating layer 124 is disposed on the second gate insulating layer 123 and covers the second gate conductive layer.

[0232] The circuit layer 120 may further include a buffer layer 121 covering the substrate 110.

[0233] In this case, the first semiconductor layer may be disposed on the buffer layer 121.

[0234] The circuit layer 120 may include an emission pixel driver EPD corresponding to the emission region EA, respectively.

[0235] Each of the emission pixel drivers EPD may include a first transistor T1, second transistors T2 to seventh transistors T7 (see Figure 8 ) electrically connected to the first transistor T1, and at least one capacitor (e.g., a first capacitor PC1 (see Figure 8 ).

[0236] Figure 9 Shows Figure 8 The first transistor T1, the sixth transistor T6, and the light-emitting element LE of the emission pixel driver EPD of

[0237] The first semiconductor layer disposed on the buffer layer 121 may include channel portions CH1 and CH6, first electrode portions E11 and E16, and second electrode portions E21 and E26 of each of the first transistor T1 and the sixth transistor T6.

[0238] In each of the first transistor T1 and the sixth transistor T6, the first electrode portions E11 and E16 may be connected to one end of the channel portions CH1 and CH6, and the second electrode portions E21 and E26 may be connected to the other end of the channel portions CH1 and CH6.

[0239] The second electrode portion E21 of the first transistor T1 may be connected to the first electrode portion E16 of the sixth transistor T6.

[0240] The first gate conductive layer disposed on the first gate insulating layer 122 may include gate electrodes G1 and G6 of each of the first transistor T1 and the sixth transistor T6.

[0241] In each of the first transistor T1 and the sixth transistor T6, the gate electrodes G1 and G6 may overlap the channel portions CH1 and CH6, respectively.

[0242] Figure 8 The second transistor T2, the first sub-transistor T31, the second sub-transistor T32, the third sub-transistor T41, the fourth sub-transistor T42, the fifth transistor T5, and the seventh transistor T7 of the emission pixel driver EPD are implemented as the same P-type MOSFETs as the first transistor T1 and the sixth transistor T6, and thus the overlapping description will be omitted below.

[0243] The second gate conductive layer disposed on the second gate insulating layer 123 may include a capacitor electrode CAE.

[0244] The capacitor electrode CAE may overlap the gate electrode G1 of the first transistor T1.

[0245] Therefore, the first capacitor PC1 (see Figure 8 ) may be provided by an overlapping region between the capacitor electrode CAE and the gate electrode G1 of the first transistor T1.

[0246] The first source / drain conductive layer disposed on the interlayer insulating layer 124 may include a first anode connection electrode ANDE1.

[0247] The first anode connection electrode ANDE1 may be electrically connected to the second electrode portion E26 of the sixth transistor T6 through a first anode connection hole ANCH1.

[0248] The second source / drain conductive layer disposed on the first planarization layer 125 may include a second anode connection electrode ANDE2.

[0249] The second anode connection electrode ANDE2 may be electrically connected to the first anode connection electrode ANDE1 through a second anode connection hole ANCH2.

[0250] The anode electrode 131 of the element layer 130 may be disposed on the second planarization layer 126 and may be electrically connected to the second anode connection electrode ANDE2 through a third anode contact hole ANCH3.

[0251] Therefore, the anode electrode 131 may be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first anode connection electrode ANDE1 and the second anode connection electrode ANDE2.

[0252] The element layer 130 disposed on the circuit layer 120 may include light-emitting elements LE respectively disposed in the emission regions EA1, EA2, and EA3.

[0253] Each of the light-emitting elements LE may have a structure in which a light-emitting layer 133 is disposed between an anode electrode 131 and a cathode electrode 134 facing each other.

[0254] According to an embodiment, the element layer 130 includes an anode electrode 131 respectively disposed in the emission region EA, a pixel defining layer 132 disposed in the non-emission region NEA and covering the edge of the anode electrode 131, a partition layer 132' disposed on a part of the pixel defining layer 132, a light-emitting layer 133 respectively disposed on the anode electrode 131, and a cathode electrode 134 disposed on the light-emitting layer 133, the pixel defining layer 132, and the partition layer 132'.

[0255] Alternatively, the light-emitting element LE may further include a first functional layer 135 respectively disposed between the anode electrode 131 and the light-emitting layer 133 and a second functional layer 136 disposed between the light-emitting layer 133 and the cathode electrode 134, wherein the first functional layer 135 is respectively disposed on the anode electrode 131, and the second functional layer 136 is commonly disposed in the emission regions EA1, EA2, and EA3.

[0256] A sealing layer 140 may be disposed on the circuit layer 120 to cover the element layer 130.

[0257] The sealing layer 140 may prevent oxygen or moisture from penetrating into the element layer 130 and reduce an electrical shock or physical shock to the circuit layer 120 and the element layer 130.

[0258] The sealing layer 140 may include: a first sealing layer 141 disposed on the circuit layer 120 to cover the element layer 130; a second sealing layer 142 disposed on the first sealing layer 141 to overlap with the element layer 130; and a third sealing layer 143 disposed on the first sealing layer 141 to cover the second sealing layer 142. The sealing layers 141, 142, and 143 may include an inorganic insulating material or be an inorganic insulating layer.

[0259] The touch sensor layer 150 may be disposed on the sealing layer 140.

[0260] The touch sensor layer 150 may include a touch buffer layer 151 disposed on the sealing layer 140, a first touch conductive layer disposed on the touch buffer layer 151, a touch interlayer insulating layer 152 covering the first touch conductive layer, a second touch conductive layer disposed on the touch interlayer insulating layer 152, and a touch planarization layer 153 covering the second touch conductive layer.

[0261] The first touch conductive layer disposed on the touch buffer layer 151 may include a bridge electrode BE.

[0262] The second touch conductive layer disposed on the touch interlayer insulating layer 152 may include a touch driving electrode TE and a receiving electrode RE.

[0263] Similar to the touch driving electrode TE and the receiving electrode RE, dummy electrodes DE disposed inside each of the touch driving electrode TE and the receiving electrode RE, a first driving line TL1 and a second driving line TL2 connected to the touch driving electrode TE, and a sensing line RL connected to the receiving electrode RE may be disposed at the second touch conductive layer disposed on the touch interlayer insulating layer 152.

[0264] The touch driving electrode TE may be electrically connected to the bridge electrode BE through a touch electrode connection hole TCNT penetrating the touch interlayer insulating layer 152.

[0265] The touch buffer layer 151 may include an inorganic insulating material or be an inorganic insulating layer.

[0266] According to an embodiment, each of the touch interlayer insulating layer 152 and the touch planarization layer 153 includes an organic insulating material or is an organic insulating layer.

[0267] The polarization layer 160 may be disposed on the touch sensor layer 150.

[0268] Meanwhile, Figure 8The emission pixel driver EPD includes first to seventh transistors T1 to T7 implemented as P-type MOSFETs. However, this is an example, and some of the first to seventh transistors T1 to T7 may also be implemented as N-type MOSFETs. As an example, the third transistor T3 and the fourth transistor T4 may be implemented as N-type MOSFETs.

[0269] Figure 10 is a schematic diagram showing an Figure 4 equivalent circuit of the emission pixel driver according to an embodiment.

[0270] Except that the third transistor T3 and the fourth transistor T4 among the first to seventh transistors T1 to T7 of the emission pixel driver EPD are implemented as N-type MOSFETs, the circuit layer 120 of the display panel 100 according to Figure 10 the embodiment is substantially the same as Figure 8 the circuit layer 120, and thus the overlapping description will be omitted below.

[0271] According to Figure 10 the embodiment, the third transistor T3 is electrically connected between the second node N2 and the third node N3. That is, the third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0272] The third transistor T3 is implemented as an N-type MOSFET, and thus, it can be turned on by the gate control signal GC of the gate control line GCL.

[0273] The voltage difference between the second node N2 and the third node N3 can be initialized by the turned-on third transistor T3.

[0274] The fourth transistor T4 may be electrically connected between the gate initialization voltage line VGIL and the third node N3. That is, the fourth transistor T4 may be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL.

[0275] The fourth transistor T4 can be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0276] The potential of the third node N3 can be initialized by the turned-on fourth transistor T4.

[0277] The third transistor T3 is implemented as an N-type MOSFET, and thus, the seventh transistor T7 can be turned on by the bias control signal GB of the bias control line GBL instead of the gate control signal GC of the gate control line GCL. For example, the gate electrode of the seventh transistor T7 may receive the bias control signal GB.

[0278] Meanwhile, since the bias control line GBL is electrically connected to the gate electrode of the seventh transistor T7, hereinafter, the bias control line GBL will be collectively referred to as the gate line GL together with the scan write line GWL, the scan initialization line GIL, the emission control line ECL, and the gate control line GCL.

[0279] Figure 11 is a cross-sectional view taken along line E-E' according to an embodiment of Figure 10 Figure 7 .

[0280] In addition to the auxiliary interlayer insulating layer 127, the third gate insulating layer 128, and the second semiconductor layer and the third gate conductive layer for implementing the N-type MOSFET, the circuit layer 120 of the display panel 100 according to the embodiment of Figure 11 Figure 11 is substantially the same as the circuit layer 120 of Figure 9 , and thus the overlapping description will be omitted hereinafter.

[0281] Figure 11 shows the light-emitting element LE and the transistors T1 to T7 of the emission pixel driver EPD (see Figure 10 ), among which the first transistor T1, the second transistor T2, and the sixth transistor T6 are implemented as P-type MOSFETs, and the fourth transistor T4 is implemented as an N-type MOSFET.

[0282] According to an embodiment of Figure 11 , the circuit layer 120 includes an interlayer insulating layer 124 provided on the substrate 110, a first source / drain conductive layer provided on the interlayer insulating layer 124, a first planarization layer 125 covering the first source / drain conductive layer, a second source / drain conductive layer provided on the first planarization layer 125, and a second planarization layer 126 covering the second source / drain conductive layer.

[0283] According to an embodiment of Figure 11 , the circuit layer 120 may further include a first semiconductor layer provided on the substrate 110, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer provided on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, and a second gate conductive layer provided on the second gate insulating layer 123.

[0284] According to an embodiment of Figure 11In an embodiment, the circuit layer 120 further includes an auxiliary interlayer insulating layer 127 covering the second gate conductive layer, a second semiconductor layer disposed on the auxiliary interlayer insulating layer 127, a third gate insulating layer 128 covering the second semiconductor layer, and a third gate conductive layer disposed on the third gate insulating layer 128 and covered by the interlayer insulating layer 124.

[0285] According to Figure 11 In the embodiment shown in, the circuit layer 120 further includes a barrier layer 129 disposed on the substrate 110 and a first light-blocking layer LB1 disposed on the barrier layer 129 and covered by the buffer layer 121.

[0286] The first semiconductor layer disposed on the buffer layer 121 may include channel portions CH1, CH2, and CH6, first electrode portions E11, E12, and E16, and second electrode portions E21, E22, and E26 of each of the first transistor T1, the second transistor T2, and the sixth transistor T6 implemented as P-type MOSFETs.

[0287] The first gate conductive layer disposed on the first gate insulating layer 122 may include gate electrodes G1, G2, and G6 of each of the first transistor T1, the second transistor T2, and the sixth transistor T6 implemented as P-type MOSFETs.

[0288] The fifth transistor T5 and the seventh transistor T7 have the same structure as the first transistor T1, the second transistor T2, and the sixth transistor T6, and thus overlapping descriptions will be omitted below.

[0289] In each of the first transistor T1, the second transistor T2, and the sixth transistor T6, the channel portions CH1, CH2, and CH6 may overlap with the gate electrodes G1, G2, and G6, respectively.

[0290] The channel portion CH1 of the first transistor T1 may overlap with the first light-blocking layer LB1 disposed below the buffer layer 121.

[0291] In each of the first transistor T1, the second transistor T2, and the sixth transistor T6, the first electrode portions E11, E12, and E16 may be connected to one end of the channel portions CH1, CH2, and CH6, and the second electrode portions E21, E22, and E26 may be connected to the other end of the channel portions CH1, CH2, and CH6.

[0292] The first electrode portion E11 of the first transistor T1 may be connected to the second electrode portion E22 of the second transistor T2.

[0293] The second electrode portion E21 of the first transistor T1 may be connected to the first electrode portion E16 of the sixth transistor T6.

[0294] The second gate conductive layer disposed on the second gate insulating layer 123 may include a capacitor electrode CAE and a second light blocking layer LB2.

[0295] The second semiconductor layer disposed on the auxiliary interlayer insulating layer 127 may include a channel portion CH4, a first electrode portion E14, and a second electrode portion E24 of a fourth transistor T4 implemented as an N-type MOSFET.

[0296] The third gate conductive layer disposed on the third gate insulating layer 128 may include a gate electrode G4 of a fourth transistor T4 implemented as an N-type MOSFET.

[0297] In the fourth transistor T4, the channel portion CH4 may overlap with the second light blocking layer LB2 disposed below the auxiliary interlayer insulating layer 127.

[0298] The channel portion CH4 of the fourth transistor T4 may overlap with the gate electrode G4 of the fourth transistor T4.

[0299] The first electrode portion E14 of the fourth transistor T4 may be connected to one end of the channel portion CH4 of the fourth transistor T4, and the second electrode portion E24 of the fourth transistor T4 may be connected to the other end of the channel portion CH4 of the fourth transistor T4.

[0300] The third transistor T3 is implemented by the same N-type MOSFET as the fourth transistor T4, and thus the description of the overlap will be omitted below.

[0301] The first source / drain conductive layer disposed on the interlayer insulating layer 124 may include a first anode connection electrode ANCE1, a data connection electrode DOE, a gate initialization voltage line VGIL, and a node auxiliary connection electrode NACE.

[0302] The second source / drain conductive layer disposed on the first planarization layer 125 may include a second anode connection electrode ANCE2 and a data line DL.

[0303] The data connection electrode DOE may be electrically connected to the first electrode portion E12 of the second transistor T2 through a first data connection hole DCH1.

[0304] The data line DL may be electrically connected to the data connection electrode DOE through a second data connection hole DCH2.

[0305] Therefore, the data line DL may be electrically connected to the first electrode portion E12 of the second transistor T2 through the data connection electrode DOE.

[0306] The gate initialization voltage line VGIL can be electrically connected to the first electrode portion E14 of the fourth transistor T4 through the gate initialization voltage connection hole VGCH.

[0307] The node auxiliary connection electrode NACE can be electrically connected to the second electrode portion E24 of the fourth transistor T4 through the node auxiliary connection hole NACH.

[0308] According to Figure 11 The element layer 130, the sealing layer 140, the touch sensor layer 150, and the polarization layer 160 of the display panel 100 according to the embodiment shown in Figure 9 are substantially the same as those of the display panel 100 according to the embodiment shown in

[0309] and thus the overlapping description will be omitted below.

[0310] Meanwhile, according to the embodiment, in order to facilitate mass production, a plurality of display panels 100 can be aligned side by side on the mother substrate and then separated from the mother substrate to manufacture the display panel 100. However, since the barrier layer 112 of the substrate 110 includes an inorganic insulating material, cracks occur in the barrier layer 112 due to physical and chemical impacts during the process of separating the display panel 100 from the mother substrate.

[0311] In addition, in the display panel 100 according to the embodiment, the peripheral display area PSA at the edge of the display area DA is transformed into a curved shape. Therefore, in the process of transforming the peripheral display area PSA into a curved shape, the cracks in the barrier layer 112 may increase, or the existing cracks in the barrier layer 112 may expand. As a result, a substrate peeling defect in which the second support layer 113 is separated from the first support layer 111 may occur, thereby reducing the lifespan and product reliability of the display device 10.

[0311] To prevent such defects, according to the embodiment, the barrier layer 112 of the substrate 110 is not provided on the entire interface between the first support layer 111 and the second support layer 113, but is not provided in the crack protection area CPTA (see Figure 12 ) that contacts at least a part of the edge of the substrate 110.

[0312] That is, according to the embodiment, in the crack protection area CPTA (see Figure 12 ) that contacts at least a part of the edge of the substrate 110 where the cracks in the barrier layer 112 may increase or expand, since the barrier layer 112 is removed, it is possible to prevent the barrier layer 112 from being directly exposed during the process of separating the display panel 100 from the mother substrate.

[0313] Figure 12 is a plan view showing a display panel according to an embodiment.Figure 13 is a cross-sectional view of a display panel taken along line F-F’ shown in Figure 12 .

[0314] As Figure 12 shown in, a substrate 110 of a display panel 100 according to an embodiment includes a main area MA, and the main area MA includes a display area DA disposed at the center of a display surface and a non-display area NDA disposed around the display area DA and not emitting light.

[0315] The main area MA may correspond to the display surface.

[0316] Edges of the main area MA may include a fifth side SD5 and a sixth side SD6 extending in a first direction DR1 and facing each other, a seventh side SD7 and an eighth side SD8 extending in a second direction DR2 and connected between the fifth side SD5 and the sixth side SD6 and facing each other, a first corner VT1 connecting the fifth side SD5 and the seventh side SD7, a second corner VT2 connecting the sixth side SD6 and the seventh side SD7, a third corner VT3 connecting the sixth side SD6 and the eighth side SD8, and a fourth corner VT4 connecting the fifth side SD5 and the eighth side SD8.

[0317] A substrate 110 according to an embodiment includes a crack protection area CPTA in contact with at least a part of one or more edges of the substrate 110.

[0318] According to an embodiment, the crack protection area CPTA is in contact with a first corner VT1, a second corner VT2, a third corner VT3, and a fourth corner VT4 of an edge of the main area MA. For example, the crack protection area CPTA may include at least one of a first sub-area in contact with the first corner VT1, a second sub-area in contact with the second corner VT2, a third sub-area in contact with the third corner VT3, and a fourth sub-area in contact with the fourth corner VT4.

[0319] That is, according to an embodiment, the crack protection area CPTA is disposed between each of a first corner area CS1, a second corner area CS2, a third corner area CS3, and a fourth corner area CS4 included in a double-curved area and an edge of the main area MA, and may extend while being in contact with each of the first corner VT1, the second corner VT2, the third corner VT3, and the fourth corner VT4.

[0320] In an embodiment, the crack protection area CPTA is disposed between a dam area DMA and an edge of the substrate 110. That is, the crack protection area CPTA may be in contact with at least a part of the edge of the substrate 110 and may be spaced apart from the dam area DMA.

[0321] In addition, considering the margin in the process of separating the display panel 100 from the mother substrate, the crack protection region CPTA may be formed to have a thickness of about 75 micrometers (μm) or more in a direction perpendicular to the edge of the substrate 110.

[0322] Reference Figure 13 , according to an embodiment, the substrate 110 of the display panel 100 of the display device 10 includes a first support layer 111, a barrier layer 112 provided on a part of the first support layer 111, and a second support layer 113 covering the barrier layer 112.

[0323] According to an embodiment, the barrier layer 112 is provided on the first support layer 111 in a region other than the crack protection region CPTA.

[0324] As a result, in the crack protection region CPTA, due to the removed barrier layer 112, the second support layer 113 may be in direct contact with the first support layer 111.

[0325] Therefore, in the crack protection region CPTA, the barrier layer 112 is not provided between the first support layer 111 and the second support layer 113. Therefore, since the barrier layer 112 may not be directly exposed during the process of separating the display panel 100 from the mother substrate, cracks in the barrier layer 112 can be reduced.

[0326] In addition, as Figure 12 and Figure 13 shown, according to an embodiment, the barrier layer 112 overlaps with the display area DA of the main area MA and extends to the non-display area NDA to further overlap with the dam area DMA.

[0327] As Figure 13 shown, according to an embodiment, like the front display area FSA, the peripheral display area CS2_PSA of the display area DA includes an emission area EA. Therefore, the element layer 130 may include a light-emitting element LE provided in the emission area EA of the peripheral display area CS2_PSA, and the circuit layer 120 may include an emission pixel driver EPD electrically connected to the light-emitting element LE of the peripheral display area CS2_PSA. In addition, the touch sensor layer 150 may include a receiving electrode RE (see Figure 6 and Figure 7 ) and a touch driving electrode TE and a bridging electrode BE provided in the peripheral display area CS2_PSA.

[0328] According to an embodiment, the display panel 100 of the display device 10 further includes at least one dam portion DM1 and DM2 disposed in the dam area DMA of the non-display area NDA. The crack protection region CPTA may be spaced apart from the dam area DMA.

[0329] As an example, at least one dam portion provided in the dam region DMA may include a first dam portion DM1 surrounding the display region DA and a second dam portion DM2 surrounding the first dam portion DM1.

[0330] At least one dam portion provided in the dam region DMA may further include at least one auxiliary dam portion ADM1 and ADM2 disposed between the display region DA and the first dam portion DM1 and surrounding the display region DA.

[0331] As an example, at least one auxiliary dam portion ADM1 and ADM2 may include a first dam layer DML13 and DML14 respectively provided on the second planarization layer 126 and a second dam layer DML23 and DML24 provided on the first dam layer DML13 and DML14.

[0332] Each of at least one dam portion DM1, DM2, ADM1 or ADM2 provided in the dam region DMA of the non-display region NDA may include two or more dam layers DML11, DML21 and DML31; DML12, DML22, DML32 and DML42; DML13 and DML23; or DML14 and DML24.

[0333] Each of two or more dam layers DML11, DML21 and DML31; DML12, DML22, DML32 and DML42; DML13 and DML23; or DML14 and DML24 may be provided on the same layer as one of the first planarization layer 125, the second planarization layer 126, the pixel defining layer 132 and the spacer layer 132’ (see Figure 9 and Figure 11 ).

[0334] The first dam portion DM1 may include a first dam layer DML11 provided on the same layer as the second planarization layer 126, a second dam layer DML21 provided on the same layer as the pixel defining layer 132, and a third dam layer DML31 provided on the same layer as the spacer layer 132’.

[0335] The second dam portion DM2 may include a first dam layer DML12 provided on the same layer as the first planarization layer 125, a second dam layer DML22 provided on the same layer as the second planarization layer 126, a third dam layer DML32 provided on the same layer as the pixel defining layer 132, and a fourth dam layer DML42 provided on the same layer as the spacer layer 132’.

[0336] The first dam layer DML13 of the first auxiliary dam portion ADM1 and the first dam layer DML14 of the second auxiliary dam portion ADM2 may be disposed on the same layer as the pixel defining layer 132.

[0337] The second dam layer DML23 of the first auxiliary dam portion ADM1 and the second dam layer DML24 of the second auxiliary dam portion ADM2 may be disposed on the same layer as the spacer layer 132’.

[0338] The circuit layer 120 of the display panel 100 of the display device 10 may further include a power supply line VSPL disposed in the non-display area NDA for transmitting a power supply ELVDD or ELVSS (see Figure 8 , Figure 9 , Figure 10 and Figure 11 ) for driving the light-emitting elements LE (see Figure 8 and 10 ).

[0339] The power supply line VSPL may transmit a first power supply ELVDD (see Figure 8 and Figure 10 ) or a second power supply ELVSS (see Figure 8 and Figure 10 ).

[0340] As an example, the power supply line VSPL may transmit the second power supply ELVSS (see Figure 8 and Figure 10 ).

[0341] The power supply line VSPL may include a first line layer VSPLL1 disposed on the same layer as the first source / drain conductive layer and a second line layer VSPLL2 disposed on the same layer as the second source / drain conductive layer.

[0342] The first planarization layer 125 and the second planarization layer 126 are removed in the region between the first dam portion DM1 and the second dam portion DM2 that are spaced apart from each other in the dam region DMA, and thus, the second line layer VSPLL2 may be in direct contact with the first line layer VSPLL1. Accordingly, the second line layer VSPLL2 may be electrically connected to the first line layer VSPLL1.

[0343] According to an embodiment, the circuit layer 120 further includes a cathode extension line 134’ disposed in the non-display area NDA.

[0344] The cathode extension line 134’ may be disposed on the same layer as the anode electrode 131. That is, the cathode extension line 134’ may be disposed on the second planarization layer 126. The cathode extension line 134’ may cover corresponding portions of the line layers VSPLL1 and VSPLL2.

[0345] When the power supply line VSPL transmits the second power supply ELVSS (see Figure 10 and Figure 12 ), the cathode extension line 134' can extend from the edge of the display area DA to the dam area DMA.

[0346] The pixel defining layer 132 and the partition layer 132' are removed in the region between the first dam portion DM1 and the second auxiliary dam portion ADM2 that are spaced apart from each other. Therefore, the cathode extension line 134' can be in direct contact with the second line layer VSPLL2 of the power supply line VSPL. Thus, the cathode extension line 134' can be electrically connected to the power supply line VSPL.

[0347] The display panel 100 of the display device 10 according to an embodiment further includes a capping portion CPP that overlaps the dam area DMA.

[0348] The capping portion CPP can be used to protect the inorganic insulating material located at the uppermost end of at least one of the dam portions DM1 and DM2 arranged in the dam area DMA from the etching process for setting the second touch conductive layer.

[0349] According to an embodiment, at least one of the dam portions DM1, DM2, ADM1, or ADM2 arranged in the dam area DMA is used to limit the diffusion range of the organic insulating material of the second sealing layer 142 of the sealing layer 140 and can have a relatively large step from the substrate 110. However, the touch interlayer insulating layer 152 of the touch sensor layer 150 can include an organic insulating material, and at least one of the dam portions DM1, DM2, ADM1, or ADM2 may not be completely covered by the touch interlayer insulating layer 152. In this case, the inorganic insulating material located on at least one of the dam portions DM1, DM2, ADM1, or ADM2 may be exposed to the etching process for setting the second touch conductive layer. To prevent this, the display panel 100 according to an embodiment can include a capping portion CPP that covers at least one of the dam portions DM1, DM2, ADM1, or ADM2.

[0350] The capping portion CPP can be provided on the same layer as the first touch conductive layer.

[0351] As described above, according to an embodiment, the crack protection area CPTA in which the barrier layer 112 of the inorganic insulating material among the substrates 110 is removed contacts the four corners VT1, VT2, VT3, and VT4 of the main area MA.

[0352] That is, in the crack protection area CPTA contacting the four corners VT1 , VT2 , VT3 , and VT4 of the main area MA, the barrier layer 112 is not exposed during a cutting process of separating the display panel 100 from the mother substrate, thereby reducing cracks of the barrier layer 112 .

[0353] Therefore, the four corners VT1, VT2, VT3, and VT4 of the main area MA can be transformed into a curved shape with a double curvature together with the first corner area CS1, the second corner area CS2, the third corner area CS3, and the fourth corner area CS4. Therefore, even when a relatively high bending stress is applied, separation defects of the substrate 110 caused by cracks in the barrier layer 112 can be prevented.

[0354] According to an embodiment, the crack protection area CPTA contacts not only the four corners VT1 , VT2 , VT3 , and VT4 of the main area MA among the edges of the substrate 110 , but also other portions of the edges of the substrate 110 .

[0355] Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 19 is a plan view of a display panel according to an embodiment.

[0356] In addition to the crack protection area CPTA of the substrate 110 being in contact with the remaining portion of the edge of the main area MA except for the portion connected to the sub-area SBA, according to Figure 14 The display panel 100 of the display device 10 of the embodiment is the same as the display panel 100 according to Figure 12 and Figure 13 The display device 10 of the embodiment shown in FIG. 1 is substantially the same, and thus overlapping descriptions will be omitted below. For example, the crack protection area CPTA may completely surround the non-display area NDA except for a portion adjacent to the sub-area SBA.

[0357] like Figure 14 As shown in FIG. 5 , according to an embodiment, the sub-region SBA may protrude from at least a portion of the fifth side SD5 of the main region MA.

[0358] according to Figure 14 In the embodiment, the crack protection area CPTA is also in contact with the seventh side SD7, the sixth side SD6 and the eighth side SD8 among the edges of the main area MA, and is also in contact with a portion of the fifth side SD5 of the main area MA except the portion in contact with the sub-area SBA.

[0359] The crack protection area CPTA can be provided between the dam area DMA and the edge of the substrate 110. That is to say, the crack protection area CPTA can be in contact with at least a part of the edge of the substrate 110 and can be spaced apart from the dam area DMA.

[0360] In addition, considering the margin of the process of separating the display panel 100 from the mother substrate, the crack protection area CPTA can be formed to have a thickness of about 75 μm or more in a direction perpendicular to the edge of the substrate 110.

[0361] According to an embodiment, a part of the edge of the main area MA other than the part in contact with the sub-area SBA is exposed to the cutting process of separating the display panel 100 from the mother substrate.

[0362] According to Figure 14 the embodiment, the crack protection area CPTA from which the barrier layer 112 has been removed is in contact with a part of the edge of the main area MA other than the part in contact with the sub-area SBA, and thus, the barrier layer 112 may not be exposed to the cutting process at the said part of the edge of the main area MA. Therefore, cracks in the barrier layer 112 can be further reduced.

[0363] Therefore, since the peripheral display area PSA of the display area DA is transformed into a curved shape, even when bending stress is applied to the edge of the main area MA, separation defects of the substrate 110 due to cracks in the barrier layer 112 can be prevented.

[0364] Except that the crack protection area CPTA of the substrate 110 further includes the bending area BA of the sub-area SBA, the display panel 100 of the display device 10 according to Figure 15 the embodiment is substantially the same as the display device 10 according to the embodiment shown in Figure 14 and thus the overlapping description will be omitted below.

[0365] According to an embodiment, the pad area PDA of the sub-area SBA is provided on the rear surface of the substrate 110 through the bending area BA transformed into a curved shape and can overlap with the main area MA.

[0366] According to Figure 15 the embodiment, the crack protection area CPTA can not only be in contact with the edge of the main area MA, but also include the bending area BA.

[0367] In this way, the barrier layer 112 of the substrate 110 can be removed from the bending area BA, thereby reducing cracks in the barrier layer 112 caused by the bending stress due to the bent bending area BA.

[0368] In addition to the crack protection region CPTA of the substrate 110 also contacting a portion of the edge of the sub-region SBA other than the portion of the sub-region SBA connected to the main region MA, according to Figure 16 the display panel 100 of the display device 10 according to the embodiment of Figure 14 is substantially the same as the display device 10 shown in

[0369] According to the embodiment, a portion of the edge of the sub-region SBA other than the portion contacting the main region MA is exposed to the cutting process for separating the display panel 100 from the mother substrate.

[0370] According to Figure 16 the embodiment, the crack protection region CPTA from which the barrier layer 112 has been removed contacts the portions exposed to the cutting process at each of the edge of the main region MA and the edge of the sub-region SBA. That is, since the barrier layer 112 is removed from the edge of the substrate 110 on which the cutting process is performed, the barrier layer 112 is not exposed to the cutting process, thereby further reducing cracks in the barrier layer 112.

[0371] Therefore, separation defects of the substrate 110 due to cracks in the barrier layer 112 can be further prevented.

[0372] According to Figure 17 the embodiment, the display panel 100 of the display device 10 is Figure 15 a combination of the embodiment of Figure 16 and the embodiment of

[0373] In addition to the crack protection region CPTA including the non-display region NDA of the main region MA, according to Figure 18 the display panel 100 of the display device 10 according to the embodiment of Figures 1 to 17 is substantially the same as the embodiment shown in

[0374] According to Figure 18 the embodiment, the crack protection region CPTA may include a non-display region NDA, which is the main region MA other than the display region DA.

[0375] That is, according to Figure 18 the embodiment, the barrier layer 112 only overlaps with the display region DA of the main region MA.

[0376] In this way, the first semiconductor layer of the display region DA can be disposed relatively flatly on the substrate 110 including the barrier layer 112. Therefore, P-type MOSFET transistors T1 to T7 included in each emission pixel driver EPD can be prevented (seeFigure 8 ) and the characteristics of the P-type MOSFET transistors T1, T2, and T5 to T7 (see Figure 10 ) deteriorate in uniformity.

[0377] That is, while it is possible to prevent deterioration in the uniformity of the characteristics of the P-type MOSFET transistors T1 to T7 provided in the display area DA (see Figure 8 ) and the P-type MOSFET transistors T1, T2, and T5 to T7 (see Figure 10 ), the barrier layer 112 can be spaced apart from the edge of the main area MA as much as possible, and thus, cracks in the barrier layer 112 can be further reduced.

[0378] Except that the circuit layer 120 further includes a gate driver in the gate circuit region GDRA provided in the non-display area NDA and the barrier layer 112 extends in the non-display area NDA to further overlap with the gate circuit region GDRA, the display panel 100 of the display device 10 according to Figure 19 's embodiment is substantially the same as the embodiment shown in Figure 18 , and thus the overlapping description will be omitted below.

[0379] According to the embodiment, the display panel 100 may further include a gate driver (e.g., a gate driver circuit) that provides a gate signal to the gate line GL.

[0380] In the display area DA, the gate line GL may extend in the first direction DR1.

[0381] The gate line GL may include a scan write-in line GWL (see Figure 8 and Figure 10 ), a scan initialization line GIL (see Figure 8 and Figure 10 ), an emission control line ECL (see Figure 8 and Figure 10 ), and a gate control line GCL (see Figure 8 and Figure 10 ).

[0382] The gate line GL may further include a bias control line GBL (see Figure 10 ).

[0383] According to Figure 19 's embodiment, the gate driver may be mounted in the circuit layer 120.

[0384] That is, according to Figure 19 's embodiment, the non-display area NDA may further include a gate circuit region GDRA facing at least one side of the display area DA in the first direction DR1.

[0385] The circuit layer 120 may include a gate driver disposed in a gate driver region GDRA of a non-display area NDA.

[0386] The gate driver may include at least one P-type MOSFET transistor.

[0387] According to Figure 19 an embodiment, the barrier layer 112 may extend to the non-display area NDA to further overlap with the gate driver region GDRA. In this way, the gate driver in the gate driver region GDRA may be arranged to be relatively flat on the substrate 110 including the barrier layer 112. Therefore, while deterioration of the characteristic uniformity of the transistors included in the gate driver can be prevented, the barrier layer 112 can be spaced apart from the edge of the main area MA as much as possible, and thus, cracks in the barrier layer 112 can be further reduced.

[0388] However, the effects of the present disclosure are not limited to those discussed above. By referring to the claims, the above and other effects of the present disclosure may become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

Claims

1. A display device, comprising: a display panel to emit light for displaying an image, Wherein, the display panel comprises: substrate; and a circuit layer, disposed on the substrate; and A component layer is arranged on the circuit layer, The main area of ​​the substrate includes a display area where an emission area is arranged and a non-display area arranged around the display area, The display area includes a front display area and a peripheral display area disposed around the front display area and having a curved shape, The substrate comprises: a first supporting layer; a barrier layer disposed on a portion of the first support layer; and a second supporting layer, covering the barrier layer, The substrate further includes a crack protection region in contact with at least a portion of an edge of the substrate, and In the crack protection region, the second supporting layer is in contact with the first supporting layer.

2. The display device according to claim 1, in, The front display area includes a first side and a second side extending in a first direction and opposite to each other, and a third side and a fourth side extending in a second direction crossing the first direction and opposite to each other, The peripheral display area includes: A first side region, a second side region, a third side region and a fourth side region are in contact with the first side, the second side, the third side and the fourth side of the front display region, respectively; a first corner region contacting a vertex at which the first side and the third side meet and disposed between the first side region and the third side region; a second corner region contacting a vertex at which the second side and the third side meet and disposed between the second side region and the third side region; a third corner region contacting the vertex at which the second side and the fourth side meet and disposed between the second side region and the fourth side region; and A fourth corner region contacts a vertex at which the first side and the fourth side meet and is disposed between the first side region and the fourth side region.

3. The display device according to claim 2, wherein: The barrier layer overlaps the display area of ​​the main area.

4. The display device according to claim 3, in, The element layer includes light emitting elements respectively arranged in the emission regions, and The circuit layer comprises: an emission pixel driver arranged in the first direction and the second direction in the display area and electrically connected to the light emitting elements, respectively; a gate line extending in the first direction and transmitting a gate signal to the emission pixel driver; and a gate driver disposed in a gate circuit region of at least one side of the non-display region facing the display region in the first direction and providing the gate signal to the gate line, Wherein, the blocking layer extends to the non-display area to further overlap with the gate circuit area.

5. The display device according to claim 3, wherein: The display panel further includes: a sealing layer, disposed on the element layer; and at least one dam portion arranged in a dam region of the non-display region surrounding the display region and spaced apart from the display region, wherein the barrier layer extends to the non-display area and also overlaps with the dam area, and The crack protection region is disposed between the dam region and the edge of the substrate.

6. The display device according to claim 1, wherein: The edge of the main area includes: a fifth side and a sixth side extending in the first direction and facing each other; a seventh side and an eighth side extending in a second direction intersecting the first direction and facing each other; a first corner at which the fifth side and the seventh side meet; a second corner, the sixth side and the seventh side meeting at the second corner; a third corner at which the sixth side and the eighth side meet; and a fourth corner at which the fifth side and the eighth side meet, and The crack protection region contacts at least one of the first corner, the second corner, the third corner, and the fourth corner.

7. The display device according to claim 6, in, The substrate further comprises a sub-region protruding from at least a portion of the fifth side, The crack protection region is also in contact with the seventh side, the sixth side and the eighth side, The crack protection region also contacts a portion of the fifth side of the edge of the main region except a portion contacting the sub-region.

8. The display device according to claim 7, in, The sub-region includes a bending region adjacent to the main region and a pad region adjacent to the bending region, and The crack protection region includes the bending region.

9. The display device according to claim 7, wherein: The crack protection region also contacts a portion of an edge of the sub-region other than a portion of the sub-region adjacent to the main region.

10. The display device according to claim 2, wherein: Each of the first supporting layer and the second supporting layer includes an organic insulating material, and the barrier layer includes an inorganic insulating material.

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