Display device

Abstract

The display device includes a pixel electrode disposed on a substrate; a pixel defining layer disposed on the substrate and provided with an opening exposing the pixel electrode; a light emitting layer disposed on the pixel electrode; a common electrode disposed on the light emitting layer and including a first layer; a first bank disposed on the pixel defining layer; and a second bank disposed on the first bank, in which a side surface of the second bank protrudes more than a corresponding side surface of the first bank, and the first layer includes a first element and a second element, in which the first element is silver (Ag) and the second element is a group XV element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2023-0182183, filed on December 14, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a display device. Background Art

[0004] With the development of the information age, the demand for display devices for displaying images has increased in various forms. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigators, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. Among such flat panel display devices, a light emitting display device includes a light emitting element in which each of the pixels of a display panel can emit light by itself, thereby displaying an image even in the absence of a backlight unit that provides light to the display panel.

[0005] Recently, a display device has been applied to a glasses-type device to provide virtual reality and augmented reality. In order to be applied to the glasses-type device, the display device is implemented in a very small size of 2 inches or less, and it is desired that the display device has a high pixel integration so that the display device can be implemented with a high resolution. For example, the display device may have a high pixel integration of 400 pixels per inch (PPI) or more. Summary of the invention

[0006] As described above, the display device applied to the glasses-type device is implemented in a very small size, but when the display device has a high pixel integration, the area of ​​the light-emitting region of the display device in which the light-emitting element is disposed is reduced. Therefore, it may be difficult to implement a light-emitting element separated for each light-emitting region through a mask process.

[0007] Embodiments of the present disclosure provide a display device that can form a light emitting element separated for each light emitting region without a mask process.

[0008] Another embodiment of the present disclosure provides a display device in which the contact resistance of a common electrode of a light emitting element is low.

[0009] The embodiments of the present disclosure are not limited to those mentioned above, and other objects of the present disclosure not mentioned herein will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0010] According to an embodiment of the present disclosure, a display device includes: a pixel electrode disposed on a substrate; a pixel defining layer disposed on the substrate and having an opening exposing the pixel electrode; a light-emitting layer disposed on the pixel electrode; a common electrode disposed on the light-emitting layer and including a first layer; a first bank disposed on the pixel defining layer; and a second bank disposed on the first bank, wherein a side surface of the second bank protrudes more than a corresponding side surface of the first bank, and the first layer includes a first element and a second element, wherein the first element is silver (Ag), and the second element is a Group XV element.

[0011] In an embodiment, a ratio of the second element to a total number of atoms included in the first layer may be in a range of about 0.2 atomic percent (at%) to about 5.0 at%.

[0012] In an embodiment, the second element may be one or both selected from bismuth (Bi) and antimony (Sb).

[0013] In an embodiment, the first layer may further include a third element including at least one selected from copper (Cu), zinc (Zn), indium (In), and tin (Sn).

[0014] In an embodiment, a sum of ratios of the second element and the third element to the total number of atoms included in the first layer may be about 0.5 at% or more.

[0015] In an embodiment, a ratio of the second element to the total number of atoms included in the first layer may be greater than a ratio of the third element to the total number of atoms included in the first layer.

[0016] In an embodiment, the common electrode may further include a second layer including at least one selected from pure silver (pure Ag) and an AgMg alloy.

[0017] In an embodiment, the first layer may be disposed on the light-emitting layer, and the second layer may be disposed on the first layer.

[0018] In an embodiment, the second layer may be disposed on the light-emitting layer, and the first layer may be disposed on the second layer.

[0019] In an embodiment, a thickness of the common electrode may be in the range of about to about

[0020] In an embodiment, a thickness of the first layer may be 0.8 times to 1.2 times a thickness of the second layer.

[0021] In an embodiment, the display device may further include an auxiliary electrode disposed on the common electrode.

[0022] ​In an embodiment, the auxiliary electrode may include a transparent conductive oxide (TCO).

[0023] In an embodiment, the display device may further include a residual pattern disposed between the upper surface of the pixel electrode and the lower surface of the pixel defining layer.

[0024] According to an embodiment of the present disclosure, a display device includes: a pixel electrode disposed on a substrate; a pixel defining layer disposed on the substrate and having an opening exposing the pixel electrode; a light-emitting layer disposed on the pixel electrode; a common electrode disposed on the light-emitting layer and including a first element and a second element, wherein the first element is silver (Ag) and the second element is a Group XV element; a first bank disposed on the pixel defining layer; a second bank disposed on the first bank, wherein a side surface of the second bank protrudes more than a corresponding side surface of the first bank; a first inorganic layer disposed on the common electrode and the second bank; and an organic encapsulation layer disposed between the second bank and the first inorganic layer.

[0025] In an embodiment, the common electrode may include: a first layer containing a first element and a second element, wherein the first element is silver (Ag) and the second element is a Group XV element; and a second layer including at least one selected from pure silver (pure Ag) and an AgMg alloy.

[0026] In an embodiment, the first inorganic layer may be in contact with a lower surface of the second bank.

[0027] In an embodiment, the organic encapsulation layer may be in contact with a side surface of the second bank.

[0028] According to an embodiment of the present disclosure, a display device includes: a pixel electrode disposed on a substrate; a pixel defining layer disposed on the substrate and having an opening exposing the pixel electrode; a light-emitting layer disposed on the pixel electrode; a common electrode disposed on the light-emitting layer and including a first layer; a first bank disposed on the pixel defining layer; and a second bank disposed on the first bank, wherein a side surface of the second bank protrudes more than a corresponding side surface of the first bank, and the first layer includes a first element, a second element, and a third element, wherein the first element is silver (Ag), the second element is one or both selected from bismuth (Bi) and antimony (Sb), the third element includes at least one selected from copper (Cu), zinc (Zn), indium (In), and tin (Sn), and a ratio of the first element to a total number of atoms included in the first layer is about 95.0 at% or more.

[0029] In an embodiment, the thickness of the common electrode may be in the range of about to about

[0030] In a display device according to an embodiment, a common electrode having a thin thickness and a low resistance can be provided, and viewing angle characteristics and / or light emission characteristics can be improved.

[0031] The effects according to the embodiments of the present disclosure are not limited to those mentioned above, and more various effects are included in the following description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other features of the embodiments of the present disclosure will become more apparent by describing the embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0033] Figure 1 is a perspective view showing a display device according to an embodiment;

[0034] Figure 2 is a cross-sectional view showing the Figure 1 display device as viewed from the side;

[0035] Figure 3 is a plan view showing the arrangement of light-emitting regions in a display region of a display device according to an embodiment;

[0036] Figure 4 is a cross-sectional view showing a part of a display device according to an embodiment;

[0037] Figure 5 is a view showing Figure 4 an enlarged view of region A1;

[0038] Figure 6 is a cross-sectional view showing an agglomeration phenomenon of a common electrode;

[0039] Figure 7 shows the agglomeration phenomenon of Comparative Example 1 observed using a scanning electron microscope (SEM);

[0040] Figure 8 shows the agglomeration phenomenon of Comparative Example 2 observed using an atomic force microscope (AFM);

[0041] Figure 9 shows the surface of Example 1 observed using AFM; and

[0042] Figures 10 to 12 is a cross-sectional view of a part of a display device according to various embodiments. DETAILED DESCRIPTION

[0043] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments of the invention are shown. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0044] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, no intervening elements are present. Throughout the specification, like reference numerals refer to like components.

[0045] It will be understood that although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the present invention, the first element discussed below could be termed the second element. Similarly, the second element could also be termed the first element.

[0046] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, “a”, “an”, “the” and “at least one” do not denote a limitation of quantity, but rather are intended to include both the singular and the plural, unless the context clearly dictates otherwise. Thus, a reference to “an” element in a claim and subsequent reference to “the” element includes one element and a plurality of elements. For example, “an element” has the same meaning as “at least one element” unless the context clearly dictates otherwise. “At least one” should not be construed as limiting “a” or “an”. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms “comprises” and / or “comprising”, or “includes” and / or “including” specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0047] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe a relationship of one element to another element as shown in the figures. It will be understood that the relative terms are intended to include different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is flipped, an element described as on the "lower" side of other elements will then be oriented on the "upper" side of the other elements. Thus, depending on the particular orientation of the figure, the term "lower" can encompass both the "lower" and "upper" orientations. Similarly, if the device in one of the figures is flipped, an element described as "below" or "beneath" other elements will then be oriented "above" the other elements. Thus, the terms "below" or "beneath" can encompass both the above and below orientations.

[0048] In view of the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the terms "about" or "approximate" as used herein include the recited value and mean within an acceptable deviation range of a particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the recited value.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms such as those defined in a commonly used dictionary should be understood to have a meaning that is consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0050] Embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Accordingly, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments described herein are not to be construed as limited to the particular shapes of regions as shown herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, regions shown or described as flat will generally have rough and / or non-linear features. Additionally, sharp corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the exact shape of a region, but are intended to limit the scope of the claims.

[0051] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0052] Figure 1 is a perspective view showing a display device according to an embodiment.

[0053] Reference Figure 1, the display device 10 according to an embodiment may be included in an electronic device to provide a screen in the electronic device. The electronic device may refer to all electronic devices that provide a display screen. For example, a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smartphone, a tablet personal computer (PC), an electronic watch, smart glasses, a smartwatch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notepad, an e-book, a portable multimedia player (PMP), a navigator, a gaming machine, a digital camera, a camcorder, etc., which provide a display screen, may be included in the electronic device.

[0054] The shape of the display device 10 may be variously modified. In an embodiment, for example, the display device 10 may have a shape similar to a rectangular shape in a plan view, the rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded to have a certain curvature, but it is not limited thereto and may be formed at right angles. The planar shape of the display device 10 may be formed to be similar to other polygonal shapes, circular shapes, or elliptical shapes, and is not limited to the rectangular shape.

[0055] In an embodiment, the display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400 (shown in Figure 2 ).

[0056] The display panel 100 may include a main area MA and a sub-area SBA.

[0057] The main area MA may include a display area DA including pixels for displaying an image and a non-display area NDA provided near the display area DA. The display area DA may emit light from a plurality of light-emitting areas or a plurality of opening areas. In an embodiment, for example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining a light-emitting area or an opening area, and a self-luminous element.

[0058] In an embodiment, for example, the self-luminous element may include at least one of an organic light-emitting diode (LED) including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but the present disclosure is not limited thereto.

[0059] A plurality of pixels, a plurality of scan lines, a plurality of data lines, and a plurality of power lines may be provided in the display area DA. Each of the plurality of pixels may be defined as a minimum unit for emitting light, and each of the above self-emitting elements may be respective pixels. The plurality of scan lines may supply scan signals received from a scan driver to the plurality of pixels. The plurality of data lines may supply data voltages received from the display driver 200 to the plurality of pixels. The plurality of power lines may supply power voltages received from the display driver 200 to the plurality of pixels.

[0060] The non-display area NDA may be an external area of the display area DA. The non-display area NDA may be defined as an edge area of the main area MA of the display panel 100. The non-display area NDA may include a scan driver for supplying scan signals to the scan lines and fan-out lines for connecting the display driver 200 to the display area DA.

[0061] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material capable of undergoing bending, folding, curling, etc. In an embodiment, for example, in a state where the sub-area SBA is bent, the sub-area SBA may overlap the main area MA in the thickness direction (third direction DR3). The sub-area SBA may include the display driver 200 and a pad portion connected to the circuit board 300. In another embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be provided in the non-display area NDA.

[0062] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to the data lines. The display driver 200 may supply power voltages to the power lines and supply a scan control signal to the scan driver. The display driver 200 may be formed of an integrated circuit (IC) and may be packaged on the display panel 100 by a chip on glass (COG) mode, a chip on plastic (COP) mode, or an ultrasonic bonding mode. In an embodiment, for example, the display driver 200 may be provided in the sub-area SBA and may overlap the main area MA in the thickness direction (third direction DR3) by bending the sub-area SBA. In another embodiment, for example, the display driver 200 may be packaged on the circuit board 300.

[0063] The circuit board 300 may be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0064] Figure 2 is shown as viewed from the sideFigure 1 Cross-sectional view of the display device. Specifically, Figure 2 relates to the side surface of the Figure 1 display device in the folded state.

[0065] Refer to Figure 2 , in an embodiment, the display panel 100 may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0066] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate capable of withstanding bending, folding, curling, etc. In an embodiment, for example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0067] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may further include a scan line, a data line, a power line, a scan control line, a fan-out line for connecting the display driver 200 to the data line, and a lead for connecting the display driver 200 to the pad portion. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. In an embodiment, for example, when the scan driver is formed on one side of the non-display area NDA of the display panel 100, the scan driver may include a thin film transistor.

[0068] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, the scan line, the data line, and the power line of each pixel of the thin film transistor layer TFTL may be disposed in the display area DA. The scan control line and the fan-out line of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0069] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements and a pixel defining layer defining a pixel, and the plurality of light emitting elements include a first electrode, a second electrode, and a light emitting layer for emitting light. The plurality of light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

[0070] In an embodiment, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin-film transistor of the thin-film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and may combine with each other in the organic light-emitting layer to emit light.

[0071] In another embodiment, the light-emitting element may include a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, or a micro LED.

[0072] The thin-film encapsulation layer TFEL may cover the upper surface and sides of the light-emitting element layer EML and protect the light-emitting element layer EML. The thin-film encapsulation layer TFEL may include at least one inorganic film and at least one organic film to encapsulate the light-emitting element layer EML.

[0073] The color filter layer CFL may be disposed on the thin-film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters corresponding to a plurality of light-emitting regions, respectively. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of another wavelength. The color filter layer CFL may absorb a part of the light introduced from the outside of the display device 10 to reduce the reflected light caused by external light. Therefore, the color filter layer CFL may prevent the occurrence of color distortion caused by external light reflection.

[0074] In an embodiment, the color filter layer CFL is directly disposed on the thin-film encapsulation layer TFEL, such that the display device 10 may not include a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively reduced.

[0075] In some embodiments, the display device 10 may further include an optical device. The optical device may emit or receive light in the infrared, ultraviolet, or visible wavelength bands. In an embodiment, for example, the optical device may be an optical sensor for sensing the light incident on the display device 10, such as a proximity sensor, an illuminance sensor, a camera sensor, a fingerprint sensor, or an image sensor.

[0076] Figure 3 is a plan view showing a part of a display device according to an embodiment. Figure 3 is a plan view showing the arrangement of the light-emitting regions EA1, EA2, and EA3 in the display region DA of the display device 10.

[0077] Reference Figure 3, an embodiment of the display device 10 may include a plurality of light-emitting regions EA1, EA2, and EA3 disposed in the display area DA. The light-emitting regions EA1, EA2, and EA3 may include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3 that emit lights of different colors, respectively. In the embodiment, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may emit red light, green light, or blue light, respectively, and the color of the light emitted from each of the light-emitting regions EA1, EA2, and EA3 may be different according to the type of light-emitting elements ( Figure 4 "ED1", "ED2", and "ED3") therein. In the embodiment, for example, the first light-emitting region EA1 may emit a first light of red color, the second light-emitting region EA2 may emit a second light of green color, and the third light-emitting region EA3 may emit a third light of blue color. However, the present disclosure is not limited thereto.

[0078] The plurality of light-emitting regions EA1, EA2, and EA3 may be arranged in a type, for example, a diamond type. In the embodiment, for example, the first light-emitting region EA1 and the third light-emitting region EA3 may be arranged to be spaced apart from each other in a first direction DR1, and may be alternately arranged in the first direction DR1 and a second direction DR2. The second light-emitting region EA2 may be spaced apart from another adjacent second light-emitting region EA2 in the first direction DR1 and the second direction DR2. The second light-emitting region EA2 and the first light-emitting region EA1 or the second light-emitting region EA2 and the third light-emitting region EA3 may be alternately arranged along any direction in the plane formed by the first direction DR1 and the second direction DR2.

[0079] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be defined by a pixel defining layer ( Figure 4 "PDL") to be described later.

[0080] Figure 4 is a cross-sectional view showing a part of the display device according to an embodiment. Specifically, Figure 4 is Figure 3 a cross-sectional view of a part taken along line I-I', and shows cross-sections of a substrate SUB, a thin film transistor layer TFTL, a light-emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0081] The thin film transistor layer TFTL may include a first buffer layer BF1, an underlying metal layer (not shown), a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0082] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing air or moisture penetration. In an embodiment, for example, the first buffer layer BF1 may include a plurality of inorganic films stacked alternately.

[0083] The underlying metal layer (not shown) may be disposed on the first buffer layer BF1. In an embodiment, for example, the underlying metal layer may be formed of or defined by a single layer or multiple layers, and each layer in the underlying metal layer includes at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, or is made of at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0084] The second buffer layer BF2 may cover the first buffer layer BF1 and the underlying metal layer. The second buffer layer BF2 may include an inorganic film capable of preventing air or moisture penetration. In an embodiment, for example, the second buffer layer BF2 may include a plurality of inorganic films stacked alternately.

[0085] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute the pixel circuit of each of the plurality of pixels. In an embodiment, for example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0086] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the underlying metal layer and the gate electrode GE in the thickness direction DR3 and may be insulated from the gate electrode GE by the gate insulating layer GI. In a part of the semiconductor layer ACT, the material of the semiconductor layer ACT may become a conductor to form the source electrode SE and the drain electrode DE.

[0087] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT in the thickness direction DR3, and the gate insulating layer GI is interposed therebetween.

[0088] The gate insulating layer GI can be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI can cover the semiconductor layer ACT and the second buffer layer BF2, and can insulate the semiconductor layer ACT and the gate electrode GE from each other. The gate insulating layer GI can include a contact hole through which the first connection electrode CNE1 passes.

[0089] The first interlayer insulating layer ILD1 can cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 can be provided with a contact hole through which the first connection electrode CNE1 extends or is provided. The contact hole of the first interlayer insulating layer ILD1 can be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0090] The capacitor electrode CPE can be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE can overlap with the gate electrode GE in the thickness direction DR3. The capacitor electrode CPE and the gate electrode GE can form a capacitance.

[0091] The second interlayer insulating layer ILD2 can cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 can be provided with a contact hole through which the first connection electrode CNE1 extends or is provided. The contact hole of the second interlayer insulating layer ILD2 can be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0092] The first connection electrode CNE1 can be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 can electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 can be inserted into the contact holes defined or formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0093] The first passivation layer PAS1 can cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 can protect the thin film transistor TFT. The first passivation layer PAS1 can include a contact hole through which the second connection electrode CNE2 passes.

[0094] The second connection electrode CNE2 can be disposed on the first passivation layer PAS1. The second connection electrode CNE2 can electrically connect the first connection electrode CNE1 to the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED to each other. The second connection electrode CNE2 can be inserted into the contact hole formed in the first passivation layer PAS1 and contact the first connection electrode CNE1.

[0095] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may be provided with contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light-emitting element ED extend or are provided.

[0096] The light-emitting element layer EML may be provided on the thin-film transistor layer TFTL. The light-emitting element layer EML may include a light-emitting element ED, a pixel defining layer PDL, and a bank structure BNS. The light-emitting element ED may include pixel electrodes AE1, AE2, and AE3, light-emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3.

[0097] Figure 5 is an enlarged view showing a first light-emitting region (specifically Figure 4 region A1).

[0098] In addition to Figure 4 also refer to Figure 5 , an embodiment of the display device 10 may include a plurality of light-emitting regions EA1, EA2, and EA3 provided in the display area DA. The light-emitting regions EA1, EA2, and EA3 may be defined as regions in which the pixel electrodes AE1, AE2, and AE3, the light-emitting layers EL1, EL2, and EL3, and the common electrodes CE1, CE2, and CE3 overlap each other in the thickness direction DR3 of the substrate SUB. The light-emitting regions EA1, EA2, and EA3 may include regions in which light is emitted from the light-emitting elements ED1, ED2, and ED3 and passes through the color filter layer CFL in the third direction DR3. In the light-emitting elements ED1, ED2, and ED3, the pixel electrodes AE1, AE2, and AE3, the light-emitting layers EL1, EL2, and EL3, and the common electrodes CE1, CE2, and CE3 are stacked in sequence. The light-emitting regions EA1, EA2, and EA3 may include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3 that are spaced apart from each other and emit light of the same color or different colors.

[0099] In an embodiment, the areas or sizes of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be the same as each other. In an embodiment, for example, in the display device 10, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have the same size (e.g., planar area) as each other, but is not limited thereto. In an embodiment of the display device 10, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have different areas or sizes from each other. In an embodiment, for example, the size of the second light-emitting region EA2 may be larger than the size of each of the first light-emitting region EA1 and the third light-emitting region EA3, and the size of the third light-emitting region EA3 may be larger than the size of the first light-emitting region EA1. The intensities of the light emitted from the respective light-emitting regions EA1, EA2, and EA3 may vary according to the sizes of the light-emitting regions EA1, EA2, and EA3, and the sizes of the light-emitting regions EA1, EA2, and EA3 may be adjusted so that the color of the image displayed on the display device 10 can be controlled. In an embodiment, as Figure 4 shown, the sizes of the light-emitting regions EA1, EA2, and EA3 may be the same as each other, but is not limited thereto.

[0100] In an embodiment of the display device 10, one first light-emitting region EA1, one second light-emitting region EA2, and one third light-emitting region EA3 that are adjacent to each other may form a pixel group. A pixel group may include the light-emitting regions EA1, EA2, and EA3 that emit light of different colors, thereby representing a white gray level, but the present disclosure is not limited thereto. The combination of the light-emitting regions EA1, EA2, and EA3 that constitute a pixel group may be variously modified according to the arrangement of the light-emitting regions EA1, EA2, and EA3 and the colors of the light emitted from the light-emitting regions EA1, EA2, and EA3.

[0101] The display device 10 may include a plurality of light-emitting elements ED1, ED2, and ED3 that are respectively provided in different light-emitting regions EA1, EA2, and EA3. The light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1 provided in the first light-emitting region EA1, a second light-emitting element ED2 provided in the second light-emitting region EA2, and a third light-emitting element ED3 provided in the third light-emitting region EA3.

[0102] The light-emitting elements ED1, ED2, and ED3 may include pixel electrodes AE1, AE2, and AE3, light-emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3, and the light-emitting elements ED1, ED2, and ED3 respectively disposed in different light-emitting regions EA1, EA2, and EA3 may emit lights of different colors according to the materials of the light-emitting layers EL1, EL2, and EL3. In an embodiment, for example, the first light-emitting element ED1 disposed in the first light-emitting region EA1 may emit first light of a first color having a peak wavelength in the range of 610 nanometers (nm) to 650 nm, the second light-emitting element ED2 disposed in the second light-emitting region EA2 may emit second green light having a peak wavelength in the range of 510 nm to 550 nm, and the third light-emitting element ED3 disposed in the third light-emitting region EA3 may emit third blue light having a peak wavelength in the range of 440 nm to 480 nm. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 constituting one pixel group may include light-emitting elements ED1, ED2, and ED3 that emit lights of different colors to represent a white gray level. Optionally, since the light-emitting layers EL1, EL2, and EL3 may include two or more materials that emit lights of different colors, one light-emitting layer may emit mixed light. In an embodiment, for example, the light-emitting layers EL1, EL2, and EL3 may simultaneously include a material for emitting red light and a material for emitting green light to emit yellow light, or may include all of a material for emitting red light, a material for emitting green light, and a material for emitting blue light to emit white light.

[0103] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer PAS2. The pixel electrodes AE1, AE2, and AE3 may be respectively disposed in the plurality of light-emitting regions EA1, EA2, and EA3. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in the first light-emitting region EA1, a second pixel electrode AE2 disposed in the second light-emitting region EA2, and a third pixel electrode AE3 disposed in the third light-emitting region EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be spaced apart from each other on the second passivation layer PAS2.

[0104] The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin-film transistor TFT through a first connection electrode CNE1 and a second connection electrode CNE2. The edges of the spaced pixel electrodes AE1, AE2, and AE3 may be covered by a pixel defining layer PDL so that the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be insulated from each other.

[0105] The pixel electrodes AE1, AE2, and AE3 may include a transparent electrode material and / or a conductive metal material, and may have a single-layer structure or a multi-layer structure. The conductive metal material may include at least one selected from silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), titanium (Ti), and titanium nitride (TiN). The transparent electrode material may include at least one selected from indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).

[0106] The pixel defining layer PDL may be disposed on the second passivation layer PAS2, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may be disposed on the second passivation layer PAS2, and may cover the sides of the pixel electrodes AE1, AE2, and AE3 and the residual pattern RP, and have an opening to expose a part of the upper surface of the pixel electrodes AE1, AE2, and AE3. In an embodiment, for example, the pixel defining layer PDL may define an opening for exposing the first pixel electrode AE1 in the first light-emitting region EA1, and the first light-emitting layer EL1 may be directly disposed on the first pixel electrode AE1.

[0107] The pixel defining layer PDL may include an inorganic insulating material. The pixel defining layer PDL may include at least one selected from silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, tantalum oxide, hafnium oxide, zinc oxide, and amorphous silicon, but the present disclosure is not limited thereto.

[0108] According to an embodiment, the pixel defining layer PDL is disposed on the pixel electrodes AE1, AE2, and AE3, and may be spaced apart from the upper surfaces of the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may not directly contact the upper surfaces of the pixel electrodes AE1, AE2, and AE3, while overlapping a part of the upper surfaces of the pixel electrodes AE1, AE2, and AE3 in the thickness direction DR3 of the substrate SUB, and the residual pattern RP may be disposed between the lower surface of the pixel defining layer PDL and the upper surfaces of the pixel electrodes AE1, AE2, and AE3. However, the pixel defining layer PDL may directly contact the sides of the pixel electrodes AE1, AE2, and AE3. The corresponding sides of the pixel defining layer PDL (i.e., the sides of the pixel defining layer PDL corresponding to the light-emitting regions EA1, EA2, and EA3 or the sides of the pixel defining layer PDL defining the opening) may protrude more inwardly toward the center of the light-emitting regions EA1, EA2, and EA3 than the corresponding sides of the second bank BN2.

[0109] The residual pattern RP can be disposed on the edges of each of the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may not directly contact the upper surfaces of the pixel electrodes AE1, AE2, and AE3 due to the residual pattern RP. The residual pattern RP may include a metal or an oxide semiconductor material. In the drawings, only the sides of the residual pattern RP pointing to the light emitting regions EA1, EA2, and EA3 are shown as being more recessed than the sides of the pixel defining layer PDL, but the present disclosure is not limited thereto. The corresponding sides of the residual pattern RP may protrude more toward the center of the light emitting regions EA1, EA2, and EA3 than the corresponding sides of the pixel defining layer PDL, or may be aligned with the corresponding sides of the pixel defining layer PDL. The corresponding sides of the pixel defining layer PDL may be the innermost sides pointing to the light emitting regions EA1, EA2, and EA3.

[0110] The light emitting layers EL1, EL2, and EL3 may be disposed on the pixel electrodes AE1, AE2, and AE3. The light emitting layers EL1, EL2, and EL3 may be organic light emitting layers including or made of an organic material, and may be formed on the pixel electrodes AE1, AE2, and AE3 by a deposition process. The light emitting layers EL1, EL2, and EL3 may have a multilayer structure, and each of a hole injection material, a hole transport material, a light emitting material, an electron transport material, and an electron injection material may constitute a layer. When the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3 of the light emitting elements ED1, ED2, and ED3 receive a common voltage or a cathode voltage, holes and electrons may be injected and transported, and the holes and electrons may be combined with each other in the light emitting layers EL1, EL2, and EL3 to emit light.

[0111] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3 disposed in different light-emitting regions EA1, EA2, and EA3, respectively. The first light-emitting layer EL1 may be disposed on a first pixel electrode AE1 in the first light-emitting region EA1, the second light-emitting layer EL2 may be disposed on a second pixel electrode AE2 in the second light-emitting region EA2, and the third light-emitting layer EL3 may be disposed on a third pixel electrode AE3 in the third light-emitting region EA3. The plurality of light-emitting layers EL1, EL2, and EL3 may emit lights of different colors, or one of the light-emitting layers EL1, EL2, and EL3 may emit mixed light. In an embodiment, the first light-emitting layer EL1 may emit red light, the second light-emitting layer EL2 may emit green light, and the third light-emitting layer EL3 may emit blue light. In another embodiment, the first light-emitting layer EL1 may emit yellow light as a mixture of red light and green light, and the second light-emitting layer EL2 may emit blue light. In yet another embodiment, the first light-emitting layer EL1 may emit white light as a mixture of red light, green light, and blue light.

[0112] The light-emitting layers EL1, EL2, and EL3 may be disposed on an upper surface of the pixel defining layer PDL. In an embodiment, a part of the light-emitting layers EL1, EL2, and EL3 may be disposed in a space between the pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL. In an embodiment, the light-emitting layers EL1, EL2, and EL3 may be in contact with the pixel defining layer PDL, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3.

[0113] The common electrodes CE1, CE2, and CE3 may be disposed on the light-emitting layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 may include a transparent conductive material so that light generated from the light-emitting layers EL1, EL2, and EL3 can be emitted. The common electrodes CE1, CE2, and CE3 may receive a common voltage or a low-potential voltage. When the pixel electrodes AE1, AE2, and AE3 receive voltages corresponding to data voltages and the common electrodes CE1, CE2, and CE3 receive low-potential voltages, a potential difference may be formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3, such that the light-emitting layers EL1, EL2, and EL3 can emit light.

[0114] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3 disposed in different light-emitting regions EA1, EA2, and EA3, respectively. The first common electrode CE1 may be disposed on the first light-emitting layer EL1 in the first light-emitting region EA1, the second common electrode CE2 may be disposed on the second light-emitting layer EL2 in the second light-emitting region EA2, and the third common electrode CE3 may be disposed on the third light-emitting layer EL3 in the third light-emitting region EA3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be spaced apart from each other.

[0115] The common electrodes CE1, CE2, and CE3 may include a first element and a second element, where the first element is silver (Ag) and the second element is a Group XV element. The common electrodes CE1, CE2, and CE3 may have a single-layer structure or a multi-layer structure and may include a first layer that includes the first element and the second element, where the first element is silver (Ag) and the second element is a Group XV element. In an embodiment, the second element may be one or both selected from bismuth (Bi) and antimony (Sb).

[0116] In the case where the common electrodes CE1, CE2, and CE3 do not include the second element (Group XV element) and include only silver (Ag), agglomeration occurs in a very thin film. Figure 6 and Figure 7 are a cross-sectional view and a scanning electron microscope (SEM) image showing the agglomeration phenomenon of the common electrode CE1a (Comparative Example 1) containing only silver (Ag). Refer to Figure 6 , it is shown that the common electrode CE1a deposited on the side surface of the first bank BN1 is agglomerated. Figure 7 shows the agglomeration phenomenon occurring in the thickness silver (Ag) electrode observed using a scanning electron microscope (SEM). Agglomeration of the common electrodes CE1, CE2, and CE3 may increase the contact resistance and cause deterioration of the light-emitting elements ED1, ED2, and ED3.

[0117] Agglomeration may also occur when the common electrodes CE1, CE2, and CE3 include elements other than Group XV elements in addition to silver (Ag). Figure 8 are atomic force microscope (AFM) images showing the agglomeration phenomenon of the common electrodes CE1, CE2, and CE3 (Comparative Example 2) containing an Ag-In alloy or an Ag-Pd-Cu alloy. Figure 8 shows the surface of the alloy film after heat treatment of the thickness alloy film at 250 °C for one hour observed by AFM. Figure 8The surface roughness measured in the Ag-In alloy is about 12.1 nanometers (nm), and the surface roughness measured in the Ag-Pd-Cu alloy is about 7.3 nm.

[0118] In an embodiment, when the first element (silver (Ag)) and the second element (Group XV element) are simultaneously included in the common electrodes CE1, CE2, and CE3, no agglomeration phenomenon occurs. Figure 9 It is an atomic force microscope (AFM) image showing the agglomeration phenomenon of the common electrodes CE1, CE2, and CE3 (Example 1) including the Ag-Bi alloy or the Ag-Sb alloy. Figure 9 It shows what was observed by AFM The surface of the alloy film after heat treatment of the alloy film with a thickness of one hour at 250 °C. Figure 9 The surface roughness measured in the Ag-Bi alloy is about 0.8 nm, and the surface roughness measured in the Ag-Sb alloy is about 0.6 nm. When both the first element (silver (Ag)) and the second element (Group XV element) are included in the common electrodes CE1, CE2, and CE3, it can be seen that the surface roughness is significantly reduced and no agglomeration phenomenon occurs.

[0119] Figure 10 and Figure 11 They are cross-sectional views respectively showing a part of a display device in which the common electrode has a multilayer structure according to an embodiment. Figure 5 In the embodiment of, the first common electrode CE1 has a single-layer structure of the first layer CE1, and the first layer CE1 includes the first element and the second element, where the first element is silver (Ag) and the second element is a Group XV element, and Figure 10 In the embodiment of, the first common electrode CE1' and Figure 11 In the embodiment of, the first common electrode CE1” has a multilayer structure including other layers in addition to the first layer CE11 or CE11'.

[0120] In an embodiment, the ratio of the second element to the total number of atoms included in the first layer CE1, CE11, or CE11' can be in the range of about 0.2 atomic percent (at%) to about 5.0 at%. In an embodiment, the ratio of the second element to the total number of atoms included in the first layer CE1, CE11, or CE11' can be in the range of about 0.5 at% to about 3.0 at%. In such an embodiment where the ratio of the second element to the total number of atoms included in the first layer CE1, CE11, or CE11' is within the above range, the electrode can be formed uniformly, and agglomeration of silver (Ag) can be effectively prevented. The elemental ratio or atomic ratio can be obtained by transmission electron microscopy (TEM) or energy-dispersive X-ray (EDX) compositional analysis.

[0121] In an embodiment, in addition to the first element and the second element, the first layer CE1, CE11 or CE11' may further include a third element. The third element may be at least one selected from copper (Cu), zinc (Zn), indium (In), and tin (Sn).

[0122] In an embodiment, the ratio of the third element to the total number of atoms included in the first layer CE1, CE11 or CE11' may be in the range of about 0.2 at% to about 3.0 at%. In such an embodiment where the ratio of the third element to the total number of atoms included in the first layer CE1, CE11 or CE11' is within the above range, the electrode may have a thin thickness. In an embodiment, the sum of the ratios of the second element and the third element to the total number of atoms included in the first layer CE1, CE11 or CE11' may be about 0.5 at% or greater, for example, in the range of about 0.5 at% to about 3.0 at%. The second element and the third element included in the first layer CE1, CE11 or CE11' may have the same ratio to each other or different atomic ratios. In an embodiment, for example, the ratio of the second element included in the first layer CE1, CE11 or CE11' may be greater than the ratio of the third element included in the first layer CE1, CE11 or CE11'.

[0123] The ratio of the first element (silver (Ag)) included in the first layer CE1, CE11 or CE11' may be significantly greater than the ratio of the second element and / or the third element in the first layer CE1, CE11 or CE11'. The ratio of the first element to the total number of atoms included in the first layer CE1, CE11 or CE11' may be about 95.0 at% or greater, for example, in the range of about 95.0 at% to about 99.8 at%, or in the range of about 97.0 at% to about 99.5 at%.

[0124] In some embodiments, the common electrode CE1' or CE1” may include the first layer CE11 or CE11' and the second layer CE12 or CE12', respectively. The second layer CE12 or CE12' may include one or both selected from pure silver (pure Ag) and AgMg alloy.

[0125] Reference Figure 10 , in an embodiment, the first layer CE11 may be disposed on the light-emitting layer EL1, and the second layer CE12 may be disposed on the first layer CE11. Reference Figure 11 , in an embodiment, the second layer CE12' may be disposed on the light-emitting layer EL1, and the first layer CE11' may be disposed on the second layer CE12'.

[0126] The common electrodes CE1, CE1' or CE1'' may have a thin thickness. In an embodiment, the thicknesses t1, t11 + t12 or t11' + t12' of each of the common electrodes CE1, CE1' and CE1'' may be in the range of about to about , or in the range of about to about . The common electrodes CE1, CE1' and CE1'' are ultrathin but have no agglomeration problem.

[0127] The thicknesses t11 or t11' of the first layer CE11 or CE11' and the thicknesses t12 or t12' of the second layer CE12 or CE12' may be the same as or similar to each other. In an embodiment, the thicknesses t11 or t11' of the first layer CE11 or CE11' may be 0.8 times to 1.2 times the thicknesses t12 or t12' of the second layer CE12 or CE12', respectively.

[0128] The thicknesses of the common electrodes CE1, CE1' or CE1'', the first layer CE11 or CE11', and the second layer CE12 or CE12' are the thicknesses of the portions thereof that overlap the opening of the second bank BN2 in the corresponding layer, or the thicknesses of their thickest portions.

[0129] Return reference Figure 4 , the common electrodes CE1, CE2 or CE3 may contact the first bank BN1. One end and the opposite end of the common electrodes CE1, CE2 and CE3 may contact the side surfaces of the first bank BN1 that define the opening. The spaced-apart common electrodes CE1, CE2 and CE3 may be electrically connected to each other through the first bank BN1 and may receive a voltage.

[0130] In an embodiment, an auxiliary electrode AXE may be disposed on the common electrodes CE1, CE2 and CE3. Figure 12 A cross-section of an embodiment of the display device 10 including the auxiliary electrode AXE is shown. The auxiliary electrode AXE may be disposed between the common electrodes CE1, CE2 and CE3 and the lower inorganic encapsulation layer TFE1 to assist the electrical connection between the common electrodes CE1, CE2 and CE3. The auxiliary electrode AXE may contact the common electrodes CE1, CE2 and CE3 and the first bank BN1.

[0131] The auxiliary electrode AXE may include a transparent conductive oxide (TCO). At least one selected from indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc indium tin oxide (ZITO), indium gallium zinc oxide (IGZO) and zinc tin oxide (ZTO) may be used as the material of the transparent conductive oxide (TCO).

[0132] In an embodiment, a capping layer (not shown) may be provided on the common electrodes CE1, CE2, and CE3. The capping layer may include an organic insulating material or an inorganic insulating material and cover the patterns provided on the light-emitting elements ED1, ED2, and ED3. The capping layer may effectively prevent the light-emitting elements ED1, ED2, and ED3 from being damaged by external air. In an embodiment, the capping layer may include an organic material such as a-NPD, NPB, TPD, m-MTDATA, Alq3, LiF, and / or CuPc or an inorganic material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0133] Return reference Figure 4 and Figure 5 , an embodiment of the display device 10 may include a plurality of bank structures BNS provided on the pixel defining layer PDL. The bank structures BNS may have a structure in which banks BN1 and BN2 including different materials are stacked in sequence, may define a plurality of openings corresponding to the light-emitting regions EA1, EA2, and EA3, and may be provided to overlap with the light-blocking regions of the color filter layer CFL to be described later. The light-emitting elements ED1, ED2, and ED3 of the display device 10 may be provided to overlap with the openings of the bank structures BNS.

[0134] The first bank BN1 may be provided on the pixel defining layer PDL. The side surface of the first bank BN1 may be more recessed in a direction opposite to the direction toward the center of the light-emitting regions EA1, EA2, and EA3 than the corresponding side surface of the pixel defining layer PDL. In a direction opposite to the direction toward the light-emitting regions EA1, EA2, and EA3, the side surface of the first bank BN1 may be more recessed than the corresponding side surface of the second bank BN2 to be described later.

[0135] According to an embodiment, the first bank BN1 may include a metal material. In an embodiment, the first bank BN1 may include aluminum (Al), an oxide of aluminum (Al), or an alloy of aluminum (Al).

[0136] The light-emitting layers EL1, EL2, and EL3 can be in direct contact with the side surface of the first bank BN1. The contact area between the common electrodes CE1, CE2, and CE3 and the side surface of the first bank BN1 can be larger than the contact area between the light-emitting layers EL1, EL2, and EL3 and the side surface of the first bank BN1. The common electrodes CE1, CE2, and CE3 can be arranged to have an area larger than that of the light-emitting layers EL1, EL2, and EL3 on the side surface of the first bank BN1, or at a higher position on the side surface of the first bank BN1. Since the common electrodes CE1, CE2, and CE3 of the different light-emitting elements ED1, ED2, and ED3 are electrically connected to each other through the first bank BN1, the area of the common electrodes CE1, CE2, and CE3 to be in contact with the first bank BN1 can become quite large.

[0137] The first bank BN1 can have an upper surface positioned higher than the common electrodes CE1, CE2, and CE3. The height from the substrate SUB to the upper surface of the first bank BN1 can be greater than the height from the substrate SUB to the common electrodes CE1, CE2, and CE3.

[0138] The second bank BN2 can be provided on the first bank BN1. The second bank BN2 can define an opening overlapping each of the light-emitting regions EA1, EA2, and EA3, and each opening can define the side surface of the second bank BN2. The second bank BN2 can include a tip TIP or an eaves, which is a protruding portion with respect to the first bank BN1 in a plan view or when observed in the third direction DR3. The side surface of the second bank BN2 can protrude more toward the center of the light-emitting regions EA1, EA2, and EA3 than the corresponding side surface of the first bank BN1.

[0139] Since the side surface of the second bank BN2 has a shape that protrudes more toward the light-emitting regions EA1, EA2, and EA3 than the corresponding side surface of the first bank BN1, an undercut structure of the first bank BN1 can be formed under the tip TIP of the second bank BN2.

[0140] In the display device 10 according to the embodiment, since the bank structure BNS includes the tips TIP protruding toward the centers of the light-emitting regions EA1, EA2, and EA3, the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 spaced apart from each other can be formed by deposition and etching processes instead of a mask process. In addition, different layers can be separately formed in the different light-emitting regions EA1, EA2, and EA3 by a deposition process. For example, even if the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 are formed by a deposition process without using a mask, the deposited materials may not be connected between the light-emitting regions EA1, EA2, and EA3 and may be disconnected from the bank structure BNS interposed therebetween by the tips TIP of the second bank BN2. Different layers can be separately formed in the different light-emitting regions EA1, EA2, and EA3 by a process of forming a material for forming a specific layer on the entire surface of the display device 10 and then etching and removing the layer formed in an unwanted region. An unwanted configuration provided additionally for the mask process can be omitted from the display device 10, and the region of the non-display area NDA (refer to Figure 1 ) can be minimized.

[0141] The second bank BN2 may include a metal material different from that of the first bank BN1. The metal material of the second bank BN2 and the metal material of the first bank BN1 are removed together by dry etching, and the metal material of the second bank BN2 may be a material having an etching rate much slower than that of the first bank BN1 or not being etched during wet etching. In the embodiment, the first bank BN1 may include aluminum (Al), an oxide of aluminum (Al), or an alloy of aluminum (Al), and the second bank BN2 may include titanium (Ti), an oxide of titanium (Ti), or an alloy of titanium (Ti).

[0142] The tips TIP of the second bank BN2 may overlap with the common electrodes CE1, CE2, and CE3, the light-emitting layers EL1, EL2, and EL3, and the pixel defining layer PDL in the direction DR3 perpendicular to the substrate SUB. The common electrodes CE1, CE2, and CE3 may be formed below the lower surface of the tips TIP of the second bank BN2. One end and the opposite end of the common electrodes CE1, CE2, and CE3 may overlap with the second bank BN2 in the thickness direction DR3 of the substrate SUB.

[0143] The thin film encapsulation layer TFEL can be disposed on the light-emitting elements ED1, ED2, and ED3 and the bank structure BNS, and can cover the plurality of light-emitting elements ED1, ED2, and ED3 and the bank structure BNS. The thin film encapsulation layer TFEL can include at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. The thin film encapsulation layer TFEL can include at least one organic film to protect the light-emitting element layer EML from particles such as dust.

[0144] In an embodiment, the thin film encapsulation layer TFEL can include a lower inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and an upper inorganic encapsulation layer TFE3 stacked in sequence.

[0145] Each of the lower inorganic encapsulation layer TFE1 and the upper inorganic encapsulation layer TFE3 can include one or more inorganic insulating materials. The inorganic insulating material can be at least one selected from silicon oxide, silicon nitride, and silicon oxynitride, and can be, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0146] The organic encapsulation layer TFE2 can include a polymer-based material. The polymer-based material can include acrylic resin, epoxy-based resin, polyimide, and polyethylene. In an embodiment, the organic encapsulation layer TFE2 can include acrylic resin, such as polymethyl methacrylate, polyacrylic acid, etc. The organic encapsulation layer TFE2 can be formed by hardening a monomer or coating a polymer.

[0147] The lower inorganic encapsulation layer TFE1 can be disposed on the light-emitting elements ED1, ED2, and ED3 and the bank structure BNS. The lower inorganic encapsulation layer TFE1 can include a first inorganic layer TL1, a second inorganic layer TL2, and a third inorganic layer TL3 respectively disposed corresponding to different light-emitting regions EA1, EA2, and EA3. Each of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can include an inorganic insulating material to cover the light-emitting elements ED1, ED2, and ED3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can effectively prevent the light-emitting elements ED1, ED2, and ED3 from being damaged by external air.

[0148] The lower inorganic encapsulation layer TFE1 (TL1, TL2, and TL3) can be formed by a chemical vapor deposition (CVD) method and can thus be formed along the step difference of the deposited layer. In an embodiment, for example, due to the tip TIP of the bank structure BNS, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can even form a thin film under the undercut. The lower inorganic encapsulation layers TL1, TL2, and TL3 can be disposed along the upper surface of the second bank BN2, the side surface of the first bank BN1, and the upper surfaces of the common electrodes CE1, CE2, and CE3. The lower inorganic encapsulation layers TL1, TL2, and TL3 can be in contact with the lower surface of the second bank BN2 to prevent moisture penetration from external air.

[0149] The first inorganic layer TL1 may not overlap with the second light-emitting element ED2 and the third light-emitting element ED3, but may be disposed only on the bank structure BNS in the periphery of the first light-emitting element ED1 and the first light-emitting element ED1. The second inorganic layer TL2 may not overlap with the first light-emitting element ED1 and the third light-emitting element ED3, but may be disposed only on the bank structure BNS in the periphery of the second light-emitting element ED2 and the second light-emitting element ED2. The third inorganic layer TL3 may not overlap with the first light-emitting element ED1 and the second light-emitting element ED2, but may be disposed only on the bank structure BNS in the periphery of the third light-emitting element ED3 and the third light-emitting element ED3.

[0150] The first inorganic layer TL1 can be formed after the formation of the first common electrode CE1, the second inorganic layer TL2 can be formed after the formation of the second common electrode CE2, and the third inorganic layer TL3 can be formed after the formation of the third common electrode CE3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be spaced apart from each other on the bank structure BNS.

[0151] The lower inorganic encapsulation layers TL1, TL2, and TL3 can be disposed on the upper surfaces of the light-emitting elements ED1, ED2, and ED3 and on the lower surface of the second bank BN2 in the periphery of the light-emitting elements ED1, ED2, and ED3, but can also be separated from the upper surface of the second bank BN2. That is, the lower inorganic encapsulation layers TL1, TL2, and TL3 can have an undercut structure on the second bank BN2. The space between the lower inorganic encapsulation layers TL1, TL2, and TL3 and the upper surface of the second bank BN2 can be a space in which the materials of the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 deposited on the upper surface of the second bank BN2 are removed.

[0152] The organic encapsulation layer TFE2 is disposed on the second bank BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3. A part of the organic encapsulation layer TFE2 may be disposed in the space between the lower inorganic encapsulation layers TL1, TL2, and TL3 and the upper surface of the second bank BN2. In the region where the second bank BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3 overlap, the second bank BN2, the organic encapsulation layer TFE2, and the lower inorganic encapsulation layers TL1, TL2, and TL3 may be stacked in sequence. In the tip TIP region, the organic encapsulation layer TFE2 and the lower inorganic encapsulation layers TL1, TL2, and TL3 may be arranged in sequence on the top surface of the second bank BN2, and the organic encapsulation layer TFE2 may be disposed again on the top surface of the lower inorganic encapsulation layers TL1, TL2, and TL3. In other words, a part of the organic encapsulation layer TFE2 may be disposed between the upper surface of the second bank BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3 on the tip TIP of the second bank BN2, and another part thereof may be disposed on the top surface of the lower inorganic encapsulation layers TL1, TL2, and TL3.

[0153] In an embodiment, the entire upper surface of the second bank BN2 may be in contact with the organic encapsulation layer TFE2. The first lower surface of the lower inorganic encapsulation layers TL1, TL2, and TL3 may be the surface opposite to the upper surface of the second bank BN2, and the first lower surface of the lower inorganic encapsulation layers TL1, TL2, and TL3 may be in contact with the organic encapsulation layer TFE2. The organic encapsulation layer TFE2 may be in contact with the side surface of the second bank BN2.

[0154] The upper inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The upper inorganic encapsulation layer TFE3 may include at least one selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0155] A light blocking layer (not shown) may be selectively disposed on the thin film encapsulation layer TFEL. The light blocking layer may be positioned among the light emitting regions EA1, EA2, and EA3. The light blocking layer may include a light absorbing material. In an embodiment, for example, the light blocking layer may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but is not limited thereto. The light blocking layer can effectively prevent color mixing caused by the penetration of visible light among the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3, thereby improving the color reproducibility of the display device 10.

[0156] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed in the light-emitting regions EA1, EA2, and EA3. Each of the plurality of color filters CF1, CF2, and CF3 may include a filter pattern region and a light-blocking region. The filter pattern region may be formed to overlap with the openings of the light-emitting regions EA1, EA2, and EA3 or the bank structure BNS, and may form a light output region from which light emitted from the light-emitting regions EA1, EA2, and EA3 is output. The light-blocking region is a region in which the plurality of color filters CF1, CF2, and CF3 are stacked such that light cannot pass therethrough.

[0157] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are respectively disposed to correspond to different light-emitting regions EA1, EA2, and EA3. The color filters CF1, CF2, and CF3 may include colorants, such as dyes or pigments, for absorbing light in another wavelength band except for light in a specific wavelength band, and may be disposed to correspond to the colors of the light emitted from the light-emitting regions EA1, EA2, and EA3. In an embodiment, for example, the first color filter CF1 may be a red color filter disposed to overlap with the first light-emitting region EA1 and configured to transmit only the first red light. The second color filter CF2 may be a green color filter disposed to overlap with the second light-emitting region EA2 and configured to transmit only the second green light. The third color filter CF3 may be a blue color filter disposed to overlap with the third light-emitting region EA3 and configured to transmit only the third blue light.

[0158] In an embodiment, when the color filters CF1, CF2, and CF3 are disposed to overlap each other, the display device 10 may reduce the intensity of reflected light caused by external light. In such an embodiment, the color sense of the reflected light caused by external light may be controlled by adjusting the layout, shape, area, etc. of the color filters CF1, CF2, and CF3 on the plan view.

[0159] An outer coating OC may be disposed on the color filters CF1, CF2, and CF3 to flatten the upper ends of the color filters CF1, CF2, and CF3. The outer coating OC may be a colorless light-transmitting layer that does not have a color in the visible light band. In an embodiment, for example, the outer coating OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0160] The present invention should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0161] Although the present invention has been specifically shown and described with reference to embodiments thereof, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display device, comprising: A pixel electrode is disposed on the substrate; A pixel defining layer, disposed on the substrate and provided with an opening exposing the pixel electrode; A light-emitting layer is disposed on the pixel electrode; A common electrode, disposed on the light-emitting layer and comprising a first layer; A first bank is disposed on the pixel defining layer; as well as a second bank disposed on the first bank, wherein a side surface of the second bank protrudes more than a corresponding side surface of the first bank, The first layer includes a first element and a second element, wherein the first element is silver and the second element is a Group XV element.

2. The display device according to claim 1, wherein: A ratio of the second element to the total number of atoms in the first layer is in a range of 0.2 at % to 5.0 at %.

3. The display device according to claim 1, wherein: The second element is one or both selected from bismuth and antimony.

4. The display device according to claim 1, wherein: The first layer further includes a third element, and the third element includes at least one selected from the group consisting of copper, zinc, indium, and tin.

5. The display device according to claim 4, wherein: A sum of ratios of the second element and the third element to the total number of atoms in the first layer is 0.5 at % or more.

6. The display device according to claim 5, wherein: A ratio of the second element to the total number of atoms in the first layer is greater than a ratio of the third element to the total number of atoms in the first layer.

7. The display device according to claim 1, wherein: The common electrode further includes a second layer including at least one selected from pure silver and AgMg alloy.

8. The display device according to claim 7, wherein: The first layer is disposed on the light emitting layer, and The second layer is disposed on the first layer.

9. The display device according to claim 7, wherein: The second layer is disposed on the light emitting layer, and The first layer is disposed on the second layer.

10. The display device according to claim 1, wherein: The thickness of the common electrode is to within the range.

11. The display device according to claim 7, wherein: The thickness of the first layer is 0.8 to 1.2 times the thickness of the second layer. 12 . The display device according to claim 1 , further comprising an auxiliary electrode disposed on the common electrode.

13. The display device according to claim 12, wherein: The auxiliary electrode includes a transparent conductive oxide. 14 . The display device according to claim 1 , further comprising a residual pattern disposed between an upper surface of the pixel electrode and a lower surface of the pixel defining layer.

15. A display device comprising: A pixel electrode is disposed on the substrate; A pixel defining layer, disposed on the substrate and provided with an opening exposing the pixel electrode; A light-emitting layer is disposed on the pixel electrode; a common electrode, disposed on the light-emitting layer and comprising a first element and a second element, wherein the first element is silver and the second element is a Group XV element; A first bank is disposed on the pixel defining layer; a second bank disposed on the first bank, wherein a side surface of the second bank protrudes more than a corresponding side surface of the first bank; A first inorganic layer is disposed on the common electrode and the second bank; and The organic encapsulation layer is disposed between the second bank and the first inorganic layer.

16. The display device according to claim 15, wherein: The common electrode comprises: A first layer includes the first element and the second element, wherein the first element is silver and the second element is the Group XV element; and The second layer includes at least one selected from pure silver and AgMg alloy.

17. The display device according to claim 15, wherein: The first inorganic layer contacts a lower surface of the second bank.

18. The display device according to claim 15, wherein: The organic encapsulating layer contacts the side surface of the second bank.

19. A display device comprising: A pixel electrode is disposed on the substrate; A pixel defining layer, disposed on the substrate and provided with an opening exposing the pixel electrode; A light-emitting layer is disposed on the pixel electrode; A common electrode, disposed on the light-emitting layer and comprising a first layer; A first bank is disposed on the pixel defining layer; as well as a second bank disposed on the first bank, wherein a side surface of the second bank protrudes more than a corresponding side surface of the first bank, The first layer includes a first element, a second element and a third element, wherein the first element is silver, the second element is selected from one or both of bismuth and antimony, and the third element includes at least one selected from copper, zinc, indium and tin, and A ratio of the first element to the total number of atoms in the first layer is 95.0 at % or more.

20. The display device according to claim 19, wherein: The thickness of the common electrode is to within the range.

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