Shifting register and driving method thereof, gate driving circuit and display device

Abstract

The invention discloses a shift register and a driving method thereof, a gate driving circuit and a display device, and the shift register comprises a shift sub-circuit and an output sub-circuit. The shift sub-circuit is configured to provide a signal to the cascade signal output end (OUTC) under the control of signals of a signal input end (IN), a first clock signal end (CK), a second clock signal end (CB), a first power supply end (VH1) and a second power supply end (VL1); and the output sub-circuit is configured to provide a signal to a driving signal output end (OUT) under the control of signals of the shift sub-circuit, the latch signal end (MS), the first control signal end (V1), the second control signal end (V2), the cascade signal output end (OUTC), the third power supply end (VH2), the fourth power supply end (VL2) and the fifth power supply end (NCX).

Description

Shift register and driving method thereof, gate driving circuit, and display device

[0001] This application claims priority to PCT international application No. PCT / CN2023 / 125026, filed on October 17, 2023, with application number PCT / CN2023 / 125026 and invention name “Display Substrate and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a shift register and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0006] In a first aspect, the present disclosure provides a shift register, comprising: a shift subcircuit and an output subcircuit;

[0007] The shift subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal and the cascade signal output terminal respectively, and is configured to provide a signal to the cascade signal output terminal under the control of the signals from the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal and the second power supply terminal;

[0008] The output sub-circuit is electrically connected to the shift sub-circuit, the latch signal terminal, the first control signal terminal, the second control signal terminal, the third power supply terminal, the fourth power supply terminal, the fifth power supply terminal, the cascade signal output terminal, and the drive signal output terminal, respectively, and is configured to provide a signal to the drive signal output terminal under the control of signals from the shift sub-circuit, the latch signal terminal, the first control signal terminal, the second control signal terminal, the cascade signal output terminal, the third power supply terminal, the fourth power supply terminal, and the fifth power supply terminal;

[0009] The shift subcircuit includes: at least one shift output transistor, the shift output transistor is electrically connected to the cascade signal output terminal; the output subcircuit includes: at least one drive output transistor, the drive output transistor is electrically connected to the drive signal output terminal; the shift subcircuit also includes: at least one transistor; the output subcircuit also includes: at least one transistor;

[0010] The shift subcircuit is provided with a third node, the control electrode of at least one driving output transistor is electrically connected to the third node through at least one transistor of the output subcircuit, and the control electrode of at least one shift output transistor is electrically connected to the third node through at least one transistor of the shift subcircuit.

[0011] In an exemplary embodiment, the shift sub-circuit is also electrically connected to the fifth power supply terminal and is configured to provide a signal to the cascade signal output terminal under the control of signals from the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal and the fifth power supply terminal.

[0012] In an exemplary embodiment, the shift subcircuit includes: first to sixteenth transistors and first to third capacitors;

[0013] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0014] The control electrode of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the tenth node;

[0015] A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the tenth node;

[0016] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node;

[0017] a control electrode of the fifth transistor electrically connected to the tenth node, a first electrode of the fifth transistor electrically connected to the first power supply terminal, and a second electrode of the fifth transistor electrically connected to the fifth node;

[0018] The control electrode of the sixth transistor is electrically connected to the sixth node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the first node;

[0019] A control electrode of the seventh transistor is electrically connected to the second clock signal terminal, a first electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to the fourth node;

[0020] a control electrode of the eighth transistor electrically connected to the third node, a first electrode of the eighth transistor electrically connected to the first power supply terminal, and a second electrode of the eighth transistor electrically connected to the fourth node;

[0021] a control electrode of the ninth transistor electrically connected to the fourth node, a first electrode of the ninth transistor electrically connected to the first power supply terminal, and a second electrode of the ninth transistor electrically connected to the cascade signal output terminal;

[0022] The gate electrode of the tenth transistor is electrically connected to the ninth node, the first electrode of the tenth transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascade signal output terminal;

[0023] The control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the tenth node, and the second electrode of the eleventh transistor is electrically connected to the sixth node;

[0024] The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the third node, and the second electrode of the twelfth transistor is electrically connected to the ninth node;

[0025] a control electrode of the thirteenth transistor electrically connected to the fifth power supply terminal, a first electrode of the thirteenth transistor electrically connected to the first power supply terminal, and a second electrode of the thirteenth transistor electrically connected to the third node;

[0026] A control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourteenth transistor is electrically connected to the signal input terminal, and a second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor;

[0027] The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the fifteenth transistor is electrically connected to the second node;

[0028] The control electrode of the sixteenth transistor is electrically connected to the second node, the first electrode of the sixteenth transistor is electrically connected to the ninth node, and the second electrode of the sixteenth transistor is electrically connected to the second node;

[0029] The first plate of the first capacitor is electrically connected to the sixth node, and the second plate of the first capacitor is electrically connected to the first node;

[0030] The first plate of the second capacitor is electrically connected to the fourth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal;

[0031] The first plate of the third capacitor is electrically connected to the second node, and the second plate of the third capacitor is electrically connected to the fifth node.

[0032] In an exemplary embodiment, the shift subcircuit includes: first to fifteenth transistors and first to third capacitors;

[0033] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0034] The control electrode of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the tenth node;

[0035] A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the tenth node;

[0036] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node;

[0037] a control electrode of the fifth transistor electrically connected to the tenth node, a first electrode of the fifth transistor electrically connected to the first power supply terminal, and a second electrode of the fifth transistor electrically connected to the fifth node;

[0038] The control electrode of the sixth transistor is electrically connected to the sixth node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the first node;

[0039] A control electrode of the seventh transistor is electrically connected to the second clock signal terminal, a first electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to the fourth node;

[0040] a control electrode of the eighth transistor electrically connected to the third node, a first electrode of the eighth transistor electrically connected to the first power supply terminal, and a second electrode of the eighth transistor electrically connected to the fourth node;

[0041] a control electrode of the ninth transistor electrically connected to the fourth node, a first electrode of the ninth transistor electrically connected to the first power supply terminal, and a second electrode of the ninth transistor electrically connected to the cascade signal output terminal;

[0042] The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascade signal output terminal;

[0043] The control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the tenth node, and the second electrode of the eleventh transistor is electrically connected to the sixth node;

[0044] The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the third node, and the second electrode of the twelfth transistor is electrically connected to the second node;

[0045] a control electrode of the thirteenth transistor electrically connected to the fifth power supply terminal, a first electrode of the thirteenth transistor electrically connected to the first power supply terminal, and a second electrode of the thirteenth transistor electrically connected to the third node;

[0046] A control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourteenth transistor is electrically connected to the signal input terminal, and a second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor;

[0047] The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the fifteenth transistor is electrically connected to the second node;

[0048] The first plate of the first capacitor is electrically connected to the sixth node, and the second plate of the first capacitor is electrically connected to the first node;

[0049] The first plate of the second capacitor is electrically connected to the fourth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal;

[0050] The first plate of the third capacitor is electrically connected to the second node, and the second plate of the third capacitor is electrically connected to the fifth node.

[0051] In an exemplary embodiment, the shift subcircuit further includes: a fourth capacitor;

[0052] The first plate of the fourth capacitor is electrically connected to the second power supply terminal, and the second plate of the fourth capacitor is electrically connected to the cascade signal output terminal.

[0053] In an exemplary embodiment, the first control signal terminal is electrically connected to the fifth node.

[0054] In an exemplary embodiment, the second control signal terminal is electrically connected to a first node in a previous stage shift register of the current stage shift register.

[0055] In an exemplary embodiment, the output sub-circuit is electrically connected to the second node, the third node, and the fourth node of the shift register, respectively.

[0056] In an exemplary embodiment, the output sub-circuit includes: a seventeenth transistor to a twenty-sixth transistor and a fifth capacitor and a sixth capacitor;

[0057] The control electrode and the first electrode of the seventeenth transistor are electrically connected to the second node respectively, and the second electrode of the seventeenth transistor is electrically connected to the sixth node;

[0058] A control electrode of the eighteenth transistor is electrically connected to the seventh node, a first electrode of the eighteenth transistor is electrically connected to the third node, and a second electrode of the eighteenth transistor is electrically connected to the sixth node;

[0059] a control electrode of the nineteenth transistor electrically connected to the second control signal terminal, a first electrode of the nineteenth transistor electrically connected to the latch signal terminal, and a second electrode of the nineteenth transistor electrically connected to the second electrode of the twentieth transistor;

[0060] The control electrode of the twentieth transistor is electrically connected to the cascade signal output terminal, and the first electrode of the twentieth transistor is electrically connected to the seventh node;

[0061] A control electrode of the twenty-first transistor is electrically connected to the seventh node, a first electrode of the twenty-first transistor is electrically connected to the fourth node, and a second electrode of the twenty-first transistor is electrically connected to the eighth node;

[0062] a control electrode of the twenty-second transistor electrically connected to the fifth power supply terminal, a first electrode of the twenty-second transistor electrically connected to the fourth power supply terminal, and a second electrode of the twenty-second transistor electrically connected to the seventh node;

[0063] A control electrode of the twenty-third transistor is electrically connected to the first control signal terminal, a first electrode of the twenty-third transistor is electrically connected to the fourth power supply terminal, and a second electrode of the twenty-third transistor is electrically connected to the seventh node;

[0064] A control electrode of the twenty-fourth transistor is electrically connected to the sixth node, a first electrode of the twenty-fourth transistor is electrically connected to the third power supply terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the eighth node;

[0065] A control electrode of the twenty-fifth transistor is electrically connected to the eighth node, a first electrode of the twenty-fifth transistor is electrically connected to the third power supply terminal, and a second electrode of the twenty-fifth transistor is electrically connected to the drive signal output terminal;

[0066] A control electrode of the twenty-sixth transistor is electrically connected to the sixth node, a first electrode of the twenty-sixth transistor is electrically connected to the fourth power supply terminal, and a second electrode of the twenty-sixth transistor is electrically connected to the drive signal output terminal;

[0067] The first plate of the fifth capacitor is electrically connected to the seventh node, and the second plate of the fifth capacitor is electrically connected to the eighth node;

[0068] The first plate of the sixth capacitor is electrically connected to the eighth node, and the second plate of the sixth capacitor is electrically connected to the third power supply terminal.

[0069] In an exemplary embodiment, the shift subcircuit includes: first to eighth transistors and first and second capacitors;

[0070] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0071] The control electrode of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node;

[0072] A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the fourth node;

[0073] The control electrode of the fourth transistor is electrically connected to the fourth node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the cascade signal output terminal;

[0074] The control electrode of the fifth transistor is electrically connected to the ninth node, the first electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the cascade signal output terminal;

[0075] a control electrode of the sixth transistor electrically connected to the fourth node, a first electrode of the sixth transistor electrically connected to the first power supply terminal, and a second electrode of the sixth transistor electrically connected to the first electrode of the seventh transistor;

[0076] The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the third node;

[0077] a control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the third node, and a second electrode of the eighth transistor electrically connected to the ninth node;

[0078] The first plate of the first capacitor is electrically connected to the ninth node, and the second plate of the first capacitor is electrically connected to the cascade signal output terminal;

[0079] The first plate of the second capacitor is electrically connected to the fourth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal.

[0080] In an exemplary embodiment, the output sub-circuit is further electrically connected to the third node and the fourth node in the shift sub-circuit, respectively.

[0081] In an exemplary embodiment, the output sub-circuit includes: eighteenth to twenty-sixth transistors and fifth and sixth capacitors;

[0082] A control electrode of the eighteenth transistor is electrically connected to the seventh node, a first electrode of the eighteenth transistor is electrically connected to the third node, and a second electrode of the eighteenth transistor is electrically connected to the sixth node;

[0083] a control electrode of the nineteenth transistor electrically connected to the second control signal terminal, a first electrode of the nineteenth transistor electrically connected to the latch signal terminal, and a second electrode of the nineteenth transistor electrically connected to the second electrode of the twentieth transistor;

[0084] The control electrode of the twentieth transistor is electrically connected to the cascade signal output terminal, and the first electrode of the twentieth transistor is electrically connected to the seventh node;

[0085] A control electrode of the twenty-first transistor is electrically connected to the seventh node, a first electrode of the twenty-first transistor is electrically connected to the fourth node, and a second electrode of the twenty-first transistor is electrically connected to the eighth node;

[0086] a control electrode of the twenty-second transistor electrically connected to the fifth power supply terminal, a first electrode of the twenty-second transistor electrically connected to the fourth power supply terminal, and a second electrode of the twenty-second transistor electrically connected to the seventh node;

[0087] A control electrode of the twenty-third transistor is electrically connected to the first control signal terminal, a first electrode of the twenty-third transistor is electrically connected to the fourth power supply terminal, and a second electrode of the twenty-third transistor is electrically connected to the seventh node;

[0088] A control electrode of the twenty-fourth transistor is electrically connected to the sixth node, a first electrode of the twenty-fourth transistor is electrically connected to the third power supply terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the eighth node;

[0089] A control electrode of the twenty-fifth transistor is electrically connected to the eighth node, a first electrode of the twenty-fifth transistor is electrically connected to the third power supply terminal, and a second electrode of the twenty-fifth transistor is electrically connected to the drive signal output terminal;

[0090] A control electrode of the twenty-sixth transistor is electrically connected to the sixth node, a first electrode of the twenty-sixth transistor is electrically connected to the fourth power supply terminal, and a second electrode of the twenty-sixth transistor is electrically connected to the drive signal output terminal;

[0091] The first plate of the fifth capacitor is electrically connected to the seventh node, and the second plate of the fifth capacitor is electrically connected to the eighth node;

[0092] The first plate of the sixth capacitor is electrically connected to the eighth node, and the second plate of the sixth capacitor is electrically connected to the third power supply terminal.

[0093] In an exemplary embodiment, the first power terminal and the third power terminal are the same signal terminal, and the second power terminal and the fourth power terminal are the same signal terminal.

[0094] In a second aspect, the present disclosure further provides a gate drive circuit, comprising: a plurality of the above-mentioned shift registers;

[0095] The cascade signal output terminal of one shift register in at least one stage of the shift register is electrically connected to the signal input terminal of the previous stage of the shift register.

[0096] In a third aspect, the present disclosure further provides a display device, comprising: the above-mentioned gate driving circuit.

[0097] In a fourth aspect, the present disclosure further provides a shift register driving method, which is configured to drive the above-mentioned shift register, the method comprising:

[0098] The shift subcircuit provides a signal to the cascade signal output terminal under the control of the signals at the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, and the second power supply terminal;

[0099] The output sub-circuit provides a signal to the driving signal output terminal under the control of signals from the shift sub-circuit, the latch signal terminal, the first control signal terminal, the second control signal terminal, the cascade signal output terminal, the third power terminal, the fourth power terminal and the fifth power terminal.

[0100] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0101] Summary of the Figures

[0102] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0103] FIG1 is a schematic structural diagram of a display device;

[0104] FIG2A is a schematic diagram of a planar structure of a display substrate;

[0105] FIG2B is a second schematic diagram of a planar structure of a display substrate;

[0106] FIG2C is a third schematic diagram of a planar structure of a display substrate;

[0107] FIG3 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure;

[0108] FIG4 is a schematic structural diagram of another shift register;

[0109] FIG5A is an equivalent circuit diagram of a shift register;

[0110] FIG5B is an equivalent circuit diagram of another shift register;

[0111] FIG6 is a timing diagram of the operation of a portion of a shift register;

[0112] FIG7 is a structural schematic diagram of a display substrate;

[0113] FIG8 is a second structural diagram of a display substrate;

[0114] FIG9 is a third structural diagram of a display substrate;

[0115] FIG10 is a fourth structural diagram of a display substrate;

[0116] FIG11 is a fifth structural diagram of a display substrate;

[0117] FIG12 is a schematic diagram of a partial structure of the display substrate provided in FIG7 , FIG9 , FIG10 and FIG11 ;

[0118] FIG13 is a schematic diagram of a partial structure of the display substrate provided in FIG8 ;

[0119] FIG14 is a schematic diagram of the display substrate provided in FIG7 and FIG9 to FIG11 after a semiconductor layer pattern is formed;

[0120] FIG15 is a schematic diagram of the display substrate provided in FIG8 after a semiconductor layer pattern is formed;

[0121] FIG16 is a schematic diagram showing a first conductive layer pattern in a display substrate provided in FIG7 and FIG9 to FIG11;

[0122] FIG17 is a schematic diagram showing a first conductive layer pattern formed on the display substrate provided in FIG7 and FIG9 to FIG11;

[0123] FIG18 is a schematic diagram showing a pattern of a first conductive layer in the display substrate provided in FIG8 ;

[0124] FIG19 is a schematic diagram showing a first conductive layer pattern formed on the display substrate provided in FIG8 ;

[0125] FIG20 is a schematic diagram of a second conductive layer pattern in a display substrate provided in FIG7 and FIG9 to FIG11;

[0126] FIG21 is a schematic diagram showing a second conductive layer pattern formed on the display substrate provided in FIG7 and FIG9 to FIG11;

[0127] FIG22 is a schematic diagram of a second conductive layer pattern in the display substrate provided in FIG8 ;

[0128] FIG23 is a schematic diagram of forming a second conductive layer pattern on the display substrate provided in FIG8 ;

[0129] FIG24 is a schematic diagram showing a third insulating layer pattern formed on the display substrate provided in FIG7 , FIG10 and FIG11 ;

[0130] FIG25 is a schematic diagram showing a third insulating layer pattern formed on the display substrate provided in FIG8 ;

[0131] FIG26 is a schematic diagram showing a third insulating layer pattern formed on the display substrate provided in FIG9 ;

[0132] FIG27 is a schematic diagram of a third conductive layer pattern in the display substrate provided in FIG7 ;

[0133] FIG28 is a schematic diagram of the display substrate provided in FIG7 after a third conductive layer pattern is formed;

[0134] FIG29 is a schematic diagram of a third conductive layer pattern in the display substrate provided in FIG8 ;

[0135] FIG30 is a schematic diagram of the display substrate provided in FIG8 after a third conductive layer pattern is formed;

[0136] FIG31 is a schematic diagram of a third conductive layer pattern in the display substrate provided in FIG9 ;

[0137] FIG32 is a schematic diagram of the display substrate provided in FIG9 after a third conductive layer pattern is formed;

[0138] FIG33 is a schematic diagram of a third conductive layer pattern in the display substrate provided in FIG10 and FIG11 ;

[0139] FIG34 is a schematic diagram of the display substrate provided in FIG10 and FIG11 after a third conductive layer pattern is formed;

[0140] FIG35 is a schematic diagram of the display substrate provided in FIG7 after a fourth insulating layer pattern is formed;

[0141] FIG36 is a schematic diagram of the display substrate provided in FIG8 after a fourth insulating layer pattern is formed;

[0142] FIG37 is a schematic diagram of the display substrate provided in FIG9 after a fourth insulating layer pattern is formed;

[0143] FIG38 is a schematic diagram of the display substrate provided in FIG10 after a fourth insulating layer pattern is formed;

[0144] FIG39 is a schematic diagram of the display substrate provided in FIG11 after a fourth insulating layer pattern is formed;

[0145] FIG40 is a schematic diagram showing a fourth conductive layer pattern in the display substrate provided in FIG7 and FIG8 ;

[0146] FIG41 is a schematic diagram of the display substrate provided in FIG7 after a fourth conductive layer pattern is formed;

[0147] FIG42 is a schematic diagram of the display substrate provided in FIG8 after a fourth conductive layer pattern is formed;

[0148] FIG43 is a schematic diagram showing a pattern of a fourth conductive layer in a display substrate provided in FIG9 and FIG10;

[0149] FIG44 is a schematic diagram of the display substrate provided in FIG9 after a fourth conductive layer pattern is formed;

[0150] FIG45 is a schematic diagram of the display substrate provided in FIG10 after a fourth conductive layer pattern is formed;

[0151] FIG46 is a schematic diagram showing a pattern of a fourth conductive layer in the display substrate provided in FIG11 ;

[0152] FIG47 is a schematic diagram of the display substrate provided in FIG11 after a fourth conductive layer pattern is formed;

[0153] FIG48 is a schematic diagram of the display substrate provided in FIG9 after a first planar layer pattern is formed;

[0154] FIG49 is a schematic diagram of the display substrate provided in FIG10 after a first planarization layer is formed;

[0155] FIG50 is a schematic diagram of the display substrate provided in FIG11 after a first planar layer pattern is formed;

[0156] FIG51 is a schematic diagram of a fifth conductive layer pattern in the display substrate provided in FIG9 ;

[0157] FIG52 is a schematic diagram of the display substrate provided in FIG9 after a fifth conductive layer pattern is formed;

[0158] FIG53 is a schematic diagram of a fifth conductive layer pattern in the display substrate provided in FIG10 ;

[0159] FIG54 is a schematic diagram of the display substrate provided in FIG10 after a fifth conductive layer pattern is formed;

[0160] FIG55 is a schematic diagram showing a pattern of a fifth conductive layer in the display substrate provided in FIG11 ;

[0161] FIG56 is a schematic diagram of the display substrate provided in FIG11 after a fifth conductive layer pattern is formed;

[0162] FIG57 is a schematic structural diagram of a shift register provided by the present disclosure;

[0163] FIG58 is an equivalent circuit diagram 1 of the shift subcircuit;

[0164] FIG59 is a second equivalent circuit diagram of the shift subcircuit;

[0165] FIG60 is an equivalent circuit diagram 1 of the output sub-circuit;

[0166] FIG61 is a third equivalent circuit diagram of the shift subcircuit;

[0167] FIG62 is a second equivalent circuit diagram of the output sub-circuit;

[0168] FIG63 is an equivalent circuit diagram 1 of a shift register;

[0169] FIG64 is a second equivalent circuit diagram of a shift register;

[0170] FIG65 is a third equivalent circuit diagram of a shift register;

[0171] FIG66 is an operation timing diagram of the shift sub-circuit provided in FIG58 and FIG59;

[0172] Figure 67 is an operating timing diagram of the shift sub-circuit provided in Figure 61.

[0173] Details

[0174] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0175] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0176] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0177] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0178] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0179] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0180] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0181] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0182] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0183] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0184] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0185] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0186] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a gate driver, and a pixel array. The timing controller is respectively connected to the data driver and the gate driver. The data driver is respectively connected to multiple data signal lines (D1 to Dn). The gate driver is respectively connected to multiple gate signal lines (G1 to Gm). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit. The pixel driving circuit may be respectively connected to the gate signal lines and the data signal lines.

[0187] In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light emitting driver to the light emitting driver. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data driver may sample the grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.

[0188] In an exemplary embodiment, the gate driver may generate a scan signal to be provided to the gate signal lines G1, G2, G3, ... to Gm by receiving a clock signal, a gate start signal, etc. from a timing controller. For example, the scan driver may sequentially provide a scan signal having an on-level pulse to the gate signal lines G1 to Gm. For example, the gate driver may be configured in the form of a shift register and may generate the scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of a clock signal. m may be a natural number.

[0189] Figure 2A is a schematic diagram of a planar structure of a display substrate (I), Figure 2B is a schematic diagram of a planar structure of a display substrate (II), and Figure 2C is a schematic diagram of a planar structure of a display substrate (III). As shown in Figures 2A to 2C, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a gate signal line and a data signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the gate signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuit of the subpixel in which they are located. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the subpixel in which they are located.

[0190] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

[0191] In an exemplary embodiment, the shape of the sub-pixel may be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally, vertically, or in a herringbone pattern, which is not limited in the present disclosure.

[0192] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged horizontally, vertically, or in a herringbone pattern, etc., without limitation in this disclosure. FIG. 2A and FIG. 2B illustrate an example of a pixel unit including three sub-pixels. The three sub-pixels in FIG. 2A are arranged horizontally, while the three sub-pixels in FIG. 2B are arranged in a herringbone pattern.

[0193] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged horizontally, vertically, or in a square pattern, which is not limited in this disclosure. FIG2C illustrates an example in which a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square pattern.

[0194] In an exemplary embodiment, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure, which is not limited in the present disclosure.

[0195] In an exemplary embodiment, the pixel driving circuit may include 7 transistors (first pixel transistor to seventh pixel transistor), 1 storage capacitor C, the pixel driving circuit may include 7 pixel transistors (first pixel transistor to seventh pixel transistor), 1 storage capacitor C, and the pixel driving circuit may be connected to 7 signal lines (data signal line, first scan signal line, second scan signal line, light emitting signal line, initial signal line, first power line and second power line).

[0196] In an exemplary embodiment, the pixel driving circuit may include a first node, a second node, and a third node. The first node is respectively connected to the first electrode of the third pixel transistor, the second electrode of the fourth pixel transistor, and the second electrode of the fifth pixel transistor, the second node is respectively connected to the second electrode of the first reset pixel transistor, the first electrode of the second pixel transistor, the control electrode of the third pixel transistor, and the second end of the storage capacitor, and the third node is respectively connected to the second electrode of the second pixel transistor, the second electrode of the third pixel transistor, and the first electrode of the sixth pixel transistor.

[0197] In an exemplary embodiment, a first end of the storage capacitor is connected to the first power line, and a second end of the storage capacitor is connected to the second node, that is, the second end of the storage capacitor is connected to the control electrode of the third pixel transistor.

[0198] The control electrode of the first pixel transistor is connected to the second scan signal line, the first electrode of the first pixel transistor is connected to the initialization signal line, and the second electrode of the first pixel transistor is connected to the second node. When an on-level scan signal is applied to the second scan signal line, the first pixel transistor transmits an initialization voltage to the control electrode of the third pixel transistor to initialize the charge amount of the control electrode of the third pixel transistor.

[0199] The control electrode of the second pixel transistor is connected to the first scan signal line, the first electrode of the second pixel transistor is connected to the second node, and the second electrode of the second pixel transistor is connected to the third node. When an on-level scan signal is applied to the first scan signal line, the second pixel transistor connects the control electrode of the third pixel transistor to the second electrode.

[0200] The control electrode of the third pixel transistor is connected to the second node, that is, the control electrode of the third pixel transistor is connected to the second end of the storage capacitor, the first electrode of the third pixel transistor is connected to the first node, and the second electrode of the third pixel transistor is connected to the third node. The third pixel transistor can be called a driving pixel transistor. The third pixel transistor determines the magnitude of the driving current flowing between the first power line and the second power line based on the potential difference between the control electrode and the first electrode of the third pixel transistor.

[0201] A control electrode of the fourth pixel transistor is connected to the first scan signal line, a first electrode of the fourth pixel transistor is connected to the data signal line, and a second electrode of the fourth pixel transistor is connected to the first node. The fourth pixel transistor may be referred to as a switching pixel transistor, a scanning pixel transistor, etc. When an on-level scan signal is applied to the first scan signal line, the fourth pixel transistor inputs a data voltage of the data signal line to the pixel driving circuit.

[0202] The control electrode of the fifth pixel transistor is connected to the light-emitting signal line, the first electrode of the fifth pixel transistor is connected to the first power line, and the second electrode of the fifth pixel transistor is connected to the first node. The control electrode of the sixth pixel transistor is connected to the light-emitting signal line, the first electrode of the sixth pixel transistor is connected to the third node, and the second electrode of the sixth pixel transistor is connected to the first electrode of the light-emitting device. The fifth and sixth pixel transistors can be referred to as light-emitting pixel transistors. When an on-level light-emitting signal is applied to the light-emitting signal line, the fifth and sixth pixel transistors form a drive current path between the first power line and the second power line, causing the light-emitting device to emit light.

[0203] The control electrode of the seventh pixel transistor is connected to the first scan signal line, the first electrode of the seventh pixel transistor is connected to the initialization signal line, and the second electrode of the seventh pixel transistor is connected to the first electrode of the light-emitting device. When an on-level scan signal is applied to the first scan signal line, the seventh pixel transistor transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0204] According to the characteristics of pixel transistors, pixel transistors can be divided into N-type pixel transistors and P-type pixel transistors. When the pixel transistor is a P-type pixel transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltages). When the pixel transistor is an N-type pixel transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltages).

[0205] In an exemplary embodiment, the first to seventh reset pixel transistors may be P-type pixel transistors or N-type pixel transistors. Using the same type of pixel transistors in the pixel drive circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh reset pixel transistors may include P-type pixel transistors and N-type pixel transistors.

[0206] In an exemplary embodiment, the first reset pixel transistor to the seventh pixel transistor may be a low-temperature polysilicon thin-film pixel transistor, or an oxide thin-film pixel transistor, or a low-temperature polysilicon thin-film pixel transistor and an oxide thin-film pixel transistor. The active layer of the low-temperature polysilicon thin-film pixel transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film pixel transistor is made of oxide semiconductor (Oxide). The low-temperature polysilicon thin-film pixel transistor has advantages such as high mobility and fast charging, and the oxide thin-film pixel transistor has advantages such as low leakage current. The low-temperature polysilicon thin-film pixel transistor and the oxide thin-film pixel transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0207] In an exemplary embodiment, the first scan signal line, the second scan signal line, the light emitting signal line, and the initial signal line may extend in a horizontal direction, and the second power line, the first power line, and the data signal line may extend in a vertical direction.

[0208] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0209] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0210] The first phase, called the reset phase, has the signal on the second scan signal line at a low level, while the signals on the first scan signal line and the light-emitting signal line at a high level. The low level signal on the second scan signal line turns on the first transistor, and the signal on the initialization signal line is supplied to the second node, initializing (resetting) the storage capacitor and clearing the original charge in the storage capacitor. The high level signals on the first scan signal line and the light-emitting signal line turn off the second, fourth, fifth, sixth, and seventh transistors, resulting in no light emission during this phase.

[0211] In the second phase, known as the data writing phase or threshold compensation phase, the signal on the first scan signal line is a low-level signal, the signals on the second scan signal line and the light-emitting signal line are high-level signals, and the data signal line outputs a data voltage. During this phase, since the second end of the storage capacitor is at a low level, the third transistor is turned on. The low-level signal on the first scan signal line turns on the second, fourth, and seventh transistors. The second and fourth transistors are turned on, causing the data voltage output by the data signal line to be provided to the second node via the first node, the turned-on third transistor, the third node, and the turned-on second transistor. The difference between the data voltage output by the data signal line and the threshold voltage of the third transistor is charged into the storage capacitor. The voltage at the second end (second node) of the storage capacitor is Vdata-|Vth|, where Vdata is the data voltage output by the data signal line and Vth is the threshold voltage of the third transistor. The seventh transistor is turned on, causing the initial voltage of the initial signal line to be provided to the first electrode, initializing (resetting) the first electrode, clearing the pre-stored voltage within it, completing initialization, and ensuring that it does not emit light. The signal on the second scan signal line is a high-level signal, turning off the first transistor. The signal of the light emitting signal line is a high level signal, which turns off the fifth transistor and the sixth transistor.

[0212] In the third phase, called the light-emitting phase, the signal on the light-emitting signal line is a low-level signal, while the signals on the first scanning signal line and the second scanning signal line are high-level signals. The low-level signal on the light-emitting signal line turns on the fifth and sixth transistors. The power supply voltage output from the first power supply line provides a driving voltage to the first electrode through the turned-on fifth, third, and sixth transistors, driving the light emission.

[0213] During the pixel driving circuit driving process, the driving current flowing through the third transistor (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage at the second node is Vdata-|Vth|, the driving current of the third transistor is: I=K*(Vgs-Vth) 2 =K*[(Vdata-Vdd] 2

[0214] Among them, I is the driving current flowing through the third transistor, that is, the driving current, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor, Vth is the threshold voltage of the third transistor, Vdata is the data voltage output by the data signal line, and Vdd is the power supply voltage output by the first power supply line.

[0215] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor is no longer affected by the threshold voltage of the third transistor, thereby eliminating the influence of the threshold voltage of the third transistor on the driving current, ensuring the uniform display brightness of the display product and improving the display effect of the entire display product.

[0216] In an exemplary embodiment, the light-emitting device may include any one of an organic light-emitting diode (OLED), a quantum dot light-emitting diode, and an inorganic light-emitting diode. For example, the light-emitting device may be a micron-sized light-emitting device, such as a micro light-emitting diode (Micro LED), a sub-millimeter light-emitting diode (Mini LED), or a micro organic light-emitting diode (Micro OLED), etc., and the embodiments of the present disclosure are not limited to this. For example, taking the light-emitting device as an organic light-emitting diode (OLED) as an example, the light-emitting device may include: a stacked first electrode (for example, as an anode), an organic light-emitting layer, and a second electrode (for example, as a cathode).

[0217] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the emissive layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0218] In the display market, most display substrates utilize low-temperature polysilicon (LTPS) technology, which boasts advantages such as high resolution, high response speed, high brightness, and a high aperture ratio. Despite its popularity, LTPS technology also has drawbacks, such as high production costs and high power consumption. This is where low-temperature polycrystalline oxide (LTPO) technology comes in. Compared to LTPS technology, LTPO offers lower leakage current and faster pixel response. The addition of an oxide layer to the display substrate reduces the energy required to excite the pixels, thereby reducing power consumption during screen display.

[0219] A display product includes a gate driver circuit and multiple sub-pixels. Each sub-pixel includes a pixel driver circuit. When the display product displays an image, the gate driver circuit generates a drive signal. Under control of the drive signal, the pixel driver circuit performs initialization and data writing, thereby achieving display. The display product refreshes its image at every frame, meaning the pixel driver circuit needs to be initialized and data written during each display frame. However, for some special images (e.g., off-screen display, static images, or images that are rarely updated), initialization and data writing to the pixel driver circuit are not required during at least some display frames. Low-leakage pixel driver circuits can maintain the original brightness. The gate driver circuit of the display product generates a drive signal for each frame, regardless of the image being displayed. This repeatedly initializes and writes data to the pixel driver circuit, resulting in high power consumption. The shift register includes multiple output transistors, some of which have their gate electrodes connected to the same node. This prevents the shift register from fully outputting output, or even if the shift register can fully output, the shift register consumes a lot of power, reducing its reliability.

[0220] FIG57 is a schematic diagram of the structure of a shift register provided by the present disclosure. As shown in FIG57 , an embodiment of the present disclosure provides a shift register, including: a shift subcircuit and an output subcircuit. FIG57 is illustrated using the i-th stage shift register as an example.

[0221] As shown in FIG57 , the shift sub-circuit can be electrically connected to the signal input terminal IN(i), the first clock signal terminal CK, the second clock signal terminal CB, the first power supply terminal VH1, the second power supply terminal VL1, and the cascade signal output terminal OUTC(i), and is configured to provide a signal to the cascade signal output terminal OUTC(i) under the control of the signals from the signal input terminal IN(i), the first clock signal terminal CK, the second clock signal terminal CB, the first power supply terminal VH1, and the second power supply terminal VL1; the output sub-circuit is electrically connected to the shift sub-circuit, the latch signal terminal M S, the first control signal terminal V1, the second control signal terminal V2, the third power supply terminal VH2, the fourth power supply terminal VL2, the fifth power supply terminal NCX, the cascade signal output terminal OUTC(i) and the drive signal output terminal OUT(i) are electrically connected, and are configured to provide a signal to the drive signal output terminal OUT(i) under the control of the signals of the shift sub-circuit, the latch signal terminal MS, the first control signal terminal V1, the second control signal terminal V2, the cascade signal output terminal OUTC(i), the third power supply terminal VH2, the fourth power supply terminal VL2 and the fifth power supply terminal NCX.

[0222] In the present disclosure, a shift subcircuit includes: at least one shift output transistor electrically connected to a cascade signal output terminal OUTC(i); an output subcircuit includes: at least one driver output transistor electrically connected to a driver signal output terminal OUT(i); the shift subcircuit further includes: at least one transistor; and the output subcircuit further includes: at least one transistor. The shift subcircuit is provided with a third node, and the control electrode of the at least one driver output transistor is electrically connected to the third node via the at least one transistor of the output subcircuit, and the control electrode of the at least one shift output transistor is electrically connected to the third node via the at least one transistor of the shift subcircuit.

[0223] In the present disclosure, the control electrode of at least one driving output transistor is electrically connected to the third node through at least one transistor of the output sub-circuit, and the control electrode of at least one shift output transistor is electrically connected to the third node through at least one transistor of the shift sub-circuit, so that the control electrode of at least one driving output transistor and the control electrode of at least one shift output transistor are not directly connected to the same node, but are electrically connected through other transistors, so that the cascade signal output end and the driving signal output end are driven through different nodes, which not only ensures the full output of the shift register, but also reduces the power consumption of the shift register and improves the reliability of the shift register.

[0224] In an exemplary embodiment, as shown in Figure 57, the shift sub-circuit is also electrically connected to the fifth power supply terminal NCX, and is configured to provide a signal to the cascade signal output terminal OUTC(i) under the control of the signals of the signal input terminal IN(i), the first clock signal terminal CK, the second clock signal terminal CB, the first power supply terminal VH1 and the second power supply terminal VL1 and the fifth power supply terminal NCX.

[0225] In an exemplary embodiment, FIG58 is an equivalent circuit diagram of a shift sub-circuit 1. As shown in FIG58, the shift sub-circuit may include: first to sixteenth transistors T1 to T16 and first to third capacitors C1 to C3.

[0226] As shown in FIG58 , the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN(i), and the second electrode of the first transistor T1 is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK, and the second electrode of the second transistor T2 is electrically connected to the tenth node N10; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VL1, and the second electrode of the third transistor T3 is electrically connected to the tenth node N10; the control electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VL1, and the second electrode of the third transistor T3 is electrically connected to the tenth node N10; The node N2 is electrically connected, a first electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB, and a second electrode of the fourth transistor T4 is electrically connected to the fifth node N5; a control electrode of the fifth transistor T5 is electrically connected to the tenth node N10, a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VH1, and a second electrode of the fifth transistor T5 is electrically connected to the fifth node N5; a control electrode of the sixth transistor T6 is electrically connected to the sixth node N6, a first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CB, and a second electrode of the sixth transistor T6 is electrically connected to the first node N1; a control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, and a first electrode of the seventh transistor T7 is electrically connected to the first node N1 The second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the control electrode of the eighth transistor T8 is electrically connected to the third node N3, the first electrode of the eighth transistor T8 is electrically connected to the first power supply terminal VH1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected to the fourth node N4, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VH1, and the second electrode of the ninth transistor T9 is electrically connected to the cascade signal output terminal OUTC(i); the gate electrode of the tenth transistor T10 is electrically connected to the ninth node N9, the first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal VL1, and the second electrode of the tenth transistor T10 is electrically connected to the cascade signal output terminal OUTC(i). a control electrode of the eleventh transistor T11 electrically connected to the second power supply terminal VL1, a first electrode of the eleventh transistor T11 electrically connected to the tenth node N10, and a second electrode of the eleventh transistor T11 electrically connected to the sixth node N6; a control electrode of the twelfth transistor T12 electrically connected to the second power supply terminal VL1, a first electrode of the twelfth transistor T12 electrically connected to the third node N3, and a second electrode of the twelfth transistor T12 electrically connected to the ninth node N9; a control electrode of the thirteenth transistor T13 electrically connected to the fifth power supply terminal NCX, a first electrode of the thirteenth transistor T13 electrically connected to the first power supply terminal VH1, and a second electrode of the thirteenth transistor T13 electrically connected to the third node N3;A control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK, a first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal IN(i), and a second electrode of the fourteenth transistor T14 is electrically connected to a first electrode of the fifteenth transistor T15; a control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VL1, and a second electrode of the fifteenth transistor T15 is electrically connected to the second node N2; a control electrode of the sixteenth transistor T16 is electrically connected to the second node N2, a first electrode of the sixteenth transistor T16 is electrically connected to the ninth node N9, and a second electrode of the sixteenth transistor T16 is electrically connected to the second node N2; a first plate of the first capacitor C1 is electrically connected to the sixth node N6, and a second plate of the first capacitor C1 is electrically connected to the first node N1; a first plate of the second capacitor C2 is electrically connected to the fourth node N4, and a second plate of the second capacitor C2 is electrically connected to the first power supply terminal VH1; a first plate of the third capacitor C3 is electrically connected to the second node N2, and a second plate of the third capacitor C3 is electrically connected to the fifth node N5.

[0227] In an exemplary embodiment, FIG59 is a second equivalent circuit diagram of a shift sub-circuit. As shown in FIG59 , the shift sub-circuit may include: first to fifteenth transistors T1 to T15 and first to third capacitors C1 to C3.

[0228] As shown in FIG59 , the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN(i), and the second electrode of the first transistor T1 is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK, and the second electrode of the second transistor T2 is electrically connected to the tenth node N10; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VL1, and the second electrode of the third transistor T3 is electrically connected to the tenth node N10; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB, and the second electrode of the fourth transistor T4 is electrically connected to the fifth node N5; the control electrode of the fifth transistor T5 is electrically connected to the tenth node N10, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VH1, and the second electrode of the fifth transistor T5 is electrically connected to the fifth node N5; The control electrode of the sixth transistor T6 is electrically connected to the sixth node N6, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CB, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, the first electrode of the seventh transistor T7 is electrically connected to the first node N1, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the control electrode of the eighth transistor T8 is electrically connected to the third node N3, the first electrode of the eighth transistor T8 is electrically connected to the first power supply terminal VH1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected to the fourth node N4, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VH1, and the second electrode of the ninth transistor T9 is electrically connected to the cascade signal output terminal OUTC(i); the control electrode of the tenth transistor T10 is electrically connected to the second clock signal terminal CB, the first electrode of the seventh transistor T7 is electrically connected to the first node N1, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; a control electrode of the thirteenth transistor T13 is electrically connected to the fifth power supply terminal NCX, a first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal VH1, and a second electrode of the thirteenth transistor T13 is electrically connected to the third node N3; a control electrode of the thirteenth transistor T13 is electrically connected to the fifth power supply terminal NCX, a first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal VH1, and a second electrode of the thirteenth transistor T13 is electrically connected to the third node N3; a control electrode of the thirteenth transistor T13 is electrically connected to the fifth power supply terminal NCX, a first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal VH1, and a second electrode of the thirteenth transistor T13 is electrically connected to the third node N3;A control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK, a first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal IN(i), and a second electrode of the fourteenth transistor T14 is electrically connected to a first electrode of the fifteenth transistor T15; a control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VL1, and a second electrode of the fifteenth transistor T15 is electrically connected to the second node N2; a first plate of the first capacitor C1 is electrically connected to the sixth node N6, and a second plate of the first capacitor C1 is electrically connected to the first node N1; a first plate of the second capacitor C2 is electrically connected to the fourth node N4, and a second plate of the second capacitor C2 is electrically connected to the first power supply terminal VH1; a first plate of the third capacitor C3 is electrically connected to the second node N2, and a second plate of the third capacitor C3 is electrically connected to the fifth node N5.

[0229] In an exemplary embodiment, the sixteenth transistor T16 and the seventeenth transistor T17 can transmit the signal of the signal input terminal IN to the control electrode of the twenty-sixth transistor T26, which can further ensure the stability of the signal of the control electrode of the twenty-sixth transistor T26 and ensure the stability of the signal output by the driving signal output terminal of the shift register.

[0230] In an exemplary embodiment, as shown in FIG. 58 and FIG. 59 , the shift sub-circuit may further include: a fourth capacitor C4 .

[0231] As shown in FIG58 and FIG59 , the first plate of the fourth capacitor C4 is electrically connected to the second power supply terminal VL1 , and the second plate of the fourth capacitor C4 is electrically connected to the cascade signal output terminal OUTC(i).

[0232] In example embodiments, the first control signal terminal V1 may be electrically connected to the fifth node N5 .

[0233] In an exemplary embodiment, the second control signal terminal V2 may be electrically connected to the first node N1 in the previous stage shift register of the current stage shift register.

[0234] In an exemplary embodiment, as shown in FIG. 58 and FIG. 59 , the output sub-circuit is electrically connected to the second node N2 , the third node N3 , and the fourth node N4 in the shift register, respectively.

[0235] In an exemplary embodiment, FIG60 is an equivalent circuit diagram of an output sub-circuit. As shown in FIG60 , when the shift sub-circuit is the shift sub-circuit provided in FIG58 and FIG59 , the output sub-circuit may include: seventeenth transistor T17 to twenty-sixth transistor T26, and fifth capacitor C5 and sixth capacitor C6.

[0236] As shown in FIG60 , the control electrode and the first electrode of the seventeenth transistor T17 are electrically connected to the second node N2, respectively, and the second electrode of the seventeenth transistor T17 is electrically connected to the sixth node N6; the control electrode of the eighteenth transistor T18 is electrically connected to the seventh node N7, the first electrode of the eighteenth transistor T18 is electrically connected to the third node N3, and the second electrode of the eighteenth transistor T18 is electrically connected to the sixth node N6; the control electrode of the nineteenth transistor T19 is electrically connected to the second control signal terminal V2, the first electrode of the nineteenth transistor T19 is electrically connected to the latch signal terminal MS, and the second electrode of the nineteenth transistor T19 is electrically connected to the second electrode of the twentieth transistor T20; the control electrode of the twentieth transistor T20 is electrically connected to the cascade signal output terminal OUTC (i) is electrically connected, a first electrode of the twentieth transistor T20 is electrically connected to the seventh node N7; a control electrode of the twenty-first transistor T21 is electrically connected to the seventh node N7, a first electrode of the twenty-first transistor T21 is electrically connected to the fourth node N4, and a second electrode of the twenty-first transistor T21 is electrically connected to the eighth node N8; a control electrode of the twenty-second transistor T22 is electrically connected to the fifth power supply terminal NCX, a first electrode of the twenty-second transistor T22 is electrically connected to the fourth power supply terminal VL2, and a second electrode of the twenty-second transistor T22 is electrically connected to the seventh node N7; a control electrode of the twenty-third transistor T23 is electrically connected to the first control signal terminal V1, a first electrode of the twenty-third transistor T23 is electrically connected to the fourth power supply terminal VL2, and a second electrode of the twenty-third transistor T23 is electrically connected to the seventh node N7; a control electrode of the twenty-fourth transistor T24 is electrically connected to the sixth node N6, and a control electrode of the twenty-fourth transistor T24 is electrically connected to the sixth node N6. a first electrode of the twenty-fourth transistor T24 is electrically connected to the eighth node N8; a control electrode of the twenty-fifth transistor T25 is electrically connected to the eighth node N8, a first electrode of the twenty-fifth transistor T25 is electrically connected to the third power supply terminal VH2, and a second electrode of the twenty-fifth transistor T25 is electrically connected to the drive signal output terminal OUT(i); a control electrode of the twenty-sixth transistor T26 is electrically connected to the sixth node N6, a first electrode of the twenty-sixth transistor T26 is electrically connected to the fourth power supply terminal VL2, and a second electrode of the twenty-sixth transistor T26 is electrically connected to the drive signal output terminal OUT(i); a first plate of the fifth capacitor C5 is electrically connected to the seventh node N7, and a second plate of the fifth capacitor C5 is electrically connected to the eighth node N8; a first plate of the sixth capacitor C6 is electrically connected to the eighth node N8, and a second plate of the sixth capacitor C6 is electrically connected to the third power supply terminal VH2.

[0237] In an exemplary embodiment, FIG61 is a third equivalent circuit diagram of a shift sub-circuit. As shown in FIG61 , the shift sub-circuit may include: first to eighth transistors T1 to T8, and a first capacitor C1 and a second capacitor C2.

[0238] As shown in Figure 61, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN(i), and the second electrode of the first transistor T1 is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VL1, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected to the fourth node N4, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VH1, and the second electrode of the fourth transistor T4 is electrically connected to the cascade signal output terminal OUTC(i); the control electrode of the fifth transistor T5 is electrically connected to the ninth node N9, and the first electrode of the fifth transistor T5 is electrically connected to the ninth node N9. The first electrode of the first capacitor C1 is electrically connected to the ninth node N9, and the second electrode of the first capacitor C1 is electrically connected to the cascade signal output terminal OUTC(i). The first plate of the second capacitor C2 is electrically connected to the fourth node N4, and the second plate of the second capacitor C2 is electrically connected to the first power supply terminal VH1.

[0239] In an exemplary embodiment, when the shift sub-circuit is the shift sub-circuit provided in FIG. 61 , the output sub-circuit is further electrically connected to the third node N3 and the fourth node N4 in the shift sub-circuit, respectively.

[0240] In an exemplary embodiment, FIG62 is a second equivalent circuit diagram of the output sub-circuit. As shown in FIG62 , when the shift sub-circuit is the shift sub-circuit provided in FIG61 , the output sub-circuit includes: eighteenth transistor T18 to twenty-sixth transistor T26 and fifth and sixth capacitors C5 and C6.

[0241] As shown in FIG62 , a control electrode of the eighteenth transistor T18 is electrically connected to the seventh node N7, a first electrode of the eighteenth transistor T18 is electrically connected to the third node N3, and a second electrode of the eighteenth transistor T18 is electrically connected to the sixth node N6; a control electrode of the nineteenth transistor T19 is electrically connected to the second control signal terminal V2, a first electrode of the nineteenth transistor T19 is electrically connected to the latch signal terminal MS, and a second electrode of the nineteenth transistor T19 is electrically connected to the second electrode of the twentieth transistor T20; A control electrode of the twentieth transistor T20 is electrically connected to the cascade signal output terminal OUTC(i), and a first electrode of the twentieth transistor T20 is electrically connected to the seventh node N7; a control electrode of the twenty-first transistor T21 is electrically connected to the seventh node N7, a first electrode of the twenty-first transistor T21 is electrically connected to the fourth node N4, and a second electrode of the twenty-first transistor T21 is electrically connected to the eighth node N8; a control electrode of the twenty-second transistor T22 is electrically connected to the fifth power supply terminal NCX, a first electrode of the twenty-second transistor T22 is electrically connected to the fourth power supply terminal VL2, and a second electrode of the twenty-second transistor T22 is electrically connected to the seventh node N7; a control electrode of the twenty-third transistor T23 is electrically connected to the first control signal terminal V1, a first electrode of the twenty-third transistor T23 is electrically connected to the fourth power supply terminal VL2, and a second electrode of the twenty-third transistor T23 is electrically connected to the seventh node N7; a control electrode of the twenty-fourth transistor T24 is electrically connected to the sixth node N6 a first electrode of the twenty-fourth transistor T24 is electrically connected to the third power supply terminal VH2, and a second electrode of the twenty-fourth transistor T24 is electrically connected to the eighth node N8; a control electrode of the twenty-fifth transistor T25 is electrically connected to the eighth node N8, a first electrode of the twenty-fifth transistor T25 is electrically connected to the third power supply terminal VH2, and a second electrode of the twenty-fifth transistor T25 is electrically connected to the drive signal output terminal OUT(i); a control electrode of the twenty-sixth transistor T26 is electrically connected to the sixth node N6, a first electrode of the twenty-sixth transistor T26 is electrically connected to the fourth power supply terminal VL2, and a second electrode of the twenty-sixth transistor T26 is electrically connected to the drive signal output terminal OUT(i); a first plate of the fifth capacitor C5 is electrically connected to the seventh node N7, and a second plate of the fifth capacitor C5 is electrically connected to the eighth node N8; a first plate of the sixth capacitor C6 is electrically connected to the eighth node N8, and a second plate of the sixth capacitor C6 is electrically connected to the third power supply terminal VH2.

[0242] In an exemplary embodiment, the first power terminal VH1 and the third power terminal VH2 are high-level power terminals configured to provide high-level power signals.

[0243] In an exemplary embodiment, the first power terminal VH1 and the third power terminal VH2 may be the same signal terminal.

[0244] In an exemplary embodiment, the second power terminal VL1 and the fourth power terminal VL2 are low-level power terminals configured to provide low-level power signals.

[0245] In an exemplary embodiment, the second power terminal VL1 and the fourth power terminal VL2 may be the same signal terminal.

[0246] In an exemplary embodiment, the twenty-fourth transistor T24 and the twenty-sixth transistor T26 are turned on or turned off simultaneously. When the twenty-sixth transistor T26 is turned on and a low-level signal from the fourth power supply terminal VL2 is written to the drive signal output terminal OUT, the twenty-fourth transistor T24 is turned on, causing a high-level signal from the third power supply terminal VH2 to be written to the eighth node N8. This causes the twenty-fifth transistor T25 to be turned off, preventing the high-level signal from the third power supply terminal VH2 from being written to the drive signal output terminal. This ensures the output stability of the drive signal output terminal and improves the reliability of the shift register.

[0247] FIG63 is an equivalent circuit diagram of a shift register. As shown in FIG63 , the shift subcircuit in the shift register includes: a first transistor T1 to a sixteenth transistor T16 and a first capacitor C1 to a fourth capacitor C4; the output subcircuit includes: a seventeenth transistor T17 to a twenty-sixth transistor T26 and a fifth capacitor C5 and a sixth capacitor C6. The control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN(i), and the second electrode of the first transistor T1 is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK, and the second electrode of the second transistor T2 is electrically connected to the tenth node N10; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VL1, and the second electrode of the third transistor T3 is electrically connected to the tenth node N10; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, and the first electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB The first electrode of the fourth transistor T4 is electrically connected to the fifth node N5; the control electrode of the fifth transistor T5 is electrically connected to the tenth node N10, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VH1, and the second electrode of the fifth transistor T5 is electrically connected to the fifth node N5; the control electrode of the sixth transistor T6 is electrically connected to the sixth node N6, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CB, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, the first electrode of the seventh transistor T7 is electrically connected to the first node N1, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the control electrode of the eighth transistor T8 is electrically connected to the third node N3, and the eighth transistor T8 is electrically connected to the a first electrode of the eighth transistor T8 is electrically connected to the first power supply terminal VH1, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; a control electrode of the ninth transistor T9 is electrically connected to the fourth node N4, a first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VH1, and a second electrode of the ninth transistor T9 is electrically connected to the cascade signal output terminal OUTC(i); a gate electrode of the tenth transistor T10 is electrically connected to the ninth node N9, a first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal VL1, and a second electrode of the tenth transistor T10 is electrically connected to the cascade signal output terminal OUTC(i); a control electrode of the eleventh transistor T11 is electrically connected to the second power supply terminal VL1, a first electrode of the eleventh transistor T11 is electrically connected to the tenth node N10, and a second electrode of the eleventh transistor T11 is electrically connected to the sixth node N6; a control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VL1, a first electrode of the twelfth transistor T12 is electrically connected to the third node N3, and a second electrode of the twelfth transistor T12 is electrically connected to the ninth node N9;A control electrode of the thirteenth transistor T13 is electrically connected to the fifth power supply terminal NCX, a first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal VH1, and a second electrode of the thirteenth transistor T13 is electrically connected to the third node N3; a control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK, a first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal IN(i), and a second electrode of the fourteenth transistor T14 is electrically connected to the first electrode of the fifteenth transistor T15; a control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VL1, and a second electrode of the fifteenth transistor T15 is electrically connected to the second node N2; a control electrode of the sixteenth transistor T16 is electrically connected to the second node N2, A first electrode of the sixteenth transistor T16 is electrically connected to the ninth node N9, and a second electrode of the sixteenth transistor T16 is electrically connected to the second node N2; a control electrode and a first electrode of the seventeenth transistor T17 are electrically connected to the second node N2, respectively, and a second electrode of the seventeenth transistor T17 is electrically connected to the sixth node N6; a control electrode of the eighteenth transistor T18 is electrically connected to the seventh node N7, a first electrode of the eighteenth transistor T18 is electrically connected to the third node N3, and a second electrode of the eighteenth transistor T18 is electrically connected to the sixth node N6; a control electrode of the nineteenth transistor T19 is electrically connected to the second control signal terminal V2, a first electrode of the nineteenth transistor T19 is electrically connected to the latch signal terminal MS, and a a second electrode of the 20th transistor T20 is electrically connected to the second electrode of the 20th transistor T20; a control electrode of the 20th transistor T20 is electrically connected to the cascade signal output terminal OUTC(i), and a first electrode of the 20th transistor T20 is electrically connected to the seventh node N7; a control electrode of the 21st transistor T21 is electrically connected to the seventh node N7, a first electrode of the 21st transistor T21 is electrically connected to the fourth node N4, and a second electrode of the 21st transistor T21 is electrically connected to the eighth node N8; a control electrode of the 22nd transistor T22 is electrically connected to the fifth power supply terminal NCX, a first electrode of the 22nd transistor T22 is electrically connected to the fourth power supply terminal VL2, and a second electrode of the 22nd transistor T22 is electrically connected to the seventh node N7; and a control electrode of the 23rd transistor T21 is electrically connected to the seventh node N7, a first electrode of the 21st transistor T21 is electrically connected to the fourth node N4, and a second electrode of the 21st transistor T21 is electrically connected to the eighth node N8. A control electrode of the transistor T23 is electrically connected to the first control signal terminal V1, a first electrode of the twenty-third transistor T23 is electrically connected to the fourth power supply terminal VL2, and a second electrode of the twenty-third transistor T23 is electrically connected to the seventh node N7; a control electrode of the twenty-fourth transistor T24 is electrically connected to the sixth node N6, a first electrode of the twenty-fourth transistor T24 is electrically connected to the third power supply terminal VH2, and a second electrode of the twenty-fourth transistor T24 is electrically connected to the eighth node N8; a control electrode of the twenty-fifth transistor T25 is electrically connected to the eighth node N8, a first electrode of the twenty-fifth transistor T25 is electrically connected to the third power supply terminal VH2, and a second electrode of the twenty-fifth transistor T25 is electrically connected to the drive signal output terminal OUT(i);A control electrode of the twenty-sixth transistor T26 is electrically connected to the sixth node N6, a first electrode of the twenty-sixth transistor T26 is electrically connected to the fourth power supply terminal VL2, and a second electrode of the twenty-sixth transistor T26 is electrically connected to the drive signal output terminal OUT(i); a first plate of the first capacitor C1 is electrically connected to the sixth node N6, and a second plate of the first capacitor C1 is electrically connected to the first node N1; a first plate of the second capacitor C2 is electrically connected to the fourth node N4, and a second plate of the second capacitor C2 is electrically connected to the first power supply terminal VH1; a first plate of the third capacitor C3 is electrically connected to the second node N2, and a second plate of the third capacitor C3 is electrically connected to the fifth node N5; a first plate of the fourth capacitor C4 is electrically connected to the second power supply terminal VL1, and a second plate of the fourth capacitor C4 is electrically connected to the cascade signal output terminal OUTC(i); a first plate of the fifth capacitor C5 is electrically connected to the seventh node N7, and a second plate of the fifth capacitor C5 is electrically connected to the eighth node N8; a first plate of the sixth capacitor C6 is electrically connected to the eighth node N8, and a second plate of the sixth capacitor C6 is electrically connected to the third power supply terminal VH2. ;

[0248] Figure 64 is a second equivalent circuit diagram of a shift register. As shown in Figure 64, the shift sub-circuit in the shift register includes: a first transistor T1 to a fifteenth transistor T15 and a first capacitor C1 to a fourth capacitor C4, and the output sub-circuit may include: a seventeenth transistor T17 to a twenty-sixth transistor T26 and a fifth capacitor C5 and a sixth capacitor C6. Among them, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN(i), and the second electrode of the first transistor T1 is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK, and the second electrode of the second transistor T2 is electrically connected to the tenth node N10; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VL1, and the second electrode of the third transistor T3 is electrically connected to the tenth node N10 The control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB, and the second electrode of the fourth transistor T4 is electrically connected to the fifth node N5; the control electrode of the fifth transistor T5 is electrically connected to the tenth node N10, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VH1, and the second electrode of the fifth transistor T5 is electrically connected to the fifth node N5; the control electrode of the sixth transistor T6 is electrically connected to the sixth node N6, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CB, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1; the seventh transistor T7 is electrically connected to the tenth node N10, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VH1, and the second electrode of the fifth transistor T5 is electrically connected to the fifth node N5; the control electrode of the sixth transistor T6 is electrically connected to the sixth node N6, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CB, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1; The control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, the first electrode of the seventh transistor T7 is electrically connected to the first node N1, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the control electrode of the eighth transistor T8 is electrically connected to the third node N3, the first electrode of the eighth transistor T8 is electrically connected to the first power supply terminal VH1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected to the fourth node N4, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VH1, and the second electrode of the ninth transistor T9 is electrically connected to the cascade signal output terminal OUTC(i); the control electrode of the tenth transistor T10 is electrically connected to the third node N3, the first electrode of the eighth transistor T8 is electrically connected to the first power supply terminal VH1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected to the fourth node N4, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VH1, and the second electrode of the ninth transistor T9 is electrically connected to the cascade signal output terminal OUTC(i); a control electrode of the eleventh transistor T11 electrically connected to the second power supply terminal VL1, a first electrode of the eleventh transistor T11 electrically connected to the tenth node N10, and a second electrode of the eleventh transistor T11 electrically connected to the sixth node N6; a control electrode of the twelfth transistor T12 electrically connected to the second power supply terminal VL1, a first electrode of the twelfth transistor T12 electrically connected to the third node N3, and a second electrode of the twelfth transistor T12 electrically connected to the second node N2;The control electrode of the thirteenth transistor T13 is electrically connected to the fifth power supply terminal NCX, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal VH1, and the second electrode of the thirteenth transistor T13 is electrically connected to the third node N3; the control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK, the first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal IN(i), and the second electrode of the fourteenth transistor T14 is electrically connected to the first electrode of the fifteenth transistor T15; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VL1, and the second electrode of the fifteenth transistor T15 is electrically connected to the second node N2; the control electrode and the first electrode of the seventeenth transistor T17 are electrically connected to the first clock signal terminal CK, the first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal IN(i), and the second electrode of the fourteenth transistor T14 is electrically connected to the first electrode of the fifteenth transistor T15; The first electrode of the eighteenth transistor T18 is electrically connected to the seventh node N7, the first electrode of the eighteenth transistor T18 is electrically connected to the third node N3, and the second electrode of the eighteenth transistor T18 is electrically connected to the sixth node N6; the control electrode of the nineteenth transistor T19 is electrically connected to the second control signal terminal V2, the first electrode of the nineteenth transistor T19 is electrically connected to the latch signal terminal MS, and the second electrode of the nineteenth transistor T19 is electrically connected to the second electrode of the twentieth transistor T20; the control electrode of the twentieth transistor T20 is electrically connected to the cascade signal output terminal OUTC(i), and the twentieth transistor T20 is electrically connected to the cascade signal output terminal OUTC(i). The first electrode of the twenty-second transistor T22 is electrically connected to the fifth power supply terminal NCX, the first electrode of the twenty-second transistor T22 is electrically connected to the fourth power supply terminal VL2, and the second electrode of the twenty-second transistor T22 is electrically connected to the seventh node N7; the control electrode of the twenty-third transistor T23 is electrically connected to the first control signal terminal V1, the first electrode of the twenty-third transistor T23 is electrically connected to the fourth power supply terminal VL2, and the second electrode of the twenty-third transistor T23 is electrically connected to the seventh node N7; the control electrode of the twenty-third transistor T23 is electrically connected to the first control signal terminal V1, the first electrode of the twenty-third transistor T23 is electrically connected to the fourth power supply terminal VL2, and the second electrode of the twenty-third transistor T23 is electrically connected to the eighth node N8. A second electrode of the transistor T23 is electrically connected to the seventh node N7; a control electrode of the twenty-fourth transistor T24 is electrically connected to the sixth node N6, a first electrode of the twenty-fourth transistor T24 is electrically connected to the third power supply terminal VH2, and a second electrode of the twenty-fourth transistor T24 is electrically connected to the eighth node N8; a control electrode of the twenty-fifth transistor T25 is electrically connected to the eighth node N8, a first electrode of the twenty-fifth transistor T25 is electrically connected to the third power supply terminal VH2, and a second electrode of the twenty-fifth transistor T25 is electrically connected to the drive signal output terminal OUT(i); a control electrode of the twenty-sixth transistor T26 is electrically connected to the sixth node N6, a first electrode of the twenty-sixth transistor T26 is electrically connected to the fourth power supply terminal VL2, and a second electrode of the twenty-sixth transistor T26 is electrically connected to the drive signal output terminal OUT(i); a first plate of the first capacitor C1 is electrically connected to the sixth node N6, and a second plate of the first capacitor C1 is electrically connected to the first node N1;A first plate of the second capacitor C2 is electrically connected to the fourth node N4, and a second plate of the second capacitor C2 is electrically connected to the first power supply terminal VH1; a first plate of the third capacitor C3 is electrically connected to the second node N2, and a second plate of the third capacitor C3 is electrically connected to the fifth node N5; a first plate of the fourth capacitor C4 is electrically connected to the second power supply terminal VL1, and a second plate of the fourth capacitor C4 is electrically connected to the cascade signal output terminal OUTC(i); a first plate of the fifth capacitor C5 is electrically connected to the seventh node N7, and a second plate of the fifth capacitor C5 is electrically connected to the eighth node N8; a first plate of the sixth capacitor C6 is electrically connected to the eighth node N8, and a second plate of the sixth capacitor C6 is electrically connected to the third power supply terminal VH2.

[0249] FIG65 is a third equivalent circuit diagram of a shift register. As shown in FIG65 , the shift subcircuit in the shift register includes: a first transistor T1 to an eighth transistor T8 and a first capacitor C1 and a second capacitor C2; the output subcircuit includes: an eighteenth transistor T18 to a twenty-sixth transistor T26 and a fifth capacitor C5 and a sixth capacitor C6. Among them, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN(i), and the second electrode of the first transistor T1 is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VL1, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4. N4 is electrically connected; the control electrode of the fourth transistor T4 is electrically connected to the fourth node N4, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VH1, and the second electrode of the fourth transistor T4 is electrically connected to the cascade signal output terminal OUTC(i); the control electrode of the fifth transistor T5 is electrically connected to the ninth node N9, the first electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CB, and the second electrode of the fifth transistor T5 is electrically connected to the cascade signal output terminal OUTC(i); the control electrode of the sixth transistor T6 is electrically connected to the fourth node N4, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VH1, and the sixth transistor T The second electrode of the eighth transistor T8 is electrically connected to the second power supply terminal VL1, the first electrode of the eighth transistor T8 is electrically connected to the third node N3, and the second electrode of the eighth transistor T8 is electrically connected to the ninth node N9; the control electrode of the eighth transistor T18 is electrically connected to the seventh node N7, the first electrode of the eighth transistor T18 is electrically connected to the third node N3, and the second electrode of the eighth transistor T18 is electrically connected to the sixth node N6; the control electrode of the eighth transistor T18 is electrically connected to the seventh node N7, the first electrode of the eighth transistor T18 is electrically connected to the third node N3, and the second electrode of the eighth transistor T18 is electrically connected to the sixth node N6; the control electrode of the eighth transistor T18 is electrically connected to the second power supply terminal VL1, the first electrode of the eighth transistor T8 is electrically connected to the third node N3, and the second electrode of the eighth transistor T18 is electrically connected to the ninth node N9; A control electrode of the transistor T19 is electrically connected to the second control signal terminal V2, a first electrode of the nineteenth transistor T19 is electrically connected to the latch signal terminal MS, and a second electrode of the nineteenth transistor T19 is electrically connected to the second electrode of the twentieth transistor T20; a control electrode of the twentieth transistor T20 is electrically connected to the cascade signal output terminal OUTC(i), and a first electrode of the twentieth transistor T20 is electrically connected to the seventh node N7; a control electrode of the twenty-first transistor T21 is electrically connected to the seventh node N7, a first electrode of the twenty-first transistor T21 is electrically connected to the fourth node N4, and a second electrode of the twenty-first transistor T21 is electrically connected to the eighth node N8;The control electrode of the twenty-second transistor T22 is electrically connected to the fifth power supply terminal NCX, the first electrode of the twenty-second transistor T22 is electrically connected to the fourth power supply terminal VL2, and the second electrode of the twenty-second transistor T22 is electrically connected to the seventh node N7; the control electrode of the twenty-third transistor T23 is electrically connected to the first control signal terminal V1, the first electrode of the twenty-third transistor T23 is electrically connected to the fourth power supply terminal VL2, and the second electrode of the twenty-third transistor T23 is electrically connected to the seventh node N7; the control electrode of the twenty-fourth transistor T24 is electrically connected to the sixth node N6, the first electrode of the twenty-fourth transistor T24 is electrically connected to the third power supply terminal VH2, and the second electrode of the twenty-fourth transistor T24 is electrically connected to the eighth node N8; the control electrode of the twenty-fifth transistor T25 is electrically connected to the eighth node N8, the first electrode of the twenty-fifth transistor T25 is electrically connected to the third power supply terminal VH2, and the second electrode of the twenty-fifth transistor T25 is electrically connected to the eighth node N8. The second electrode of transistor T25 is electrically connected to the drive signal output terminal OUT(i); the control electrode of transistor T26 is electrically connected to the sixth node N6, the first electrode of transistor T26 is electrically connected to the fourth power supply terminal VL2, and the second electrode of transistor T26 is electrically connected to the drive signal output terminal OUT(i); the first plate of capacitor C1 is electrically connected to the ninth node N9, and the second plate of capacitor C1 is electrically connected to the cascade signal output terminal OUTC(i); the first plate of capacitor C2 is electrically connected to the fourth node N4, and the second plate of capacitor C2 is electrically connected to the first power supply terminal VH1; the first plate of capacitor C5 is electrically connected to the seventh node N7, and the second plate of capacitor C5 is electrically connected to the eighth node N8; the first plate of capacitor C6 is electrically connected to the eighth node N8, and the second plate of capacitor C6 is electrically connected to the third power supply terminal VH2.

[0250] In an exemplary embodiment, as shown in Figures 63 and 65, in the shift register provided by the present disclosure, the twenty-sixth transistor T26 (also a driving output transistor of the output sub-circuit) is electrically connected to the third node N3 via the first and second electrodes of the eighteenth transistor, and the tenth transistor T10 (also a shift output sub-circuit of the shift sub-circuit) is electrically connected to the third node N3 via the first and second electrodes of the twelfth transistor. The configuration of the twelfth transistor T12 and the eighteenth transistor T18 ensures that the gate electrodes of the tenth transistor T10 and the twenty-sixth transistor T26 are not directly connected to the same node. Whether the signal of the third node N3 is written to the control electrode of the twenty-sixth transistor T26 is controlled by the signal of the seventh node of the output sub-circuit, ensuring that the driving output transistors of the output sub-circuit can be independently controlled. This not only ensures sufficient output of the shift register, but also reduces the power consumption of the shift register and improves the reliability of the shift register.

[0251] An embodiment of the present disclosure provides a display substrate having a display area and a non-display area. The display area is provided with a pixel driving circuit, and the non-display area is provided with a gate driving circuit. The gate driving circuit includes a plurality of cascaded shift registers.

[0252] Figure 3 is a schematic diagram of the structure of a shift register provided by an embodiment of the present disclosure. As shown in Figure 3, at least one stage of the shift register includes: a shift subcircuit and an output subcircuit, and a first node N1 is provided in the shift subcircuit. Among them, for the i-th stage shift register, the shift sub-circuit is respectively connected to the signal input terminal IN(i), the first clock signal terminal CK, the second clock signal terminal CB, the first power supply terminal VH1, the second power supply terminal VL1 and the cascade signal output terminal OUTC(i), and is configured to provide the signal of the first power supply terminal VH1 or the second power supply terminal VL1 to the cascade signal output terminal OUTC(i) under the control of the signals of the signal input terminal IN(i), the first clock signal terminal CK and the second clock signal terminal CB; the output sub-circuit is respectively connected to the latch signal terminal MS, the control signal terminal G, the third power supply terminal VH2, the fourth power supply terminal VL2, the cascade signal output terminal OUTC(i) and the drive signal output terminal OUT(i), and is configured to provide the signals of the third power supply terminal VH2 and the fourth power supply terminal VL2 to the drive signal output terminal OUT(i) under the control of the signals of the latch signal terminal MS, the control signal terminal G and the cascade signal output terminal OUTC(i). FIG3 illustrates the shift register at the i-th stage as an example, wherein IN(i) represents the signal input terminal of the shift register at the i-th stage, OUTC(i) represents the cascade signal output terminal of the shift register at the i-th stage, OUT(i) represents the drive signal output terminal of the shift register at the i-th stage, the second node N2(i) represents the second node of the shift register at the i-th stage, the third node N3(i) represents the third node of the shift register at the i-th stage, and the fourth node N4(i) represents the fourth node of the shift register at the i-th stage. FIG3 illustrates the shift sub-circuit provided in FIG58 as an example. The control signal terminal G in FIG3 represents the first control signal terminal V1 in FIG58.

[0253] As shown in Figure 3, for the i-th stage shift register, the control signal terminal G is connected to the first node N1(i-1) of the previous stage shift register of the current stage shift register, the drive signal output terminal OUT is connected to the pixel driving circuit, and the cascade signal output terminal OUTC is connected to the signal input terminal IN of at least one stage shift register other than the current stage shift register.

[0254] In an exemplary embodiment, since the control signal terminal G is connected to the first node of the previous-stage shift register of the current-stage shift register, the control signal terminal in the first-stage shift register in the shift register provides a signal through a signal line, and the control signal terminals of the remaining shift registers except the first-stage shift register are all connected to the first node of the previous-stage shift register.

[0255] The present disclosure sets a shift subcircuit to output a cascade signal provided by other shift registers to a cascade signal output terminal, and sets an output subcircuit to output a drive signal provided by a pixel drive circuit to a drive signal output terminal, thereby achieving the output of the cascade signal and the drive signal using different subcircuits. This can control whether to output the drive signal to the pixel drive circuit while ensuring the normal output of the cascade signal.

[0256] The above-mentioned shift register provided by the present disclosure can, through the cooperation of the shift sub-circuit and the output sub-circuit, latch the signal of the corresponding latch signal end in the output sub-circuit according to the refresh rate requirement of the display area, thereby realizing the control of the signal output by the drive signal output end, and realizing different refresh rates in different areas of the display panel, that is, high and low refresh rates can coexist in the same frame picture, and the embodiment of the present disclosure is not limited to realizing different refresh rates in fixed areas of the display panel, and can realize dynamic refresh of any area, thereby reducing the power consumption of the display panel; at the same time, the output sub-circuit can use the phase difference of the cascade signals output by the front and rear stages of the shift sub-circuit to store the control signal of the latch signal end in each stage of the shift register, thereby realizing continuous and correct output of the shift register of this stage.

[0257] In an exemplary embodiment, the shift sub-circuit is further provided with a second node N2, a third node N3, a fourth node N4 and a fifth node N5. The output sub-circuit is also connected to the second node N2, the third node N3 and the fourth node N4.

[0258] Figure 4 is a schematic diagram of the structure of another shift register. In an exemplary embodiment, the capacitor group further includes: a fourth capacitor C4; the first plate of the fourth capacitor C4 is connected to the second power supply terminal VL1, and the second plate of the fourth capacitor C4 is connected to the cascade output signal terminal OUTC(i). The setting of the fourth capacitor C4 can ensure the stability of the signal of the cascade output signal terminal OUTC(i), and is used to stabilize the input of the next-stage shift register, prevent the input signal of the next-stage shift register from being unstable due to jitter during the transmission of the cascade signal output by the cascade output signal terminal, and improve the stability of the shift register. Figure 4 is illustrated by taking the shift sub-circuit provided by Figure 58 as an example. The control signal terminal G in Figure 4 is the first control signal terminal V1 in Figure 58, and the fifth node N5 is the second control signal terminal V2 in Figure 58.

[0259] In an exemplary embodiment, the capacitance value of the fourth capacitor C4 ranges from 10 farads to 80 farads.

[0260] Figure 5A is an equivalent circuit diagram of a shift register, and Figure 5B is an equivalent circuit diagram of another shift register. As shown in Figures 5A and 5B, in an exemplary embodiment, the shift sub-circuit includes: a first transistor group and a capacitor group, or includes: a first transistor group, a second transistor group, and a capacitor group. The first transistor group includes at least: a first transistor T1 to a tenth transistor T10; the second transistor group includes at least: an eleventh transistor T11 to a twelfth transistor T12, or a thirteenth transistor T11 to a thirteenth transistor T13, or a sixteenth transistor T11 to a sixteenth transistor T16; the capacitor group includes: a first capacitor C1 to a third capacitor C3, and any of the first capacitors C1 to C3 includes: a first plate and a second plate. When the shift sub-circuit includes: a thirteenth transistor T13, the shift sub-circuit is also connected to the fifth power supply terminal NCX. Figures 5A and 5B illustrate an example in which a shift subcircuit includes a first transistor group, a second transistor group, and a capacitor group, with the second transistor group including eleventh to sixteenth transistors T11 through T16. The shift subcircuit in the shift register shown in Figure 5A is illustrated using the shift subcircuit shown in Figure 58 , excluding the fourth capacitor C4, as an example, and the output subcircuit is illustrated using the output subcircuit shown in Figure 60 as an example. The shift subcircuit in the shift register shown in Figure 5B is illustrated using the shift subcircuit shown in Figure 58 , and the output subcircuit is illustrated using the output subcircuit shown in Figure 60 as an example. The fifth node N5 in Figures 5A and 5B represents the first control signal terminal V1 in Figure 58 , and the control signal terminal G in Figures 5A and 5B represents the second control signal terminal V2.

[0261] In an exemplary embodiment, a gate electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, a first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and a second electrode of the first transistor T1 is electrically connected to the third node N3; a gate electrode of the second transistor T2 is electrically connected to the third node N3, a first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK, a second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3, a gate electrode of the fifth transistor T5, and a first electrode of the eleventh transistor T11; a gate electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, a first electrode of the third transistor T3 is electrically connected to the second power supply terminal VL1; a gate electrode of the fourth transistor T4 is electrically connected to the second node N3, and a first electrode of the fourth transistor T5 is electrically connected to the second power supply terminal VL1. 2, a first electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB, and a second electrode of the fourth transistor T4 is electrically connected to the fifth node N5; a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VH1, and a second electrode of the fifth transistor T5 is electrically connected to the fifth node N5; a gate electrode of the sixth transistor T6 is electrically connected to the second electrode of the eleventh transistor T11 and the first plate C11 of the first capacitor, a first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CB, and a second electrode of the sixth transistor T6 is electrically connected to the first node N1; a gate electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, a first electrode of the seventh transistor T7 is electrically connected to the first node N1, and a second electrode of the seventh transistor T7 is electrically connected to the The fourth node N4 is electrically connected; the gate electrode of the eighth transistor T8 is electrically connected to the third node N3, the first electrode of the eighth transistor T8 is electrically connected to the first power supply terminal VH1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the gate electrode of the ninth transistor T9 is electrically connected to the fourth node N4, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VH1, and the second electrode of the ninth transistor T9 is electrically connected to the cascade signal output terminal OUTC(i); the gate electrode of the tenth transistor T10 is electrically connected to the ninth node N9, the first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal VL1, and the second electrode of the tenth transistor T10 is electrically connected to the cascade signal output terminal OUTC(i); the gate electrode of the eleventh transistor T11 is electrically connected to the fourth node N4, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VH1, and the second electrode of the ninth transistor T9 is electrically connected to the cascade signal output terminal OUTC(i); a gate electrode of a twelfth transistor T12 electrically connected to the second power supply terminal VL1, a first electrode of the twelfth transistor T12 electrically connected to the third node N3, and a second electrode of the twelfth transistor T12 electrically connected to the ninth node N9; a gate electrode of a thirteenth transistor T13 electrically connected to the fifth power supply terminal NCX, a first electrode of the thirteenth transistor T13 electrically connected to the first power supply terminal VH1, and a second electrode of the thirteenth transistor T13 electrically connected to the third node N3; a gate electrode of a fourteenth transistor T14 electrically connected to the first clock signal terminal CK, a first electrode of the fourteenth transistor T14 electrically connected to the signal input terminal IN, and a second electrode of the fourteenth transistor T14 electrically connected to the first electrode of the fifteenth transistor T15;A gate electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VL1, and a second electrode of the fifteenth transistor T15 is electrically connected to the second node N2. A gate electrode of the sixteenth transistor T16 is electrically connected to the second node N2, and a first electrode of the sixteenth transistor T16 is electrically connected to the ninth node N9. A second plate of the first capacitor C1 is electrically connected to the first power supply terminal VH1, a first plate C21 of the second capacitor C2 is electrically connected to the fourth node N4, a second plate C22 of the second capacitor C2 is electrically connected to the first power supply terminal VH1, a first plate C31 of the third capacitor C3 is electrically connected to the second node N2, and a second plate C32 of the third capacitor C3 is electrically connected to the fifth node N5.

[0262] In an exemplary embodiment, the shift subcircuit may have a circuit structure of 10T3C, 10T4C, 12T3C, 12T4C, 13T3C, 13T4C, 16T3C, or 16T4C, which is not limited in the present disclosure.

[0263] In an exemplary embodiment, when the shift sub-circuit has a circuit structure of 10T3C, the shift sub-circuit includes: first to tenth transistors T1 to T10 and first to third capacitors C1 to C3.

[0264] In an exemplary embodiment, when the shift sub-circuit has a circuit structure of 10T4C, the shift sub-circuit includes: first to tenth transistors T1 to T10 and first to fourth capacitors C1 to C4.

[0265] In an exemplary embodiment, when the shift sub-circuit has a 12T3C circuit structure, the shift sub-circuit includes: first to twelfth transistors T1 to T12 and first to third capacitors C1 to C3.

[0266] In an exemplary embodiment, when the shift sub-circuit has a 12T4C circuit structure, the shift sub-circuit includes: first to twelfth transistors T1 to T12 , first to third capacitors C1 to C3 , and a fourth capacitor C4 .

[0267] In an exemplary embodiment, when the shift sub-circuit has a circuit structure of 13T3C, the shift sub-circuit includes: first to thirteenth transistors T1 to T13 and first to third capacitors C1 to C3.

[0268] In an exemplary embodiment, when the shift sub-circuit has a circuit structure of 13T4C, the shift sub-circuit includes: first to thirteenth transistors T1 to T13 and first to fourth capacitors C1 to C4.

[0269] In an exemplary embodiment, when the shift sub-circuit has a 16T3C circuit structure, the shift sub-circuit includes: first to sixteenth transistors T1 to T16 and first to third capacitors C1 to C3.

[0270] In an exemplary embodiment, as shown in FIG5A , the output sub-circuit includes: seventeenth to twenty-first transistors T17 to T21, a twenty-fourth transistor T24, a twenty-fifth transistor T25, a twenty-sixth transistor T26, a fifth capacitor C5, and a sixth capacitor C6, wherein either the fifth capacitor C5 or the sixth capacitor C6 includes: a first plate and a second plate. The gate electrode and first electrode of the seventeenth transistor T17 are connected to the second node N2, the second electrode of the seventeenth transistor T17 is connected to the sixth node N6, the gate electrode of the eighteenth transistor T18 is connected to the seventh node N7, the first electrode of the eighteenth transistor T18 is connected to the third node N3, the second electrode of the eighteenth transistor T18 is connected to the sixth node N6, the gate electrode of the nineteenth transistor T18 is connected to the control signal terminal G, the first electrode of the nineteenth transistor T19 is connected to the latch signal terminal MS, the second electrode of the nineteenth transistor T19 is connected to the first electrode of the twentieth transistor T20, the gate electrode of the twentieth transistor T20 is connected to the cascade signal output terminal OUTC, the second electrode of the twentieth transistor T20 is connected to the seventh node N7, the gate electrode of the twenty-first transistor T21 is connected to the seventh node N7, the first electrode of the twenty-first transistor T21 is connected to the fourth node N4, the second electrode of the twenty-first transistor T21 is connected to the eighth node N8, and the gate electrode of the twenty-fourth transistor T24 is connected to the sixth node N8. The gate electrode of the twenty-fourth transistor T24 is connected to the sixth node N6, the first electrode of the twenty-fourth transistor T24 is connected to the third power supply terminal VH3, the second electrode of the twenty-fourth transistor T24 is connected to the eighth node N8, the gate electrode of the twenty-fifth transistor T25 is connected to the eighth node N8, the first electrode of the twenty-fifth transistor T25 is connected to the third power supply terminal VH2, the second electrode of the twenty-fifth transistor T25 is connected to the drive signal output terminal OUT, the gate electrode of the twenty-sixth transistor T26 is connected to the sixth node N6, the first electrode of the twenty-sixth transistor T26 is connected to the fourth power supply terminal VL2, the second electrode of the twenty-sixth transistor T26 is connected to the drive signal output terminal OUT, the first plate C51 of the fifth capacitor C5 is connected to the seventh node N7, the second plate C52 of the fifth capacitor C5 is connected to the eighth node N8, the first plate C61 of the sixth capacitor C6 is connected to the eighth node N8, and the second plate C62 of the sixth capacitor C6 is connected to the third power supply terminal VH3.

[0271] In an exemplary embodiment, as shown in FIG5B , the output sub-circuit includes: seventeenth to twenty-sixth transistors T17 to T26, a fifth capacitor C5, and a sixth capacitor C6, wherein each of the fifth capacitor C5 and the sixth capacitor C6 includes a first plate and a second plate. The gate electrode and the first electrode of the seventeenth transistor T17 are connected to the second node N2, the second electrode of the seventeenth transistor T17 is connected to the sixth node N6, the gate electrode of the eighteenth transistor T18 is connected to the seventh node N7, the first electrode of the eighteenth transistor T18 is connected to the third node N3, the second electrode of the eighteenth transistor T18 is connected to the sixth node N6, the gate electrode of the nineteenth transistor T18 is connected to the control signal terminal G, the first electrode of the nineteenth transistor T19 is connected to the latch signal terminal MS, the second electrode of the nineteenth transistor T19 is connected to the first electrode of the twentieth transistor T20, and the twentieth transistor T20 is connected to the latch signal terminal MS. The gate electrode of the 22nd transistor T22 is connected to the cascade signal output terminal OUTC, the second electrode of the 20th transistor T20 is connected to the seventh node N7, the gate electrode of the 21st transistor T21 is connected to the seventh node N7, the first electrode of the 21st transistor T21 is connected to the fourth node N4, the second electrode of the 21st transistor T21 is connected to the eighth node N8, the gate electrode of the 22nd transistor T22 is connected to the fifth power supply terminal NCX, the first electrode of the 22nd transistor T22 is connected to the fourth power supply terminal VL2, the second electrode of the 22nd transistor T22 is connected to the seventh node N7, and the gate electrode of the 23rd transistor T23 is connected to the The first electrode of the twenty-fourth transistor T24 is connected to the third power supply terminal VH2, the second electrode of the twenty-fourth transistor T24 is connected to the eighth node N8, the gate electrode of the twenty-fifth transistor T25 is connected to the eighth node N8, and the first electrode of the twenty-fifth transistor T25 is connected to the third power supply terminal VH2. In addition, a second electrode of the twenty-fifth transistor T25 is connected to the driving signal output terminal OUT, a gate electrode of the twenty-sixth transistor T26 is connected to the sixth node N6, a first electrode of the twenty-sixth transistor T26 is connected to the second power supply terminal VL1, a second electrode of the twenty-sixth transistor T26 is connected to the driving signal output terminal OUT, a first plate C51 of the fifth capacitor C5 is connected to the seventh node N7, a second plate C52 of the fifth capacitor C5 is connected to the eighth node N8, a first plate C61 of the sixth capacitor C6 is connected to the eighth node N8, and a second plate C62 of the sixth capacitor C6 is connected to the third power supply terminal VH3.

[0272] In an exemplary embodiment, any capacitor among the first capacitor C1 to the sixth capacitor C6 can be a capacitor device made by a process. For example, a capacitor device can be realized by making a special capacitor electrode, and multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. Alternatively, any capacitor among the first capacitor C1 to the sixth capacitor C6 can be a parasitic capacitance between multiple devices, which can be realized by the transistor itself and other devices and circuits. The connection method of any capacitor among the first capacitor C1 to the sixth capacitor C6 includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored. Here, the exemplary embodiment of the present disclosure is not limited to this.

[0273] In an exemplary embodiment, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0274] In an exemplary embodiment, the first to twenty-sixth transistors T1 to T26 are all P-type transistors.

[0275] In an exemplary embodiment, the signal at the latch signal terminal MS may be a low level signal or a high level signal. When the signal at the latch signal terminal MS is a low level signal, it may be -20V to -5V; when the signal at the latch signal terminal MS is a high level signal, it may be 5V to 20V.

[0276] In an exemplary embodiment, the signals of the first power terminal VH1 and the third power terminal VH2 may be high level signals, for example, 5V to 10V; the signals of the second power terminal VL1 and the fourth power terminal VL2 may be low level signals, for example, -10V to -5V.

[0277] In an exemplary embodiment, the signal at either the first clock signal terminal CK or the second clock signal terminal CB is a square wave signal that repeats a high voltage and a low voltage. For example, the signal at the first clock signal terminal CK and the second clock signal terminal CB may have the same period and may be configured as phase-shifted signals. Here, the signal at the second clock signal terminal CB may be phase-shifted by half a period compared to the signal at the first clock signal terminal CK. The high voltage period in each period of the signal at either the first clock signal terminal CK or the second clock signal terminal CB may be set to be longer than the low voltage period.

[0278] In an exemplary embodiment, the fifth power supply terminal NCX provides a low-level signal during the power-on initialization phase to prevent the ninth transistor T9 and the tenth transistor T10 of the final-stage control shift register from being simultaneously turned on due to output signal delay. Alternatively, the fifth power supply terminal NCX provides a low-level signal during the abnormal shutdown phase to prevent the ninth transistor T9 and the tenth transistor T10 from being simultaneously turned on. The fifth power supply terminal NCX continuously provides a high-level signal during the normal display phase, meaning that the thirteenth transistor T13 is turned off during the normal display phase.

[0279] In the exemplary embodiment, due to the presence of the latch signal terminal MS, the outputs of the shift sub-circuit and the output sub-circuit are independent. The working processes of the shift sub-circuit and the output sub-circuit are now described separately.

[0280] In the exemplary embodiment, the first power supply terminal VH1 continuously provides a high-level signal, and the second power supply terminal VL1 continuously provides a low-level signal. Since the second power supply terminal VL1 continuously provides a low-level signal, the eleventh transistor T11, the twelfth transistor T12, and the fifteenth transistor T15 in Figures 58 and 59 are continuously turned on, and the eighth transistor T8 in Figure 61 is continuously turned on.

[0281] Figure 66 is a timing diagram of the operation of the shift sub-circuit provided in Figures 58 and 59. Figure 66 takes the example of the first transistor T1 to the sixteenth transistor T16 being P-type transistors. As shown in Figure 66, the operation process of the shift sub-circuit provided in Figure 58 may include the following stages:

[0282] In the first phase A1, the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals, the signal at the first clock signal terminal CK is low level signal, the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned on, and the seventh transistor T7 is turned off.

[0283] The first transistor T1 is turned on, transmitting the high-level signal from the signal input terminal IN to the third node N3. The twelfth transistor T12 is turned on, transmitting the high-level signal from the third node N3 to the ninth node N9. The fourteenth and fifteenth transistors T14 and T15 are turned on, transmitting the high-level signal from the signal input terminal IN to the second node N2. The fourth and sixteenth transistors T4 and T16 are turned off. The third and eleventh transistors T3 and T11 are turned on, transmitting the low-level signal from the second power supply terminal VL2 to the sixth and tenth nodes N6 and N10, respectively. The fifth and sixth transistors T5 and T6 are turned on, writing the high-level signal from the first power supply terminal VH1 to the fifth node N5 and the high-level signal from the second clock signal terminal CB to the first node N1. Since the seventh transistor T7 is turned off, the signal from the first node N1 is not written to the fourth node N4 and remains at a low-level signal. The ninth transistor T9 is turned off, and the signal from the cascade signal output terminal OUTC remains at its previous low level. In this stage, the signals of the first node N1 , the second node N2 , the third node N3 , the fourth node N4 , the fifth node N5 and the ninth node N9 are high level signals, and the signal of the cascade signal output terminal OUTC is a low level signal.

[0284] In the second phase A2, the signal at the second clock signal terminal CB is a low level signal, the signals at the signal input terminal IN and the first clock signal terminal CK are high level signals, the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned off, and the seventh transistor T7 is turned on.

[0285] Under the action of the first capacitor C1, the signals at the sixth node N6 and the tenth node N10 remain low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on. The high-level signal at the first power supply terminal VH1 is written to the fifth node N5. The low-level signal at the second clock signal terminal CB is written to the first node N1. The signal at the first node N1 is written to the fourth node N4 via the turned-on seventh transistor T7. The ninth transistor T9 is turned on, and the high-level signal at the first power supply terminal VH1 is transmitted to the cascade signal output terminal OUTC via the turned-on ninth transistor T9. Under the action of the third capacitor C3, the second node N2 can continue to maintain the high-level signal from the previous stage. The third node N3 and the ninth node N9 also maintain the high-level signals from the previous stage. The second transistor T2, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, and the sixteenth transistor T16 are turned off. In this stage, the signals at the second node N2, the third node N3, the fifth node N5, and the ninth node N9 are high-level signals. The signals at the first node N1 and the fourth node N4 are low-level signals. The signal at the cascade signal output terminal OUTC is high-level.

[0286] In the third phase A3, the signal at the first clock signal terminal CK is a low level signal, the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals, the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned on, and the seventh transistor T7 is turned off.

[0287] The first transistor T1 is turned on, transmitting the high-level signal from the signal input terminal IN to the third node N3. The twelfth transistor T12 is turned on, transmitting the high-level signal from the third node N3 to the ninth node N9. The fourteenth and fifteenth transistors T14 and T15 are turned on, transmitting the high-level signal from the signal input terminal IN to the second node N2. The fourth and sixteenth transistors T4 and T16 are turned off. The third and eleventh transistors T3 and T11 are turned on, transmitting the low-level signal from the second power supply terminal VL2 to the sixth and tenth nodes N6 and N10, respectively. The fifth and sixth transistors T5 and T6 are turned on, writing the high-level signal from the first power supply terminal VH1 to the fifth node N5, and writing the high-level signal from the second clock signal terminal CB to the first node N1. Since the seventh transistor T7 is turned off, the fourth node N4 maintains the low-level signal from the previous stage under the action of the second capacitor C2. The ninth transistor T9 is turned on, and the signal from the cascade signal output terminal OUTC is a high-level signal. In this stage, the signals of the first node N1, the second node N2, the third node N3, the fifth node N5 and the ninth node N9 are high level signals, the signal of the fourth node N4 is low level signal, and the signal of the cascade signal output terminal OUTC is low level signal.

[0288] In the fourth phase A4, the signals at the signal input terminal IN and the second clock signal terminal CB are low level signals, the signal at the first clock signal terminal CK is high level signal, the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned off, and the seventh transistor T7 is turned on.

[0289] Under the action of the third capacitor C3, the signals at the second node N2, the third node N3, and the ninth node N9 remain high-level signals from the previous stage. The second transistor T2, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, and the sixteenth transistor T16 are turned off. Under the action of the first capacitor C1, the sixth node N6 and the tenth node N10 remain low-level signals from the previous stage. The fifth transistor T5 and the sixth transistor T6 are turned on. The high-level signal from the first power supply terminal VH1 is written to the fifth node N5, the low-level signal from the second clock signal terminal CB is written to the first node N1, and the signal from the first node N1 is written to the fourth node N4 via the turned-on seventh transistor T7. The ninth transistor T9 is turned on, and the high-level signal from the first power supply terminal VH1 is transmitted to the cascade signal output terminal OUTC via the turned-on ninth transistor T9. In this stage, the signals at the second node N2, the third node N3, the fifth node N5, and the ninth node N9 are high-level signals, the signals at the first node N1 and the fourth node N4 are low-level signals, and the signal at the cascade signal output terminal OUTC is high-level.

[0290] In the fifth phase A5, the signal at the second clock signal terminal CB is a high level signal, the signals at the signal input terminal IN and the first clock signal terminal CK are low level signals, the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned on, and the seventh transistor T7 is turned off.

[0291] The first transistor T1 is turned on and transmits the low-level signal from the signal input terminal IN to the third node N3. The twelfth transistor T12 is turned on and transmits the low-level signal from the third node N3 to the ninth node N9, causing the signal at the ninth node N9 to become a low-level signal. The fourteenth and fifteenth transistors T14 and T15 are turned on and transmit the low-level signal from the signal input terminal IN to the second node N2, causing the signal at the second node N2 to become a low-level signal. The second transistor T2, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, and the sixteenth transistor T16 are turned on. The second transistor T2 is turned on and transmits the low-level signal from the first clock signal terminal CK to the tenth node N10. The sixth node N6 continues to maintain the low-level signal from the previous stage. The fifth and sixth transistors T5 and T6 are turned on. The high-level signal from the second clock signal terminal CB is written to the first node N1 via the sixth transistor T6, and then to the fourth node N4 via the seventh transistor T7. The high-level signal from the second clock signal terminal CB is written to the fifth node N5 via the fourth transistor T4. The high-level signal of the first power supply terminal VH1 is transmitted to the fourth node N4 through the conductive eighth transistor T8, and the ninth transistor T9 is turned off. The low-level signal of the second power supply terminal VL1 is transmitted to the cascade signal output terminal OUTC through the conductive tenth transistor T10, and the signal of the cascade signal output terminal OUTC becomes a low-level signal. In this stage, the second node N2, the third node N3, and the ninth node N9 are low-level signals, the signals of the first node N1, the fourth node N4, and the fifth node N5 are high-level signals, and the signal of the cascade signal output terminal OUTC is a low-level signal.

[0292] As shown in FIG66 , the operation process of the shift subcircuit provided in FIG59 may include the following stages:

[0293] In the first phase A1, the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals, the signal at the first clock signal terminal CK is low level signal, the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned on, and the seventh transistor T7 is turned off.

[0294] The first transistor T1 is turned on, transmitting the high-level signal from the signal input terminal IN to the third node N3. The twelfth transistor T12 is turned on, transmitting the high-level signal from the third node N3 to the second node N2. The fourteenth transistor T14 and the fifteenth transistor T15 are turned on, transmitting the high-level signal from the signal input terminal IN to the second node N2. The fourth transistor T4 is turned off. The third transistor T3 and the eleventh transistor T11 are turned on, transmitting the low-level signal from the second power supply terminal VL2 to the sixth node N6 and the tenth node N10. The fifth transistor T5 and the sixth transistor T6 are turned on, writing the high-level signal from the first power supply terminal VH1 to the fifth node N5, and writing the high-level signal from the second clock signal terminal CB to the first node N1. Since the seventh transistor T7 is turned off, the signal from the first node N1 is not written to the fourth node N4 and remains at a low-level signal. The ninth transistor T9 is turned off, and the signal from the cascade signal output terminal OUTC remains at the previous low level. In this stage, the signals at the first node N1 , the second node N2 , the third node N3 , the fourth node N4 , and the fifth node N5 are high-level signals, and the signal at the cascade signal output terminal OUTC is a low-level signal.

[0295] In the second phase A2, the signal at the second clock signal terminal CB is a low level signal, the signals at the signal input terminal IN and the first clock signal terminal CK are high level signals, the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned off, and the seventh transistor T7 is turned on.

[0296] Under the action of the first capacitor C1, the signals at the sixth node N6 and the tenth node N10 remain low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on. The high-level signal at the first power supply terminal VH1 is written to the fifth node N5. The low-level signal at the second clock signal terminal CB is written to the first node N1. The signal at the first node N1 is written to the fourth node N4 via the turned-on seventh transistor T7. The ninth transistor T9 is turned on, and the high-level signal at the first power supply terminal VH1 is transmitted to the cascade signal output terminal OUTC via the turned-on ninth transistor T9. Under the action of the third capacitor C3, the second node N2 can continue to maintain the high-level signal from the previous stage. The third node N3 and the second node N2 maintain the high-level signals from the previous stage. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off. In this stage, the signals at the second node N2, the third node N3, and the fifth node N5 are high-level signals, the signals at the first node N1 and the fourth node N4 are low-level signals, and the signal at the cascade signal output terminal OUTC is high-level.

[0297] In the third phase A3, the signal at the first clock signal terminal CK is a low level signal, the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals, the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned on, and the seventh transistor T7 is turned off.

[0298] The first transistor T1 is turned on, transmitting the high-level signal from the signal input terminal IN to the third node N3. The twelfth transistor T12 is turned on, transmitting the high-level signal from the third node N3 to the second node N2. The fourteenth transistor T14 and the fifteenth transistor T15 are turned on, transmitting the high-level signal from the signal input terminal IN to the second node N2. The fourth transistor T4 is turned off. The third transistor T3 and the eleventh transistor T11 are turned on, transmitting the low-level signal from the second power supply terminal VL2 to the sixth node N6 and the tenth node N10. The fifth transistor T5 and the sixth transistor T6 are turned on, writing the high-level signal from the first power supply terminal VH1 to the fifth node N5, and writing the high-level signal from the second clock signal terminal CB to the first node N1. Since the seventh transistor T7 is turned off, the fourth node N4 maintains the low-level signal from the previous stage under the action of the second capacitor C2. The ninth transistor T9 is turned on, and the signal from the cascade signal output terminal OUTC is a high-level signal. In this stage, the signals of the first node N1, the second node N2, the third node N3 and the fifth node N5 are high level signals, the signal of the fourth node N4 is low level signal, and the signal of the cascade signal output terminal OUTC is low level signal.

[0299] In the fourth phase A4, the signals at the signal input terminal IN and the second clock signal terminal CB are low level signals, the signal at the first clock signal terminal CK is high level signal, the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned off, and the seventh transistor T7 is turned on.

[0300] Under the action of the third capacitor C3, the signals at the second node N2, the third node N3, and the second node N2 remain high-level signals from the previous stage. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off. Under the action of the first capacitor C1, the sixth node N6 and the tenth node N10 remain low-level signals from the previous stage. The fifth transistor T5 and the sixth transistor T6 are turned on. The high-level signal from the first power supply terminal VH1 is written to the fifth node N5, the low-level signal from the second clock signal terminal CB is written to the first node N1, and the signal from the first node N1 is written to the fourth node N4 via the turned-on seventh transistor T7. The ninth transistor T9 is turned on, and the high-level signal from the first power supply terminal VH1 is transmitted to the cascade signal output terminal OUTC via the turned-on ninth transistor T9. In this stage, the signals at the second node N2, the third node N3, and the fifth node N5 are high-level signals, the signals at the first node N1 and the fourth node N4 are low-level signals, and the signal at the cascade signal output terminal OUTC is high-level.

[0301] In the fifth phase A5, the signal at the second clock signal terminal CB is a high level signal, the signals at the signal input terminal IN and the first clock signal terminal CK are low level signals, the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned on, and the seventh transistor T7 is turned off.

[0302] The first transistor T1 is turned on and transmits the low-level signal from the signal input terminal IN to the third node N3. The twelfth transistor T12 is turned on and transmits the low-level signal from the third node N3 to the second node N2, causing the signal at the second node N2 to become a low-level signal. The fourteenth and fifteenth transistors T14 and T15 are turned on and transmit the low-level signal from the signal input terminal IN to the second node N2, causing the signal at the second node N2 to become a low-level signal. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned on. The second transistor T2 is turned on and transmits the low-level signal from the first clock signal terminal CK to the tenth node N10. The sixth node N6 continues to maintain the low-level signal from the previous stage. The fifth and sixth transistors T5 and T6 are turned on. The high-level signal from the second clock signal terminal CB is written to the first node N1 via the turned-on sixth transistor T6 and then to the fourth node N4 via the turned-on seventh transistor T7. The high-level signal from the second clock signal terminal CB is written to the fifth node N5 via the turned-on fourth transistor. The high-level signal of the first power supply terminal VH1 is transmitted to the fourth node N4 through the conductive eighth transistor T8, and the ninth transistor T9 is turned off. The low-level signal of the second power supply terminal VL1 is transmitted to the cascade signal output terminal OUTC through the conductive tenth transistor T10, and the signal of the cascade signal output terminal OUTC becomes a low-level signal. In this stage, the second node N2 and the third node N3 are low-level signals, the signals of the first node N1, the fourth node N4, and the fifth node N5 are high-level signals, and the signal of the cascade signal output terminal OUTC is a low-level signal.

[0303] As shown in FIG66 , when the output signal of the cascade signal output terminal OUTC is a high-level signal, the fourth node N4 is a low-level signal, and the second node N2 and the third node N3 are high-level signals. When the output signal of the cascade signal output terminal OUTC is a low-level signal, the fourth node N4 is a high-level signal, and the second node N2 and the third node N3 are low-level signals.

[0304] FIG67 is a timing diagram of the operation of the shift sub-circuit provided in FIG61. FIG66 takes the first transistor T1 to the eighth transistor T8 as an example of P-type transistors. As shown in FIG66, the operation process of the shift sub-circuit provided in FIG61 may include the following stages:

[0305] In the first phase C1, the signals at the first clock signal terminal CK and the signal input terminal IN are low level signals, the signal at the second clock signal terminal CB is high level signal, the first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 is turned off.

[0306] The conductive first transistor T1 writes the low-level signal from the signal input terminal IN to the third node N3. The conductive eighth transistor T8 writes the low-level signal from the third node N3 to the ninth node N9. The conductive fifth transistor T5 writes the high-level signal from the second clock signal terminal CB to the cascade signal output terminal OUTC. The conductive third transistor T3 writes the low-level signal from the second power supply terminal VL2 to the fourth node N4. The conductive fourth transistor T4 and sixth transistor T6 write the high-level signal from the first power supply terminal VH1 to the cascade signal output terminal OUTC. In this stage, the third node N3, the fourth node N4, and the ninth node N9 are low-level signals, and the signal at the cascade signal output terminal OUTC is high-level.

[0307] In the second phase C2, the signals at the first clock signal terminal CK and the signal input terminal IN are high level signals, the signal at the second clock signal terminal CB is low level signal, the first transistor T1 and the third transistor T3 are turned off, and the seventh transistor T7 is turned on.

[0308] The third node N3 and the ninth node N9 maintain low-level signals, the fifth transistor T5 is turned on, the low-level signal at the second clock signal terminal CB is written to the cascade signal output terminal OUTC, the second transistor T2 is turned on, the high-level signal at the first clock signal terminal CK is written to the fourth node N4, and the fourth transistor T4 is turned off. In this stage, the signals at the third node N3 and the ninth node N9 are low-level signals, the signal at the fourth node N4 is high-level signal, and the signal at the cascade signal output terminal OUTC is low-level signal.

[0309] In the third phase C3, the signals at the first clock signal terminal CK and the second clock signal terminal CB are both high-level signals, the signal at the signal input terminal IN is a high-level signal, and the first transistor T1, the third transistor T3, and the seventh transistor T7 are turned on.

[0310] The third node N3 and the ninth node N9 maintain low-level signals, the fifth transistor T5 is turned on, the low-level signal at the second clock signal terminal CB is written to the cascade signal output terminal OUTC, the second transistor T2 is turned on, the high-level signal at the first clock signal terminal CK is written to the fourth node N4, and the fourth transistor T4 is turned off. In this stage, the signals at the third node N3 and the ninth node N9 are low-level signals, the signal at the fourth node N4 is high-level signal, and the signal at the cascade signal output terminal OUTC is low-level signal.

[0311] In the first sub-phase C41 of the fourth phase C4, the signal at the first clock signal terminal CK is a low level signal, the signals at the second clock signal terminal CB and the signal input terminal IN are high level signals, the first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 is turned off.

[0312] The conductive first transistor T1 writes the high-level signal from the signal input terminal IN to the third node N3. The conductive eighth transistor T8 writes the high-level signal from the third node N3 to the ninth node N9. The fifth transistor T5 is turned off. The conductive third transistor T3 writes the low-level signal from the second power supply terminal VL1 to the fourth node N4. The fourth transistor T4 and the sixth transistor T6 are both conductive, and the conductive fourth transistor T4 writes the high-level signal from the first power supply terminal VH1 to the cascade signal output terminal OUTC. In this stage, the third node N3 and the ninth node N9 are high-level signals, the fourth node N4 is low-level signal, and the signal at the cascade signal output terminal OUTC is high-level signal.

[0313] In the second sub-phase C42 of the stable phase C4, the signals at the first clock signal terminal CK and the signal input terminal IN are high level signals, the signal at the second clock signal terminal CB is low level signal, the first transistor T1 and the third transistor T3 are turned off, and the seventh transistor T7 is turned on.

[0314] The third node N3 and the ninth node N9 maintain high-level signals, the second transistor T2 is turned off, and the high-level signal of the first clock signal terminal CK cannot be written to the fourth node N4. In addition, under the holding effect of the first capacitor C1, the fourth node N4 maintains the low-level signal of the previous stage. The fourth transistor T4 and the sixth transistor T6 are both turned on, and the high-level signal of the first power supply terminal VH1 is written to the cascade signal output terminal OUTC. In this stage, the third node N3 and the ninth node N9 are high-level signals, the fourth node N4 is low-level signal, and the signal of the cascade signal output terminal OUTC is high-level signal.

[0315] In the third sub-phase C43 , the signals of the first clock signal terminal CK, the second clock signal CB and the signal input terminal IN are all high-level signals, and the first transistor T1 , the third transistor T3 and the seventh transistor T7 are turned off.

[0316] The third node N3 and the ninth node N9 still maintain high-level signals, the second transistor T2 is turned off, and the high-level signal of the first clock signal terminal CK cannot be written to the fourth node N4. In addition, under the holding effect of the first capacitor C1, the fourth node N4 maintains the low-level signal of the previous stage. The fourth transistor T4 and the sixth transistor T6 are both turned on, and the high-level signal of the first power supply terminal VH1 is written to the cascade signal output terminal OUTC. In this stage, the third node N3 and the ninth node N9 are high-level signals, the fourth node N4 is a low-level signal, and the signal of the cascade signal output terminal OUTC is a high-level signal.

[0317] As shown in FIG67 , when the output signal of the cascade signal output terminal OUTC is a high level signal, the fourth node N4 is a low level signal. When the output signal of the cascade signal output terminal OUTC is a low level signal, the third node N3 is a low level signal.

[0318] In an exemplary embodiment, as shown in FIG63 , when the signal at the cascade signal output terminal OUTC in the shift register is a low-level signal, the signals at the second node N2, the third node N3, and the ninth node N9 are also low-level signals, the tenth transistor T10 is turned on, and the signal at the second power supply terminal VL1 is written to the cascade signal output terminal OUTC. Because the signal at the second node N2 is a low-level signal, the sixteenth transistor T16 and the seventeenth transistor T17 are turned on, the signal at the sixth node N6 is a low-level signal, the twenty-fourth transistor T24 and the twenty-sixth transistor T26 are turned on, the signal at the fourth power supply terminal VL2 is written to the drive signal output terminal OUT, and the high-level signal at the third power supply terminal VH2 is written to the eighth node N8. The twenty-fifth transistor T25 is turned off, and the high-level signal at the third power supply terminal VH2 cannot be written to the drive signal output terminal OUT. In other words, the signal at the cascade signal output terminal OUTC in the shift register is a low-level signal, and the drive signal output terminal OUT also outputs a low-level signal.

[0319] In an exemplary embodiment, as shown in FIG64 , when the signal at the cascade signal output terminal OUTC in the shift register is a low-level signal, the signals at the second node N2 and the third node N3 are also low-level signals, the tenth transistor T10 is turned on, and the signal at the second power supply terminal VL1 is written to the cascade signal output terminal OUTC. Since the signal at the second node N2 is a low-level signal, the seventeenth transistor T17 is turned on, the signal at the sixth node N6 is a low-level signal, the twenty-fourth transistor T24 and the twenty-sixth transistor T26 are turned on, the signal at the fourth power supply terminal VL2 is written to the drive signal output terminal OUT, and the high-level signal at the third power supply terminal VH2 is written to the eighth node N8. The twenty-fifth transistor T25 is turned off, and the high-level signal at the third power supply terminal VH2 cannot be written to the drive signal output terminal OUT. In other words, the signal at the cascade signal output terminal OUTC in the shift register is a low-level signal, and the drive signal output terminal OUT also outputs a low-level signal.

[0320] In an exemplary embodiment, in the shift register provided in Figures 63 and 64, when the signal at the cascade signal output terminal in the shift register is a high-level signal, the signal at the fourth node N4 is a low-level signal, and the ninth transistor T9 is turned on. Due to the presence of the twenty-first transistor T21, the signal at the fourth node N4 will not be directly written to the twenty-fifth transistor T25, and the gate electrode of the twenty-first transistor T21 is determined by the nineteenth transistor T19, the twentieth transistor T20 and the fifth capacitor C5.

[0321] In the exemplary embodiment, in the shift register shown in FIG65 , when the signal at the cascade signal output terminal of the shift register is a high-level signal, the signal at the fourth node N4 is a low-level signal, and the fourth transistor T4 is turned on. Due to the presence of the twenty-first transistor T21, the signal at the fourth node N4 is not directly written to the twenty-fifth transistor T25. The gate electrode of the twenty-first transistor T21 is determined by the nineteenth transistor T19, the twentieth transistor T20, and the fifth capacitor C5, which can be referred to as a latch sub-circuit. In the shift register shown in FIG65 , when the signal at the cascade signal output terminal of the shift register is a low-level signal, the signal at the third node N3 is a low-level signal, and the fifth transistor T5 is turned on. Due to the presence of the eighteenth transistor T18, the signal at the third node N3 is not directly written to the twenty-sixth transistor T26. The gate electrode of the eighteenth transistor T18 is determined by the nineteenth transistor T19, the twentieth transistor T20, and the fifth capacitor C5.

[0322] In an exemplary embodiment, the nineteenth transistor T19, the twentieth transistor T20, and the fifth capacitor C5 can be referred to as a latch sub-circuit. The gate electrode of the nineteenth transistor T19 is electrically connected to the second control signal terminal V2 (also the first node of the previous shift register), and the gate electrode of the twentieth transistor T20 is connected to the cascade signal output terminal OUTC. When the signal at the cascade signal output terminal OUTC and the signal at the first node of the previous shift register are both low-level signals, the nineteenth transistor T19 and the twentieth transistor T20 are turned on, and the signal at the latch signal terminal MS is written to the seventh node N7 and the fifth capacitor C5, thereby controlling whether the eighteenth transistor T18 and the twentieth transistor T21 are turned on. Whether the twenty-first transistor T21 is turned on determines whether the signal at the fourth node N4 is written to the eighth node N8, that is, whether the twenty-fifth transistor T25 is turned on. Whether the twenty-fifth transistor T25 is turned on determines whether the signal at the third power supply terminal VH3 is written to the drive signal output terminal. Whether the eighteenth transistor T18 is turned on determines whether the signal of the third node N3 is written into the sixth node N6, that is, whether the twenty-fifth transistor T25 is turned on. Whether the twenty-fifth transistor T25 is turned on determines whether the signal of the fourth power supply terminal VHL is written into the driving signal output terminal OUT.

[0323] In an exemplary embodiment, the twenty-second transistor T22 and the twenty-third transistor T23 can be referred to as an initial stabilization unit. During the power-on initialization phase, the fifth power supply terminal NCX is a low-level signal, the twenty-second transistor T22 is turned on, and since the display substrate is not displaying at this time, the signal at the fourth node N4 is a high-level signal. The signal at the fourth power supply terminal VL2 is written to the seventh node N7, the twenty-first transistor T21 is turned on, the high-level signal at the fourth node N4 is written to the eighth node N8, and the twenty-fifth transistor T25 is turned off, thereby preventing the drive signal output terminal from outputting a high-level signal to the pixel drive circuit. Furthermore, during the power-on initialization phase, the cascade signal output terminal OUTC outputs a low-level signal, the signal at the first control signal terminal V1 (also the fifth node N5) is a low-level signal, the twenty-third transistor T23 is turned on, the signal at the fourth power supply terminal VL2 is written to the seventh node N7, the signal at the latch signal terminal MS pre-stored in the latch sub-circuit is replaced by the signal at the fourth power supply terminal VL2, the twenty-first transistor T21 is turned on, the high-level signal at the fourth node N4 is written to the eighth node N8, and the twenty-fifth transistor T25 is turned off. The initial stabilization unit prevents the drive signal output terminal from outputting a high-level signal to the pixel drive circuit during the power-on initialization phase. The initial stabilization unit ensures that at least one shift register stage has no leakage during the power-on initialization phase, thereby improving the reliability of the shift register.

[0324] In an exemplary embodiment, the drive signal output terminal of the shift register is primarily used to control at least one transistor in a pixel drive circuit of a display substrate. When the display substrate is in a refresh frame, the drive signal output terminal outputs a high-level signal for a period of time, and a low-level signal for the remainder of the frame, thereby refreshing the data voltage. When the display substrate is not in a refresh frame, the drive signal output terminal continuously outputs a low-level signal.

[0325] Figure 6 is a timing diagram of the operation of a portion of the shift register. The following describes the operating principle of the shift registers provided by the present disclosure, using the shift registers shown in Figures 5A and 5B as an example, in conjunction with the signal timing diagram shown in Figure 6, to control the display panel to achieve different refresh rates in different areas. Figure 6 illustrates this using the first four stages of the shift register as an example.

[0326] The signal timing diagram shown in FIG6 is only an example of the first four-stage shift register. For example, when the area corresponding to the second row of sub-pixels and the third row of sub-pixels in the display substrate is a low refresh rate area, and the first row of sub-pixels and the fourth row of sub-pixels are a high refresh rate area, when the signal at the cascade signal output terminal OUTC(1) of the first stage shift register and the signal at the first node of the previous stage shift register are both low level signals (at time t1), the nineteenth transistor T19 and the twentieth transistor T20 are both turned on, that is, at time t1, the low level signal at the latch signal terminal MS is latched in the fifth capacitor C5, and the signal at the cascade signal output terminal OUTC(1) of the first stage shift register is turned on. 1) When outputting a high level (at time T1'), since the fifth capacitor C5 maintains the low level signal of the latch signal terminal MS at time t1, the twenty-first transistor T21 and the twenty-fifth transistor T25 are turned on. Then, at time T1', the drive signal output terminal OUT(1) of the first-stage shift register outputs a high level signal of the third power supply terminal VH3, thereby achieving a high refresh rate of the first row of sub-pixels in the display area; the maintenance time of the high level signal outputted by the drive signal output terminal OUT(1) of the first-stage shift register from the third power supply terminal VH3 can be set according to actual needs. For example, the duration of the high level signal outputted by the drive signal output terminal OUT(1) of the first-stage shift register from the third power supply terminal VH3 can overlap with the duration of the high level signal outputted by the drive signal output terminal OUT(4) of the fourth-stage shift register from the third power supply terminal VH3, thereby precharging the pixel drive circuit corresponding to the drive signal output terminal OUT(4) of the fourth-stage shift register. Similarly, the duration of the output level signal of the drive signal output terminal OUT(n) of the other-stage shift register is similar and will not be described in detail.

[0327] As shown in FIG6 , when the signal of the cascade signal output terminal OUTC(2) of the second-stage shift register and the signal of the first node of the first-stage shift register are both low-level signals (at time t2), the nineteenth transistor T19 and the twentieth transistor T20 are both turned on, that is, the high-level signal of the latch signal terminal MS is latched in the fifth capacitor C5 at time t2; when the cascade signal output terminal OUTC(2) of the second-stage shift register outputs a high-level signal (at time T2′), since the fourth capacitor C4 maintains the high-level signal of the latch signal terminal MS at time t2, the twenty-fifth transistor T25 is turned off and the twenty-sixth transistor T26 is turned on. Then, at time T2′, the driving signal output terminal OUT(2) of the second-stage shift register outputs a low-level signal of the fourth power supply terminal VL2, thereby realizing a low refresh rate for the second row of sub-pixels in the display area.

[0328] As shown in FIG6 , when the signal of the cascade signal output terminal OUTC (3) of the third-stage shift register and the signal of the first node of the second-stage shift register are both low-level signals (at time t3), the nineteenth transistor T19 and the twentieth transistor T20 are both turned on, that is, the high-level signal of the latch signal terminal MS is latched in the fifth capacitor C5 at time t3; when the cascade signal output terminal OUTC (3) of the third-stage shift register outputs a high-level signal (at time T3′), since the fourth capacitor C4 maintains the high-level signal of the latch signal terminal MS at time t3, the twenty-fifth transistor T25 is turned off and the twenty-sixth transistor T26 is turned on, and at time T3′, the drive signal output terminal OUT (3) of the third-stage shift register outputs a low-level signal of the fourth power supply terminal VL2, thereby realizing a low refresh rate of the third row of sub-pixels in the display area;

[0329] As shown in FIG6 , when the signal of the cascade signal output terminal OUTC(4) of the fourth-stage shift register and the signal of the first node of the third-stage shift register are both low-level signals (at time t4), the nineteenth transistor T19 and the twentieth transistor T20 are both turned on, that is, the low-level signal of the latch signal terminal MS is latched in the fifth capacitor C5 at time t4. When the cascade signal output terminal OUTC(4) of the fourth-stage shift register outputs a high-level signal (at time T4′), since the fourth capacitor C4 maintains the low-level signal of the latch signal terminal MS at time t4, the twenty-first transistor T21 and the twenty-fifth transistor T25 are turned on. At time T4′, the drive signal output terminal OUT(4) of the fourth-stage shift register outputs a high-level signal of the third power supply terminal VH2, thereby achieving a high refresh rate for the fourth row of sub-pixels in the display area.

[0330] Therefore, when a certain area of ​​the display substrate requires a low refresh rate, a high-level signal is input through the latch signal terminal MS, and the driving signal output terminal continuously outputs a low-level signal so that part of the transistors of the pixel driving circuit in the corresponding display substrate are cut off. The data voltage in the display substrate is not charged, and the state of the previous frame is maintained, thereby achieving a low refresh rate in this area.

[0331] In an exemplary embodiment, FIG7 is a schematic diagram of the structure of a display substrate, FIG8 is a schematic diagram of the structure of a display substrate, FIG9 is a schematic diagram of the structure of a display substrate, FIG10 is a schematic diagram of the structure of a display substrate, FIG11 is a schematic diagram of the structure of a display substrate, FIG12 is a schematic diagram of the partial structure of the display substrate provided in FIG7, FIG9, FIG10, and FIG11, and FIG13 is a schematic diagram of the partial structure of the display substrate provided in FIG8. FIG7 to FIG11 are described using two shift registers GOA(i) and GOA(i+1), where the shift registers in FIG7, FIG9, FIG10, and FIG11 are the shift registers of FIG5B, and the shift register in FIG8 is the shift register provided in FIG5A.

[0332] In an exemplary embodiment, as shown in FIG7 to FIG13 , the transistor includes an active pattern. A length of the active pattern of at least one of the twenty-fifth transistor T25 and the twenty-sixth transistor T26 along a first direction D1 is greater than a length of the active pattern of at least one of the ninth transistor T9 and the tenth transistor T10 along the first direction D1. A length of the active pattern of at least one of the twenty-fifth transistor T25 and the twenty-sixth transistor T26 along a second direction D2 is greater than a length of the active pattern of at least one of the ninth transistor T9 and the tenth transistor T10 along the second direction D2. The first direction D1 and the second direction D2 intersect.

[0333] In an exemplary embodiment, a channel width-to-length ratio of an active pattern of at least one of the twenty-fifth transistor T25 and the twenty-sixth transistor T26 is greater than or equal to 80 / 3.

[0334] In an exemplary embodiment, as shown in Figures 7 to 11, it also includes: a plurality of signal lines located in the non-display area, the shift register includes a plurality of transistors and a plurality of capacitors, the plurality of signal lines are connected to the shift register, at least one of the plurality of signal lines extends at least partially along the second direction D2, and the transistor includes: an active pattern, a gate electrode, a first electrode, and a second electrode.

[0335] In an exemplary embodiment, a display substrate includes: a base and a driving structure layer provided on the base, the driving structure layer being provided with a pixel driving circuit and a gate driving circuit, the driving structure layer including: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the base;

[0336] The semiconductor layer includes at least: an active pattern of at least one transistor among the plurality of transistors;

[0337] The first conductive layer includes at least: a gate electrode of at least one transistor among the plurality of transistors and a first plate of at least one capacitor among the plurality of capacitors;

[0338] The second conductive layer includes at least: a second plate of at least one capacitor among the plurality of capacitors;

[0339] The third conductive layer includes at least: a first electrode and a second electrode of at least one transistor among the plurality of transistors;

[0340] The fourth conductive layer includes at least one of the plurality of signal lines.

[0341] In an exemplary embodiment, as shown in Figures 12 and 13, the orthographic projections of all transistors (the seventeenth transistor T17 to the twenty-sixth transistor T26) and all capacitors (the fifth capacitor C5 and the sixth capacitor C6) included in the output sub-circuit on the substrate are arranged on one side of the orthographic projections of all transistors (the first transistor T1 to the sixteenth transistor T16) and the first capacitor C1 to the third capacitor C3 included in the shift sub-circuit on the substrate, and are located on the side of the shift sub-circuit close to the display area.

[0342] In an exemplary embodiment, as shown in Figures 12 and 13, the seventeenth transistor T17 to the twentieth transistor T20, the twenty-second transistor T22, and the twenty-third transistor T23 are located on a side of part of the transistors in the shift sub-circuit close to the next stage shift register, the twenty-first transistor T21 and the twenty-fourth transistor T24 are located on a side of part of the transistors in the shift sub-circuit close to the display area, and the twenty-fifth transistor T25 and the twenty-sixth transistor T26 are located on a side of at least one of the first transistor T1 to the twenty-fourth transistor T24 close to the display area.

[0343] In an exemplary embodiment, as shown in FIG12 , when the shift sub-circuit includes the fourth capacitor C4, the orthographic projections of all transistors included in the output sub-circuit on the substrate are arranged around at least one side of the orthographic projection of the fourth capacitor C4 on the substrate; the fourth capacitor C4 is located on a side of the twenty-fourth transistor T24 close to the next-stage shift register, on a side of the seventeenth transistor T17 to the twentieth transistor T20, the twenty-second transistor T22, and the twenty-third transistor T23 close to the display area, and on a side of the twenty-fifth transistor T25 and the twenty-sixth transistor T26 away from the display area.

[0344] In an exemplary embodiment, as shown in FIG8 and FIG13 , when the shift register includes: first to twenty-sixth transistors T1 to T26 and first to third capacitors C1 to C3, the display substrate further includes: N voltage-stabilizing connecting lines RL, N cascade connecting lines CL, and N cascade output lines OUTL. The second electrode 94 of the ninth transistor T9 and the second electrode 104 of the tenth transistor T10 in the shift register are integrally formed, and the gate electrode 212 of the twenty-first transistor T21 and the first electrode plate C51 of the fifth capacitor C5 are integrally formed. The nth voltage-stabilizing connecting line RL is respectively connected to the integral structure of the second electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10 in the nth stage of the shift register and the nth cascade connecting line CL. The nth cascade output line OUTL is respectively connected to the nth cascade connecting line CL and the first electrode of the first transistor T1 of the n+1th stage of the shift register, where 1≤n≤N, and N is the total number of stages of the shift register.

[0345] In an exemplary embodiment, as shown in Figures 8 and 13, for at least one stage of the shift register, an orthographic projection of an integrated structure of the second electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10 on the substrate at least partially overlaps with an orthographic projection of an integrated structure of the gate electrode of the twenty-first transistor T21 and the first electrode plate C51 of the fifth capacitor C5 on the substrate.

[0346] In an exemplary embodiment, the voltage stabilizing connection line RL is located in the semiconductor layer, the cascade output line OUTL is located in the second conductive layer, and the cascade connection line CL is located in the third conductive layer.

[0347] In an exemplary embodiment, the line width of the voltage stabilizing connection line RL is greater than the line width of the cascade connection line and the line width of the cascade output line;

[0348] In an exemplary embodiment, the resistance value of the voltage stabilizing connection line RL ranges from 500 ohms to 5000 ohms.

[0349] In an exemplary embodiment, the provision of the voltage-stabilizing connection line RL can increase the load of the connection structure connecting the second electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10 in the n-th stage shift register and the first electrode of the first transistor T1 of the n+1-th stage shift register, thereby ensuring the stability of the signal transmitted between the second electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10 in the n-th stage shift register and the first electrode of the first transistor T1 of the n+1-th stage shift register.

[0350] In an exemplary embodiment, as shown in Figures 7, 9, 10, 11, and 12, when the shift register includes transistors T1 to T26 and capacitors C1 to C4, the display substrate further includes N cascade output lines OUTL, the second electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10 in the shift register are integrally formed, and the gate electrode of the twenty-first transistor T21 and the first plate of the fifth capacitor are integrally formed. The integral structure of the second electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10 in the n-th stage shift register is connected to the i-th cascade output line OUTL and the second plate C42 of the fourth capacitor C4 in the n-th stage shift register, respectively.

[0351] In an exemplary embodiment, as shown in Figures 7, 9, 10, 11 and 12, for at least one stage of the shift register, an orthographic projection of the integrated structure of the second electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10 on the substrate does not overlap with an orthographic projection of the integrated structure of the gate electrode of the twenty-first transistor T21 and the first plate of the fifth capacitor on the substrate.

[0352] In an exemplary embodiment, as shown in FIG. 7 , FIG. 9 , FIG. 10 , FIG. 11 and FIG. 12 , the cascade output line is located in the second conductive layer.

[0353] In an exemplary embodiment, as shown in Figures 7 to 11, the display substrate further includes: N-1 node connection lines NL, wherein the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7 in the shift register are integrally connected. The i-th node connection line NL(i) is respectively connected to the integral structure of the second electrode 64 of the sixth transistor T6 and the first electrode 73 of the seventh transistor T7 in the i-th stage shift register GOA(i), and the gate electrode 192 of the nineteenth transistor T19 in the i+1-th stage shift register GOA(i+1), where 1≤i≤N-1.

[0354] In an exemplary embodiment, as shown in Figures 7 and 8, the node connection lines include: a first node connection line and a second node connection line arranged in different layers. For the i-th node connection line NL(i), the first node connection line NL1(i) is respectively connected to the integrated structure of the second electrode 64 of the sixth transistor T6 and the first electrode 73 of the seventh transistor T7 of the i-th stage shift register GOA(i) and the second node connection line NL2(i), and the second node connection line NL1(i) is electrically connected to the gate electrode 192 of the nineteenth transistor T19 of the i+1-th stage shift register GOA(i+1).

[0355] In an exemplary embodiment, as shown in FIG. 7 and FIG. 8 , at least one of the first node connection line and the second node connection line at least partially extends along the second direction D2 .

[0356] In an exemplary embodiment, as shown in Figures 7 and 8, there is no overlapping area between the orthographic projection of the first node connection line on the substrate and the orthographic projection of at least one of the multiple signal lines on the substrate, the orthographic projection of the second node connection line on the substrate at least partially overlaps with the orthographic projection of some of the multiple signal lines on the substrate, and the orthographic projection of some of the second node connection line on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate, wherein the first signal line is a signal line among the multiple signal lines that is away from the display area.

[0357] In an exemplary embodiment, as shown in FIG. 7 and FIG. 8 , the first node connection line is located in the fourth conductive layer, and the second node connection line is located in the third conductive layer.

[0358] In an exemplary embodiment, as shown in FIG9 , a node connection line includes a first node connection portion and a second node connection portion, the first node connection portion and the second node connection portion being an integral structure. For the i-th node connection line NL(i), the first node connection portion NLA(i) is connected to the integral structure of the second electrode 64 of the sixth transistor T6 and the first electrode 73 of the seventh transistor T7 of the i-th stage shift register GOA(i), and the second node connection portion NLB(i). The second node connection portion NLB(i) is electrically connected to the gate electrode 192 of the nineteenth transistor T19 of the i+1-th stage shift register GOA(i+1).

[0359] In an exemplary embodiment, as shown in FIG9 , the first node connection portion extends at least partially along the second direction D2, the second node connection portion extends at least partially along the first direction D1, the orthographic projection of the second node connection portion on the substrate at least partially overlaps with the orthographic projections of some of the plurality of signal lines on the substrate, and the orthographic projection of some of the second node connection portion on the substrate is located on a side of the orthographic projection of the first signal line on the substrate that is closer to the display area, wherein the first signal line is a signal line of the plurality of signal lines that is farther away from the display area. This arrangement of the node connection lines can reduce the coupling capacitance between the node connection lines and the signal lines, prevent interference with the signals of the node connection lines, and improve the reliability of the display substrate.

[0360] In an exemplary embodiment, as shown in FIG. 9 , an orthographic projection of the first node connection portion on the substrate may at least partially overlap with an orthographic projection of some of the plurality of signal lines on the substrate.

[0361] In an exemplary embodiment, as shown in FIG9 , the driving structure layer further includes: a fifth conductive layer located on a side of the fourth conductive layer away from the substrate; and the node connection line is located in the fifth conductive layer.

[0362] In an exemplary embodiment, as shown in FIG10 , the node connection lines include: a first node connection line and a second node connection line arranged in different layers. For the i-th node connection line NL(i), the first node connection line NL1(i) is respectively connected to the integrated structure of the second electrode 64 of the sixth transistor T6 and the first electrode 73 of the seventh transistor T7 of the i-th stage shift register GOA(i) and the second node connection line NL2(i). The second node connection line NL2(i) is electrically connected to the gate electrode 192 of the nineteenth transistor T19 of the i+1-th stage shift register GOA(i+1).

[0363] In an exemplary embodiment, as shown in FIG10 , a first node connection line extends at least partially along the second direction D2, and a second node connection line extends at least partially along the first direction D1. The orthographic projection of the second node connection line on the substrate at least partially overlaps with the orthographic projections of some of the plurality of signal lines on the substrate, and the orthographic projection of some of the second node connection line on the substrate is located on a side of the orthographic projection of the first signal line on the substrate that is closer to the display area. The first signal line is a signal line of the plurality of signal lines that is further away from the display area. This arrangement of the node connection lines can reduce coupling capacitance between the node connection lines and the signal lines, preventing interference with the signals of the node connection lines, and improving the reliability of the display substrate.

[0364] In an exemplary embodiment, as shown in FIG. 10 , an orthographic projection of the first node connection line on the substrate may at least partially overlap with orthographic projections of some of the plurality of signal lines on the substrate.

[0365] In an exemplary embodiment, as shown in FIG10 , the driving structure layer further includes: a fifth conductive layer located on a side of the fourth conductive layer away from the substrate; the first node connection line is located in the fifth conductive layer, and the second node connection line is located in the third conductive layer.

[0366] In an exemplary embodiment, as shown in FIG11 , the node connection lines include a first node connection line, a second node connection line, and a third node connection line, which are arranged in different layers. For the i-th node connection line NL(i), the first node connection line NL1(i) is respectively connected to the integrated structure of the second electrode 64 of the sixth transistor T6 and the first electrode 73 of the seventh transistor T7 of the i-th stage shift register GOA(i) and the third node connection line NL3(i). The second node connection line NL2(i) is respectively electrically connected to the third node connection line NL3(i) and the gate electrode 192 of the nineteenth transistor T19 of the i+1-th stage shift register GOA(i+1).

[0367] In an exemplary embodiment, as shown in FIG11 , the first and third node connection lines extend at least partially along the second direction D2, the second node connection line extends at least partially along the first direction D1, the orthographic projection of the third node connection line on the substrate does not overlap with the orthographic projection of at least one of the plurality of signal lines on the substrate, the orthographic projection of the second node connection line on the substrate at least partially overlaps with the orthographic projections of some of the plurality of signal lines on the substrate, and the orthographic projection of some of the second node connection line on the substrate is located on a side of the orthographic projection of the first signal line on the substrate that is closer to the display area, wherein the first signal line is a signal line of the plurality of signal lines that is farther away from the display area. This arrangement of the node connection lines can reduce coupling capacitance between the node connection lines and the signal lines, prevent interference with the signals of the node connection lines, and improve the reliability of the display substrate.

[0368] In an exemplary embodiment, as shown in FIG11 , the driving structure layer further includes: a fifth conductive layer located on a side of the fourth conductive layer away from the substrate; the first node connection line is located in the fifth conductive layer, the third node connection line is located in the fourth conductive layer, and the second node connection line is located in the third conductive layer.

[0369] In an exemplary embodiment, as shown in Figures 7 to 11, the plurality of signal lines include: a latch signal line MSL, a second clock signal line CLK2, a first clock signal line CLK1, a first power line VGL-1, a second power line VGH-1, a third power line VGL-2, a fourth power line VCX, a fifth power line VGL-3, a sixth power line VGH-2, a seventh power line VGH-3, an eighth power line VGH-4, and a ninth power line VGL-4 arranged in sequence near the display area. The latch signal line MSL is configured to provide a signal to a latch signal terminal connected to the shift register, and at least one of the first power line VGL-1, the third power line VGL-2, the fifth power line VGL-3, and the ninth power line VGL-4 is configured to provide a signal to the second power terminal or the fourth power terminal connected to the shift register. The second power line VGH-1, the sixth power line VGH-2, the seventh power line VGH-3, and the eighth power line VGH-4 are configured to provide signals to the first power terminal and the third power terminal connected to the shift register, and the fourth power line VCX is configured to provide a signal to the fifth power terminal connected to the shift register. The seventh power line VGH-3 is configured to provide a signal to the third power terminal connected to the i-th stage shift register, and the eighth power line VGH-4 is configured to provide a signal to the third power terminal connected to the i+1-th stage shift register.

[0370] In an exemplary embodiment, the first power line to which some transistors in the shift sub-circuit are connected is different from the first power line to which some transistors in the output sub-circuit are connected and is independently set, and the second power line to which some transistors in the shift sub-circuit are connected is different from the second power line to which some transistors in the output sub-circuit are connected and is independently set, thereby achieving independent regulation of the shift sub-circuit and the output sub-circuit.

[0371] In an exemplary embodiment, the seventh power line VGH-3 is configured to provide a signal to the third power terminal connected to the i-th stage shift register, and the eighth power line VGH-4 is configured to provide a signal to the third power terminal connected to the i+1-th stage shift register. Connecting the third power terminals of adjacent stages of shift registers to different power lines can improve the stability of the output of high-level signals of adjacent shift registers, thereby improving the reliability of the display substrate.

[0372] In an exemplary embodiment, the orthographic projection of the latch signal line MSL on the substrate is located on a side of the orthographic projection of the multiple transistors in the shift register on the substrate away from the display area, and the orthographic projection of at least one signal line among the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGL-1, the second power line VGH-1, the third power line VGL-2, the fourth power line, the fifth power line VGL-3, the sixth power line VGH-2, the seventh power line VGH-3, the eighth power line VGH-4 and the ninth power line VGL-4 on the substrate at least partially overlaps with the orthographic projection of some transistors in the shift register on the substrate. The above signal line setting method can reduce the area occupied by the gate drive circuit and the signal lines connected thereto, and can achieve a narrow frame of the display substrate.

[0373] In an exemplary embodiment, signals of at least two of the second power line VGH-1, the sixth power line VGH-2, the seventh power line VGH-3, and the eighth power line VGH-4 are the same; alternatively, signals of the second power line VGH-1 and the sixth power line VGH-2 are the same, signals of the seventh power line VGH-3 and the eighth power line VGH-4 are the same, and voltage values ​​of the signals of the second power line VGH-1 and the seventh power line VGH-3 are different; alternatively, signals of the sixth power line VGH-2, the seventh power line VGH-3, and the eighth power line VGH-4 are the same, and voltage values ​​of the signals of the second power line VGH-1 and the sixth power line VGH-2 are different.

[0374] In an exemplary embodiment, signals of at least two of the first power line VGL-1, the third power line VGL-2, the fifth power line VGL-3, and the ninth power line VGL-4 are the same, or signals of at least two of the first power line VGL-1, the third power line VGL-2, and the fifth power line VGL-3 are the same and different from the signal of the ninth power line VGL-4.

[0375] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer located on a side of the drive circuit layer away from the substrate. The light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel drive circuit via a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. Driven by the anode and cathode, the organic light-emitting layer emits light of a corresponding color.

[0376] In an exemplary embodiment, the display substrate may further include an encapsulation structure layer located on a side of the light-emitting structure layer away from the substrate. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of an organic material. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0377] In an exemplary embodiment, the display substrate may further include a touch structure layer located on a side of the encapsulation structure layer away from the base. The touch structure layer may include a first touch insulation layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulation layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, and the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes may be connected to the bridging electrodes through vias.

[0378] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a gate driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0379] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0380] (1) Forming a semiconductor layer pattern on a substrate. In an exemplary embodiment, forming a semiconductor layer pattern on a substrate may include: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern. As shown in Figures 14 and 15, Figure 14 is a schematic diagram of the display substrate provided in Figures 7 and 9 to 11 after a semiconductor layer pattern is formed, and Figure 15 is a schematic diagram of the display substrate provided in Figure 8 after a semiconductor layer pattern is formed.

[0381] In an exemplary embodiment, as shown in FIG14 , the semiconductor layer pattern in the display substrate provided in FIG7 and FIG9 to FIG11 may include at least active patterns 11 to 231 of the first to twenty-sixth transistors of each stage of the shift register.

[0382] In an exemplary embodiment, as shown in FIG. 15 , the semiconductor layer pattern in the display substrate provided in FIG. 8 may include at least active patterns 11 to 231 of the first to twenty-sixth transistors of each stage of the shift register and a stabilizing link line RL.

[0383] In an exemplary embodiment, as shown in Figures 14 and 15, the active pattern 21 of the second transistor and the active pattern 111 of the eleventh transistor are an integrated structure, the active pattern 81 of the eighth transistor, the active pattern 121 of the twelfth transistor, the active pattern 131 of the thirteenth transistor, the active pattern 161 of the sixteenth transistor, and the active pattern 171 of the seventeenth transistor are an integrated structure, the active pattern 141 of the fourteenth transistor and the active pattern 151 of the fifteenth transistor are an integrated structure, the active pattern 191 of the nineteenth transistor and the active pattern 201 of the twentieth transistor are an integrated structure, the active pattern 221 of the twenty-second transistor and the active pattern 231 of the twenty-third transistor are an integrated structure, and the active pattern 251 of the twenty-fifth transistor and the active pattern 261 of the twenty-sixth transistor are an integrated structure. The active pattern 11 of the first transistor, the active pattern 31 of the third transistor, the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 71 of the seventh transistor, the active pattern 91 of the ninth transistor, the active pattern 101 of the tenth transistor, the active pattern 181 of the eighteenth transistor, the active pattern 211 of the twenty-first transistor, and the active pattern 241 of the twenty-fourth transistor can be set separately.

[0384] In an exemplary embodiment, as shown in FIG. 15 , the stabilizing link line RL is separately provided.

[0385] In an exemplary embodiment, as shown in Figures 14 and 15, the active pattern 11 of the first transistor is located on a side of the integrated structure of the active pattern 141 of the fourteenth transistor and the active pattern 151 of the fifteenth transistor close to the display area, and is arranged along the second direction D2 with the active pattern 31 of the third transistor, and the active pattern 31 of the third transistor of the current level shift register is located on a side of the active pattern 11 of the first transistor close to the next level shift register.The integrated structure of the active pattern 21 of the second transistor and the active pattern 111 of the eleventh transistor is located on the side of the active pattern 31 of the third transistor close to the display area, the active pattern 51 of the fifth transistor and the active pattern 61 of the sixth transistor are located on the side of the integrated structure of the active pattern 21 of the second transistor and the active pattern 111 of the eleventh transistor close to the display area, and the active pattern 51 of the fifth transistor of the current stage shift register is located on the side of the active pattern 61 of the sixth transistor close to the next stage shift register, the active pattern 71 of the seventh transistor is located on the side of the active pattern 61 of the sixth transistor close to the display area, and the active pattern 51 of the fifth transistor of the current stage shift register is located on the side of the active pattern 61 of the sixth transistor close to the display area. The active pattern 211 of the seventh transistor is located on a side of the active pattern 71 of the seventh transistor close to the display area, the active pattern 81 of the eighth transistor, the active pattern 121 of the twelfth transistor, the active pattern 131 of the thirteenth transistor, the active pattern 161 of the sixteenth transistor and the active pattern 171 of the seventeenth transistor are located on a side of the active pattern 51 of the fifth transistor close to the display area, the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor are located on the active pattern 81 of the eighth transistor, the active pattern 121 of the twelfth transistor, the active pattern 131 of the thirteenth transistor, the active pattern 161 of the sixteenth transistor and the active pattern 171 of the sixteenth transistor. 61 and the active pattern 171 of the seventeenth transistor are located on a side of the display area, the active pattern 241 of the twenty-fourth transistor is located on a side of the active pattern 101 of the tenth transistor and the active pattern 181 of the eighteenth transistor that are close to the display area, the active pattern 41 of the fourth transistor is located on a side of the active pattern 31 of the third transistor of the current-stage shift register that is close to the next-stage shift register, the active pattern 191 of the nineteenth transistor of the current-stage shift register and the active pattern 201 of the twentieth transistor are located on a side of the active pattern 41 of the fourth transistor that is close to the next-stage shift register, the active pattern 201 of the twenty-second transistor is located on a side of the active pattern 41 of the fourth transistor that is close to the next-stage shift register, and the active pattern 201 of the twenty-second transistor is located on a side of the active pattern 101 of the tenth transistor and the active pattern 181 of the eighteenth transistor that are close to the display area. The active pattern 221 and the active pattern 231 of the twenty-third transistor are an integrated structure located on the side of the integrated structure of the active pattern 191 of the nineteenth transistor and the active pattern 201 of the twentieth transistor close to the display area, and are arranged along the first direction D1 with the active pattern 191 of the nineteenth transistor and the active pattern 201 of the twentieth transistor. The active pattern 181 of the eighteenth transistor is located on the side of the active pattern 41 of the fourth transistor close to the display area, and the active pattern 251 of the twenty-fifth transistor and the active pattern 261 of the twenty-sixth transistor are an integrated structure located on the side of the active pattern 241 of the twenty-fourth transistor close to the display area.

[0386] In an exemplary embodiment, as shown in Figure 15, the voltage-stabilizing connection line RL is located between the active pattern 221 of the twenty-second transistor and the active pattern 231 of the twenty-third transistor, which are an integrated structure, the active pattern 251 of the twenty-fifth transistor, and the active pattern 261 of the twenty-sixth transistor, and is located on the side of the active pattern 241 of the twenty-fourth transistor of the current level shift register close to the next level shift register.

[0387] In an exemplary embodiment, at least one of the active pattern 11 of the first transistor, the active pattern 21 of the second transistor, and the active pattern 111 of the eleventh transistor, the active pattern 31 of the third transistor, the active pattern 51 of the fifth transistor, the active pattern 71 of the seventh transistor, the active pattern 91 of the ninth transistor, the active pattern 141 of the fourteenth transistor, and the active pattern 151 of the fifteenth transistor, the active pattern 211 of the twenty-first transistor, the active pattern 241 of the twenty-fourth transistor, the active pattern 251 of the twenty-fifth transistor, and the active pattern 261 of the twenty-sixth transistor is shaped like a strip and extends along the second direction D2.

[0388] In an exemplary embodiment, the active pattern 41 of the fourth transistor, the active pattern 61 of the sixth transistor, the active pattern 101 of the tenth transistor, the active pattern 181 of the eighteenth transistor, the active pattern 191 of the nineteenth transistor, and the active pattern 201 of the twentieth transistor, the active pattern 221 of the twenty-second transistor, and the active pattern 231 of the twenty-third transistor are an integrated structure, and at least one active pattern in the integrated structure is strip-shaped and extends along the first direction D1.

[0389] In an exemplary embodiment, the integrated structure of the active patterns 81 of the eighth transistor, 121 of the twelfth transistor, 131 of the thirteenth transistor, 161 of the sixteenth transistor, and 171 of the seventeenth transistor has an inverted T shape.

[0390] In an exemplary embodiment, the voltage stabilizing link line RL is shaped like a bar and extends along the second direction D2.

[0391] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region 21-2 of the active pattern 21 of the second transistor may serve as the first region 111-1 of the active pattern 111 of the eleventh transistor, the first region 81-1 of the active pattern 81 of the eighth transistor may serve as the first region 131-1 of the active pattern 131 of the thirteenth transistor, the first region 121-1 of the active pattern 121 of the twelfth transistor may serve as the second region 131-2 of the active pattern 131 of the thirteenth transistor, the second region 121-2 of the active pattern 121 of the twelfth transistor may serve as the second region 161-2 of the active pattern 161 of the sixteenth transistor, and the second region 141 of the active pattern 141 of the fourteenth transistor may serve as the second region 141-2 of the active pattern 141 of the fourteenth transistor. -2 can serve as the first area 151-1 of the active pattern 151 of the fifteenth transistor, the first area 161-1 of the active pattern 161 of the sixteenth transistor can serve as the first area 171-1 of the active pattern 171 of the seventeenth transistor, the second area 191-2 of the active pattern 191 of the nineteenth transistor can serve as the first area 201-1 of the active pattern of the twentieth transistor, the first area 221-1 of the active pattern 221 of the twenty-second transistor can serve as the first area 231-1 of the active pattern 231 of the twenty-third transistor, and the second area 251-2 of the active pattern of the twenty-fifth transistor can serve as the second area 261-2 of the active pattern of the twenty-sixth transistor.a first area 11-1 and a second area 11-2 of the active pattern 11 of the first transistor, a first area 21-1 of the active pattern 21 of the second transistor, a first area 31-1 and a second area 31-2 of the active pattern 31 of the third transistor, a first area 41-1 and a second area 41-2 of the active pattern 41 of the fourth transistor, a first area 51-1 and a second area 51-2 of the active pattern 51 of the fifth transistor, a first area 61-1 and a second area 61-2 of the active pattern 61 of the sixth transistor, a first area 71-1 and a second area 71-2 of the active pattern 71 of the seventh transistor, a second area 81-2 of the active pattern 81 of the eighth transistor, a first area 91-1 and a second area 91-2 of the active pattern 91 of the ninth transistor, a first area 101-1 and a second area 101-2 of the active pattern 101 of the tenth transistor, a second area 111-2 of the active pattern 111 of the eleventh transistor, and a second area 131 of the active pattern 131 of the thirteenth transistor. 131-2, the first area 141-1 of the active pattern 141 of the fourteenth transistor, the second area 151-2 of the active pattern 151 of the fifteenth transistor, the second area 171-2 of the active pattern 171 of the seventeenth transistor, the first area 181-1 and the second area 181-2 of the active pattern 181 of the eighteenth transistor, the first area 191-1 of the active pattern 191 of the nineteenth transistor, the second area 201-2 of the active pattern of the twentieth transistor, the first area 211-1 and the second area 211-2 of the active pattern 211 of the twenty-first transistor, the second area 221-2 of the active pattern 221 of the twenty-second transistor, the first area 231-1 of the active pattern 231 of the twenty-third transistor, the first area 241-1 and the second area 241-2 of the active pattern of the twenty-fourth transistor, the first area 251-1 of the active pattern of the twenty-fifth transistor, and the first area 261-1 of the active pattern of the twenty-sixth transistor are separately provided.

[0392] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film on a substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in Figures 16 to 19, Figure 16 is a schematic diagram of the first conductive layer pattern in the display substrate provided in Figures 7, 9 to 11, Figure 17 is a schematic diagram of the display substrate provided in Figures 7, 9 to 11 forming the first conductive layer pattern, Figure 18 is a schematic diagram of the first conductive layer pattern in the display substrate provided in Figure 8, and Figure 19 is a schematic diagram of the display substrate provided in Figure 8 forming the first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0393] In an exemplary embodiment, as shown in Figures 16 and 17, the first conductive layer pattern in the display substrate provided in Figures 7, 9 to 11 may include at least: the gate electrode 12 of the first transistor to the gate electrode 262 of the twenty-sixth transistor located in each stage of the shift register, and the first plate C11 of the first capacitor to the first plate C61 of the sixth capacitor.

[0394] In an exemplary embodiment, as shown in Figures 18 and 19, the first conductive layer pattern in the display substrate provided in Figure 8 may include at least: the gate electrode 12 of the first transistor to the gate electrode 262 of the twenty-sixth transistor located in each stage of the shift register, the first plate C11 of the first capacitor to the first plate C31 of the third capacitor, the first plate C51 of the fifth capacitor and the first plate C61 of the sixth capacitor.

[0395] In an exemplary embodiment, the gate electrode 12 of the first transistor is provided separately. The gate electrode 12 of the first transistor is in a stripe shape and extends along the first direction D1.

[0396] In an exemplary embodiment, the gate electrode 22 of the second transistor and the gate electrode 82 of the eighth transistor are integrally formed. The gate electrode 22 of the second transistor may be in an "n" shape with an opening toward the display area, and the gate electrode 82 of the eighth transistor may be in a zigzag shape, extending at least partially along the first direction D1.

[0397] In an exemplary embodiment, the gate electrode 32 of the third transistor and the gate electrode 142 of the fourteenth transistor are integrally formed. The integral structure of the gate electrode 32 of the third transistor and the gate electrode 142 of the fourteenth transistor may be strip-shaped and extend along the first direction D1.

[0398] In an exemplary embodiment, the gate electrode 42 of the fourth transistor, the gate electrode 162 of the sixteenth transistor, the gate electrode 172 of the seventeenth transistor, and the first plate C31 of the third capacitor are integrally formed. The shape of the third capacitor C31 is rectangular. The gate electrode 42 of the fourth transistor and the gate electrode 172 of the seventeenth transistor of the current shift register are located on the side of the third capacitor C31 close to the next shift register. The gate electrode 42 of the fourth transistor and the gate electrode 172 of the seventeenth transistor are strip-shaped and extend along the second direction D2. The gate electrode 162 of the sixteenth transistor is located on the side of the first plate C31 of the third capacitor close to the display area. The gate electrode 162 of the sixteenth transistor is shaped like a letter "┐". The gate electrode 42 of the fourth transistor, the gate electrode 162 of the sixteenth transistor, the gate electrode 172 of the seventeenth transistor, and the first plate C31 of the third capacitor are integrally formed and may be shaped like an "M".

[0399] In an exemplary embodiment, the gate electrode 52 of the fifth transistor is provided separately. The gate electrode 52 of the fifth transistor may be in a shape of a Chinese character "└".

[0400] In an exemplary embodiment, the gate electrode 62 of the sixth transistor and the first plate C11 of the first capacitor are integrally formed. The gate electrode 62 of the sixth transistor is located on a side of the first plate C11 of the first capacitor that is closer to the display area. The first plate C11 of the first capacitor may be T-shaped, and the gate electrode 62 of the sixth transistor may be strip-shaped, extending at least partially along the second direction D2. The integral structure of the gate electrode 62 of the sixth transistor and the first plate C11 of the first capacitor may be N-shaped.

[0401] In an exemplary embodiment, the gate electrode 72 of the seventh transistor is separately provided. The gate electrode 72 of the seventh transistor is in a zigzag shape and at least partially extends along the first direction D1. The gate electrode 72 of the seventh transistor is at least partially located on one side of the first plate C11 of the first capacitor.

[0402] In an exemplary embodiment, the gate electrode 92 of the ninth transistor and the first plate C21 of the second capacitor are integrally formed. The gate electrode 92 of the ninth transistor is located on the side of the first plate C21 of the second capacitor that is closer to the display area. The integral structure of the gate electrode 92 of the ninth transistor and the first plate C21 of the second capacitor may be in an "F" shape.

[0403] In an exemplary embodiment, the gate electrode 102 of the tenth transistor is provided separately. The gate electrode 102 of the tenth transistor is in a strip shape and extends along the second direction D2.

[0404] In an exemplary embodiment, the gate electrode 112 of the eleventh transistor and the gate electrode 152 of the fifteenth transistor are integrally formed. The gate electrode 112 of the eleventh transistor (also the gate electrode 152 of the fifteenth transistor) is strip-shaped and extends along the first direction D1.

[0405] In an exemplary embodiment, the gate electrode 122 of the twelfth transistor is separately provided. The gate electrode 122 of the twelfth transistor may be in a stripe shape and at least partially extend along the first direction D1.

[0406] In an exemplary embodiment, the gate electrode 132 of the thirteenth transistor is separately provided. The gate electrode 132 of the thirteenth transistor is in a stripe shape and extends along the first direction D1.

[0407] In an exemplary embodiment, the gate electrode 182 of the eighteenth transistor is provided separately. The gate electrode 182 of the eighteenth transistor may be shaped like a letter "└".

[0408] In an exemplary embodiment, the gate electrode 192 of the nineteenth transistor is provided separately. The gate electrode 192 of the nineteenth transistor is in a stripe shape and extends along the second direction D2.

[0409] In an exemplary embodiment, the gate electrode 202 of the twentieth transistor is provided separately. The gate electrode 202 of the twentieth transistor may be in a strip shape and extend along the second direction D2.

[0410] In an exemplary embodiment, the gate electrode 212 of the twenty-first transistor and the first plate C51 of the fifth capacitor are integrally formed. The gate electrode 212 of the twenty-first transistor is located on a side of the first plate C51 of the fifth capacitor away from the display area. The integral structure of the gate electrode 212 of the twenty-first transistor and the first plate C51 of the fifth capacitor is strip-shaped and extends at least partially along the second direction D2.

[0411] In an exemplary embodiment, the gate electrode 222 of the 22nd transistor is provided separately. The gate electrode 222 of the 22nd transistor may be in a shape of a Chinese character "└".

[0412] In an exemplary embodiment, the gate electrode 232 of the twenty-third transistor is separately provided, and the gate electrode 232 of the twenty-third transistor may be in a strip shape and extend along the second direction D2.

[0413] In an exemplary embodiment, the gate electrode 242 of the 24th transistor and the gate electrode 262 of the 26th transistor are integrally formed. The gate electrode 242 of the 24th transistor is located on a side of the gate electrode 262 of the 26th transistor that is away from the display area. The integral structure of the gate electrode 242 of the 24th transistor and the gate electrode 262 of the 26th transistor is shaped like a comb, with the teeth of the comb located on the side of the back of the comb that is closer to the display area.

[0414] In this exemplary embodiment, the gate electrode 252 of the twenty-fifth transistor and the first plate C61 of the sixth capacitor are integrally formed. The gate electrode 252 of the twenty-fifth transistor is located on the side of the first plate C61 of the sixth capacitor that is closest to the display area. The integral structure of the gate electrode 252 of the twenty-fifth transistor and the first plate C61 of the sixth capacitor is shaped like a comb, with the teeth located on the side of the back of the comb that is closest to the display area.

[0415] In an exemplary embodiment, the first electrode plate C1 of the fourth capacitor is provided separately. The first electrode plate C1 of the fourth capacitor may be in a shape of a Chinese character "└".

[0416] In an exemplary embodiment, the gate electrode 12 of the first transistor is arranged across the active pattern of the first transistor, the gate electrode 22 of the second transistor (also the gate electrode 82 of the eighth transistor) is arranged across the active pattern of the second transistor and the active pattern of the eighth transistor, the gate electrode 32 of the third transistor (also the gate electrode 142 of the fourteenth transistor) is arranged across the active pattern of the third transistor and the active pattern of the fourteenth transistor, and the gate electrode 42 of the fourth transistor (also the first plate C31 of the third capacitor, the gate electrode 162 of the sixteenth transistor, and the gate electrode 172 of the seventeenth transistor) is arranged across the active pattern of the fourth transistor. The gate electrode 52 of the fifth transistor is arranged across the active pattern of the fifth transistor, the gate electrode 62 of the sixth transistor (also the first plate C11 of the first capacitor) is arranged across the active pattern of the sixth transistor, the gate electrode 72 of the seventh transistor is arranged across the active pattern of the seventh transistor, the gate electrode 92 of the ninth transistor (also the first plate C21 of the second capacitor) is arranged across the active pattern of the ninth transistor, the gate electrode 102 of the tenth transistor is arranged across the active pattern of the tenth transistor, and the gate electrode 112 of the eleventh transistor (also the gate electrode of the fifteenth transistor) is arranged across the active pattern of the tenth transistor. The gate electrode 152 of the transistor is arranged across the active pattern of the eleventh transistor and the active pattern of the fifteenth transistor, the gate electrode 122 of the twelfth transistor is arranged across the active pattern of the twelfth transistor, the gate electrode 132 of the thirteenth transistor is arranged across the active pattern of the thirteenth transistor, the gate electrode 182 of the eighteenth transistor is arranged across the active pattern of the eighteenth transistor, the gate electrode 192 of the nineteenth transistor is arranged across the active pattern of the nineteenth transistor, the gate electrode 202 of the twentieth transistor is arranged across the active pattern of the twentieth transistor, and the gate electrode 212 of the twenty-first transistor (also the first plate C of the fifth capacitor) is arranged across the active pattern of the twentieth transistor. 51) is arranged across the active pattern of the twenty-first transistor, the gate electrode 222 of the twenty-second transistor is arranged across the active pattern of the twenty-second transistor, the gate electrode 232 of the twenty-third transistor is arranged across the active pattern of the twenty-third transistor, the gate electrode 242 of the twenty-fourth transistor (which is also the gate electrode 262 of the twenty-sixth transistor) is arranged across the active pattern of the twenty-fourth transistor and the active pattern of the twenty-sixth transistor, and the gate electrode 252 of the twenty-fifth transistor is arranged across the active pattern of the twenty-fifth transistor. That is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0417] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductively processed using the first conductive layer as a shield. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first to twenty-sixth transistors, and the semiconductor layer in the area not shielded by the first conductive layer is conductively processed. That is, the first and second areas of the active pattern of any transistor from the first to the twenty-sixth transistors are both conductively processed. As shown in Figures 17 and 19, after the conductive processing, the second area of ​​the active pattern of the fourteenth transistor (also the first area of ​​the active pattern of the fifteenth transistor) in the present disclosure serves as the second electrode 144 of the fourteenth transistor (also the first electrode 153 of the fifteenth transistor), and the second area of ​​the active pattern of the nineteenth transistor (also the first area of ​​the active pattern of the twentieth transistor) serves as the second electrode 194 of the nineteenth transistor (also the first electrode 203 of the twentieth transistor).

[0418] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film on a substrate having the aforementioned pattern, patterning the second conductive film through a patterning process to form a second insulating layer pattern covering the first conductive layer pattern and a second conductive layer pattern located on the second insulating layer pattern, as shown in Figures 20 to 23, Figure 20 is a schematic diagram of the second conductive layer pattern in the display substrate provided in Figures 7, 9 to 11, Figure 21 is a schematic diagram of forming the second conductive layer pattern on the display substrate provided in Figures 7, 9 to 11, Figure 22 is a schematic diagram of the second conductive layer pattern in the display substrate provided in Figure 8, and Figure 23 is a schematic diagram of forming the second conductive layer pattern on the display substrate provided in Figure 8. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0419] In an exemplary embodiment, as shown in Figures 20 and 21, in the display substrate provided in Figures 7, 9 to 11, the second conductive layer pattern may include at least: the second plate C12 of the first capacitor to the second plate C62 of the sixth capacitor located in each stage of the shift register, the cascade output line OUTL, the first connection line L1 and the second connection line L2.

[0420] In an exemplary embodiment, in the display substrate provided in FIG8 , the second conductive layer pattern may include at least: a second plate C12 of the first capacitor to a second plate C32 of the third capacitor located in each stage of the shift register, a second plate C52 of the fifth capacitor, a second plate C62 of the sixth capacitor, a cascade output line OUTL, a first connection line L1, and a second connection line L2.

[0421] In an exemplary embodiment, an orthographic projection of the second plate C12 of the first capacitor on the substrate at least partially overlaps an orthographic projection of the first plate of the first capacitor on the substrate. The area of ​​the second plate C12 of the first capacitor is smaller than the area of ​​the first plate of the first capacitor. The shape of the second plate C12 of the first capacitor is the same as the shape of the first plate of the first capacitor.

[0422] In an exemplary embodiment, an orthographic projection of the second plate C22 of the second capacitor on the substrate at least partially overlaps an orthographic projection of the first plate of the second capacitor on the substrate, wherein an area of ​​the second plate C22 of the second capacitor is smaller than an area of ​​the first plate of the second capacitor. The shape of the second plate C22 of the second capacitor is the same as that of the first plate of the second capacitor.

[0423] In an exemplary embodiment, an orthographic projection of the second plate C32 of the third capacitor on the substrate at least partially overlaps an orthographic projection of the first plate of the third capacitor on the substrate. The area of ​​the second plate C32 of the third capacitor is smaller than the area of ​​the first plate of the third capacitor. The shape of the second plate C32 of the third capacitor is the same as the shape of the first plate of the third capacitor.

[0424] In an exemplary embodiment, the orthographic projection of the second plate C42 of the fourth capacitor on the substrate at least partially overlaps the orthographic projection of the first plate of the fourth capacitor on the substrate. The area of ​​the second plate C42 of the fourth capacitor is smaller than the area of ​​the first plate of the fourth capacitor.

[0425] In an exemplary embodiment, the orthographic projection of the second plate C52 of the fifth capacitor on the substrate at least partially overlaps the orthographic projection of the first plate of the fifth capacitor on the substrate. The shape of the second plate C52 of the fifth capacitor is the same as the shape of the first plate of the fifth capacitor, and the area of ​​the second plate C52 of the fifth capacitor is smaller than the area of ​​the first plate of the fifth capacitor.

[0426] In an exemplary embodiment, the orthographic projection of the second plate C62 of the sixth capacitor on the substrate at least partially overlaps the orthographic projection of the first plate of the sixth capacitor on the substrate. The shape of the second plate C62 of the sixth capacitor is the same as the shape of the first plate C51 of the sixth capacitor, and the area of ​​the second plate C62 of the sixth capacitor is smaller than the area of ​​the first plate of the sixth capacitor.

[0427] In an exemplary embodiment, the cascode output line OUTL has a bar shape and extends along the first direction D1.

[0428] In an exemplary embodiment, an orthographic projection of the first connection line L1 on the substrate is located between an orthographic projection of the gate electrode of the eighteenth transistor and an orthographic projection of the gate electrode of the twenty-first transistor (also serving as the first plate of the fifth capacitor) on the substrate. The first connection line L1 may be shaped like a zigzag line and extend at least partially along the first direction D1.

[0429] In an exemplary embodiment, the orthographic projection of the second connection line L2 on the substrate is located on a side of the orthographic projection of the gate electrode of the twenty-fifth transistor (also the gate electrode of the twenty-sixth transistor) on the substrate closer to the display area. The second connection line L2 may be strip-shaped and extend along the second direction D2.

[0430] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate having the aforementioned pattern formed thereon, patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned structure, wherein the third insulating layer is provided with a plurality of via patterns, as shown in Figures 24 and 25. Figure 24 is a schematic diagram of forming a third insulating layer pattern on the display substrate provided in Figures 7, 10, and 11, Figure 25 is a schematic diagram of forming a third insulating layer pattern on the display substrate provided in Figure 8, and Figure 26 is a schematic diagram of forming a third insulating layer pattern on the display substrate provided in Figure 9.

[0431] In an exemplary embodiment, as shown in FIG. 24 , in the display substrate provided in FIG. 7 , FIG. 10 , and FIG. 11 , the third insulating layer pattern may include at least: first to seventy-first via holes V1 to V71 located in each stage of the shift register.

[0432] In an exemplary embodiment, as shown in FIG25 , in the display substrate provided in FIG8 , the third insulating layer pattern may include at least: first to sixty-first via holes V1 to V61 , sixty-third to seventieth via holes V63 to V70 , and seventy-second via holes V72 located in each stage of the shift register.

[0433] In an exemplary embodiment, as shown in FIG. 26 , in the display substrate provided in FIG. 9 , the third insulating layer pattern may include at least first to fifty-fourth via holes V1 to V54 and fifty-sixth to seventy-first via holes V56 to V71 located in each stage of the shift register.

[0434] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first transistor on the substrate, the first insulating layer and the second insulating layer within the first via V1 are etched away, exposing the surface of the first area of ​​the active pattern of the first transistor, and the first via V1 is configured to connect the first electrode of the subsequently formed first transistor (also the first electrode of the fourteenth transistor) to the first area of ​​the active pattern of the first transistor through the via.

[0435] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first transistor on the substrate, the first insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the second area of ​​the active pattern of the first transistor, and the second via V2 is configured to connect the second electrode of the subsequently formed first transistor to the second area of ​​the active pattern of the first transistor through the via.

[0436] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the second transistor on the substrate, the first insulating layer and the second insulating layer in the third via V3 are etched away, exposing the surface of the first area of ​​the active pattern of the second transistor, and the third via V3 is configured to connect the first electrode of the subsequently formed second transistor to the first area of ​​the active pattern of the second transistor through the via.

[0437] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second transistor (also the first area of ​​the active pattern of the eleventh transistor) on the substrate, the first insulating layer and the second insulating layer in the fourth via V4 are etched away to expose the surface of the second area of ​​the active pattern of the second transistor (also the first area of ​​the active pattern of the eleventh transistor), and the fourth via V4 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the second area of ​​the active pattern of the second transistor (also the first area of ​​the active pattern of the eleventh transistor) through the via.

[0438] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the third transistor on the substrate, the first insulating layer and the second insulating layer in the fifth via V5 are etched away to expose the surface of the first area of ​​the active pattern of the third transistor, and the fifth via V5 is configured to connect the first electrode of the subsequently formed third transistor to the first area of ​​the active pattern of the third transistor through the via.

[0439] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the third transistor on the substrate, the first insulating layer and the second insulating layer within the sixth via V6 are etched away to expose the surface of the second area of ​​the active pattern of the third transistor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the second area of ​​the active pattern of the third transistor through the via.

[0440] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the first area of ​​the active pattern of the fourth transistor, and the seventh via V7 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active pattern of the fourth transistor through the via.

[0441] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fourth transistor on the substrate, the first insulating layer and the second insulating layer within the eighth via V8 are etched away to expose the surface of the second area of ​​the active pattern of the fourth transistor, and the eighth via V8 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second area of ​​the active pattern of the fourth transistor through the via.

[0442] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifth transistor on the substrate, the first insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the second area of ​​the active pattern of the fifth transistor, and the ninth via V9 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of ​​the active pattern of the fifth transistor through the via.

[0443] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fifth transistor on the substrate, the first insulating layer and the second insulating layer within the tenth via V10 are etched away, exposing the surface of the second area of ​​the active pattern of the fifth transistor, and the tenth via V10 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second area of ​​the active pattern of the fifth transistor through the via.

[0444] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the sixth transistor on the substrate, the first insulating layer and the second insulating layer within the eleventh via V11 are etched away, exposing the surface of the first area of ​​the active pattern of the sixth transistor, and the eleventh via V11 is configured to connect the first electrode of the subsequently formed sixth transistor to the first area of ​​the active pattern of the sixth transistor through the via.

[0445] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the sixth transistor on the substrate, the first insulating layer and the second insulating layer in the twelfth via V12 are etched away to expose the surface of the second area of ​​the active pattern of the sixth transistor, and the twelfth via V12 is configured to connect the second electrode of the subsequently formed sixth transistor (which is also the first electrode of the seventh transistor) to the second area of ​​the active pattern of the sixth transistor through the via.

[0446] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the seventh transistor on the substrate, the first insulating layer and the second insulating layer in the thirteenth via V13 are etched away, exposing the surface of the first area of ​​the active pattern of the seventh transistor, and the thirteenth via V13 is configured to connect the second electrode of the subsequently formed sixth transistor (which is also the first electrode of the seventh transistor) to the first area of ​​the active pattern of the seventh transistor through the via.

[0447] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the seventh transistor on the substrate, the first insulating layer and the second insulating layer in the fourteenth via V14 are etched away to expose the surface of the second area of ​​the active pattern of the seventh transistor, and the fourteenth via V14 is configured to connect the second electrode of the subsequently formed seventh transistor (which is also the second electrode of the eighth transistor) to the second area of ​​the active pattern of the seventh transistor through the via.

[0448] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the eighth transistor (the first area of ​​the active pattern of the thirteenth transistor) on the substrate, the first insulating layer and the second insulating layer within the fifteenth via V15 are etched away to expose the surface of the first area of ​​the active pattern of the eighth transistor (the first area of ​​the active pattern of the thirteenth transistor), and the fifteenth via V15 is configured to connect the first electrode of the subsequently formed eighth transistor (which is also the first electrode of the ninth transistor, the first electrode of the thirteenth transistor, and the first electrode of the twenty-fifth transistor) to the first area of ​​the active pattern of the eighth transistor (the first area of ​​the active pattern of the thirteenth transistor) through the via.

[0449] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the eighth transistor on the substrate, the first insulating layer and the second insulating layer in the sixteenth via V16 are etched away to expose the surface of the second area of ​​the active pattern of the eighth transistor, and the sixteenth via V16 is configured to connect the second electrode of the subsequently formed seventh transistor (which is also the first electrode of the eighth transistor) to the second area of ​​the active pattern of the eighth transistor through the via.

[0450] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the ninth transistor on the substrate, the first insulating layer and the second insulating layer in the seventeenth via V17 are etched away to expose the surface of the first area of ​​the active pattern of the ninth transistor, and the seventeenth via V17 is configured to connect the first electrode of the subsequently formed eighth transistor (which is also the first electrode of the ninth transistor, the first electrode of the thirteenth transistor, and the first electrode of the twenty-fifth transistor) to the first area of ​​the active pattern of the ninth transistor through the via.

[0451] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the ninth transistor on the substrate, the first insulating layer and the second insulating layer in the eighteenth via V18 are etched away to expose the surface of the second area of ​​the active pattern of the ninth transistor, and the eighteenth via V18 is configured to connect the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the tenth transistor) to the second area of ​​the active pattern of the ninth transistor through the via.

[0452] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the tenth transistor on the substrate, the first insulating layer and the second insulating layer in the nineteenth via V19 are etched away to expose the surface of the first area of ​​the active pattern of the tenth transistor, and the nineteenth via V19 is configured to connect the first electrode of the subsequently formed tenth transistor to the first area of ​​the active pattern of the tenth transistor through the via.

[0453] In an exemplary embodiment, the orthographic projection of the twentieth via V20 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the tenth transistor on the substrate, the first insulating layer and the second insulating layer within the twentieth via V20 are etched away to expose the surface of the second area of ​​the active pattern of the tenth transistor, and the twentieth via V20 is configured to connect the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the tenth transistor) to the second area of ​​the active pattern of the tenth transistor through the via.

[0454] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the eleventh transistor on the substrate, the first insulating layer and the second insulating layer in the twenty-first via V21 are etched away to expose the surface of the second area of ​​the active pattern of the eleventh transistor, and the twenty-first via V21 is configured to connect the second electrode of the subsequently formed eleventh transistor to the second area of ​​the active pattern of the eleventh transistor through the via.

[0455] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the twelfth transistor (also the second area of ​​the active pattern of the thirteenth transistor) on the substrate, the first insulating layer and the second insulating layer within the twenty-second via V22 are etched away to expose the surface of the first area of ​​the active pattern of the twelfth transistor (also the second area of ​​the active pattern of the thirteenth transistor), and the twenty-second via V22 is configured to connect the first electrode of the subsequently formed twelfth transistor (also the second electrode of the thirteenth transistor and the first electrode of the eighteenth transistor) to the first area of ​​the active pattern of the twelfth transistor (also the second area of ​​the active pattern of the thirteenth transistor) through the via.

[0456] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the twelfth transistor (also the second area of ​​the active pattern of the sixteenth transistor) on the substrate, the first insulating layer and the second insulating layer in the twenty-third via V23 are etched away to expose the surface of the second area of ​​the active pattern of the twelfth transistor (also the second area of ​​the active pattern of the sixteenth transistor), and the twenty-third via V23 is configured to connect the second electrode of the subsequently formed twelfth transistor (also the second electrode of the sixteenth transistor) to the second area of ​​the active pattern of the twelfth transistor (also the second area of ​​the active pattern of the sixteenth transistor) through the via.

[0457] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourteenth transistor on the substrate, the first insulating layer and the second insulating layer within the twenty-fourth via V24 are etched away to expose the surface of the first area of ​​the active pattern of the fourteenth transistor, and the twenty-fourth via V24 is configured to connect the first electrode of the subsequently formed first transistor (which is also the first electrode of the fourteenth transistor) to the first area of ​​the active pattern of the fourteenth transistor through the via.

[0458] In an exemplary embodiment, the orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fifteenth transistor on the substrate, the first insulating layer and the second insulating layer in the twenty-fifth via V25 are etched away to expose the surface of the second area of ​​the active pattern of the fifteenth transistor, and the twenty-fifth via V25V26 is configured to connect the second electrode of the subsequently formed fifteenth transistor to the second area of ​​the active pattern of the fifteenth transistor through the via.

[0459] In an exemplary embodiment, the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the sixteenth transistor (also the first area of ​​the active pattern of the seventeenth transistor) on the substrate, the first insulating layer and the second insulating layer within the twenty-sixth via V26 are etched away to expose the surface of the first area of ​​the active pattern of the sixteenth transistor (also the first area of ​​the active pattern of the seventeenth transistor), and the twenty-sixth via V26 is configured to connect the first electrode of the subsequently formed sixteenth transistor (also the first electrode of the seventeenth transistor) to the first area of ​​the active pattern of the sixteenth transistor (also the first area of ​​the active pattern of the seventeenth transistor) through the via.

[0460] In an exemplary embodiment, the orthographic projection of the twenty-seventh via V27 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the seventeenth transistor on the substrate, the first insulating layer and the second insulating layer within the twenty-seventh via V27 are etched away to expose the surface of the second area of ​​the active pattern of the seventeenth transistor, and the twenty-seventh via V27 is configured to connect the second electrode of the subsequently formed seventeenth transistor (which is also the second electrode of the eighteenth transistor) to the second area of ​​the active pattern of the seventeenth transistor through the via.

[0461] In an exemplary embodiment, the orthographic projection of the twenty-eighth via V28 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the eighteenth transistor on the substrate, the first insulating layer and the second insulating layer within the twenty-eighth via V28 are etched away to expose the surface of the first area of ​​the active pattern of the eighteenth transistor, and the twenty-eighth via V28 is configured to connect the first electrode of the subsequently formed twelfth transistor (which is also the second electrode of the thirteenth transistor and the first electrode of the eighteenth transistor) to the first area of ​​the active pattern of the eighteenth transistor through the via.

[0462] In an exemplary embodiment, the orthographic projection of the twenty-ninth via V29 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the eighteenth transistor on the substrate, the first insulating layer and the second insulating layer in the twenty-ninth via V29 are etched away to expose the surface of the second area of ​​the active pattern of the eighteenth transistor, and the twenty-ninth via V29 is configured to connect the second electrode of the subsequently formed seventeenth transistor (which is also the second electrode of the eighteenth transistor) to the second area of ​​the active pattern of the eighteenth transistor through the via.

[0463] In an exemplary embodiment, the orthographic projection of the thirtieth via V30 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the nineteenth transistor on the substrate, the first insulating layer and the second insulating layer in the thirtieth via V30 are etched away to expose the surface of the first area of ​​the active pattern of the nineteenth transistor, and the thirtieth via V30 is configured to connect the first electrode of the subsequently formed nineteenth transistor to the first area of ​​the active pattern of the nineteenth transistor through the via.

[0464] In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the twentieth transistor on the substrate, the first insulating layer and the second insulating layer within the thirty-first via V31 are etched away to expose the surface of the second area of ​​the active pattern of the twentieth transistor, and the thirty-first via V31 is configured to connect the second electrode of the subsequently formed twentieth transistor (which is also the second electrode of the twenty-second transistor and the second electrode of the twenty-third transistor) to the second area of ​​the active pattern of the twentieth transistor through the via.

[0465] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the twenty-first transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-second via V32 are etched away to expose the surface of the first area of ​​the active pattern of the twenty-first transistor, and the thirty-second via V32 is configured to connect the first electrode of the subsequently formed twenty-first transistor to the first area of ​​the active pattern of the twenty-first transistor through the via.

[0466] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the twenty-first transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-third via V33 are etched away to expose the surface of the second area of ​​the active pattern of the twenty-first transistor, and the thirty-third via V33 is configured to connect the second electrode of the subsequently formed twenty-first transistor (which is also the second electrode of the twenty-fourth transistor) to the second area of ​​the active pattern of the twenty-first transistor through the via.

[0467] In an exemplary embodiment, the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the twenty-second transistor (also the first area of ​​the active pattern of the twenty-third transistor) on the substrate, and the fourth insulating layer in the thirty-fourth via V34 is etched away to expose the surface of the first area of ​​the active pattern of the twenty-second transistor (also the first area of ​​the active pattern of the twenty-third transistor). The thirty-fourth via V34 is configured to connect the first electrode of the subsequently formed twenty-second transistor (also the first electrode of the twenty-third transistor) to the first area of ​​the active pattern of the twenty-second transistor (also the first area of ​​the active pattern of the twenty-third transistor) through the via.

[0468] In an exemplary embodiment, the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the twenty-second transistor on the substrate, the fourth insulating layer in the thirty-fifth via V35 is etched away to expose the surface of the second area of ​​the active pattern of the twenty-second transistor, and the thirty-fifth via V35 is configured to connect the second electrode of the subsequently formed twentieth transistor (also the second electrode of the twenty-second transistor and the second electrode of the twenty-third transistor) to the second area of ​​the active pattern of the twenty-second transistor through the via.

[0469] In an exemplary embodiment, the orthographic projection of the thirty-sixth via V36 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the twenty-third transistor on the substrate, the first insulating layer and the second insulating layer within the thirty-sixth via V36 are etched away to expose the surface of the second area of ​​the active pattern of the twenty-third transistor, and the thirty-sixth via V36 is configured to connect the second electrode of the subsequently formed twentieth transistor (also the second electrode of the twenty-second transistor and the second electrode of the twenty-third transistor) to the second area of ​​the active pattern of the twenty-third transistor through the via.

[0470] In an exemplary embodiment, the orthographic projection of the thirty-seventh via V37 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the twenty-fourth transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-seventh via V37 are etched away to expose the surface of the first area of ​​the active pattern of the twenty-fourth transistor, and the thirty-seventh via V37 is configured to connect the first electrode of the subsequently formed twenty-fourth transistor to the first area of ​​the active pattern of the twenty-fourth transistor through the via.

[0471] In an exemplary embodiment, the orthographic projection of the thirty-eighth via V38 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the twenty-fourth transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-eighth via V38 are etched away to expose the surface of the second area of ​​the active pattern of the twenty-fourth transistor, and the thirty-eighth via V38 is configured to connect the second electrode of the subsequently formed twenty-first transistor (which is also the second electrode of the twenty-fourth transistor) to the second area of ​​the active pattern of the twenty-fourth transistor through the via.

[0472] In an exemplary embodiment, the orthographic projection of the thirty-ninth via V39 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the twenty-fifth transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-ninth via V39 are etched away to expose the surface of the first area of ​​the active pattern of the twenty-fifth transistor, and the thirty-ninth via V39 is configured to connect the first electrode of the subsequently formed eighth transistor (which is also the first electrode of the ninth transistor, the first electrode of the thirteenth transistor, and the first electrode of the twenty-fifth transistor) to the first area of ​​the active pattern of the twenty-fifth transistor through the via.

[0473] In an exemplary embodiment, the orthographic projection of the 40th via V40 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the twenty-fifth transistor (also the second area of ​​the active pattern of the twenty-sixth transistor) on the substrate, and the first insulating layer and the second insulating layer in the thirty-ninth via V39 are etched away to expose the surface of the second area of ​​the active pattern of the twenty-fifth transistor (also the second area of ​​the active pattern of the twenty-sixth transistor), and the thirty-ninth via V39 is configured to connect the second electrode of the subsequently formed twenty-fifth transistor (also the second electrode of the twenty-sixth transistor) to the second area of ​​the active pattern of the twenty-fifth transistor (also the second area of ​​the active pattern of the twenty-sixth transistor) through the via.

[0474] In an exemplary embodiment, the orthographic projection of the forty-first via V41 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the twenty-sixth transistor on the substrate, the first insulating layer and the second insulating layer within the forty-first via V41 are etched away to expose the surface of the first area of ​​the active pattern of the twenty-sixth transistor, and the forty-first via V41 is configured to connect the first electrode of the subsequently formed twenty-sixth transistor to the first area of ​​the active pattern of the twenty-sixth transistor through the via.

[0475] In an exemplary embodiment, the orthographic projection of the forty-second via V42 on the substrate is located within the range of the orthographic projection of the gate electrode of the first transistor on the substrate, the second insulating layer in the forty-second via V42 is etched away to expose the surface of the gate electrode of the first transistor, and the forty-second via V42 is configured to connect one of the subsequently formed first clock signal line and the second clock signal line and the first pole of the second transistor to the gate electrode of the first transistor through the via.

[0476] In an exemplary embodiment, the orthographic projection of the forty-third via V43 on the substrate is located within the range of the orthographic projection of the gate electrode of the second transistor (also the gate electrode of the eighth transistor) on the substrate, the second insulating layer in the forty-third via V43 is etched away to expose the surface of the gate electrode of the second transistor (also the gate electrode of the eighth transistor), and the forty-third via V43 is configured to connect the second electrode of the first transistor and the first electrode of the twelfth transistor (also the second electrode of the thirteenth transistor and the first electrode of the eighteenth transistor) formed subsequently to the gate electrode of the second transistor (also the gate electrode of the eighth transistor) through the via.

[0477] In an exemplary embodiment, the orthographic projection of the forty-fourth via V44 on the substrate is located within the range of the orthographic projection of the gate electrode of the third transistor (also the gate electrode of the fourteenth transistor) on the substrate, the second insulating layer in the forty-fourth via V44 is etched away to expose the surface of the gate electrode of the third transistor (also the gate electrode of the fourteenth transistor), and the forty-fourth via V44 is configured to connect the subsequently formed first clock signal line and one of the second clock signal lines and the third connecting line to the gate electrode of the third transistor (also the gate electrode of the fourteenth transistor) through the via.

[0478] In an exemplary embodiment, the orthographic projection of the forty-fifth via V45 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth transistor (also the gate electrode of the sixteenth transistor, the gate electrode of the seventeenth transistor and the first plate of the third capacitor) on the substrate, and the second insulating layer in the forty-fifth via V45 is etched away to expose the surface of the gate electrode of the fourth transistor (also the gate electrode of the sixteenth transistor, the gate electrode of the seventeenth transistor and the first plate of the third capacitor). The forty-fifth via V45 is configured to connect the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor formed subsequently to the gate electrode of the fourth transistor (also the gate electrode of the sixteenth transistor, the gate electrode of the seventeenth transistor and the first plate of the third capacitor) through the via.

[0479] In an exemplary embodiment, the orthographic projection of the forty-sixth via V46 on the substrate is located within the range of the orthographic projection of the gate electrode of the fifth transistor on the substrate, the second insulating layer in the forty-sixth via V46 is etched away to expose the surface of the gate electrode of the fifth transistor, and the forty-sixth via V46 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the gate electrode of the fifth transistor through the via.

[0480] In an exemplary embodiment, the orthographic projection of the forty-seventh via V47 on the substrate is located within the range of the orthographic projection of the gate electrode of the sixth transistor (the first plate of the first capacitor) on the substrate, the second insulating layer in the forty-seventh via V47 is etched away to expose the surface of the gate electrode of the sixth transistor (the first plate of the first capacitor), and the forty-seventh via V47 is configured to connect the second electrode of the subsequently formed eleventh transistor to the gate electrode of the sixth transistor (the first plate of the first capacitor) through the via.

[0481] In an exemplary embodiment, the orthographic projection of the forty-eight via V48 on the substrate is located within the range of the orthographic projection of the gate electrode of the seventh transistor on the substrate, the second insulating layer in the forty-eight via V48 is etched away to expose the surface of the gate electrode of the seventh transistor, and the forty-eight via V48 is configured to connect the fourth connecting line and the first pole of the sixth transistor to the gate electrode of the seventh transistor through the via.

[0482] In an exemplary embodiment, the orthographic projection of the forty-ninth via V49 on the substrate is located within the range of the orthographic projection of the gate electrode of the ninth transistor (also the first plate of the second capacitor) on the substrate, the second insulating layer in the forty-ninth via V49 is etched away to expose the surface of the gate electrode of the ninth transistor (also the first plate of the second capacitor), and the forty-ninth via V49 is configured to connect the second electrode of the subsequently formed seventh transistor (also the second electrode of the eighth transistor) to the gate electrode of the ninth transistor (also the first plate of the second capacitor) through the via.

[0483] In an exemplary embodiment, the orthographic projection of the fiftieth via V50 on the substrate is located within the range of the orthographic projection of the gate electrode of the tenth transistor on the substrate, the second insulating layer in the fiftieth via V50 is etched away to expose the surface of the gate electrode of the tenth transistor, and the fiftieth via V50 is configured to connect the second electrode of the subsequently formed twelfth transistor (which is also the second electrode of the sixteenth transistor) to the gate electrode of the tenth transistor through the via.

[0484] In an exemplary embodiment, the orthographic projection of the fifty-first via V51 on the substrate is located within the range of the orthographic projection of the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor) on the substrate, the second insulating layer in the fifty-first via V51 is etched away to expose the surface of the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor), and the fifty-first via V51 is configured to connect the first electrode of the subsequently formed third transistor to the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor) through the via.

[0485] In an exemplary embodiment, the orthographic projection of the fifty-second via V52 on the substrate is located within the range of the orthographic projection of the gate electrode of the twelfth transistor on the substrate, the second insulating layer in the fifty-second via V52 is etched away to expose the surface of the gate electrode of the twelfth transistor, and the fifty-second via V52 is configured to connect a subsequently formed fifth connecting line to the gate electrode of the twelfth transistor through the via.

[0486] In an exemplary embodiment, the orthographic projection of the fifty-third via V53 on the substrate is located within the range of the orthographic projection of the gate electrode of the thirteenth transistor on the substrate, the second insulating layer in the fifty-third via V53 is etched away to expose the surface of the gate electrode of the thirteenth transistor, and the fifty-third via V53 is configured to connect the subsequently formed sixth connecting line to the gate electrode of the thirteenth transistor through the via.

[0487] In an exemplary embodiment, the orthographic projection of the fifty-fourth via V54 on the substrate is located within the range of the orthographic projection of the gate electrode of the eighteenth transistor on the substrate, the second insulating layer in the fifty-fourth via V54 is etched away to expose the surface of the gate electrode of the eighteenth transistor, and the fifty-fourth via V54 is configured to connect the second electrode of the subsequently formed twentieth transistor (also the second electrode of the twenty-second transistor and the second electrode of the twenty-third transistor) and the seventh connecting line to the gate electrode of the eighteenth transistor through the via.

[0488] In an exemplary embodiment, the orthographic projection of the fifty-fifth via V55 on the substrate is located within the range of the orthographic projection of the gate electrode of the nineteenth transistor on the substrate, the second insulating layer in the fifty-fifth via V55 is etched away to expose the surface of the gate electrode of the nineteenth transistor, and the fifty-fifth via V55 is configured to connect a subsequently formed node connection line to the gate electrode of the nineteenth transistor through the via.

[0489] In an exemplary embodiment, the orthographic projection of the fifty-sixth via V56 on the substrate is located within the range of the orthographic projection of the gate electrode of the twentieth transistor on the substrate, the second insulating layer in the fifty-sixth via V56 is etched away to expose the surface of the gate electrode of the twentieth transistor, and the fifty-sixth via V56 is configured to connect the first electrode of the first transistor of the next-stage shift register formed subsequently (which is also the first electrode of the fourteenth transistor) to the gate electrode of the twentieth transistor through the via.

[0490] In an exemplary embodiment, the orthographic projection of the fifty-seventh via V57 on the substrate is located within the range of the orthographic projection of the gate electrode of the twenty-first transistor (which is also the first plate of the fifth capacitor) on the substrate, and the second insulating layer in the fifty-sixth via V56 is etched away to expose the surface of the gate electrode of the twentieth transistor. The fifty-sixth via V56 is configured to connect the subsequently formed seventh connecting line to the gate electrode of the twentieth transistor through the via.

[0491] In an exemplary embodiment, the orthographic projection of the fifty-eighth via V58 on the substrate is located within the range of the orthographic projection of the gate electrode of the twenty-second transistor on the substrate, the second insulating layer in the fifty-eighth via V58 is etched away to expose the surface of the gate electrode of the twenty-second transistor, and the fifty-eighth via V58 is configured to connect the subsequently formed eighth connecting line to the gate electrode of the twenty-second transistor through the via.

[0492] In an exemplary embodiment, the orthographic projection of the fifty-ninth via V59 on the substrate is located within the range of the orthographic projection of the gate electrode of the twenty-third transistor on the substrate, the fifty-ninth via V59 exposes the surface of the gate electrode of the twenty-third transistor, and the fifty-ninth via V59 is configured to connect the subsequently formed eighth connecting line and the seventh connecting line to the gate electrode of the twenty-third transistor through the via.

[0493] In an exemplary embodiment, the orthographic projection of the fifty-ninth via V59 on the substrate is located within the range of the orthographic projection of the gate electrode of the twenty-third transistor on the substrate, the second insulating layer in the fifty-ninth via V59 is etched away to expose the surface of the gate electrode of the twenty-third transistor, and the fifty-ninth via V59 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the gate electrode of the twenty-third transistor through the via.

[0494] In an exemplary embodiment, the orthographic projection of the 60th via V60 on the substrate is located within the range of the orthographic projection of the gate electrode of the 24th transistor (the gate electrode of the 26th transistor) on the substrate, the second insulating layer in the 60th via V60 is etched away to expose the surface of the gate electrode of the 24th transistor (the gate electrode of the 26th transistor), and the 60th via V60 is configured to connect a subsequently formed ninth connecting line to the gate electrode of the 24th transistor (the gate electrode of the 26th transistor) through the via.

[0495] In an exemplary embodiment, the orthographic projection of the sixty-first via V61 on the substrate is located within the range of the orthographic projection of the gate electrode of the twenty-fifth transistor (also the first plate of the sixth capacitor) on the substrate, the second insulating layer in the sixty-first via V61 is etched away to expose the surface of the gate electrode of the twenty-fifth transistor (also the first plate of the sixth capacitor), and the sixty-first via V61 is configured to connect the second electrode of the subsequently formed twenty-first transistor (also the second electrode of the twenty-fourth transistor) to the gate electrode of the twenty-fifth transistor (also the first plate of the sixth capacitor) through the via.

[0496] In an exemplary embodiment, the orthographic projection of the sixty-second via V62 on the substrate is located within the range of the orthographic projection of the first plate of the fourth capacitor on the substrate, the second insulating layer in the sixty-second via V62 is etched away, exposing the surface of the first plate of the fourth capacitor, and the sixty-second via V62 is configured to connect the subsequently formed tenth connecting line to the first plate of the fourth capacitor through the via.

[0497] In an exemplary embodiment, the orthographic projection of the sixty-third via V63 on the substrate is located within the range of the orthographic projection of the second plate of the first capacitor on the substrate, the sixty-third via V63 exposes the surface of the second plate of the first capacitor, and the sixty-third via V63 is ...

Claims

1. A shift register, comprising: a shift subcircuit and an output subcircuit; The shift subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal and the cascade signal output terminal respectively, and is configured to provide a signal to the cascade signal output terminal under the control of the signals of the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal and the second power supply terminal; The output subcircuit is electrically connected to the shift subcircuit, the latch signal terminal, the first control signal terminal, the second control signal terminal, the third power supply terminal, the fourth power supply terminal, the fifth power supply terminal, the cascade signal output terminal and the drive signal output terminal, respectively, and is configured to provide a signal to the drive signal output terminal under the control of the signals of the shift subcircuit, the latch signal terminal, the first control signal terminal, the second control signal terminal, the cascade signal output terminal, the third power supply terminal, the fourth power supply terminal and the fifth power supply terminal; The shift subcircuit includes: at least one shift output transistor, the shift output transistor is electrically connected to the cascade signal output terminal, the output subcircuit includes: at least one drive output transistor, the drive output transistor is electrically connected to the drive signal output terminal; the shift subcircuit also includes: at least one transistor, the output subcircuit also includes: at least one transistor; The shift subcircuit is provided with a third node, the control electrode of at least one driving output transistor is electrically connected to the third node through at least one transistor of the output subcircuit, and the control electrode of at least one shift output transistor is electrically connected to the third node through at least one transistor of the shift subcircuit.

2. The shift register according to claim 1, wherein: The shift subcircuit is also electrically connected to the fifth power supply terminal and is configured to provide a signal to the cascade signal output terminal under the control of signals from the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal and the fifth power supply terminal.

3. The shift register according to claim 2, wherein: The shift subcircuit comprises: a first transistor to a sixteenth transistor and a first capacitor to a third capacitor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the tenth node; A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the tenth node; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node; The control electrode of the fifth transistor is electrically connected to the tenth node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the fifth node; The control electrode of the sixth transistor is electrically connected to the sixth node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the first node; The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the first node, and the second electrode of the seventh transistor is electrically connected to the fourth node; The control electrode of the eighth transistor is electrically connected to the third node, the first electrode of the eighth transistor is electrically connected to the first power supply terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node; The control electrode of the ninth transistor is electrically connected to the fourth node, and the first electrode of the ninth transistor is electrically connected to the first power supply terminal. The second electrode of the ninth transistor is electrically connected to the cascade signal output terminal; The gate electrode of the tenth transistor is electrically connected to the ninth node, the first electrode of the tenth transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascade signal output terminal; The control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the tenth node, and the second electrode of the eleventh transistor is electrically connected to the sixth node; The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the third node, and the second electrode of the twelfth transistor is electrically connected to the ninth node; The control electrode of the thirteenth transistor is electrically connected to the fifth power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the third node; A control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourteenth transistor is electrically connected to the signal input terminal, and a second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor; The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the fifteenth transistor is electrically connected to the second node; The control electrode of the sixteenth transistor is electrically connected to the second node, the first electrode of the sixteenth transistor is electrically connected to the ninth node, and the second electrode of the sixteenth transistor is electrically connected to the second node; The first plate of the first capacitor is electrically connected to the sixth node, and the second plate of the first capacitor is electrically connected to the first node; The first plate of the second capacitor is electrically connected to the fourth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal; The first plate of the third capacitor is electrically connected to the second node, and the second plate of the third capacitor is electrically connected to the fifth node.

4. The shift register according to claim 2, wherein: The shift subcircuit comprises: a first transistor to a fifteenth transistor and a first capacitor to a third capacitor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the tenth node; A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the tenth node; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node; The control electrode of the fifth transistor is electrically connected to the tenth node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the fifth node; The control electrode of the sixth transistor is electrically connected to the sixth node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the first node; The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the first node, and the second electrode of the seventh transistor is electrically connected to the fourth node; The control electrode of the eighth transistor is electrically connected to the third node, the first electrode of the eighth transistor is electrically connected to the first power supply terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node; The control electrode of the ninth transistor is electrically connected to the fourth node, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the cascade signal output terminal; The control electrode of the tenth transistor is electrically connected to the second node, and the first electrode of the tenth transistor is electrically connected to the second power supply terminal. The second electrode of the tenth transistor is electrically connected to the cascade signal output terminal; The control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the tenth node, and the second electrode of the eleventh transistor is electrically connected to the sixth node; The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the third node, and the second electrode of the twelfth transistor is electrically connected to the second node; The control electrode of the thirteenth transistor is electrically connected to the fifth power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the third node; A control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourteenth transistor is electrically connected to the signal input terminal, and a second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor; The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the fifteenth transistor is electrically connected to the second node; The first plate of the first capacitor is electrically connected to the sixth node, and the second plate of the first capacitor is electrically connected to the first node; The first plate of the second capacitor is electrically connected to the fourth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal; The first plate of the third capacitor is electrically connected to the second node, and the second plate of the third capacitor is electrically connected to the fifth node.

5. The shift register according to claim 3 or 4, wherein: The shift subcircuit further includes: a fourth capacitor; The first plate of the fourth capacitor is electrically connected to the second power supply terminal, and the second plate of the fourth capacitor is electrically connected to the cascade signal output terminal.

6. The shift register according to any one of claims 3 to 5, wherein: The first control signal terminal is electrically connected to the fifth node.

7. The shift register according to claim 6, wherein: The second control signal terminal is electrically connected to a first node in a previous stage shift register of the current stage shift register.

8. The shift register according to claim 3 or 4, wherein: The output sub-circuit is electrically connected to the second node, the third node and the fourth node in the shift register respectively.

9. The shift register according to claim 8, wherein: The output sub-circuit comprises: a seventeenth transistor to a twenty-sixth transistor and a fifth capacitor and a sixth capacitor; The control electrode and the first electrode of the seventeenth transistor are electrically connected to the second node respectively, and the second electrode of the seventeenth transistor is electrically connected to the sixth node; The control electrode of the eighteenth transistor is electrically connected to the seventh node, the first electrode of the eighteenth transistor is electrically connected to the third node, and the second electrode of the eighteenth transistor is electrically connected to the sixth node; The control electrode of the nineteenth transistor is electrically connected to the second control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the latch signal terminal, and the second electrode of the nineteenth transistor is electrically connected to the second electrode of the twentieth transistor; The control electrode of the twentieth transistor is electrically connected to the cascade signal output terminal, and the first electrode of the twentieth transistor is electrically connected to the seventh node; A control electrode of the twenty-first transistor is electrically connected to the seventh node, a first electrode of the twenty-first transistor is electrically connected to the fourth node, and a second electrode of the twenty-first transistor is electrically connected to the eighth node; The control electrode of the twenty-second transistor is electrically connected to the fifth power supply terminal, the first electrode of the twenty-second transistor is electrically connected to the fourth power supply terminal, and the second electrode of the twenty-second transistor is electrically connected to the seventh node; The control electrode of the twenty-third transistor is electrically connected to the first control signal terminal, and the first electrode of the twenty-third transistor is electrically connected to the fourth The power supply terminal is electrically connected, and the second electrode of the twenty-third transistor is electrically connected to the seventh node; A control electrode of the twenty-fourth transistor is electrically connected to the sixth node, a first electrode of the twenty-fourth transistor is electrically connected to the third power supply terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the eighth node; The control electrode of the twenty-fifth transistor is electrically connected to the eighth node, the first electrode of the twenty-fifth transistor is electrically connected to the third power supply terminal, and the second electrode of the twenty-fifth transistor is electrically connected to the drive signal output terminal; The control electrode of the twenty-sixth transistor is electrically connected to the sixth node, the first electrode of the twenty-sixth transistor is electrically connected to the fourth power supply terminal, and the second electrode of the twenty-sixth transistor is electrically connected to the drive signal output terminal; The first electrode plate of the fifth capacitor is electrically connected to the seventh node, and the second electrode plate of the fifth capacitor is electrically connected to the eighth node; The first electrode plate of the sixth capacitor is electrically connected to the eighth node, and the second electrode plate of the sixth capacitor is electrically connected to the third power supply terminal.

10. The shift register according to claim 1, wherein: The shift subcircuit comprises: a first transistor to an eighth transistor and a first capacitor and a second capacitor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node; A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the fourth node; The control electrode of the fourth transistor is electrically connected to the fourth node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the cascade signal output terminal; The control electrode of the fifth transistor is electrically connected to the ninth node, the first electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the cascade signal output terminal; The control electrode of the sixth transistor is electrically connected to the fourth node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the first electrode of the seventh transistor; The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the third node; The control electrode of the eighth transistor is electrically connected to the second power supply terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the ninth node; The first plate of the first capacitor is electrically connected to the ninth node, and the second plate of the first capacitor is electrically connected to the cascade signal output terminal; The first plate of the second capacitor is electrically connected to the fourth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal.

11. The shift register according to claim 10, wherein: The output sub-circuit is also electrically connected to the third node and the fourth node in the shift sub-circuit respectively.

12. The shift register according to claim 11, wherein: The output sub-circuit comprises: an eighteenth transistor to a twenty-sixth transistor and a fifth capacitor and a sixth capacitor; The control electrode of the eighteenth transistor is electrically connected to the seventh node, the first electrode of the eighteenth transistor is electrically connected to the third node, and the second electrode of the eighteenth transistor is electrically connected to the sixth node; The control electrode of the nineteenth transistor is electrically connected to the second control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the latch signal terminal, and the second electrode of the nineteenth transistor is electrically connected to the second electrode of the twentieth transistor; The control electrode of the twentieth transistor is electrically connected to the cascade signal output terminal, and the first electrode of the twentieth transistor is electrically connected to the seventh node. Electrical connection; A control electrode of the twenty-first transistor is electrically connected to the seventh node, a first electrode of the twenty-first transistor is electrically connected to the fourth node, and a second electrode of the twenty-first transistor is electrically connected to the eighth node; The control electrode of the twenty-second transistor is electrically connected to the fifth power supply terminal, the first electrode of the twenty-second transistor is electrically connected to the fourth power supply terminal, and the second electrode of the twenty-second transistor is electrically connected to the seventh node; The control electrode of the twenty-third transistor is electrically connected to the first control signal terminal, the first electrode of the twenty-third transistor is electrically connected to the fourth power supply terminal, and the second electrode of the twenty-third transistor is electrically connected to the seventh node; A control electrode of the twenty-fourth transistor is electrically connected to the sixth node, a first electrode of the twenty-fourth transistor is electrically connected to the third power supply terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the eighth node; The control electrode of the twenty-fifth transistor is electrically connected to the eighth node, the first electrode of the twenty-fifth transistor is electrically connected to the third power supply terminal, and the second electrode of the twenty-fifth transistor is electrically connected to the drive signal output terminal; The control electrode of the twenty-sixth transistor is electrically connected to the sixth node, the first electrode of the twenty-sixth transistor is electrically connected to the fourth power supply terminal, and the second electrode of the twenty-sixth transistor is electrically connected to the drive signal output terminal; The first electrode plate of the fifth capacitor is electrically connected to the seventh node, and the second electrode plate of the fifth capacitor is electrically connected to the eighth node; The first electrode plate of the sixth capacitor is electrically connected to the eighth node, and the second electrode plate of the sixth capacitor is electrically connected to the third power supply terminal.

13. The shift register according to claim 1, wherein: The first power supply terminal and the third power supply terminal are the same signal terminal, and the second power supply terminal and the fourth power supply terminal are the same signal terminal.

14. A gate drive circuit comprising: A plurality of shift registers as claimed in any one of claims 1 to 13; The cascade signal output terminal of one shift register in at least one stage of the shift register is electrically connected to the signal input terminal of the previous stage of the shift register.

15. A display device, comprising: The gate drive circuit as claimed in claim 14.

16. A shift register driving method, configured to drive the shift register according to any one of claims 1 to 13, the method comprising: The shift subcircuit provides a signal to the cascade signal output terminal under the control of the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, and the second power supply terminal; The output subcircuit provides a signal to the drive signal output terminal under the control of signals from the shift subcircuit, the latch signal terminal, the first control signal terminal, the second control signal terminal, the cascade signal output terminal, the third power supply terminal, the fourth power supply terminal and the fifth power supply terminal.

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