Array substrate, display panel and display device
By optimizing the sub-pixel area layout and transistor channel width-length ratio in the array substrate of the liquid crystal display, the problem of color bias of the liquid crystal display at different viewing angles is solved, and better color performance and viewing angles are achieved.
Patent Information
- Application Number
- CN202311764627.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-20
- Publication Date
- 2025-06-20
AI Technical Summary
Existing LCD monitors are prone to color shift problems at different viewing angles, which affects the display effect.
An array substrate is designed, including a substrate substrate, data lines, discharge lines, transistors and pixel electrodes, to improve color shift by optimizing the layout of the sub-pixel region and the channel width-length ratio of the transistor.
It effectively improves the problem of poor color shift, improves the chromaticity performance of the display panel at different viewing angles, and increases the viewing angle.
Smart Images
Figure CN120178562A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of display technologies, and particularly to an array substrate, a display panel, and a display device. Background Art
[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, high image quality, no radiation, and convenient carrying. In recent years, it has developed rapidly and has gradually replaced the traditional Cathode Ray Tube display (CRT) and occupied the dominant position in the current flat panel display market. At present, TFT-LCD has been widely used in various products of large, medium, and small sizes, covering almost all the main electronic products in today's information society, such as liquid crystal TVs, high-definition digital TVs, computers (desktop and notebook), mobile phones, tablet computers, navigators, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays, etc. Summary of the Invention
[0003] An array substrate, a display panel, and a display device provided by an embodiment of the present disclosure can effectively improve the color deviation defect.
[0004] The array substrate, the display panel, and the display device provided by the embodiments of the present disclosure are specifically as follows:
[0005] On the one hand, an embodiment of the present disclosure provides an array substrate, including:
[0006] A substrate, the substrate includes a plurality of sub-pixel regions arranged in an array, and each sub-pixel region includes a bright pixel region and a dark pixel region arranged side by side in a first direction;
[0007] Data lines, extending along the first direction between the sub-pixel regions;
[0008] Discharge lines, extending along the first direction;
[0009] A first pixel electrode, located in the dark pixel region;
[0010] A first transistor, located between the opening region of the bright pixel region and the opening region of the dark pixel region, a first pole of the first transistor is electrically connected to the data line, and a second pole of the first transistor is electrically connected to the first pixel electrode;
[0011] A second transistor is located between the opening region of the bright pixel region and the opening region of the dark pixel region. A first pole of the second transistor is multiplexed with a second pole of the first transistor, and a second pole of the second transistor is electrically connected to the power line. A channel width-to-length ratio of the second transistor is 30% to 40% of a channel width-to-length ratio of the first transistor.
[0012] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, a ratio of an area of the opening region of the bright pixel region to an area of the opening region of the dark pixel is greater than or equal to 1:2.3 and less than or equal to 1:1.8.
[0013] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, a voltage of the power line is greater than or equal to 7V and less than or equal to 10V.
[0014] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, a second pixel electrode located in the bright pixel region and a third transistor located between the opening region of the bright pixel region and the opening region of the dark pixel region are further included. Among them,
[0015] A first pole of the third transistor is multiplexed with a first pole of the first transistor, a second pole of the third transistor is electrically connected to the second pixel electrode, and a channel width-to-length ratio of the third transistor is the same as a channel width-to-length ratio of the first transistor.
[0016] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, a gate line extending along a second direction between the bright pixel region and the dark pixel region is further included. The gate line is electrically connected to a gate of the first transistor, a gate of the second transistor, and a gate of the third transistor.
[0017] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, a common electrode line that is in the same layer as the first pixel electrode and the second pixel electrode and is disposed at intervals is further included. The common electrode line extends along the second direction between the bright pixel region and the dark pixel region;
[0018] The gate line includes two edge portions extending along the second direction and an intermediate portion located between the edge portions. At least a partial region of the edge portion is located within a positive projection of the common electrode line on the substrate, and a positive projection of the intermediate portion on the substrate does not overlap with a positive projection of the common electrode line on the substrate.
[0019] Based on the same inventive concept, embodiments of the present disclosure further provide a display panel, including the above array substrate provided by the embodiments of the present disclosure and an opposing substrate disposed opposite to the array substrate.
[0020] In some embodiments, in the above display panel provided by the embodiments of the present disclosure, the counter substrate includes a black matrix, and a positive projection of the black matrix on the substrate does not overlap with the opening region of the sub-pixel region.
[0021] In some embodiments, in the above display panel provided by the embodiments of the present disclosure, it further includes a common electrode layer located on a side of the black matrix facing the array substrate, and a positive projection of the common electrode layer on the substrate covers the plurality of sub-pixel regions.
[0022] Based on the same inventive concept, the embodiments of the present disclosure further provide a display device, including the above display panel provided by the embodiments of the present disclosure.
[0023] The beneficial effects of the present disclosure are as follows:
[0024] The array substrate, display panel and display device provided by the present disclosure can effectively improve color deviation defects. The array substrate includes a substrate, the substrate includes a plurality of sub-pixel regions arranged in an array, the sub-pixel region includes a bright pixel region and a dark pixel region arranged side by side in a first direction; a data line extending in the first direction between the sub-pixel regions; a discharge line extending in the first direction; a first pixel electrode located in the dark pixel region; a first transistor located between the opening region of the bright pixel region and the opening region of the dark pixel region, a first pole of the first transistor is electrically connected to the data line, and a second pole of the first transistor is electrically connected to the first pixel electrode; a second transistor located between the opening region of the bright pixel region and the opening region of the dark pixel region, a first pole of the second transistor is multiplexed with a second pole of the first transistor, and a second pole of the second transistor is electrically connected to the discharge line; a channel width-to-length ratio of the second transistor is 30% - 40% of a channel width-to-length ratio of the first transistor. Description of the Drawings
[0025] Figure 1 It is a light effect simulation diagram of 8-domain display;
[0026] Figure 2 It is a schematic structural diagram of a pixel region in the display panel provided by the embodiment of the present disclosure;
[0027] Figure 3 It is Figure 2 an enlarged structural diagram of the array substrate in the M region in
[0028] Figure 4 It is Figure 2 a schematic structural diagram of a layer where a gate line of the array substrate is located in
[0029] Figure 5 It is Figure 2 a schematic structural diagram of an active layer of the array substrate in
[0030] Figure 6 is Figure 2 a schematic structural diagram of the layer where the data lines of the array substrate in
[0031] Figure 7 is Figure 2 a schematic structural diagram of the layer where the vias of the array substrate in
[0032] Figure 8 is Figure 2 a schematic structural diagram of the layer where the pixel electrodes of the array substrate in
[0033] Figure 9 is along Figure 2 a cross-sectional structural diagram of the I-II line in
[0034] Figure 10 is along Figure 2 a cross-sectional structural diagram of the III-IV line in
[0035] Figure 11 is along Figure 2 a cross-sectional structural diagram of the V-VI line in
[0036] Figure 12 is Figure 2 an equivalent circuit diagram of a sub-pixel region in
[0037] Figure 13 a gamma curve diagram provided by an embodiment of the present disclosure;
[0038] Figure 14 another gamma curve diagram provided by an embodiment of the present disclosure;
[0039] Figure 15 another gamma curve diagram provided by an embodiment of the present disclosure. Detailed implementation manners
[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are enlarged for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Accordingly, the embodiments described in the present disclosure should not be construed as limited to the specific shapes of the regions shown in the present disclosure, but include deviations in shape resulting from, for example, manufacturing. For example, regions illustrated or described as flat may typically have rough and / or non-linear features; the sharp corners illustrated may be rounded, etc. Thus, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the exact shape of the regions, do not reflect true proportions, and are intended only to schematically illustrate the content of the present disclosure. Also, the same or similar reference numerals throughout the specification denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components are omitted from the present disclosure.
[0041] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the specification and claims of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms "comprising", "including", or similar terms mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" or similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "inner", "outer", "upper", "lower", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.
[0042] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer can be directly on the other element or layer, directly connected to the other element or layer, or there can be intermediate elements or intermediate layers. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer can be directly on one side of the other element or layer, directly connected to the other element or layer, or there can be intermediate elements or intermediate layers. However, when an element or layer is referred to as being "directly on" another element or layer or "directly connected to" another element or layer, there are no intermediate elements or layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.
[0043] With the development of display technology, consumers' requirements for the picture quality of liquid crystal display screens are becoming increasingly strict. Due to the increasing size, the large viewing angle color shift is becoming more and more obvious. Therefore, the color shift of the liquid crystal display screen at different viewing angles has become an important indicator for evaluating the performance of the panel. There are many factors affecting the chromaticity of the liquid crystal display screen, such as the backlight unit (BLU), polarizer (POL), liquid crystal (LC), color filter (CF), and array substrate, etc.
[0044] Multi-domain display can divide a sub-pixel into different regions, and the deflection degrees of the liquid crystals in different regions are different. When viewing the liquid crystal display screen from different angles, the comprehensive effect of the deflection of the liquid crystals in each region is seen, thereby reducing the contrast difference at different angles caused by the same deflection of all the liquid crystals in the pixel, and further reducing the color shift and increasing the viewing angle. For example, in Figure 1 In the 8-domain display shown, the color shift effect can be made better by adjusting the brightness ratio of the upper 4 domains and the lower 4 domains. The pixels with higher brightness are called bright pixels, and the pixels with lower brightness are called dark pixels. In some embodiments, the dark pixels can be discharged through transistors connected to the discharge lines, making the dark pixels darker. However, there are sudden changes in the color shift of the low, medium, and high gray levels in this scheme, which affects the viewing experience.
[0045] In order to at least solve the above technical problems existing in the related art, the embodiments of the present disclosure provide an array substrate, a display panel, and a display device. Figure 2 shows the structure of a pixel region in the display panel. Figure 3 is Figure 2 an enlarged schematic structural view of the array substrate in the M region in Figures 4 to 8 is Figure 2 a schematic structural view of each film layer on the array substrate in Figure 9 is Figure 2 a cross-sectional structural view along the I-II line in Figure 10 is Figure 2 a cross-sectional structural view along the III-IV line inFigure 11 Cross-sectional structural schematic diagram along the Figure 2 V-VI line in Figure 12 is Figure 2 equivalent circuit diagram of a sub-pixel region in Figures 2 to 12 As can be seen, the array substrate 001 may include:
[0046] Substrate 101, the substrate 101 includes a plurality of sub-pixel regions SPX arranged in an array. The plurality of sub-pixel regions SPX may include a plurality of red sub-pixel regions R, a plurality of green sub-pixel regions G, a plurality of blue sub-pixel regions B, etc. The sub-pixel region SPX includes a bright pixel region H and a dark pixel region L arranged side by side in the first direction Y. Optionally, the bright pixel region H and the dark pixel region L are both 4-domain displays, so that each sub-pixel SPX realizes an 8-domain display. Among them, the 4 domains can be realized by alignment through the alignment film. The electrodes of the bright pixel region H and the dark pixel region L can be block-shaped or have slits. The slit electrodes can be cross-shaped or square-shaped; the substrate 101 is a substrate that allows visible light to pass through, such as made of glass, quartz, plastic, etc.;
[0047] Data lines 102, extending along the first direction Y between the sub-pixel regions SPX; the materials used for the data lines 102 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc. In some embodiments, the layer where the data lines 102 are located may be a single-layer structure or a stacked structure. Exemplarily, the layer where the data lines 102 are located is a stacked structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer;
[0048] Discharge lines 103, extending along the first direction Y; optionally, the discharge lines 103 are arranged on the same layer and made of the same material as the data lines 102; in some embodiments, the discharge lines 103 may extend along the first direction Y through the middle region of the sub-pixel region SPX. As Figure 1 can be seen, the middle region between the bright pixels and the dark pixels is a dark stripe region. Setting the discharge lines 103 in the dark stripe region will not affect the transmittance;
[0049] The first pixel electrode 104 is located within the dark pixel region L; in some embodiments, the material of the first pixel electrode 104 includes but is not limited to at least one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and gallium zinc oxide (GZO); optionally, the first pixel electrode 104 and the first common electrode line 105 overlap in the direction Z perpendicular to the substrate 101 to form a first storage capacitor Cst1, and the first pixel electrode 104 can overlap with the common electrode 201 of the opposing substrate 002 in the direction Z perpendicular to the substrate 101 to form a first liquid crystal capacitor Cpx1; wherein, the first storage capacitor Cst1 is used to charge the first pixel electrode 104 during the off period of the first gate line 103 and maintain the voltage on the first pixel electrode 104 (equivalent to the voltage after discharging the charge) until the next frame update, and the first liquid crystal capacitor Cpx1 is used to cause the liquid crystal molecules corresponding to the dark pixel region L to deflect under the electric field in the first liquid crystal capacitor Cpx1 during the on period of the first gate line 103 to achieve dark display;
[0050] The first transistor TFT1 is located between the opening region HO of the bright pixel region H and the opening region LO of the dark pixel region L. The first pole s1 of the first transistor TFT1 is electrically connected to the data line 102 (for example, the first pole s1 of the first transistor TFT1 is integrally provided with the data line 102). The second pole d1 of the first transistor TFT1 is electrically connected to the first pixel electrode 104. For example, the second pole d1 of the first transistor TFT1 is electrically connected to the first pixel electrode 104 through the first via hole h1 penetrating through the passivation layer 106 and the planarization layer 107. In some embodiments, the present disclosure may not provide the planarization layer 107. At this time, the second pole d1 of the first transistor TFT1 can be electrically connected to the first pixel electrode 104 through the first via hole h1 penetrating through the passivation layer 106. The present disclosure is illustrated by taking the case where the planarization layer 107 is provided as an example;
[0051] The second transistor TFT2 is located between the opening region HO of the bright pixel region H and the opening region LO of the dark pixel region L. The first pole s2 of the second transistor TFT2 is multiplexed with the second pole d1 of the first transistor TFT1. The second pole d2 of the second transistor TFT2 is electrically connected to the discharge line 103. Optionally, a part of the discharge line 103 is multiplexed as the second pole d2 of the second transistor TFT2; the channel width-to-length ratio of the second transistor TFT2 is 30% - 40% of the channel width-to-length ratio of the first transistor TFT1, such as 30%, 31%, 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39%, 40%, etc.
[0052] In the above-mentioned array substrate provided by the embodiments of the present disclosure, the data voltage of the data line 102 can be applied to the first pixel electrode 104 through the first transistor TFT1, so that the electric field between the first pixel electrode 104 and the common electrode 201 can drive the corresponding liquid crystal molecules in the dark pixel region L to rotate; at the same time, the second transistor TFT2 is turned on and shares the data voltage from the data line 102 with the first transistor TFT1 to discharge the first pixel electrode 104. The larger the ratio of the channel width-to-length ratio of the second transistor TFT2 to the channel width-to-length ratio of the first transistor TFT1, the more leakage current the second transistor TFT2 has in the dark pixel region L, which can improve color shift; however, if the ratio of the channel width-to-length ratio of the second transistor TFT2 to the channel width-to-length ratio of the first transistor TFT1 is too large, it will cause the color shift of medium and high gray levels to deteriorate. Therefore, the ratio of the channel width-to-length ratio of the second transistor TFT2 to the channel width-to-length ratio of the first transistor TFT1 needs to be set reasonably.
[0053] Figure 13 It is a gamma curve when the ratio of the channel width-to-length ratio of the second transistor TFT2 to the channel width-to-length ratio of the first transistor TFT1 is 50% and 35%. The closer to the standard curve gamma 2.2, the less obvious the color shift; and the smoother the curve transition (that is, there is no obvious upward or downward convexity in the curve), the better the balance of low, medium, and high gray levels, no mutation, and the better the color shift improvement effect. Combining Figure 13 the two gamma curves, it can be seen that: on the one hand, compared with the scheme with a ratio of 35%, the scheme with a ratio of 50% has a reduced Gamma shift in the low and medium gray level ranges of L0 - L145, but an increased Gamma shift in the high gray level ranges of L145 - L255; on the other hand, the gamma curve with a ratio of 50% has an obvious downward convexity in the gray level range of L80 - L120, while the gamma curve with a ratio of 30% is relatively smooth as a whole. Based on this, the present disclosure sets the ratio of the channel width-to-length ratio of the second transistor TFT2 to the channel width-to-length ratio of the first transistor TFT1 to be 30% - 40% to ensure a better balance of low, medium, and high gray levels, no mutation, and a better color shift improvement effect.
[0054] In some embodiments, the present disclosure can also improve color shift by adjusting the ratio between the opening area HO of the bright pixel region H and the opening area LO of the dark pixel region L. Optionally, the ratio of the area of the opening area HO of the bright pixel region H to the area of the opening area LO of the dark pixel L in the present disclosure is greater than or equal to 1:2.3 and less than or equal to 1:1.8, such as 1:1.8, 1:1.9, 1:2, 1:2.1, 1:2.2, 1:2.3, etc.
[0055] The smaller the area of the opening region HO of the bright pixel region H, the flatter the liquid crystal in the opening region HO of the bright pixel region, the earlier the bright point appears, and the better the low gray scale color shift. However, the medium and high gray scales will deteriorate. For example, in Figure 14 the gamma curve graphs shown in Figure 14 where the ratio of the area of the opening region HO of the bright pixel region H to the area of the opening region LO of the dark pixel region L is 1:2 and 1:2.5 respectively can be seen. In the low gray scale range of L0 - L85, the Gamma shift of the 1:2.5 ratio scheme is smaller than that of the 1:2 ratio scheme. In the medium and high gray scale range of L85 - L190, the Gamma shift of the 1:2.5 ratio scheme is larger than that of the 1:2 ratio scheme, and the color shift deteriorates. And from Figure 14 it can be seen that overall, the curve transition of the 1:2 ratio scheme is smoother. That is, the 1:2 ratio scheme has better uniformity of the Gamma shift change amount compared to the standard curve gamma 2.2 in the low, medium, and high gray scales, which means that the 1:2 ratio scheme has better balance in the low, medium, and high gray scales without mutation and has a better effect on improving color shift. Therefore, in the present disclosure, the ratio of the area of the opening region HO of the bright pixel region H to the area of the opening region LO of the dark pixel region L can be set to 1:1.8 - 1:2.3, preferably 1:2.
[0056] In some embodiments, the lower the voltage of the discharge line 103, the more dark pixel leakage, the greater the difference in the light and dark pressure difference, the lower the transmittance (Tr%), and the greater the contrast difference between the dark pixel region L and the bright pixel region H, which has a certain impact on the color shift. Based on this, the present disclosure can also improve the color shift by adjusting the voltage of the discharge line 103. Optionally, the voltage of the discharge line 103 in the present disclosure is greater than or equal to 7V and less than or equal to 10V, such as 7V, 8V, 9V, 10V, etc.
[0057] Figure 15 The gamma curve graph shows the ratio of the channel width - length ratio of the second transistor TFT2 to the channel width - length ratio of the first transistor TFT1 is 50%, the gamma curve graph with the ratio of the area of the opening region HO of the bright pixel region H to the area of the opening region LO of the dark pixel L being 1:2, and the gamma curve graph with the ratio of the channel width - length ratio of the second transistor TFT2 to the channel width - length ratio of the first transistor TFT1 being 35%, the ratio of the area of the opening region HO of the bright pixel region H to the area of the opening region LO of the dark pixel L being 1:2, and the voltage of the discharge line 103 being 8V. The closer to the standard curve gamma 2.2, the less obvious the color shift; and the smoother the curve transition (that is, the curve has no obvious upward or downward convexity), the better the balance of the low, medium, and high gray scales without mutation, and the better the color shift improvement effect. From Figure 15It can be seen that the ratio of the channel width-to-length ratio of the second transistor TFT2 to that of the first transistor TFT1 is 35%, the ratio of the area of the opening region HO of the bright pixel region H to the area of the opening region LO of the dark pixel L is 1:2, and the gamma curve with the voltage of the discharge line 103 being 8V is the smoothest, the balance of low, medium, and high gray levels is the best, there are no mutations, and the color deviation improvement effect is the best.
[0058] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, as Figure 2 , Figure 4 , Figures 6 to 8 shown, it may further include a second pixel electrode 108 located in the bright pixel region H, and a third transistor TFT3 located between the opening region HO of the bright pixel region H and the opening region LO of the dark pixel region L; wherein, the first pole s3 of the third transistor TFT3 is multiplexed with the first pole s1 of the first transistor TFT1, the second pole d3 of the third transistor TFT3 is electrically connected to the second pixel electrode 108, for example, the second pole d3 of the third transistor TFT3 is electrically connected to the second pixel electrode 108 through a second via hole h2 penetrating through the passivation layer 106 and the planarization layer 107; optionally, the channel width-to-length ratio of the third transistor TFT3 is the same as that of the first transistor TFT1, so that the data voltage of the data line 102 is synchronously written into the first pixel electrode 104 and the second pixel electrode 108 through the first transistor TFT1 and the third transistor TFT3.
[0059] In some embodiments, in combination with Figure 4 , Figure 8 , Figure 11 and Figure 12 it can be known that the second pixel electrode 108 and the first common electrode line 105 overlap in the direction Z perpendicular to the substrate 101 to form a second storage capacitor Cst2, and the second pixel electrode 108 can overlap with the common electrode 201 of the counter substrate 002 in the direction Z perpendicular to the substrate 101 to form a second liquid crystal capacitor Cpx2; wherein, the second storage capacitor Cst2 is used to charge the second pixel electrode 108 during the period when the first gate line 103 is closed and maintain the voltage (equivalent to the data voltage) on the second pixel electrode 108 until the next frame update, and the second liquid crystal capacitor Cpx2 is used to cause the liquid crystal molecules corresponding to the bright pixel region H to deflect under the electric field in the second liquid crystal capacitor Cpx2 during the period when the first gate line 103 is open to achieve bright display.
[0060] In some embodiments, as Figures 2 to 8As shown, a gate line 109 extending along the second direction X is provided between the bright pixel region H and the dark pixel region L. The gate line 109 can be electrically connected to the gate g1 of the first transistor TFT1, the gate g2 of the second transistor TFT2, and the gate g3 of the third transistor TFT3. For example, a part of the gate line 109 is multiplexed as the gate g1 of the first transistor TFT1 and the gate g3 of the third transistor TFT3, and another part of the gate line 109 is multiplexed as the gate g2 of the second transistor TFT2. In this way, the same gate line 109 can be used to control the first transistor TFT1 to charge the first pixel electrode 104, control the third transistor TFT3 to charge the second pixel electrode 108, and control the second transistor TFT2 to discharge the first pixel electrode 104. Compared with the solution of using three gate lines to control three transistors respectively, it is beneficial to save the wiring space, reduce the gap of the opening area, and improve the pixel aperture ratio.
[0061] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, as Figure 3 、 Figure 4 、 Figure 8 and Figure 11 shown, it may further include a second common electrode line 110 that is in the same layer as the first pixel electrode 104 and the second pixel electrode 108 and is disposed at intervals. The second common electrode line 110 extends along the second direction X between the bright pixel region H and the dark pixel region L; the gate line 109 includes two edge portions 901 extending along the second direction X and an intermediate portion 902 located between the edge portions 901. At least a part of the edge portion 901 is located within the projection of the second common electrode line 110 on the substrate 101, and the projection of the intermediate portion 902 on the substrate 101 does not overlap with the projection of the second common electrode line 110 on the substrate 101.
[0062] By providing a second common electrode line 110 that is on the same layer and made of the same material as the first pixel electrode 104 and the second pixel electrode 108, and ensuring that the orthographic projection of the second common electrode line 110 on the substrate 101 overlaps with the orthographic projection of the edge portion 401 of the gate line 109 on the substrate 101, the signal of the gate line 109 can be effectively shielded by the second common electrode line 110. In this way, the first pixel electrode 104 and the second pixel electrode 108 will no longer be interfered with by the gate line 109, but rather a coupling capacitance will be formed between them and the second common electrode line 110. The voltage of the second common electrode line 110 is about 7V (e.g., 8V), and the voltage difference between the second common electrode line 110 and the first pixel electrode 104 and the second pixel electrode 108 is about 0 - 7V, which is less than the voltage difference of 16V - 30V between the gate line 109 and the first pixel electrode 104 and the second pixel electrode 108 in the related art. Thus, the phenomenon of abnormal rotation and lighting of liquid crystal molecules caused by the formation of an electric field due to a large voltage difference can be effectively improved. Moreover, the orthographic projection of the middle portion 902 on the substrate 101 does not overlap with the orthographic projection of the second common electrode line 110 on the substrate 101, which is beneficial to reducing the load of the gate line 109.
[0063] In some embodiments, considering the alignment deviation and process fluctuations, to ensure that the second common electrode line 105 can completely shield the edge portion 901 of the gate line 109, as Figure 11 shown, the overhang distance D1 of the second common electrode line 105 relative to the edge portion 901 can be set to 1.5μm - 2.5μm (e.g., 2μm), and the width w1 of the edge portion 901 is 2μm - 3μm (e.g., 2.5μm).
[0064] In some embodiments, as Figure 2 and Figure 8 shown, it may further include a third common electrode line 111 extending along the first direction Y between the sub - pixel regions SPX. The third common electrode line 111 can be integrally provided with the second common electrode line 110 so that the second common electrode line 110 and the third common electrode line 111 form a mesh structure to improve the uniformity of the common voltage signal.
[0065] Optionally, as Figure 2 、 Figure 6 and Figure 8 shown, the orthographic projection of the data line 102 on the substrate 101 is located within the orthographic projection of the third common electrode line 111 on the substrate 101 to use the third common electrode line 111 to shield the signal of the data line 103 and avoid interference between adjacent and uncoupled data lines 102 and the first pixel electrode 104 or the second pixel electrode 108. See Figure 9It can be known that since the line width w2 of the data line 102 is relatively narrow (for example, 8 μm), even if the third common electrode line 111 completely covers the data line 102, it will not cause a large load on the data line 102. However, the third common electrode line 111 completely covering the data line 102 can ensure that its line width w3 is greater than or equal to the line width w2 of the data line 102, reducing the risk of breakage of the third common electrode line 111. Optionally, the unilateral overhanging distance D2 of the third common electrode line 111 relative to the data line 102 is 1.5 μm to 2.5 μm (for example, 2 μm).
[0066] In some embodiments, as Figures 3 to 8 shown, the positive projection of the edge portion 901 of the gate line 109 on the substrate 101 overlaps with the positive projections of the first electrodes (such as s1, s2, s3) and the second electrodes (such as d1, d2, d3) of the transistors (such as TFT1, TFT2, TFT3) on the substrate 101, and at least part of the overlapping region does not overlap with the positive projection of the second common electrode line 110 on the substrate 101.
[0067] In the process of manufacturing the array substrate, the first electrodes (such as s1, s2, s3) and the second electrodes (such as d1, d2, d3) of the transistors (such as TFT1, TFT2, TFT3) may be short-circuited with the gate line 109 through conductive particles (particles) remaining in the process. At this time, the present disclosure can cut off the first electrodes (such as s1, s2, s3) and the second electrodes (such as d1, d2, d3) at the short-circuit position to solve the problem of short-circuit between the first electrodes (such as s1, s2, s3) and the second electrodes (such as d1, d2, d3) and the gate line 109; and, the present disclosure can perform cross-layer lap joint at the position where the overlapping region does not overlap with the second common electrode line 110 by using the material of the layer where the second common electrode line 110 is located to connect the cut-off first electrodes (such as s1, s2, s3) and the second electrodes (such as d1, d2, d3), ensuring the normal operation of the transistors (such as TFT1, TFT2, TFT3).
[0068] In some embodiments, as Figure 2 、 Figure 4 and Figure 10 shown, the first common electrode line 105 can be set on the same layer and made of the same material as the gate line 109, and to prevent the first common electrode line 105 from being short-circuited with the gate line 109, the distance D3 between the two can be set to 4.5 μm to 7.5 μm (for example, 6 μm). As Figure 9As shown, to reduce the parasitic capacitance between the data line 102 and the first common electrode line 105, the distance D4 between the data line 102 and the first common electrode line 105 can be set to 1.5 μm to 2.5 μm (for example, 2 μm). Additionally, to prevent the second common electrode line 110 from being short-circuited with the second pixel electrode 108, the distance D5 between the second pixel electrode 108 and the second common electrode line 110 can be set to 4 μm to 6 μm (for example, 5 μm). Similarly, the distance between the first pixel electrode 104 and the second common electrode line 110 can be set to 4 μm to 6 μm (for example, 5 μm) to prevent the second common electrode line 110 from being short-circuited with the first pixel electrode 104.
[0069] In some embodiments, as Figure 4 , Figure 7 and Figure 8 shown, two second common electrode lines 110 overlapping with two edge portions 901 of the same gate line 109 are connected by a connection line 112. Optionally, the second common electrode line 110 and the connection line 112 are integrally formed, and the connection line 112 is electrically connected to the first common electrode line 105 through a third via hole h3 penetrating through the planarization layer 107, the passivation layer 106, and the gate insulating layer 113. And to ensure good connection, the first common electrode line 105 is widened at the connection position, and the connection line 112 is electrically connected to the first common electrode line 105 at the wider end portion. By electrically connecting the second common electrode line 110 with the first common electrode line 105, the overall resistance between the second common electrode line 110 and the first common electrode line 105 can be made smaller, reducing the voltage drop (IR drop) of the common voltage signal and improving the uniformity and anti-interference ability of the common voltage signal.
[0070] In some embodiments, according to different materials, the transistors of the present disclosure can be P-type transistors or N-type transistors; according to different gate positions, the transistors of the present disclosure can be bottom-gate transistors, top-gate transistors, or double-gate transistors, etc., which are not limited herein. Additionally, in the present disclosure, the first pole of the transistor can be the source electrode and the second pole can be the drain electrode, or the first pole of the transistor can be the drain electrode and the second pole can be the source electrode; the active layer material of the transistor can be amorphous silicon (a-Si), polycrystalline silicon (poly), oxide (Oxide, such as indium gallium zinc oxide IGZO), etc.
[0071] Based on the same inventive concept, embodiments of the present disclosure provide a display panel, as Figures 9 to 11As shown, the above-mentioned array substrate 001 provided by the embodiments of the present disclosure, and the opposing substrate 002 disposed opposite to the array substrate 001. Among them, the common electrode 201 of the opposing substrate 002 can be disposed over the entire surface within the display area AA and cover the entire sub-pixel area SPX; the opposing substrate 002 may further include a substrate 202, a black matrix 203 located between the substrate 202 and the common electrode 201, and a color resist 204 located between the black matrix 203 and the common electrode 201. Optionally, the black matrix 203 exposes the opening area HO of the bright pixel area H and the opening area LO of the dark pixel area L, and the black matrix 203 covers the data line 102, the gate line 109, the first common electrode line 105, the second common electrode line 110, the third common electrode line 111, the connection line 112, the first transistor TFT1, the second transistor TFT2, and the third transistor TFT3.
[0072] In some embodiments, the display panel provided by the embodiments of the present disclosure may further include a liquid crystal layer between the array substrate and the opposing substrate, a first polarizer on the side of the array substrate away from the opposing substrate, and a second polarizer on the side of the opposing substrate away from the array substrate, and the polarization direction of the first polarizer is perpendicular to the polarization direction of the second polarizer. Other essential components in the display panel should be understood by those of ordinary skill in the art and will not be elaborated here, nor should it be regarded as a limitation to the present disclosure.
[0073] Based on the same inventive concept, the embodiments of the present disclosure provide a display device, including the above-mentioned display panel provided by the embodiments of the present disclosure, and a backlight module located on the light incident side of the display panel. The backlight module can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include a light bar, a reflective sheet, a light guide plate, a diffusion sheet, a prism group, etc. stacked, and the light bar is located on one side in the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffusion plate, a brightness enhancement film, etc. stacked on the light-emitting side of the matrix light source, and the reflective sheet includes openings disposed opposite to the positions of the lamp beads in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).
[0074] Micro light-emitting diodes in the sub-millimeter or even micron range are self-emitting devices like organic light-emitting diodes (OLEDs). Similar to OLEDs, they have a series of advantages such as high brightness, ultra-low latency, and extremely large viewing angles. Moreover, since inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life compared to OLEDs that emit light based on organic substances. When micro light-emitting diodes are used as backlights, they can achieve a more precise dynamic backlight effect, effectively improving the screen brightness and contrast while also solving the glare phenomenon caused by traditional dynamic backlights between bright and dark areas of the screen, thus optimizing the visual experience.
[0075] In some embodiments, the above-mentioned display device provided by the embodiments of the present disclosure may be: a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smart watch, fitness wristband, personal digital assistant, or any other product or component with a display function. Optionally, the display device provided by the present disclosure includes, but is not limited to: a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip, etc. Optionally, the control chip is a central processing unit, digital signal processor, system-on-chip (SoC), etc. For example, the control chip may further include a memory and a power module, etc., and realizes the power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may further include a hardware circuit and computer-executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays, as well as existing semiconductors such as logic chips and transistors, or other discrete components; the hardware circuit may also include a field programmable gate array, programmable array logic, programmable logic device, etc. Additionally, those skilled in the art can understand that the above structure does not constitute a limitation on the above-mentioned display device provided by the embodiments of the present disclosure. In other words, the above-mentioned display device provided by the embodiments of the present disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.
[0076] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.
[0077] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these changes and modifications.
Claims
1. An array substrate, characterized in that, Comprising: A substrate, the substrate including a plurality of sub-pixel regions arranged in an array, the sub-pixel regions including a light pixel region and a dark pixel region arranged side by side in a first direction; Data lines extending in the first direction between the sub-pixel regions; Discharge lines extending in the first direction; A first pixel electrode located within the dark pixel region; A first transistor located between the opening region of the light pixel region and the opening region of the dark pixel region, a first pole of the first transistor being electrically connected to the data line, and a second pole of the first transistor being electrically connected to the first pixel electrode; A second transistor located between the opening region of the light pixel region and the opening region of the dark pixel region, a first pole of the second transistor being multiplexed with the second pole of the first transistor, and a second pole of the second transistor being electrically connected to the discharge line; the channel width-to-length ratio of the second transistor is 30% to 40% of the channel width-to-length ratio of the first transistor.
2. The array substrate according to claim 1, characterized in that, The ratio of the area of the opening region of the light pixel region to the area of the opening region of the dark pixel is greater than or equal to 1:2.3 and less than or equal to 1:1.
8.
3. The array substrate according to claim 1, characterized in that, The voltage of the discharge line is greater than or equal to 7V and less than or equal to 10V.
4. The array substrate according to any one of claims 1 to 3, characterized in that, Further comprising a second pixel electrode located in the light pixel region, and a third transistor located between the opening region of the light pixel region and the opening region of the dark pixel region; wherein, A first pole of the third transistor is multiplexed with the first pole of the first transistor, a second pole of the third transistor is electrically connected to the second pixel electrode, and the channel width-to-length ratio of the third transistor is the same as the channel width-to-length ratio of the first transistor.
5. The array substrate according to claim 4, characterized in that, Further comprising gate lines extending in a second direction between the light pixel region and the dark pixel region, the gate lines being electrically connected to the gate of the first transistor, the gate of the second transistor, and the gate of the third transistor.
6. The array substrate according to claim 5, characterized in that, Further comprising a common electrode line that is in the same layer as and spaced apart from the first pixel electrode and the second pixel electrode, the common electrode line extending in the second direction between the light pixel region and the dark pixel region; The gate lines include two edge portions extending in the second direction and an intermediate portion located between the edge portions, at least a partial region of the edge portions is orthogonally projected onto the substrate within the orthographic projection of the common electrode line on the substrate, and the orthographic projection of the intermediate portion on the substrate does not overlap with the orthographic projection of the common electrode line on the substrate.
7. A display panel, characterized in that, Comprising the array substrate according to any one of claims 1 to 6, and an opposing substrate disposed opposite to the array substrate.
8. The display panel according to claim 7, characterized in that, The opposing substrate includes a black matrix, and the orthographic projection of the black matrix on the substrate does not overlap with the opening region of the sub-pixel region.
9. The display panel according to claim 8, characterized in that, Further comprising a common electrode layer located on a side of the black matrix facing the array substrate, and the orthographic projection of the common electrode layer on the substrate covers the plurality of sub-pixel regions.
10. A display device, characterized in that, Comprising the display panel according to any one of claims 7 to 9.