Small PLC instruction architecture optimization method and system

Abstract

The invention discloses a small PLC instruction architecture optimization method and system, and the method comprises the steps: a compiler module generates a parameter general table according to a parameter table of a user, and generates an instruction code which can be recognized by an address conversion module according to an instruction character string of an original instruction, finding a relative address of an instruction parameter in a data space according to a parameter character string and a parameter general table of the original instruction; the address conversion module stores a mapping table of a relative address and an absolute address of data, stores a mapping table of an instruction code and an instruction function address, replaces the instruction code of a target instruction generated by the compiler module with an instruction function absolute address, replaces a parameter relative address with a parameter absolute address, and stores the parameter absolute address; the processed multiple target instructions are combined into an executable file; and the instruction executor module executes each instruction according to the instruction function absolute address and the parameter absolute address in the executable file. The execution efficiency can be improved, the task scanning period can be shortened, and the method is easy to implement.

Description

Technical Field

[0001] The present invention relates to a PLC motion control method, and particularly to an optimization method and system for the instruction architecture of a small PLC. Background Art

[0002] Currently, commonly used PLCs (Programmable Logic Controllers) are basically divided into several types such as large-scale machines, medium-scale machines, and small-scale machines. With the increasing intensity of market competition, end customers have higher and higher performance requirements for medium and small PLCs. Currently, the instruction technical solutions of medium and small PLCs are mainly divided into two types:

[0003] One is the interpreted execution type. The PLC instructions written by users will be compiled into intermediate code and interpreted and executed in the address conversion module of the PLC. The instruction execution efficiency of this solution is relatively low, and the corresponding PLC performance is also relatively weak. For example, the iconic product FX series of Mitsubishi, and small PLCs of Inovance such as H5U and Easy series, etc.;

[0004] The other is the compiled execution type. The PLC instructions written by users are compiled into binary code and can be directly recognized by the CPU of the PLC without an interpreter. The instruction execution efficiency of this solution is high, and the corresponding PLC performance is also stronger. A typical example is the codesys platform. After the LD language or ST language is compiled into a binary file, it is downloaded to the runtime (runtime kernel). In addition, some controllers of Zhengyun Motion Company support embedding a C language compilation module in the RTSys IDE software, which can compile C language into binary code; The PLCs of XINJE also support the embedded C language programming function, which is a similar solution.

[0005] The following problems still exist in these two architectures: First, in the interpretive execution instruction scheme, there is a problem of low execution efficiency. Taking Mitsubishi's FX series as an example, when the LD instruction is executed in the address conversion module, it is first necessary to judge the instruction code, find the instruction execution function, and find the corresponding parameter address according to the parameter type value and index parameter value in the instruction code. Finally, the instruction function itself is executed. There are many logical operations and function call operations involved, which ultimately lead to low instruction execution efficiency. Moreover, the compiled execution instruction scheme has a problem of high development difficulty. A feasible solution is to compile several programming languages (such as LD, ST, and SFC, etc.) of the IEC-61131 standard into C language, and then use the C language compiler to compile the.c file into a binary file. The process of compiling languages such as LD, ST, and SFC into C language requires high software capabilities of developers and a long development cycle. Many small and medium-sized companies do not have the ability to promote such projects. The current mainstream compiled execution solution is the editor, compiler, and runtime kernel provided by codesys. The product (RTSys IDE) of Zhengyun Company provides an editing interface and compiler for other high-level languages such as C language, which can compile high-level languages such as C language into binary files and download them to the controller for operation. However, at present, only a small number of field engineers in the industrial control industry have the development ability of high-level languages such as C language, and the promotion of this solution is relatively limited. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide an optimization method and system for a small PLC instruction architecture that can improve the execution efficiency of an interpretive execution type PLC, reduce the task scan cycle, and is easy to implement, aiming at the deficiencies of the prior art.

[0007] To solve the above technical problems, the present invention adopts the following technical solutions.

[0008] An optimization method for a small PLC instruction architecture, which is implemented based on a compiler module, an address conversion module, and an instruction executor module. The method includes: the compiler module generates a total parameter table according to the user's parameter table, generates an instruction code recognizable by the address conversion module according to the instruction string of the original instruction, and finds the relative address of the instruction parameter in the data space according to the parameter string of the original instruction and the total parameter table. The combination of the instruction code and the relative address of the instruction parameter is used as the target instruction to be downloaded to the address conversion module; the address conversion module stores the mapping table of the relative address and absolute address of the data, and stores the mapping table of the instruction code and the instruction function address, and replaces the instruction code of the target instruction generated by the compiler module with the absolute address of the instruction function, and replaces the relative address of the parameter with the absolute address of the parameter. Multiple processed target instructions are merged into an executable file; the instruction executor module executes each instruction according to the absolute address of the instruction function and the absolute address of the parameter in the executable file.

[0009] Preferably, the compiler module also allocates corresponding auxiliary registers according to the index value of the instruction parameter, generates auxiliary index instructions to process index operations.

[0010] Preferably, the address conversion module and the instruction executor module run in the PLC entity.

[0011] A small PLC instruction architecture optimization system includes a compiler module, an address conversion module, and an instruction executor module. The system is used to execute the small PLC instruction architecture optimization method described above.

[0012] Preferably, the compiler module is also used to allocate corresponding auxiliary registers according to the index value of the instruction parameter, generate auxiliary index instructions to process index operations.

[0013] The small PLC instruction architecture optimization method disclosed by the present invention is based on an interpretive execution instruction scheme, optimizes the instruction code, instruction structure, and parameter storage method therein, and provides additional auxiliary registers. Auxiliary instructions are used to implement index operations. Based on this method, when an instruction is executed in the instruction executor module, it is no longer necessary to judge the instruction code, and it can directly jump to the instruction execution function. Moreover, it is no longer necessary to judge the parameter type, parameter index, etc., and directly access the parameter address, greatly reducing the logical operations and function calls during the instruction execution process, thereby achieving the purpose of optimizing the instruction execution efficiency. Compared with the prior art, the present invention is implemented based on the interpretive execution scheme, supports most PLC instructions of the current mainstream scheme, and the usage method remains basically unchanged. Under the condition that users are accustomed to the programming method of similar Mitsubishi FX series PLCs, they can seamlessly switch to the new optimization scheme without changing the programming habit. At the same time, the present invention can significantly improve the execution efficiency of the interpretive execution type PLC, reduce the task scan cycle. In addition, the present invention is an improvement based on the existing interpretive execution scheme, and the implementation difficulty is relatively low. Description of the Drawings

[0014] Figure 1 is the block diagram of the compiler module in the preferred embodiment of the present invention;

[0015] Figure 2 is the index block diagram of the compiler module in the preferred embodiment of the present invention;

[0016] Figure 3 is the block diagram of the address conversion module in the preferred embodiment of the present invention;

[0017] Figure 4 is the block diagram of the instruction executor module in the preferred embodiment of the present invention. Detailed Embodiments

[0018] The present invention will be described in more detail below with reference to the accompanying drawings and embodiments.

[0019] The present invention discloses a method for optimizing the instruction architecture of a small PLC, which is implemented based on a compiler module, an address conversion module, and an instruction executor module. The method includes: Figures 1 to 4 As shown, the method is implemented based on a compiler module, an address conversion module, and an instruction executor module. The method includes:

[0020] The compiler module generates a total parameter table according to the user's parameter table, generates an instruction code recognizable by the address conversion module according to the instruction string of the original instruction, and finds the relative address of the instruction parameter in the data space according to the parameter string of the original instruction and the total parameter table. The combination of the instruction code and the relative address of the instruction parameter is used as the target instruction to be downloaded to the address conversion module;

[0021] The address conversion module stores the mapping table of the relative address and the absolute address of the data, and stores the mapping table of the instruction code and the instruction function address. It replaces the instruction code of the target instruction generated by the compiler module with the absolute address of the instruction function, and replaces the relative address of the parameter with the absolute address of the parameter. Multiple processed target instructions are merged into an executable file;

[0022] The instruction executor module executes each instruction according to the absolute address of the instruction function and the absolute address of the parameter in the executable file. The address conversion module and the instruction executor module run in the PLC entity.

[0023] Further, the compiler module also allocates corresponding auxiliary registers according to the index value of the instruction parameter, and generates auxiliary index instructions to process index operations.

[0024] In the above method, based on the interpreted execution instruction scheme, the instruction code, instruction structure, and parameter storage method are optimized, and additional auxiliary registers are provided. The index operation is implemented using auxiliary instructions. Based on this method, when the instruction is executed in the instruction executor module, it is not necessary to judge the instruction code anymore, and it can directly jump to the instruction execution function. Moreover, it is not necessary to judge the parameter type, parameter index, etc. anymore, and it can directly access the parameter address, which greatly reduces the logical operations and function calls during the instruction execution process, so as to achieve the purpose of optimizing the instruction execution efficiency. Compared with the prior art, the present invention is implemented based on the interpreted execution scheme, supports most of the PLC instructions of the current mainstream scheme, and the usage method remains basically unchanged. Under the condition that users are accustomed to the programming method of similar Mitsubishi FX series PLCs, they can seamlessly switch to the new optimized scheme without changing the programming habit. At the same time, the present invention can significantly improve the execution efficiency of the interpreted execution type PLC, reduce the task scan cycle. In addition, the present invention is an improvement based on the existing interpreted execution scheme, and the implementation difficulty is relatively low.

[0025] To implement the above method, the present invention proposes a small PLC instruction architecture optimization system, which includes a compiler module, an address conversion module, and an instruction executor module. The system is used to execute the small PLC instruction architecture optimization method described above.

[0026] Specifically, the system of the present invention includes a compiler module, an address conversion module, and an instruction executor module, where:

[0027] The compiler module is used to: generate a total parameter table according to the user's parameter table; generate an instruction code recognizable by the address conversion module according to the instruction string of the original instruction; find the relative address of the instruction parameter in the data space according to the parameter string of the original instruction and the total parameter table; combine the instruction code and the relative address of the instruction parameter, which is the target instruction to be downloaded to the address conversion module; in addition, the compiler module is also used to allocate corresponding auxiliary registers according to the index value of the instruction parameter and generate auxiliary index instructions to process index operations.

[0028] The address conversion module is used to: save the mapping table of the relative address and absolute address of the data, and also save the mapping table of the instruction code and instruction function address, replace the instruction code in the target instruction generated by the compiler module with the absolute address of the instruction function, replace the relative address of the parameter with the absolute address of the parameter, and merge multiple processed target instructions into an executable file;

[0029] The instruction executor module is used to: execute each instruction according to the absolute address of the instruction function and the absolute address of the parameter in the executable file. Here, the instruction executor module actually runs in the PLC entity.

[0030] In a preferred embodiment of the present invention:

[0031] As Figure 1 shown, the compiler inputs the source instruction string, finds the corresponding instruction code in the instruction mapping table, and in the data table, finds the relative address of the variable corresponding to the parameter string (the relative address has been allocated), so as to obtain the target instruction composed of the instruction code and the relative address of the parameter;

[0032] As Figure 2 shown, if there is an index in the parameter of the source instruction string, according to the syntax rules, generate the corresponding auxiliary instruction, put the indexed parameter value into the auxiliary register, and then generate the target instruction, and replace the relative address of the parameter in the target instruction with the address of the auxiliary register, so as to achieve the purpose of indexing;

[0033] When the source instruction is converted into a target instruction, they are assembled together to form an intermediate file, and the parameter addresses in the intermediate file are all relative addresses, which can be decoupled from the execution environment of the instruction executor module;

[0034] AsFigure 3 As shown, before the intermediate file is downloaded to the instruction executor module for execution, it needs to be processed by the address translation module first. The instruction codes in it are replaced with the absolute addresses of the instruction functions, and the relative addresses of the parameters are replaced with the absolute addresses of the parameters. The resulting executable file is the file that can finally be recognized by the instruction executor module;

[0035] As Figure 4 shown, the instruction executor module executes each instruction according to the instruction function address and the absolute parameter address. After the instruction is executed, it is judged whether it is the last instruction. If not, it jumps to the next instruction to continue execution, otherwise the instruction executor module ends.

[0036] It should be noted that while the present invention increases the instruction execution efficiency, it will increase the memory space occupied by the same instructions. However, with the increase in the available memory space of current embedded processors, the slight increase in the instruction space will not cause a great impact.

[0037] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, or improvements made within the technical scope of the present invention shall be included within the scope protected by the present invention.

Claims

1. A small PLC instruction architecture optimization method, characterized in that: The method is implemented based on a compiler module, an address conversion module and an instruction executor module, and the method includes: The compiler module generates a parameter summary table according to the user's parameter table, generates an instruction code recognizable by the address conversion module according to the instruction string of the original instruction, finds the relative address of the instruction parameter in the data space according to the parameter string of the original instruction and the parameter summary table, and uses the combination of the instruction code and the relative address of the instruction parameter as the target instruction to be downloaded to the address conversion module; The address conversion module stores a mapping table of relative addresses and absolute addresses of data, as well as a mapping table of instruction codes and instruction function addresses, and replaces the instruction code of the target instruction generated by the compiler module with the instruction function absolute address, and replaces the parameter relative address with the parameter absolute address, and merges the processed multiple target instructions into an executable file; The instruction executor module executes each instruction according to the instruction function absolute address and parameter absolute address in the executable file.

2. The small PLC instruction architecture optimization method according to claim 1, characterized in that: The compiler module also allocates corresponding auxiliary registers according to the displacement value of the instruction parameter and generates auxiliary displacement instructions to process the displacement operation.

3. The small PLC instruction architecture optimization method according to claim 1, characterized in that: The address conversion module and the instruction executor module run in the PLC entity.

4. A small PLC instruction architecture optimization system, characterized in that: The system comprises a compiler module, an address conversion module and an instruction executor module, and the system is used to execute the small PLC instruction architecture optimization method described in claim 1.

5. The small PLC instruction architecture optimization system according to claim 4, characterized in that: The compiler module is also used to allocate corresponding auxiliary registers according to the displacement value of the instruction parameter, and generate auxiliary displacement instructions to process the displacement operation.

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