Memory control device and method, electronic equipment, medium and chip

Abstract

The invention provides a memory control device which comprises an address logic judgment circuit connected with a bus so as to receive a memory access instruction sent by the bus, and the address logic judgment circuit is used for judging a required bandwidth memory based on the memory access instruction; the memory interleaving circuit is connected with the address logic judgment circuit so as to determine a called memory interleaving scheme according to a judgment result of the address logic judgment circuit, and the memory interleaving circuit is connected with the physical layer channel so as to be connected with the memory channel through the physical layer channel; the memory channel configuration register is connected with the memory interleaving circuit so as to determine a called memory channel, and the memory channel configuration register is connected with the physical layer channel so as to supply power to the memory channel, so that power-on and power-off of a single memory channel are realized; the unused memory channel is powered off, the memory power consumption is reduced, and the overall device performance is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of memory control, and in particular, to a memory control device, method, electronic device, medium, and chip. Background Art

[0002] Low Power Double Data Rate (LPDDR) is a memory communication standard commonly used in mobile phones, in-vehicle infotainment systems, and other consumer electronics terminals. It has now evolved to the LPDDR5 version. Compared with the LPDDR4 version, the data transfer rate of LPDDR5 has been significantly improved, from 4266 Mbps to 5500 Mbps, and the bandwidth has increased from 34 GB / s to 44 GB / s. The performance has been improved by 50% compared with the previous generation, and the power consumption has been reduced by 20%. LPDDR5 can effectively increase the total memory bandwidth to meet the data transfer and processing requirements of high-speed processors. However, some multi-channel DDR technologies cannot achieve interleaved memory allocation between channels, and some can only parallel fixed-size channels, resulting in limited access bandwidth. Therefore, how to obtain a technical solution for efficient memory interleaving remains a problem to be solved in the prior art. Summary of the Invention

[0003] The present disclosure provides a memory control device, method, electronic device, medium, and chip to solve the problems in the related art.

[0004] In a first aspect embodiment of the present disclosure, a memory control device is proposed. The memory control device includes: an address logic judgment circuit connected to a bus to receive a memory access instruction sent by the bus. The address logic judgment circuit is configured to judge the memory with the required bandwidth based on the memory access instruction; a memory interleaving circuit connected to the address logic judgment circuit to determine the called memory interleaving scheme through the judgment result of the address logic judgment circuit. The memory interleaving scheme includes a full-channel storage area interleaving scheme and / or a non-full-channel storage area interleaving scheme. The memory interleaving circuit is connected to a physical layer channel to be connected to a memory channel through the physical layer channel; a memory channel configuration register connected to the memory interleaving circuit to determine the called memory channel. The memory channel configuration register is connected to the physical layer channel to supply power to the memory channel.

[0005] In some embodiments, based on the called memory interleaving scheme, the memory interleaving circuit is further configured to determine the called memory channel.

[0006] In some embodiments, the memory channel configuration register is configured with a 1-bit enable bit and a 31-bit channel configuration bit. The enable bit is used to enable the memory configuration register, and the channel configuration bit is used to supply power to the memory channel.

[0007] A second aspect embodiment of the present disclosure provides a memory control method, the method comprising: receiving a memory access instruction from a bus; determining a memory with required bandwidth based on the memory access instruction; determining a memory interleaving scheme to be invoked based on the memory with required bandwidth; and powering the invoked memory channels based on the memory interleaving scheme.

[0008] In some embodiments, determining a memory interleaving scheme to be invoked based on the memory with required bandwidth includes: when the memory with required bandwidth is high-bandwidth memory, determining to invoke a full-channel storage area interleaving scheme; when the memory with required bandwidth is low-bandwidth memory, determining to invoke a non-full-channel storage area interleaving scheme.

[0009] In some embodiments, powering the invoked memory channels based on the memory interleaving scheme includes: when the memory interleaving scheme is a full-channel storage area interleaving scheme, powering all memory channels; or when the memory interleaving scheme is a non-full-channel storage area interleaving scheme, enabling a memory channel configuration register to power the memory channels corresponding to the non-full-channel storage area interleaving scheme.

[0010] A third aspect of the present disclosure provides a memory control virtual device, comprising: a receiving unit configured to receive a memory access instruction from a bus; a first processing unit configured to determine a memory with required bandwidth based on the memory access instruction; a second processing unit configured to determine a memory interleaving scheme to be invoked based on the memory with required bandwidth; and a third processing unit configured to power the invoked memory channels based on the memory interleaving scheme.

[0011] A fourth aspect embodiment of the present disclosure provides an electronic device, the device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions, when executed by the at least one processor, enable the at least one processor to execute the method described in the second aspect above.

[0012] A fifth aspect embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the method described in the second aspect of the present disclosure.

[0013] A sixth aspect embodiment of the present disclosure provides a chip, the chip comprising at least one processor and a communication interface; the communication interface is configured to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method described in the second aspect of the present disclosure through logic circuits or by executing code instructions.

[0014] In summary, the memory control device proposed according to the present disclosure includes: an address logic judgment circuit, which is connected to the bus to receive a memory access instruction sent by the bus. The address logic judgment circuit is used to judge the memory with the required bandwidth based on the memory access instruction; a memory interleaving circuit, which is connected to the address logic judgment circuit to determine the called memory interleaving scheme through the judgment result of the address logic judgment circuit. The memory interleaving circuit is connected to the physical layer channel to be connected to the memory channel through the physical layer channel; a memory channel configuration register, which is connected to the memory interleaving circuit to determine the called memory channel. The memory channel configuration register is connected to the physical layer channel to supply power to the memory channel, so as to realize the power-on and power-off of a single memory channel. When adopting a non-full-channel storage area interleaving scheme, the unused memory channel can be powered off, reducing the memory power consumption and improving the overall device performance.

[0015] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure, and do not constitute an improper limitation to the present disclosure.

[0017] Figure 1 It is an application scenario diagram of a memory control method provided by an embodiment of the present disclosure;

[0018] Figure 2 It is an application scenario diagram of a memory control method provided by an embodiment of the present disclosure;

[0019] Figure 3 It is a schematic structural diagram of another memory control device provided by an embodiment of the present disclosure;

[0020] Figure 4 It is a schematic structural diagram of a memory channel configuration register provided by an embodiment of the present disclosure;

[0021] Figure 5 It is a schematic flowchart of a memory control method provided by an embodiment of the present disclosure;

[0022] Figure 6 It is a flow example diagram of a memory control method provided by an embodiment of the present disclosure;

[0023] Figure 7 It is a schematic diagram of a memory control virtual device provided by an embodiment of the present disclosure;

[0024] Figure 8 It is a schematic structural diagram of a communication device provided by an embodiment of the present disclosure;

[0025] Figure 9 A structural schematic diagram of a chip provided by an embodiment of the present disclosure. Detailed implementation manners

[0026] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the embodiments of the present disclosure as detailed in the appended claims.

[0027] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present disclosure. The singular forms "a" and "the" used in the embodiments of the present disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0028] It should be understood that although the terms first, second, third, etc. may be used in the embodiments of the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the embodiments of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "when" used herein may be interpreted as "when" or "when" or "in response to determining".

[0029] For ease of understanding, the background technology related to this application is first introduced.

[0030] With the development of emulator technology, memory control technology has been widely applied to multiple scenarios. However, in the related technology, a fixed interleaving scheme is usually adopted, that is, the memory chips are regarded as a partition, and all memory channels in the entire memory chips are directly accessed without distinguishing the service types; or the memory is divided into two storage areas, where the large storage area is used for heavy-load service memory control, and the small storage area is used for normal memory control. When the application initiates memory control, the memory controller converts the access command to the address range of the corresponding area according to the bandwidth size requirement of the access command. In both of the above two methods, when only some memory channels in the memory area are called to meet the service requirements, the remaining memory channels that do not need to be called are still powered on, resulting in unnecessary power consumption.

[0031] Therefore, to solve the problems existing in the related art, the present disclosure proposes a memory control circuit. By connecting a memory channel configuration register to a memory interleaving circuit, the memory channel configuration register determines the memory channel to be called, so as to achieve power supply only to the required memory channels and power down the memory channels that do not need to be called, improving the flexibility of memory channel calls and reducing the overall power consumption of the memory channels at the same time.

[0032] Before introducing the detailed solution of the present disclosure, the scenario to which the solution of the present disclosure is applied will be described first.

[0033] As Figure 1 shown in the heterogeneous workload scenario of a mobile system on chip (SOC), devices such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and a neural network processing unit (NPU) can send memory access instructions to a memory controller through a data bus when performing actions such as operating systems, multimedia processing, camera and image processing, display, and graphics rendering. The memory controller then performs dynamic memory interleaving on the access commands according to the different requirements of the above heterogeneous load services for memory bandwidth to select the corresponding memory storage area. At the same time, the memory controller dynamically controls the power on and off of the memory channels according to the memory interleaving scheme to achieve the purpose of reducing power consumption.

[0034] It can be understood that the description of the embodiments of the present disclosure is to more clearly illustrate the technical solutions of the embodiments of the present disclosure, and does not constitute a limitation on the memory control circuit, method, system, device, and chip proposed in the embodiments of the present disclosure. Those of ordinary skill in the art know that with the evolution of the system architecture and the emergence of new service scenarios, the technical solutions proposed in the embodiments of the present disclosure are equally applicable to similar technical problems.

[0035] Figure 2 This is a schematic structural diagram of a memory control device provided by an embodiment of the present disclosure.

[0036] In some embodiments, the memory control device includes: an address logic judgment circuit, a memory interleaving circuit, and a memory channel configuration register. Optionally, the memory control device may further include a physical layer channel.

[0037] In some embodiments, the address logic judgment circuit is connected to the bus to receive the memory access instruction sent by the bus.

[0038] In some embodiments, the address logic judgment circuit is used to judge the memory with required bandwidth based on a memory access instruction.

[0039] In some embodiments, the memory access instruction may carry the service type of the service that calls the memory channel, so that the address logic judgment circuit can judge the memory with required bandwidth for the service according to the service type in the memory access instruction.

[0040] In some embodiments, the memory interleaving circuit is connected to the address logic judgment circuit to determine the called memory interleaving scheme based on the judgment result of the address logic judgment circuit.

[0041] In some embodiments, the memory interleaving scheme includes a full-channel storage area interleaving scheme and / or a non-full-channel storage area interleaving scheme.

[0042] In some embodiments, the non-full-channel storage area interleaving scheme may be a half-channel storage area interleaving scheme, but is not limited thereto, and may also be a storage area interleaving scheme with other numbers of channels. The present disclosure does not limit this. Taking the full-channel storage area interleaving scheme as a 4-memory-channel interleaving scheme as an example, the non-full-channel storage area interleaving scheme may be a 3-memory-channel interleaving scheme or a 2-memory-channel interleaving scheme.

[0043] In some embodiments, the memory interleaving circuit may also determine the called memory channels based on the called memory interleaving scheme. In other words, when the memory interleaving circuit determines that the called memory interleaving scheme is a non-full-channel memory interleaving scheme, the memory interleaving circuit may call the memory channel selection algorithm stored in itself to determine the called memory channels.

[0044] For example: when the service type carried in the memory access instruction sent by the bus to the address logic judgment circuit is a game, the address logic judgment circuit can judge that the memory with required bandwidth is high-bandwidth memory according to the game service type, and send the judgment result to the memory interleaving circuit; when the memory interleaving circuit receives the judgment result of high-bandwidth memory sent by the address logic judgment circuit, it can determine that the called memory interleaving scheme is a full-channel storage area interleaving scheme to call all memory channels to provide the required bandwidth memory for the game service.

[0045] In some embodiments, memory channels can be stored separately by multiple storage areas. Then, the memory interleaving circuit can call the same or different memory interleaving schemes to separately call the memory channels in different storage areas. Taking the example where the memory channels are stored separately by two storage areas, with 4 memory channels stored in the first storage area and 4 memory channels stored in the second storage area, if the memory interleaving circuit determines that 6 memory channels need to be called through the judgment result sent by the address logic judgment circuit, the memory interleaving circuit can determine to call the full-channel storage area interleaving scheme in the first storage area to call 4 memory channels in the first storage area, and call the non-full-channel storage area interleaving scheme in the second area to call 2 of the 4 memory channels in the second storage area, thereby providing appropriate bandwidth memory and avoiding waste of memory resources.

[0046] In some embodiments, for example Figure 3 As shown, the memory interleaving circuit is connected to the physical layer channel to be connected to the memory channel through the physical layer channel, so as to realize the call of the required memory channel. In other words, the physical layer channel is used to realize the connection between the memory interleaving circuit and the memory channel, where the memory channel is, for example, CH0-CHn as shown in the figure.

[0047] In an alternative embodiment, the physical layer channel can be a memory channel slot inserted on the memory interleaving circuit, and the memory channel is inserted into this slot to realize the connection between the memory interleaving circuit and the memory channel.

[0048] In some embodiments, the memory channel configuration register is connected to the memory interleaving circuit to determine the called memory channel, so as to supply power only to the called memory channel to reduce the power consumption of the device.

[0049] In some embodiments, for example Figure 3 As shown, the memory channel configuration register is connected to the physical layer channel to supply power to the called memory channel.

[0050] In some embodiments, the memory channel configuration register is configured with an enable bit and a channel configuration bit. As Figure 4 shown, the enable bit of the memory channel configuration register can occupy 1 bit of storage space, and the channel configuration bit can occupy 31 bits of storage space, but it is not limited thereto. The present disclosure does not limit the storage space occupied by the enable bit and the channel configuration bit.

[0051] In some embodiments, the enable bit is used to enable the memory configuration register, and the channel configuration bit is used to supply power to the memory channel.

[0052] Specifically, when the memory channel configuration register determines that the memory channels to be invoked are all memory channels (i.e., the memory interleaving circuit determines to invoke the full-channel storage area interleaving scheme), the enable memory channel configuration register (such as the enable bit at position 0) can be disabled to power on all memory channels; when the memory channel configuration register determines that the memory channels to be invoked are partial memory channels (i.e., the memory interleaving circuit determines to invoke a non-full-channel storage area interleaving scheme), the enable memory channel configuration register (such as the enable bit at position 1) is enabled, and at the same time, by configuring the channel configuration bits, power is supplied to the corresponding memory channels.

[0053] In some embodiments, different channel configuration bits correspond to different memory channel power supply methods. For example: Taking a full-channel with 4-channel memory and the channel configuration bit being 31 bits as an example, when the last two bits of the channel configuration bit are set to 1 and the rest are set to 0, power is supplied to memory channel #1 and memory channel #2; when the last three bits of the channel configuration bit are set to 1 and the rest are set to 0, power is supplied to memory channel #1, memory channel #2, and memory channel #3. Thus, power is supplied only to the memory channels required for services, avoiding waste of memory resources.

[0054] In summary, the memory control circuit proposed according to the present disclosure includes: an address logic judgment circuit, the address logic judgment circuit is connected to the bus to receive a memory access instruction sent by the bus, and the address logic judgment circuit is used to judge the memory with the required bandwidth based on the memory access instruction; a memory interleaving circuit, the memory interleaving circuit is connected to the address logic judgment circuit to determine the invoked memory interleaving scheme through the judgment result of the address logic judgment circuit, and the memory interleaving circuit is connected to the physical layer channel to be connected to the memory channel through the physical layer channel; a memory channel configuration register, the memory channel configuration register is connected to the memory interleaving circuit to determine the invoked memory channels, and the memory channel configuration register is connected to the physical layer channel to supply power to the memory channels, thereby realizing power on and off of a single memory channel, and being able to power off the unused memory channels when adopting a non-full-channel storage area interleaving scheme, reducing memory power consumption and improving the performance of the overall device.

[0055] Figure 5 The flowchart of a memory control method proposed by an embodiment of the present disclosure is as Figure 5 shown, based on Figures 1-4 the embodiment shown, further explained, the method includes steps 501-504.

[0056] Step 501, receive a memory access instruction from the bus.

[0057] In some embodiments, the memory control device can receive a memory access instruction from the bus to determine the memory with the required bandwidth corresponding to the access instruction.

[0058] Step 502: Determine the memory with the required bandwidth based on the memory access instruction.

[0059] In some embodiments, the memory control device may determine the memory with the required bandwidth based on the memory access instruction, and then determine the memory interleaving scheme to be invoked.

[0060] Specifically, the memory access instruction may carry the service type of the service invoking the memory channel, and the memory control device may determine the memory with the required bandwidth based on the service type in the memory access instruction.

[0061] Step 503: Determine the memory interleaving scheme to be invoked based on the memory with the required bandwidth.

[0062] In some embodiments, the memory control device may determine the memory interleaving scheme to be invoked based on the memory with the required bandwidth.

[0063] Specifically, when the memory with the required bandwidth is high-bandwidth memory, determine to invoke the full-channel storage area interleaving scheme; when the memory with the required bandwidth is low-bandwidth memory, determine to invoke the non-full-channel storage area interleaving scheme.

[0064] In some embodiments, when it is determined that the memory interleaving scheme to be invoked is the non-full-channel memory interleaving scheme, the memory control device may invoke the memory channel selection algorithm stored in itself to determine the memory channels to be invoked.

[0065] Step 504: Power on the memory channels to be invoked based on the memory interleaving scheme.

[0066] In some embodiments, when the memory interleaving scheme is the full-channel storage area interleaving scheme, power on all memory channels.

[0067] In some embodiments, when the memory interleaving scheme is the non-full-channel storage area interleaving scheme, enable the memory channel configuration register to power on the memory channels corresponding to the non-full-channel storage area interleaving scheme.

[0068] In the present disclosure, the principles of steps 501 - 504 are the same as those of the Figures 1-4 embodiments shown, and reference may be made to the Figures 1-4 relevant descriptions therein, which will not be elaborated here.

[0069] In summary, the memory control method proposed according to the present disclosure includes: receiving a memory access instruction from a bus; determining the memory with the required bandwidth based on the memory access instruction; determining the memory interleaving scheme to be invoked based on the memory with the required bandwidth; and powering on the memory channels to be invoked based on the memory interleaving scheme, thereby realizing the power-on and power-off of a single memory channel, being able to power off the unused memory channels when adopting the non-full-channel storage area interleaving scheme, reducing the memory power consumption, and improving the overall device performance.

[0070] The following is an exemplary description of the memory control method proposed in the present disclosure.

[0071] Figure 6 As shown in the flowchart example of a memory control method proposed in an embodiment of the present disclosure, Figure 6 the method includes the following steps:

[0072] 1. Initiate a memory access.

[0073] In some embodiments, an application executing a service can initiate a memory access to request a memory channel for the executed service.

[0074] 2. Determine whether it is a high memory bandwidth scenario.

[0075] In some embodiments, a memory control device can judge the access instruction to determine whether the service requesting memory allocation requires high memory bandwidth.

[0076] 3. If high memory bandwidth is required, access storage area 1.

[0077] In some embodiments, storage area 1 is the memory channel storage area corresponding to the full-channel storage area interleaving scheme.

[0078] In some embodiments, when the memory control device determines that high memory bandwidth is required, it selects to use the full-channel storage area interleaving scheme to access storage area 1.

[0079] 4. If high memory bandwidth is not required, access storage area 0.

[0080] In some embodiments, storage area 0 is the memory channel storage area corresponding to the non-full-channel storage area interleaving scheme.

[0081] In some embodiments, when the memory control device determines that high memory bandwidth is not required, it selects to use the non-full-channel storage area interleaving scheme to access storage area 0.

[0082] In some embodiments, the memory control device can also call the memory channel selection algorithm stored in itself to determine the specific memory channel to be called in the interleaving scheme.

[0083] 5. Enable the channel configuration register.

[0084] In some embodiments, enable the memory channel configuration register (for example, set the enable position to 1), and at the same time, power the called memory channel by configuring the channel configuration bits.

[0085] 6. Allocate memory.

[0086] In some embodiments, by powering the memory channel, memory is allocated for the service requesting memory allocation.

[0087] Therefore, the present solution has the following beneficial effects:

[0088] 1. The memory interleaving circuit accesses the judgment result sent by the address logic judgment circuit, and invokes the stored full-channel storage area interleaving scheme and / or non-full-channel storage area interleaving scheme to achieve reasonable invocation of memory channels and reduce waste of memory resources.

[0089] 2. By setting the memory channel configuration register, power-on and power-off of a single memory channel can be realized. When the non-full-channel storage area interleaving scheme is adopted, the unused memory channels can be powered off to reduce memory power consumption, which is convenient for power-on and power-off of memory channels when the services invoking the memory channels change.

[0090] Figure 7 FIG. 12 is a schematic structural diagram of a memory control virtual device 700 provided by an embodiment of the present disclosure. The memory control virtual device includes:

[0091] A receiving unit 710, configured to receive a memory access instruction of a bus; a first processing unit 720, configured to determine a memory with a required bandwidth based on the memory access instruction; a second processing unit 730, configured to determine an invoked memory interleaving scheme based on the memory with the required bandwidth; and a third processing unit 740, configured to supply power to the invoked memory channels based on the memory interleaving scheme.

[0092] In some embodiments, the second processing unit 730 is further configured to determine to invoke a full-channel storage area interleaving scheme when the memory with the required bandwidth is a high-bandwidth memory, and determine to invoke a non-full-channel storage area interleaving scheme when the memory with the required bandwidth is a low-bandwidth memory.

[0093] In some embodiments, the third processing unit 740 is further configured to supply power to all memory channels when the memory interleaving scheme is a full-channel storage area interleaving scheme; or enable the memory channel configuration register to supply power to the memory channels corresponding to the non-full-channel storage area interleaving scheme when the memory interleaving scheme is a non-full-channel storage area interleaving scheme.

[0094] In summary, the memory control virtual device proposed according to the present disclosure includes: a receiving unit, configured to receive a memory access instruction of a bus; a first processing unit, configured to determine a memory with a required bandwidth based on the memory access instruction; a second processing unit, configured to determine an invoked memory interleaving scheme based on the memory with the required bandwidth; and a third processing unit, configured to supply power to the invoked memory channels based on the memory interleaving scheme, so as to realize power-on and power-off of a single memory channel, be able to power off the unused memory channels when the non-full-channel storage area interleaving scheme is adopted, reduce memory power consumption, and improve the performance of the overall device.

[0095] Since the device provided by the embodiments of the present disclosure corresponds to the methods provided by the above several embodiments, the implementation manners of the methods are also applicable to the device provided by this embodiment and will not be described in detail in this embodiment.

[0096] In the above embodiments provided by the present application, the methods and devices provided by the embodiments of the present application are introduced. To implement each function in the methods provided by the above embodiments of the present application, a communication device may include a hardware structure, software modules, and implement the above functions in the form of a hardware structure, software modules, or a combination of a hardware structure and software modules. A certain function among the above functions may be executed in the form of a hardware structure, software modules, or a combination of a hardware structure and software modules.

[0097] In the above embodiments provided by the present application, the methods and devices provided by the embodiments of the present application are introduced. To implement each function in the methods provided by the above embodiments of the present application, an electronic device may include a hardware structure, software modules, and implement the above functions in the form of a hardware structure, software modules, or a combination of a hardware structure and software modules. A certain function among the above functions may be executed in the form of a hardware structure, software modules, or a combination of a hardware structure and software modules.

[0098] Figure 8 FIG. is a block diagram of an electronic device 800 for implementing the above memory control method according to an exemplary embodiment. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0099] Referring to Figure 8 , the electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0100] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, telephone calls, data communication, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above methods. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0101] The memory 804 is configured to store various types of data to support the operation of the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, and the like. The memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0102] The power supply component 806 provides power to various components of the electronic device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 800.

[0103] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can not only sense the boundaries of touch or swipe actions but also detect the duration and pressure associated with the touch or swipe operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.

[0104] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 further includes a speaker for outputting audio signals.

[0105] The I / O interface 812 provides an interface between the processing component 802 and a peripheral interface module, and the peripheral interface module can be a keyboard, a click wheel, buttons, etc. These buttons can include, but are not limited to: a home button, a volume button, a power-on button, and a lock button.

[0106] The sensor assembly 814 includes one or more sensors for providing an assessment of various aspects of the state of the electronic device 800. For example, the sensor assembly 814 can detect the on / off state of the electronic device 800, the relative positioning of components, such as the display and keypad of the electronic device 800. The sensor assembly 814 can also detect a change in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and a change in the temperature of the electronic device 800. The sensor assembly 814 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 can also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0107] The communication component 816 is configured to facilitate communication between the electronic device 800 and other devices in a wired or wireless manner. The electronic device 800 can access a wireless network based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (New Radio), or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0108] In an exemplary embodiment, the electronic device 800 can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above-described methods.

[0109] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, which can be executed by a processor 820 of the electronic device 800 to complete the above-described methods. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0110] Embodiments of the present disclosure also propose a chip, such as Figure 9The chip shown includes at least one processor 901 and a communication interface 902. Among them, the communication interface 902 is used to receive signals input to the chip or signals output from the chip, and the processor 901 communicates with the communication interface 902 and implements the method described in the above embodiments of the present disclosure through logic circuits or by executing code instructions.

[0111] Optionally, the chip further includes a memory 903, and the memory 903 is used to store necessary computer programs and data.

[0112] An embodiment of the present disclosure also proposes a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the method described in the above embodiments of the present disclosure.

[0113] Those skilled in the art can also understand that the various illustrative logical blocks and steps listed in the embodiments of the present application can be implemented by electronic hardware, computer software, or a combination of both. Whether such a function is implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art can use various methods to implement the functions for each specific application, but such implementation should not be construed as exceeding the scope protected by the embodiments of the present application.

[0114] It should be noted that the terms "first", "second", etc. in the description, claims, and drawings of the present disclosure are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described here can be implemented in an order different from those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0115] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0116] Any process or method description represented in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present invention includes additional implementations where functions may be executed not in the order shown or discussed, including in a substantially simultaneous manner according to the functions involved or in a reverse order, which should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0117] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing a logical function and can be embodied specifically in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processing module, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device. As used in this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of the computer-readable medium include the following: an electrical connection (control method) having one or more wirings, a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable medium on which a program can be printed, as the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpretation, or otherwise processing as appropriate, and then stored in a computer memory.

[0118] It should be understood that various parts of the embodiments of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0119] Those of ordinary skill in the art can understand that all or part of the steps carried out in implementing the above-described embodiment methods can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes one or a combination of the steps of the method embodiment.

[0120] In addition, each functional unit in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disc, etc.

[0121] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A memory control device, characterized in that, The device includes: An address logic judgment circuit, which is connected to the bus to receive a memory access instruction sent by the bus. The address logic judgment circuit is used to judge the memory with the required bandwidth based on the memory access instruction; A memory interleaving circuit, which is connected to the address logic judgment circuit to determine the called memory interleaving scheme through the judgment result of the address logic judgment circuit. Among them, the memory interleaving scheme includes a full-channel storage area interleaving scheme and / or a non-full-channel storage area interleaving scheme. The memory interleaving circuit is connected to the physical layer channel to be connected to the memory channel through the physical layer channel; A memory channel configuration register, which is connected to the memory interleaving circuit to determine the called memory channel. The memory channel configuration register is connected to the physical layer channel to supply power to the memory channel; 2. The memory control device according to claim 1, characterized in that, Based on the called memory interleaving scheme, the memory interleaving circuit is further used to determine the called memory channel; 3. The memory control device according to claim 1, characterized in that, The memory channel configuration register is configured with a 1-bit enable bit and a 31-bit channel configuration bit. The enable bit is used to enable the memory configuration register, and the channel configuration bit is used to supply power to the memory channel; 4. A memory control method, characterized in that, The method includes: Receiving a memory access instruction from the bus; Determining the memory with the required bandwidth based on the memory access instruction; Determining the called memory interleaving scheme based on the memory with the required bandwidth; Supplying power to the called memory channel based on the memory interleaving scheme; 5. The method according to claim 4, characterized in that, The determining the called memory interleaving scheme based on the memory with the required bandwidth includes: When the memory with the required bandwidth is high-bandwidth memory, determining to call the full-channel storage area interleaving scheme; When the memory with the required bandwidth is low-bandwidth memory, determining to call the non-full-channel storage area interleaving scheme; 6. The method according to claim 4, characterized in that, The supplying power to the called memory channel based on the memory interleaving scheme includes: When the memory interleaving scheme is the full-channel storage area interleaving scheme, supplying power to all memory channels; or, When the memory interleaving scheme is the non-full-channel storage area interleaving scheme, enabling the memory channel configuration register to supply power to the memory channel corresponding to the non-full-channel storage area interleaving scheme; 7. A memory control virtual device, characterized in that, Includes: A receiving unit, which is used to receive a memory access instruction from the bus; A first processing unit, which is used to determine the memory with the required bandwidth based on the memory access instruction; A second processing unit, which is used to determine the called memory interleaving scheme based on the memory with the required bandwidth; A third processing unit, which is used to supply power to the called memory channel based on the memory interleaving scheme; 8. An electronic device, characterized in that, Includes: At least one processor; And A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor. The instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 4-6; 9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the method according to claims 4-6.

10. A chip, characterized in that, Comprising at least one processor and a communication interface; the communication interface is used for receiving signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method as described in claims 4-6 through logic circuits or by executing code instructions.

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