Method for solving conflict between BMC and CPU accessing RTC

Abstract

The invention discloses a method for solving conflict between a baseboard management controller (BMC) and a central processing unit (CPU) accessing a real-time clock (RTC), which relates to the technical field of computer firmware, and comprises the following steps: before a central processing unit (CPU) of a server accesses the RTC, a first signal representing that the CPU accesses the RTC is transmitted to the BMC through a complex programmable logic device (CPLD); the information indicating that the RTC is occupied by the CPU is notified to the BMC; after the CPU transmits the first signal representing that the CPU accesses the RTC to the BMC, the CPU accesses the RTC through a hardware link between the CPU and the RTC, wherein the hardware link is controlled by the BMC and the CPLD to be communicated with the CPU and the RTC; and before accessing the RTC, the BMC determines that the CPU is accessing the RTC according to the first signal representing that the CPU accesses the RTC, and delays accessing the RTC when determining that the CPU accesses the RTC so as to eliminate access conflicts. In the invention, the BMC and the CPU do not access the RTC at the same time, and time abnormity caused by access conflicts can be eliminated.

Description

Technical Field

[0001] The present invention relates to the technical field of computer firmware, and in particular to a method for resolving the conflict between BMC and CPU accessing RTC. Background Art

[0002] The server baseboard management controller (BMC) can monitor and manage the server.

[0003] The Basic Input Ouput System (BIOS) is a set of programs embedded in a ROM chip on the computer motherboard. It is the underlying software running in the CPU. It stores the computer's most important basic input and output programs, self-test programs after power-on, and system startup programs. Its main function is to provide the computer with the lowest-level and most direct hardware settings and controls.

[0004] Real-Time Clock (RTC) is an integrated circuit, usually called a clock chip. It provides accurate real-time time or provides an accurate time reference for electronic systems. Most real-time clock chips use a high-precision crystal oscillator as the clock source.

[0005] The BMC and CPU in the server can obtain the accurate current time, i.e., the real-time time, by accessing the RTC. The CPU accesses the RTC in two stages, namely, the BIOS operation stage and the operating system (OS) operation stage. Obviously, since the BMC and CPU in the server share one RTC, once the BMC and CPU access the RTC at the same time, a conflict will occur, resulting in abnormal BMC and CPU time, which in turn affects the normal operation of the system services. The CPU time mainly refers to the BIOS time and the OS time. Specifically, the BMC and the CPU share one RTC. In the BIOS operation stage (including the boot BIOS operation process and the stage of entering the BIOS configuration interface), when the BIOS accesses the RTC, there is a conflict with the BMC accessing the RTC, resulting in abnormal BIOS time. In the time configuration function of the BIOS configuration interface, the BIOS time is abnormal and cannot communicate normally with the RTC; in the OS operation stage, when the OS accesses the RTC, there is a conflict with the BMC accessing the RTC, resulting in the OS not being able to access the RTC normally, and the OS operation time is abnormal, which in turn affects the normal operation of the system services. Summary of the invention

[0006] The invention provides a method for resolving the conflict between BMC and CPU accessing RTC, aiming to overcome the problem of conflict between BMC and CPU accessing RTC.

[0007] The present invention provides a method for solving the access conflict of RTC between BMC and CPU. The method includes: before the CPU of the server accesses the RTC, the first signal representing the CPU accessing the RTC is transmitted to the BMC through the CPLD, so as to notify the BMC of the information that the RTC is occupied by the CPU; after the CPU transmits the first signal representing the CPU accessing the RTC to the BMC, the CPU accesses the RTC through the hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD; before the BMC accesses the RTC, according to the first signal representing the CPU accessing the RTC, it is determined that the CPU is accessing the RTC, and when it is determined that the CPU accesses the RTC, the access to the RTC is delayed to eliminate the access conflict.

[0008] Preferably, the first signal representing the CPU accessing the RTC is the first-level signal of the A1 pin of the CPU; correspondingly, before the central processing unit CPU accesses the real-time clock RTC, transmitting the first signal representing the CPU accessing the RTC to the baseboard management controller BMC through the complex programmable logic device CPLD is specifically: before the CPU accesses the RTC, setting the level signal of the A1 pin of the CPU to the first-level signal, and transmitting the first-level signal of the A1 pin of the CPU to the B1 pin of the BMC through the CPLD.

[0009] Preferably, after the CPU transmits the first signal representing the CPU accessing the RTC to the BMC, the CPU accessing the RTC through the hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD includes: after the CPU transmits the first signal representing the CPU accessing the RTC to the BMC, reading the register X of the CPLD for controlling the access to the RTC; when the value of the register X of the CPLD for controlling the access to the RTC is the value representing the CPU accessing the RTC, the CPU directly accesses the RTC through the hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD; when the value of the register X of the CPLD for controlling the access to the RTC is the value representing the BMC accessing the RTC, the CPU accesses the RTC through the hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD after delaying for a preset time.

[0010] Preferably, the method further includes: after the CPU accesses the RTC through the hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD, the CPU transmits, through the CPLD, a second signal indicating the BMC's access to the RTC to the BMC, so as to notify the BMC of the information that the RTC can be accessed by the BMC; the BMC accesses the RTC through the hardware link between the BMC and the RTC controlled and connected by the BMC and the CPLD according to the second signal indicating the BMC's access to the RTC.

[0011] Preferably, the second signal indicating the BMC's access to the RTC is the second-level signal of the A1 pin of the CPU; correspondingly, after the CPU accesses the RTC through the hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD, the specific operation of the CPU transmitting, through the CPLD, the second signal indicating the BMC's access to the RTC to the BMC is: after the CPU accesses the RTC through the hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD, the CPU sets the level signal of the A1 pin to the second-level signal, and transmits the second-level signal of the A1 pin of the CPU to the B1 pin of the BMC through the CPLD.

[0012] Preferably, the BMC accessing the RTC through the hardware link between the BMC and the RTC controlled and connected by the BMC and the CPLD according to the second signal indicating the BMC's access to the RTC includes: the BMC modifies the value of register X of the CPLD for controlling the access to the RTC to a value indicating the BMC's access to the RTC according to the second-level signal of the B1 pin, so as to control the connection of the hardware link between the BMC and the RTC; the BMC accesses the RTC through the connected hardware link between the BMC and the RTC; after the BMC finishes accessing the RTC, the BMC modifies the value of register X of the CPLD for controlling the access to the RTC to a value indicating the CPU's access to the RTC, so as to control the connection of the hardware link between the CPU and the RTC.

[0013] Preferably, the method further includes: the CPLD monitors whether the BMC fails; if the CPLD monitors that the BMC fails, the CPLD controls the connection of the hardware link between the CPU and the RTC by modifying the value of register X of the CPLD for controlling the access to the RTC to a value indicating the CPU's access to the RTC.

[0014] Preferably, the method further includes: when the value of register X of the CPLD for controlling access to the RTC represents the value of the CPU accessing the RTC, the CPU directly accesses the RTC through the hardware link between the CPU and the RTC controlled by the CPLD.

[0015] Preferably, the method further includes: before the BMC accesses the RTC, determining whether the server has been powered on; when the BMC determines that the server has not been powered on, directly accessing the RTC through the hardware link between the BMC and the RTC controlled by the BMC and the CPLD; after accessing the RTC, modifying the value of register X of the CPLD for controlling access to the RTC to represent the value of the CPU accessing the RTC, so as to control the connection of the hardware link between the CPU and the RTC.

[0016] Preferably, when the server is powered on for the first time, the BMC accesses the RTC through the hardware link between the connected BMC and the RTC according to the second signal representing the BMC accessing the RTC default on its B1 pin and the value representing the BMC accessing the RTC default in register X of the CPLD for controlling access to the RTC. After the BMC finishes accessing the RTC, it modifies the value of register X of the CPLD for controlling access to the RTC to represent the value of the CPU accessing the RTC.

[0017] A method for solving the conflict between the BMC and the CPU accessing the RTC provided by the present invention. The CPU transmits a first signal representing the CPU accessing the RTC to the BMC through the CPLD, and notifies the BMC of the information that the RTC is accessed by the CPU, so that the BMC will not access the RTC simultaneously when the CPU accesses the RTC, eliminating the time anomaly caused by the access conflict between the two. Description of the Drawings

[0018] Figure 1 is a flowchart for solving the conflict between the BMC and the CPU accessing the RTC provided by the present invention;

[0019] Figure 2 is a hardware schematic diagram provided by an embodiment of the present invention;

[0020] Figure 3 is a flowchart of the BMC accessing the RTC provided by an embodiment of the present invention;

[0021] Figure 4 is a flowchart of the CPU accessing the RTC provided by an embodiment of the present invention. Detailed Embodiments

[0022] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0023] The present invention discloses a method for solving the conflict between the BMC and the CPU accessing the RTC. Before the CPU of the server accesses the RTC, the CPLD transmits a first signal representing the CPU accessing the RTC to the BMC, so as to notify the BMC of the information that the RTC is occupied by the CPU; then, the CPU accesses the RTC through a hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD; before the BMC accesses the RTC, according to the first signal representing the CPU accessing the RTC, it determines that the CPU is accessing the RTC, and when it determines that the CPU accesses the RTC, it delays accessing the RTC. In this way, the BMC and the CPU do not access the RTC at the same time, thereby eliminating the time anomaly caused by the access conflict.

[0024] See Figure 1 , a method for solving the conflict between the BMC and the CPU accessing the RTC may include the following steps:

[0025] Step S101: Before the CPU of the server accesses the RTC, the CPLD transmits a first signal representing the CPU accessing the RTC to the BMC, so as to notify the BMC of the information that the RTC is occupied by the CPU.

[0026] The first signal representing the CPU accessing the RTC is the first level signal of the A1 pin of the CPU. The first level signal can be a low level signal or a high level signal. Correspondingly, step S101 may be specifically: before the CPU accesses the RTC, it sets the level signal of the A1 pin of the CPU to the first level signal, and transmits the first level signal of the A1 pin of the CPU to the B1 pin of the BMC through the CPLD, that is, the information that the RTC is occupied by the CPU is transmitted through the transmission of the first level signal.

[0027] Step S102: After the CPU transmits the first signal representing the CPU accessing the RTC to the BMC, it accesses the RTC through a hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD.

[0028] The step S102 may include: after the CPU sends the first signal indicating the CPU's access to the RTC to the BMC, the CPU reads the register X of the CPLD for controlling the access to the RTC, and according to the value of the register X of the CPLD for controlling the access to the RTC, directly accesses the RTC through the hardware link between the CPU and the RTC controlled by the CPLD or accesses the RTC through the hardware link between the CPU and the RTC controlled by the CPLD after delaying for a preset time, so as to avoid the CPU accessing the RTC when the BMC accesses the RTC. Specifically, when the value of the register X of the CPLD for controlling the access to the RTC is a value indicating the CPU's access to the RTC, for example, the value is 0, the CPU directly accesses the RTC through the hardware link between the CPU and the RTC controlled by the BMC and the CPLD; when the value of the register X of the CPLD for controlling the access to the RTC is a value indicating the BMC's access to the RTC, for example, the value is the default value 1, the CPU accesses the RTC through the hardware link between the CPU and the RTC controlled by the BMC and the CPLD after delaying for a preset time. In this way, when the CPU needs to access the RTC, enough time (i.e., the preset time) can be reserved for the current BMC system with time setting requirements, ensuring that the BMC obtains the real-time time from the RTC, thereby guaranteeing the reliability of the BMC system. After the BMC accesses the RTC, the CPU obtains the real-time time from the RTC, avoiding abnormal BIOS time and OS time, and thus ensuring the normal communication between the BIOS and the RTC and the normal operation of time-related services in the OS.

[0029] Step S103: Before accessing the RTC, the BMC determines that the CPU is accessing the RTC according to the first signal indicating the CPU's access to the RTC, and delays accessing the RTC when it determines that the CPU is accessing the RTC, so as to eliminate access conflicts.

[0030] The step S103 may be specifically: before accessing the RTC, the BMC determines that the CPU is accessing the RTC according to the first-level signal of the B1 pin of the BMC, and then delays accessing the RTC, avoiding the BMC accessing the RTC when the CPU accesses the RTC.

[0031] Further, the method may further include: after performing the step S102, that is, after the CPU accesses the RTC through the hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD, the CPU transmits, through the CPLD, a second signal indicating the BMC's access to the RTC to the BMC, so as to notify the BMC of the information that the RTC can be accessed by the BMC; the BMC accesses the RTC through the hardware link between the BMC and the RTC controlled and connected by the BMC and the CPLD according to the second signal indicating the BMC's access to the RTC.

[0032] Wherein, the second signal indicating the BMC's access to the RTC is the second level signal of the A1 pin of the CPU, and the second level signal is different from the first level signal. That is, if the first level signal uses a low level signal, then the second level signal uses a high level signal; conversely, if the first level signal uses a high level signal, then the second level signal uses a low level signal, so that the BMC can distinguish the two level signals and execute different processing programs according to the two level signals. Correspondingly, after the CPU accesses the RTC through the hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD, the CPU transmitting, through the CPLD, the second signal indicating the BMC's access to the RTC to the BMC may be specifically: after the CPU accesses the RTC through the hardware link between the CPU and the RTC controlled and connected by the CPLD, the CPU sets the level signal of the A1 pin to the second level signal, and transmits, through the CPLD, the second level signal of the A1 pin of the CPU to the B1 pin of the BMC, that is, the information that the RTC can be accessed by the BMC is transmitted through the transmission of the second level signal.

[0033] Wherein, the BMC accessing the RTC through the hardware link between the BMC and the RTC controlled and connected by the BMC and the CPLD according to the second signal indicating the BMC's access to the RTC may include: the BMC modifies the value of register X of the CPLD for controlling access to the RTC to a value indicating the BMC's access to the RTC according to the second level signal of the B1 pin, so as to control the connection of the hardware link between the BMC and the RTC; the BMC accesses the RTC through the connected hardware link between the BMC and the RTC; after the BMC finishes accessing the RTC, the BMC modifies the value of register X of the CPLD for controlling access to the RTC to a value indicating the CPU's access to the RTC, so as to control the connection of the hardware link between the CPU and the RTC.

[0034] From the steps of the BMC accessing the RTC, it can be seen that in the foregoing steps, the value representing the BMC accessing the RTC is modified by the BMC when it needs to access the RTC and the level signal of its B1 pin is the second level signal, and the value representing the CPU accessing the RTC is modified by the BMC when the level signal of its B1 pin is the second level signal and the access to the RTC has been completed. The values of the two are different. For example, the former value adopts the default value 1, and the latter value adopts 0.

[0035] In addition, in the prior art, generally, the BMC controls the CPU's access permission to the RTC. When the BMC switches the permission to access the RTC, if the BMC fails, the BMC cannot normally switch the access permission to the RTC to the CPU, which will cause the CPU (or the BIOS running in the CPU) to access the RTC abnormally, thereby affecting the time-related services in the system. In the present invention, even if the BMC fails, it will not affect the CPU's access to the RTC through the hardware link between the CPU and the RTC, improving the reliability of the service system. Specifically, the CPLD of the present invention monitors whether the BMC fails. For example, the CPLD determines whether the BMC fails by cyclically reading the watchdog register of the BMC. If it is monitored that the BMC fails, the CPLD modifies the value of register X used to control the access to the RTC to the value representing the CPU accessing the RTC, so as to control the connection of the hardware link between the CPU and the RTC. In this way, when the CPU reads that the value of register X used by the CPLD to control the access to the RTC is the value representing the CPU accessing the RTC, it can directly access the RTC through the hardware link between the CPU and the RTC controlled by the CPLD, achieving the purpose that the BMC failure does not affect the CPU's access to the RTC.

[0036] In addition, when the server is powered on and booted for the first time, the BMC accesses the RTC through the hardware link between the connected BMC and the RTC according to the second signal representing the BMC accessing the RTC default on its B1 pin and the value representing the BMC accessing the RTC default in the register X of the CPLD used to control the access to the RTC. For example, when the server is powered on and booted, the BMC detects its B1 pin. If the second signal representing the BMC accessing the RTC of this pin is detected, it means that the BMC is allowed to access the RTC; at this time, the BMC accesses the RTC through the hardware link between the BMC and the RTC according to the value representing the BMC accessing the RTC default in the CPLD register X, and after the access to the RTC is completed, the value of the register X of the CPLD used to control the access to the RTC is modified to the value 0 representing the CPU accessing the RTC.

[0037] When the server is powered on, the foregoing method is implemented to avoid access conflicts. When the server is not powered on, the BMC directly accesses the RTC through the hardware link between the BMC and the RTC controlled by the BMC and the CPLD.

[0038] In the present invention, the CPU and the BMC can access the RTC via the same control switch SWITCH. Wherein, when the BMC is normal, the BMC controls the SWITCH by modifying the value of register X of the CPLD for controlling access to the RTC. Specifically, the BMC modifies the value of register X of the CPLD for controlling access to the RTC, and the CPLD controls the SWITCH to connect the hardware link between the CPU and the RTC or the hardware link between the BMC and the RTC according to the value of register X for controlling access to the RTC. For example, when the value of register X of the CPLD modified by the BMC for controlling access to the RTC is the default value 1, the CPLD controls the SWITCH to connect the hardware link between the BMC and the RTC according to the value 1. When the value of register X of the CPLD modified by the BMC for controlling access to the RTC is 0, the CPLD controls the SWITCH to connect the hardware link between the CPU and the RTC according to the value 0. In the case of BMC failure, the CPLD controls the SWITCH by modifying the value of register X for controlling access to the RTC. For example, when the CPLD monitors a BMC failure, it modifies the value of register X for controlling access to the RTC to 0 and controls the SWITCH to connect the hardware link between the CPU and the RTC according to the value 0.

[0039] Without adding new hardware, the present invention solves the access conflict problem between the BMC and the CPU to the RTC, and the BMC and the CPU can directly obtain the real-time time by accessing the RTC, which is applicable to the BIOS operation stage including the startup BIOS operation process and the BIOS configuration interface stage, and is also applicable to the OS operation stage.

[0040] Taking the first level signal as a high level signal and the second level signal as a low level signal, which represents that the value of the BMC accessing the RTC is the default value 1 and the value of the CPU accessing the RTC is 0 as an example, combined with Figures 2 to 4 , the present invention will be described in detail.

[0041] See Figure 2 , the present invention provides a system for solving the access conflict between the BMC and the CPU to the RTC. The system includes a BMC, a CPU, a CPLD, a SWITCH, and an RTC, wherein:

[0042] 1. Implement level transparent transmission through the CPLD.

[0043] The CPU (such as the BIOS running on the CPU) pulls up a specific level signal to pin A1, and the CPLD transmits the level signal of pin A1 to pin B1 of the BMC. By changing the level of A1 of the CPU, the level of B1 of the BMC is changed, achieving the function of signal control.

[0044] For example, when the CPU accesses the RTC and pulls up the level to pin A1, the CPLD transmits the high level of pin A1 to pin B1 of the BMC, enabling the BMC to determine that the CPU accesses the RTC to obtain the real-time time based on the high level of pin B1. After the CPU finishes accessing the RTC, it pulls down the level to pin A1, and the CPLD transmits the low level of pin A1 to pin B1 of the BMC, enabling the BMC to determine that the CPU has finished accessing the RTC and can access the RTC to obtain the real-time time according to the low level of pin B1.

[0045] 2. The BMC accesses the RTC to modify the CPLD register.

[0046] The BMC controls the SWITCH by modifying the value of the CPLD register X, achieving the function of accessing the RTC hardware link.

[0047] For example, before the BMC accesses the RTC, it modifies the value of the CPLD register X to the default value 1, enabling the CPLD to control the SWITCH to connect the hardware link between the BMC and the RTC according to the value 1 of the CPLD register X. After the BMC accesses the RTC, it modifies the value of the CPLD register X to 0, enabling the CPLD to control the SWITCH to disconnect the hardware link between the BMC and the RTC according to the value 0 of the CPLD register X.

[0048] 3. The delay time for the CPU to access the RTC

[0049] When the CPU accesses the RTC and pulls up the level to pin A1, if the BMC is accessing the RTC at this time, it will cause an RTC access conflict between the CPU and the BMC, and the CPU and the BMC cannot obtain the real-time time from the RTC. Before accessing the RTC, the CPU of the present invention first reads the register X of the CPLD. When the value of the CPLD register X is 1, if the BMC is normal, it means that the BMC is accessing the RTC, and the CPU delays the access to wait for the BMC to complete the access. If the BMC fails, the CPU delays the access to wait for the CPLD to complete the switch. In actual implementation, the maximum time that the CPU needs to wait in the two cases can be taken as the delay time.

[0050] 4. The CPLD detects whether the WatchDog register is normal.

[0051] The CPLD cyclically detects the BMC watchdog to determine whether the BMC system is working properly. If the BMC is abnormal, the CPLD sets the value of register X to 1 to switch the hardware link for accessing the RTC to the CPU.

[0052] See Figure 3 , the process of the BMC accessing the RTC in the present invention may include: when the BMC needs to access the RTC, that is, before the BMC accesses the RTC, it first determines whether the server is powered on. When the server system is not powered on, the BMC does not need to determine whether the CPU occupies the RTC and can directly access the RTC. After accessing the RTC, the BMC modifies the value of the CPLD register X to 0 and then ends the process. When the server system is powered on, it first detects the level signal of the B1 pin of the BMC to determine whether the level of the B1 pin is low. If it is low, the BMC modifies the CPLD register X to the default value 1 to control and allow the BMC to access the RTC. The BMC starts to access the RTC. After accessing the RTC, the BMC modifies the value of the CPLD register X to 0, controls and allows the CPU to access the RTC, and then ends the process; if it is high, the BMC delays accessing the RTC and ends the process.

[0053] Among them, the CPU uses the CPLD to control the A1 level signal of the CPU to be transmitted to the B1 of the BMC.

[0054] From Figure 3 It can be seen that the BMC controls the CPLD register X and only executes when the BMC accesses the RTC. By default, the value of the CPLD register X is 1, allowing the BMC to access the RTC.

[0055] See Figure 4 , the process of the CPU accessing the RTC in the present invention may include:

[0056] When the CPU needs to access the RTC, that is, before the CPU accesses the RTC, the BIOS running on the CPU pulls up a specific level signal A1. At the same time as or after the BIOS pulls up A1, the BIOS reads the CPLD register X to determine whether the value of the register X is 0; if it is 0, the CPU starts to access the RTC; if it is 1, the CPU delays waiting for the BMC to finish accessing the RTC and then accesses the RTC; after the CPU accesses the RTC, the BIOS pulls down the specific level signal A1, pulls down A1, allows the BMC to access the RTC, and the process ends.

[0057] From Figure 4 It can be seen that the CPU controls the A1 level and executes when the CPU accesses the RTC. By default, the A1 level is low, allowing the BMC to access the RTC.

[0058] In addition, the CPLD is used to periodically read the watchdog register of the BMC in a loop to monitor whether the BMC is normal. If the BMC fails, the CPLD switches the value of register X that controls its access to the RTC to 0, and only allows the CPU to access it.

[0059] The method of the present invention can be applied to server products in models where the BMC and the CPU share a single RTC.

[0060] In summary, the present invention has the following advantages:

[0061] 1. The BMC and the CPU of the present invention do not access the RTC simultaneously, and can eliminate time anomalies caused by access conflicts;

[0062] 2. When the BMC sets the time, if the CPU occupies the RTC, it does not affect the BMC system's time setting, ensuring the reliability of the BMC system;

[0063] 3. When the CPU accesses the RTC, it will not be unable to access the RTC due to a BMC failure, improving the reliability of the business system.

[0064] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, this does not limit the scope of the present invention. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the present invention shall fall within the scope of the present invention.

Claims

1. A method for solving the conflict between BMC and CPU accessing RTC, characterized in that, The method includes: Before the central processing unit (CPU) of the server accesses the real-time clock (RTC), the CPU transmits a first signal representing the CPU's access to the RTC to the baseboard management controller (BMC) through a complex programmable logic device (CPLD), so as to notify the BMC of the information that the RTC is occupied by the CPU; After transmitting the first signal representing the CPU's access to the RTC to the BMC, the CPU accesses the RTC through a hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD; Before accessing the RTC, the BMC determines that the CPU is accessing the RTC according to the first signal representing the CPU's access to the RTC, and when it determines that the CPU is accessing the RTC, it delays accessing the RTC to eliminate access conflicts.

2. The method according to claim 1, characterized in that, The first signal representing the CPU's access to the RTC is the first-level signal of the A1 pin of the CPU; Correspondingly, before the central processing unit (CPU) accesses the real-time clock (RTC), transmitting the first signal representing the CPU's access to the RTC to the baseboard management controller (BMC) through a complex programmable logic device (CPLD) is specifically: before accessing the RTC, the CPU sets the level signal of the A1 pin of the CPU to the first-level signal, and transmits the first-level signal of the A1 pin of the CPU to the B1 pin of the BMC through the CPLD.

3. The method according to claim 1, characterized in that, After transmitting the first signal representing the CPU's access to the RTC to the BMC, the CPU accessing the RTC through a hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD includes: After transmitting the first signal representing the CPU's access to the RTC to the BMC, the CPU reads register X of the CPLD for controlling access to the RTC; When the value of register X of the CPLD for controlling access to the RTC is a value representing the CPU's access to the RTC, the CPU directly accesses the RTC through a hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD; When the value of register X of the CPLD for controlling access to the RTC is a value representing the BMC's access to the RTC, the CPU accesses the RTC through a hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD after delaying for a preset time.

4. The method according to claim 1, characterized in that, The method further includes: After the CPU finishes accessing the RTC through a hardware link between the CPU and the RTC controlled and connected by the BMC and the CPLD, the CPU transmits a second signal representing the BMC's access to the RTC to the BMC through the CPLD, so as to notify the BMC of the information that the RTC can be accessed by the BMC; The BMC accesses the RTC through a hardware link between the BMC and the RTC controlled and connected by the BMC and the CPLD according to the second signal representing the BMC's access to the RTC.

5. The method according to claim 4, characterized in that, The second signal indicating the BMC's access to the RTC is the second-level signal of the A1 pin of the CPU; Accordingly, after the CPU completes accessing the RTC through the hardware link between the CPU and the RTC controlled by the BMC and the CPLD, the CPU transmits the second signal indicating the BMC's access to the RTC to the BMC through the CPLD, specifically as follows: After the CPU completes accessing the RTC through the hardware link between the CPU and the RTC controlled by the BMC and the CPLD, the CPU sets the level signal of the A1 pin of the CPU to the second-level signal, and transmits the second-level signal of the A1 pin of the CPU to the B1 pin of the BMC through the CPLD.

6. The method according to claim 5, characterized in that, The BMC's access to the RTC through the hardware link between the BMC and the RTC controlled by the BMC and the CPLD according to the second signal indicating the BMC's access to the RTC includes: The BMC modifies the value of register X of the CPLD for controlling access to the RTC to the value indicating the BMC's access to the RTC according to the second-level signal of the B1 pin, so as to control the connection of the hardware link between the BMC and the RTC; The BMC accesses the RTC through the connected hardware link between the BMC and the RTC; After the BMC completes accessing the RTC, the BMC modifies the value of register X of the CPLD for controlling access to the RTC to the value indicating the CPU's access to the RTC, so as to control the connection of the hardware link between the CPU and the RTC.

7. The method according to claim 1, characterized in that, The method further includes: The CPLD monitors whether the BMC fails; If the CPLD monitors that the BMC fails, the CPLD modifies the value of register X of the CPLD for controlling access to the RTC to the value indicating the CPU's access to the RTC, so as to control the connection of the hardware link between the CPU and the RTC.

8. The method according to claim 7, characterized in that, The method further includes: When the value of register X of the CPLD for controlling access to the RTC is the value indicating the CPU's access to the RTC, the CPU directly accesses the RTC through the hardware link between the CPU and the RTC controlled by the CPLD.

9. The method according to claim 1, characterized in that, The method further includes: Before accessing the RTC, the BMC determines whether the server has been powered on; When the BMC determines that the server has not been powered on, the BMC directly accesses the RTC through the hardware link between the BMC and the RTC controlled by the BMC and the CPLD; After accessing the RTC is completed, the BMC modifies the value of register X of the CPLD for controlling access to the RTC to the value indicating the CPU's access to the RTC, so as to control the connection of the hardware link between the CPU and the RTC.

10. The method according to claim 2 or 5, characterized in that, The method further includes: When the server is powered on for the first time, the BMC accesses the RTC through the hardware link between the connected BMC and the RTC according to the second signal representing the BMC's access to the RTC default on its B1 pin and the value representing the BMC's access to the RTC default in register X of the CPLD for controlling access to the RTC. After the BMC finishes accessing the RTC, it modifies the value of register X of the CPLD for controlling access to the RTC to the value representing the CPU's access to the RTC.

Images