A control method and system for dynamic management of DDR memory addresses

Abstract

The application provides a DDR memory address dynamic management control method and system, which manages DDR cache addresses in the form of an address cache queue, and the write data is in the form of a plurality of target data blocks. The priority of each target data block is arbitrated, so that each target data block can be written into the DDR cache area through the data transmission channel corresponding to the target data block, and each target data block in the DDR cache can be read out and recycled synchronously according to the DDR address cache queue, so that the DDR address space can be fully utilized under the condition of multi-channel data transmission, and the DDR address space is maximally utilized.

Description

Technical Field

[0001] This application belongs to the field of data transmission technology, and specifically relates to a control method and system for dynamic management of DDR memory addresses. Background Technology

[0002] With the development of digital information technology, the bandwidth of information transmission is increasing, the types of data are becoming more and more diverse during transmission, and the data transmission rate is not constant, with a large number of bursts, which puts forward higher requirements for backend data processing.

[0003] During data transmission, to cope with sudden data bandwidth fluctuations and prevent information loss due to untimely information processing during data bursts, DDR (Double Data Rate SDRAM) is often used as a buffer along the data transmission path. DDR can transmit data once on the rising edge and once on the falling edge of the clock, thus transmitting data twice within one clock cycle. DDR SDRAM is widely used in computer systems as main memory, providing higher bandwidth and faster data access speeds. In computer network systems and video image processing, DDR has wide applications due to its small size, low power consumption, and high performance.

[0004] Most existing DDR memory address management methods employ fixed address range allocation. This method pre-divides the DDR address space by channel based on the number of channels and the known bandwidth of each channel before data transmission begins, ensuring each data channel has a fixed address space and performs read and write operations cyclically within its respective address space. However, this fixed address range allocation method has the following problems: 1. When not all channels are transmitting simultaneously, because the DDR address space is pre-divided by channel, it cannot be fully utilized, resulting in significant address space waste. 2. DDR fixed address range allocation is often based on the known bandwidth of each data channel; for example, data channels with larger bandwidth will receive a larger cache address space. If the bandwidth of each channel is uncertain or changes during transmission, the pre-allocated address space may be unreasonable, failing to achieve the expected data buffering effect. Summary of the Invention

[0005] To address the problems of existing address management methods that allocate fixed address ranges in DDR memory, this specification describes a control method and system for dynamic management of DDR memory addresses through one or more embodiments.

[0006] According to the first aspect, a control method for dynamic management of DDR memory addresses is provided, the method comprising:

[0007] Acquire data to be written, the data to be written includes at least one target data block, cache the initial address corresponding to each target data block to the initial address queue, the initial address is used to determine the position and data size of the target data block corresponding to the initial address in the data to be written, wherein the target data block has a corresponding target write address, the target write address is used to determine the storage location and data size of the target data block corresponding to the target write address in the DDR cache area;

[0008] Priority arbitration is performed on the initial addresses in the initial address queue to determine the transmission order of each target data block, and a corresponding data transmission channel is allocated to each target data block according to the transmission order. The target address to be written corresponding to each target data block is cached in the DDR address cache queue according to the transmission order.

[0009] Based on the target address to be written corresponding to each target data block, each target data block is written to the DDR cache area through the data transmission channel corresponding to each target data block;

[0010] When the DDR address cache queue is detected to be non-empty, the data to be read is read from the DDR cache area corresponding to the DDR address cache queue, and when the amount of data to be read reaches the amount of data of any target data block, the target address to be written of the data to be read in the address cache queue is reclaimed.

[0011] Preferably, the step of performing priority arbitration on the initial addresses of the initial address queue to determine the transmission order of each target data block, allocating a corresponding data transmission channel to each target data block according to the transmission order, and caching the target address to be written corresponding to each target data block into the DDR address cache queue according to the transmission order includes:

[0012] The data volume of each target data block is obtained based on each initial address of the initial address queue;

[0013] Based on the queue sorting of each initial address in the initial address queue, the data volume of the target data block corresponding to each initial address is summed to obtain the initial total amount of data to be judged, until the initial total amount of data to be judged reaches the second preset value.

[0014] When the total amount of the initial data to be judged reaches the second preset value, priority arbitration is performed on the initial address corresponding to each target data block.

[0015] The transmission order of each target data block is determined based on the arbitration result, and a corresponding data transmission channel is allocated to each target data block.

[0016] Based on the initial address corresponding to each target data block and the transmission order, a target write address corresponding to each target data block is generated, and the target write address is cached in the DDR address cache queue according to the transmission order.

[0017] Preferably, the first preset value is any one of 2kb, 4kb, 8kb and 16kb.

[0018] Preferably, the step of writing each target data block to the DDR cache area based on the target address to be written corresponding to each target data block, and respectively through the data transmission channel corresponding to each target data block, includes:

[0019] Write the target data block to the data transmission channel corresponding to each target data block according to the target write address corresponding to each target data block;

[0020] Based on the target write address corresponding to each target data block, determine whether the data volume of the target data block reaches a first preset value or whether the first target end identifier of the target write address corresponding to each target data block exists.

[0021] When the first target end identifier of the target write address corresponding to the target data block exists or the data volume of the target data block reaches the first preset value, each target data block is written to the DDR cache area corresponding to the target data block through the corresponding data transmission channel, and the target write address of each target data block is cached in the DDR address cache queue.

[0022] Preferably, when the first target end marker is identified, the target data block corresponding to the first target end marker is padded with data so that the data volume of the target data block reaches a second preset value.

[0023] Preferably, the data volume of the second preset value is not less than the data volume of the target data block, and the data volume of the second preset value is not greater than the upper limit of the data capacity of the data transmission channel corresponding to the target data block.

[0024] Preferably, reading the target data to be read from the DDR cache includes:

[0025] The target data to be read is read from the DDR cache and synchronously output from the DDR cache to any storage device connected to the DDR.

[0026] According to a second aspect, a control system for dynamic management of DDR memory addresses is provided, comprising: a memory, an interface center, and a main controller; the memory is used to store data read from the DDR cache, the interface center is used to provide a transmission channel for writing and reading data from the DDR cache; and the main controller is used to implement the steps of the method provided by the first aspect or any possible implementation thereof when executing the computer program.

[0027] Preferably, the DDR cache write and read data both adopt the AXI bus format, and each interface in the interface center is an AXI bus protocol interface.

[0028] According to a third aspect, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed on a computer or processor, cause the computer or processor to perform the steps of the method as described in any of the first aspects.

[0029] Beneficial Effects: 1. This invention manages DDR cache addresses using an address cache queue. The data to be written is composed of multiple target data blocks. By prioritizing and arbitrating these target data blocks, each block can be written to the DDR cache via its corresponding data transmission channel. Simultaneously, the DDR cache can be read and its addresses synchronized and reclaimed according to the DDR address cache queue. This allows for full utilization of the DDR address space in multi-channel data transmission, maximizing its utilization. 2. This invention also utilizes the target end marker of each target data block as a data padding flag. It can pad data blocks shorter than the preset burst length, ensuring that each data block can be written to or read from the DDR cache in a timely manner. Without this operation, brief pauses in read or write operations would occur during DDR cache data writing or reading. Therefore, this invention effectively improves the utilization rate and data transmission efficiency of each DDR transmission channel. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A schematic diagram of a control system for dynamic management of DDR memory addresses provided in an embodiment of this application;

[0032] Figure 2A flowchart illustrating a control method for dynamic management of DDR memory addresses provided in an embodiment of this application;

[0033] Figure 3 This is a schematic diagram of a partial channel data transmission method for a control method of dynamic management of DDR memory addresses provided in an embodiment of this application. Detailed Implementation

[0034] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0035] In the following description, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The following description provides multiple embodiments of this application, which can be substituted or combined with each other. Therefore, this application can also be considered to include all possible combinations of the same and / or different embodiments described. Thus, if one embodiment includes features A, B, and C, and another embodiment includes features B and D, then this application should also be considered to include embodiments containing one or more other possible combinations of A, B, C, and D, even if such embodiments are not explicitly described in the following text.

[0036] The following description provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the described elements without departing from the scope of this application. Various processes or components may be appropriately omitted, substituted, or added to the examples. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined into other examples.

[0037] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a control system for dynamic management of DDR memory addresses provided in an embodiment of this application. The system in this embodiment includes: a memory, an interface center, and a main controller; the memory is used to store data read from the DDR cache, the interface center is used to provide a transmission channel for writing and reading data from the DDR cache, and the main controller is used to run any of the steps in the method of this embodiment.

[0038] In the embodiments described in this specification, the applicable hardware circuits are Field-Programmable Gate Arrays (FPGAs) and Double Data Rate Synchronous Dynamic Random Access Memory (DDR), but are not limited to FPGA hardware circuits. For ease of explanation, the control system provided in this embodiment uses a system based on FPGA hardware circuits, and the main controller is a main controller based on FPGA hardware circuits. In this embodiment, the main controller includes an AIX controller and a DDR controller. The AIX controller can control the opening and closing of each interface in the interface center, and can also control the process of data transmission through the control interface. It can also cooperate with the DDR controller to arbitrate the initial address queue of data input to the DDR buffer, thereby determining the order in which data is written to the DDR buffer. The DDR controller also includes a DDR write controller and a DDR read controller, which can respectively execute the writing and reading of data in the DDR buffer according to the method provided in this embodiment.

[0039] Both DDR cache writes and reads use the AXI bus format, a commonly used bus format in FPGA hardware circuits. The interfaces in the interface center, such as... Figure 1 As shown, the first write interface, the first read interface, and the output interface are all AXI bus protocol interfaces, but the system provided in this application is not limited to hardware circuits and systems using the AXI bus protocol. Figure 1 As shown in the example, only a portion of the interfaces in the Interface Center are displayed; the number of interfaces in the Interface Center is not limited.

[0040] like Figure 2 As shown, Figure 2 This is a flowchart illustrating a control method for dynamic management of DDR memory addresses provided in an embodiment of this application. The execution entity of the method in this embodiment is the main controller.

[0041] The method in this embodiment includes:

[0042] S1. Obtain the data to be written, which includes at least one target data block. Cache the initial address corresponding to each target data block into an initial address queue. The initial address is used to determine the position and data size of the target data block corresponding to the initial address in the data to be written. The target data block has a corresponding target write address, which is used to determine the storage location and data size of the target data block corresponding to the target write address in the DDR cache area.

[0043] In the embodiments described in this specification, when the data to be written is transmitted in the FPGA circuit, it is done through the FIFO (First In First Out) logic resource inside the FPGA chip. FIFO is a storage structure used for data caching and transmission. Before the AIX controller controls the AIX interface to transmit the data to be written to the DDR cache channel, it typically uses an initial address queue to store the storage location and data size of each target data block in the data to be written. The data itself is stored in the corresponding storage unit, which is generally the FIFO logic resource inside the FPGA chip corresponding to each data to be written. The initial address queue and the DDR cache queue can also be stored in the corresponding logical resource FIFO. During the transmission of the data to be written, it is accurately read from the FIFO logic resource inside the FPGA chip corresponding to each data to be written using the corresponding initial address in the initial address queue. In this embodiment, the data to be written is composed of multiple target data blocks to improve the efficiency of dynamic management of DDR cache addresses. In actual operation, the size of the target data block can be preset according to requirements. Under the control of the DDR write controller, each target data block is written to the DDR cache through its corresponding DDR data transmission channel. Simultaneously, the DDR read controller reads each target data block from the DDR cache according to the transmission order in the DDR address cache queue corresponding to each target data block, and synchronously reclaims the addresses corresponding to each read target data block in the DDR address cache queue. This allows for full utilization of the DDR address space in multi-channel data transmission scenarios. Address reclamation is a crucial step in memory or cache operation, especially in variable partition memory management. When data transmission is complete, to ensure the normal transmission of subsequent data, the address corresponding to the data needs to be removed from the address queue (i.e., reclaimed) to store the new address.

[0044] S2. Priority arbitration is performed on the initial addresses in the initial address queue to determine the transmission order of each target data block, and a corresponding data transmission channel is allocated to each target data block according to the transmission order. The target address to be written corresponding to each target data block is cached in the DDR address cache queue according to the transmission order.

[0045] In the embodiments of this specification, priority arbitration of the initial address queue refers to the need for a mechanism to determine which request or data packet should be processed first when managing addresses accessed by multiple requests or data packets in a system or network. Addresses in memory or cache can store information such as the storage location, data size, functional flags, and data importance of the corresponding data. As an example, the priority arbitration rule in this embodiment can be determined based on the data importance of each target data block. This is based on the data importance information stored in the initial address corresponding to each target data block. The importance information can be a segment of address characters set in each initial address. When the controller controlling data transmission recognizes this address character, it can obtain the importance of the target data block corresponding to each initial address, thereby prioritizing the initial addresses in the initial address queue according to the importance of the target data blocks from high to low. This priority arbitration mechanism ensures that high-priority target data blocks can obtain service or be transmitted over the network earlier than low-priority target data blocks. Such a mechanism can guarantee the reasonable allocation of system resources and improve system efficiency.

[0046] like Figure 3 As shown, DDR can be configured with multiple data transmission channels depending on the specific version and model. Even single-channel DDR can perform read and write operations in a shared mode, that is, the channel of a single-channel DDR is split into two segments for read and write operations respectively. In this embodiment, a data transmission channel of the DDR cache is allocated for each target data block. One channel is selected from the dual channels as the write data channel and the other as the read data channel, which are used to write to or read from the corresponding target data block from the DDR cache respectively. Only one channel is allocated for a single target data block during read or write operations, thus only a single read or write operation can be performed on a single target data block.

[0047] In one possible implementation, the step of performing priority arbitration on the initial addresses of the initial address queue to determine the transmission order of each target data block, allocating a corresponding data transmission channel to each target data block according to the transmission order, and caching the target write addresses corresponding to each target data block into the DDR address cache queue according to the transmission order includes:

[0048] The data volume of each target data block is obtained based on each initial address of the initial address queue;

[0049] Based on the queue sorting of each initial address in the initial address queue, the data volume of the target data block corresponding to each initial address is summed to obtain the initial total amount of data to be judged, until the initial total amount of data to be judged reaches a first preset value.

[0050] When the total amount of the initial data to be judged reaches a first preset value, priority arbitration is performed on the initial address corresponding to each target data block.

[0051] The transmission order of each target data block is determined based on the arbitration result, and a corresponding data transmission channel is allocated to each target data block.

[0052] Based on the initial address corresponding to each target data block and the transmission order, a target write address corresponding to each target data block is generated, and the target write address is cached in the DDR address cache queue according to the transmission order.

[0053] In the embodiments of this specification, setting a first preset value to determine the amount of data to be cached corresponding to the initial address queue is to ensure that enough data to be cached can be written into the DDR cache. Since the data to be cached needs to reach the corresponding burst length of the DDR cache when DDR caches and transmits data, setting the first preset value ensures that the DDR only performs power-on and initialization operations during operation, thereby reducing DDR usage losses. Since the application environment of the method in this embodiment is the internal environment of an FPGA, the initial address queue information is cached by the FIFO internal data buffer called by the FPGA. The addresses of each target data block written to the DDR cache are obtained by priority arbitration of the addresses corresponding to each target data block in the initial address queue of the FIFO cache, and then requesting them from the DDR cache queue according to the priority arbitration result.

[0054] In one possible implementation, the first preset value can be any one of 2kb, 4kb, 8kb, and 16kb.

[0055] In the embodiments described in this specification, the first preset value is set according to the burst length of the corresponding DDR. The first preset value corresponds to the burst length of the selected DDR version model. For example, the burst length of DDR2 is usually 4 or 8, but can also be set to 2 through a specific mode; the burst length of DDR3 is generally 8, but can also be set to 4 through a specific mode; and the burst length of DDR5 is 16. The purpose of setting the value of the first preset value in this way is to improve data transmission efficiency, reduce command cycle, and optimize bus bandwidth.

[0056] S3. Based on the target address to be written corresponding to each target data block, write each target data block to the DDR cache area through the data transmission channel corresponding to each target data block.

[0057] In the embodiments described in this specification, before writing data to the DDR cache, the DDR chip is powered on, and then the external DDR chip is initialized by the DDR controller, thereby putting the DDR cache in a write-ready state. The DDR controller can receive read and write commands from the AIX controller through the Axi_Interconnect module to begin executing DDR read and write operations.

[0058] The Axi_Interconnect module is an IP core for managing the AXI bus. It can be used for multi-device connection management, automatic protocol conversion between devices, arbitration, and communication. In system designs containing multiple AXI interface modules, using Axi_Interconnect can avoid complex wiring and configuration work, achieving efficient bus arbitration and data transmission. For example, in a SoC design containing multiple processor cores, memory, and peripherals, Axi_Interconnect can easily connect the various modules, enabling efficient data transmission and sharing.

[0059] In one possible implementation, the step of writing each target data block to the DDR cache area based on the target address to be written corresponding to each target data block, respectively, through the data transmission channel corresponding to each target data block, includes:

[0060] Write the target data block to the data transmission channel corresponding to each target data block according to the target write address corresponding to each target data block;

[0061] Based on the target write address corresponding to each target data block, determine whether the data volume of the target data block reaches the second preset value or whether the first target end identifier of the target write address corresponding to each target data block exists.

[0062] When the first target end identifier of the target write address corresponding to the target data block exists or the data volume of the target data block reaches the second preset value, each target data block is written to the DDR cache area corresponding to the target data block through the corresponding data transmission channel, and the target write address of each target data block is cached in the DDR address cache queue.

[0063] In the embodiments described in this specification, such as Figure 3 As shown, determining whether the size of the target data block reaches the second preset value is to ensure that the target data block can be completely written to or read from the DDR cache during transmission, rather than being split into several segments for data transmission, thereby reducing the loss of transmitted data in the event of a sudden transmission termination. The setting of the first target end marker has the same effect.

[0064] In one possible implementation, the data volume of the second preset value is not less than the data volume of the target data block, and the data volume of the second preset value is not greater than the upper limit of the data capacity of the data transmission channel corresponding to the target data block.

[0065] In the embodiments of this specification, the data volume of the second preset value is set to be no less than the data volume of the target data block in order to ensure that no other data is introduced during the process of writing or reading the target data block from the DDR cache, so as to reduce data pollution.

[0066] In one possible implementation, when the first target end marker is identified, the target data block corresponding to the first target end marker is padded with data so that the data volume of the target data block reaches a second preset value.

[0067] In the embodiments of this specification, setting a first target end marker can reduce the phenomenon of brief pauses in read or write operations during the writing or reading of data in the DDR cache. This means that any target data block can be written or read promptly, instead of waiting for the data accumulation in the data transmission channel corresponding to the target data block to reach a second preset value, thereby improving the read / write efficiency of the DDR cache, as well as the utilization rate and data transmission efficiency of each DDR transmission channel. As one implementation, in this embodiment, the first target end marker is specifically a segment on the target address to be written, which corresponds to the LAST signal of the AXI interface. The LAST signal of the AXI interface is used to indicate whether the current data transmission is the last data in a burst transmission. In the write data channel, the master device uses the WLAST signal to indicate that the current data it sends is the last in a burst transmission; while in the read data channel, the slave device uses the RLAST signal to indicate that the current data it sends is the last transmission. In this embodiment, the LAST signal can be used for burst transmission of a single target data block. Figure 1 The identification of the first target end marker and the padding of the target data block are handled by the DDR write controller within the DDR controller. The write controller identifies the first target end marker of the target data block. When the first target end marker is identified, the LAST signal of the AXI interface corresponding to the data transmission channel of the target data block is recognized by the AXI master controller. The AXI master controller then controls the DDR and its corresponding interfaces to begin operation, preparing for the DDR to write the data to be written. Simultaneously, the DDR write controller generates characters such as null characters to pad the length of the target data block, ensuring that the data size of the target data block reaches the second preset value.

[0068] S4. When it is detected that the DDR address cache queue of the DDR cache is not empty, the target data to be read is read from the DDR cache, and when the amount of the target data to be read reaches the amount of any target data block, the target address to be written of the target data to be read in the address cache queue is reclaimed.

[0069] In the embodiments of this specification, the process of reclaiming the target address to be written is carried out in real time to ensure that all DDR address cache queues can be effectively utilized. In addition, in conjunction with the dynamic address allocation and writing method of each channel in this embodiment, dynamic adjustment and recycling of DDR addresses can be realized.

[0070] In one possible implementation, reading the target data to be read from the DDR cache further includes: reading the target data to be read from the DDR cache, and synchronously outputting the target data to be read from the DDR cache to any storage device connected to the DDR.

[0071] In the embodiments described in this specification, such as Figure 1 As shown, the target data to be read is read from the DDR cache and synchronously output to any storage device connected to the DDR. This process is completed through the AIX interface. In this embodiment, the data is read from the DDR cache through the first read interface. The read order follows the first-in-first-out principle. The target data to be read is first read into the corresponding data transmission channel at the center of the interface, and then transmitted to the relevant memory that needs the target data. Synchronously outputting the target data to be read from the DDR cache to any storage device connected to the DDR is the main function of the DDR, namely, to temporarily store frequently accessed data to speed up data reading and improve system performance. In this embodiment, the target data to be read can also be directly read from the DDR cache and directly transmitted to other memory through interfaces of other protocols besides AIX, such as AHB (Advanced High-performance Bus), APB (Advanced Peripheral Bus), and PCIe (Peripheral Component Interconnect Express).

[0072] Those skilled in the art will clearly understand that the technical solutions of the embodiments of this application can be implemented by means of software and / or hardware. In this specification, "controller" and "memory" refer to software and / or hardware that can independently complete or cooperate with other components to complete a specific function, wherein the hardware may be, for example, a field-programmable gate array (FPGA), an integrated circuit (IC), etc.

[0073] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method provided in this embodiment. The computer-readable storage medium may include, but is not limited to, any type of disk, including floppy disks, optical disks, DVDs, CD-ROMs, microdrives, as well as magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic cards or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.

[0074] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0075] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0076] Furthermore, if the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0077] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0078] The foregoing description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of embodiments of this disclosure upon considering the specification and practicing the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described herein. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

Claims

1. A control method for dynamic management of DDR memory addresses, characterized in that, The method includes: Acquire data to be written, the data to be written includes at least one target data block, cache the initial address corresponding to each target data block to the initial address queue, the initial address is used to determine the position and data size of the target data block corresponding to the initial address in the data to be written, wherein the target data block has a corresponding target write address, the target write address is used to determine the storage location and data size of the target data block corresponding to the target write address in the DDR cache area; Priority arbitration is performed on the initial addresses in the initial address queue to determine the transmission order of each target data block, and a corresponding data transmission channel is allocated to each target data block according to the transmission order. The target address to be written corresponding to each target data block is cached in the DDR address cache queue according to the transmission order. Based on the target address to be written corresponding to each target data block, each target data block is written to the DDR cache area through the data transmission channel corresponding to each target data block; When the DDR address cache queue is detected to be non-empty, the data to be read is read from the DDR cache area corresponding to the DDR address cache queue, and when the amount of data to be read reaches the amount of data of any target data block, the target address to be written of the data to be read in the address cache queue is reclaimed.

2. The method according to claim 1, characterized in that, The step of prioritizing the initial addresses of the initial address queue to determine the transmission order of each target data block, allocating a corresponding data transmission channel to each target data block according to the transmission order, and caching the target write addresses corresponding to each target data block into the DDR address cache queue according to the transmission order includes: The data volume of each target data block is obtained based on each initial address of the initial address queue; Based on the queue sorting of each initial address in the initial address queue, the data volume of the target data block corresponding to each initial address is summed to obtain the initial total amount of data to be judged, until the initial total amount of data to be judged reaches a first preset value. When the total amount of the initial data to be judged reaches a first preset value, priority arbitration is performed on the initial address corresponding to each target data block. The transmission order of each target data block is determined based on the arbitration result, and a corresponding data transmission channel is allocated to each target data block. Based on the initial address corresponding to each target data block and the transmission order, a target write address corresponding to each target data block is generated, and the target write address is cached in the DDR address cache queue according to the transmission order.

3. The method according to claim 2, characterized in that, The first preset value is any one of 2kb, 4kb, 8kb and 16kb.

4. The method according to claim 1, characterized in that, The step of writing each target data block to the DDR cache area based on the target address to be written corresponding to each target data block, through the data transmission channel corresponding to each target data block, includes: Write the target data block to the data transmission channel corresponding to each target data block according to the target write address corresponding to each target data block; Based on the target write address corresponding to each target data block, determine whether the data volume of the target data block reaches the second preset value or whether the first target end identifier of the target write address corresponding to each target data block exists. When the first target end identifier of the target write address corresponding to the target data block exists or the data volume of the target data block reaches the second preset value, each target data block is written to the DDR cache area corresponding to the target data block through the corresponding data transmission channel, and the target write address of each target data block is cached in the DDR address cache queue.

5. The method according to claim 4, characterized in that, The method includes: When the first target end marker is identified, the target data block corresponding to the first target end marker is padded with data so that the data volume of the target data block reaches the second preset value.

6. The method according to claim 4, characterized in that, The data volume of the second preset value is not less than the data volume of the target data block, and the data volume of the second preset value is not greater than the upper limit of the data capacity of the data transmission channel corresponding to the target data block.

7. The method according to claim 1, characterized in that, The step of reading the data to be read from the DDR cache corresponding to the DDR address cache queue includes: The data to be read is read from the DDR cache and synchronously output from the DDR cache to any storage device connected to the DDR.

8. A control system for dynamic management of DDR memory addresses, characterized in that, include: Memory, interface center, and main controller; The memory is used to store data read from the DDR cache, and the interface center is used to provide a transmission channel for writing and reading data from the DDR cache. The main controller is used to implement the steps of the method as described in any one of claims 1-7 when executing a computer program.

9. The control system for dynamic management of DDR memory addresses according to claim 8, characterized in that, The DDR cache write and read data both adopt the AXI bus format, and each interface in the interface center is an AXI bus protocol interface.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer-readable storage medium stores instructions that, when executed on a computer or processor, cause the computer or processor to perform the steps of the method as described in any one of claims 1-7.

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