An address allocation method and device, a storage medium and an electronic device

Abstract

Embodiments of the present disclosure provide an address allocation method and device, a storage medium and an electronic device, and relate to the technical field of computers. The method comprises: in response to a write request, obtaining snapshot information; and according to a mapping rule, allocating a physical block address corresponding to a logical block address of at least one data by using the snapshot information; wherein the snapshot information is used to allocate adjacent logical block addresses to physical block addresses in different areas. In this way, by allocating adjacent logical block addresses to different physical areas, the situation of some data being concentrated in high pages is avoided, thereby improving reading performance and user experience.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to an address allocation method, apparatus, storage medium and electronic device. Background Technology

[0002] Non-volatile solid-state storage has shown a trend towards high density. Currently, some manufacturers at home and abroad have completed the commercialization of solid-state storage products based on quad-level cell (QLC) particles, leading a new direction for SSD development.

[0003] The Flash Translation Layer (FTL) shields users from the physical characteristics of flash memory and enables software management within the SSD. It primarily consists of key algorithms such as address mapping, garbage collection, and wear leveling. Address mapping is a crucial function of the FTL, allocating flash memory addresses for host-initiated write commands, thus translating logical addresses into physical addresses. Related technologies have proposed a super-management approach, a common method being the layer-by-layer allocation of physical block addresses (PBAs) on a multi-word line (MWL). This method effectively improves the parallelism of data read and write operations.

[0004] However, the above physical address allocation method does not take into account the error characteristics of each page in the QLC. The four pages of each word line (WL) in a QLC granular unit are named from bottom to top as LSB (Least Significant Bit), CSB (Central Significant Bit), MSB (Most Significant Bit), and TSB (Top Significant Bit). Studies have shown that the read latency of higher pages (such as MSB and TSB) is generally greater than that of lower pages (such as LSB and CSB). This is mainly due to the following three reasons:

[0005] 1) Reading high pages requires more reference voltage;

[0006] 2) Higher pages are more prone to errors and have a higher bit error rate;

[0007] 3) The error correction process increases the reading time.

[0008] Therefore, if host data is processed using the ordinary address allocation method in QLC solid-state storage, some data may be concentrated in high-page areas, which seriously affects read performance and user experience. Summary of the Invention

[0009] This disclosure provides an address allocation method, apparatus, storage medium, and electronic device to at least solve the above-mentioned technical problems existing in the prior art.

[0010] The technical solution of this disclosure embodiment is implemented as follows:

[0011] In a first aspect, embodiments of this disclosure provide an address allocation method applied to a solid-state drive, the method comprising:

[0012] In response to a write request, retrieve snapshot information;

[0013] According to the mapping rules, the snapshot information is used to allocate the physical block address corresponding to the logical block address of at least one piece of data; wherein, the snapshot information is used to allocate adjacent logical block addresses to physical block addresses located in different regions.

[0014] The method in the above scheme further includes:

[0015] Snapshot information is generated, including: offset snapshots; the offset snapshots are used to record the offset relationships between physical block addresses.

[0016] In the above scheme, the step of allocating the physical block address corresponding to the logical block address of at least one piece of data using the snapshot information includes:

[0017] The physical block address corresponding to the logical block address of at least one data on each multiword line is allocated using the snapshot information.

[0018] In the above scheme, generating the offset snapshot includes:

[0019] Obtain a first number and a second number of word lines, where the first number is the number of page layers per word line and the second number is the number of planes involved in the parallel storage operation of the word line;

[0020] Construct a first matrix, a second matrix, and a third matrix based on the first quantity and the second quantity;

[0021] Based on the first matrix, the second matrix, and the third matrix, an offset snapshot is obtained;

[0022] The first matrix is ​​used to record pages with allocable physical block addresses using diagonal lines;

[0023] The second matrix is ​​used to shift the allocation order of the pages;

[0024] The third matrix is ​​used to accumulate the number of pages with allocable physical block addresses.

[0025] In the above scheme, the number of rows in the first matrix is ​​related to the first quantity, and the number of columns in the first matrix is ​​related to the second quantity;

[0026] The number of rows in the second matrix is ​​related to the second quantity, and the number of columns in the second matrix is ​​related to the second quantity;

[0027] The number of rows in the third matrix is ​​related to the first quantity, and the number of columns in the third matrix is ​​related to the second quantity.

[0028] In the above scheme, obtaining the offset snapshot based on the first matrix, the second matrix, and the third matrix includes:

[0029] The total number of iterations is determined based on the second quantity;

[0030] The order matrix is ​​processed sequentially according to the total number of iterations to obtain the target order matrix. Each process includes: determining the product of the iteration number and the third matrix, adding the product to the first matrix to obtain the translation result, multiplying the translation result by the second matrix, and then adding it to the order matrix of the previous round.

[0031] The offset snapshot is determined based on the target order matrix.

[0032] In the above scheme, the target order matrix is ​​used to indicate the planes corresponding to the multiple physical block addresses, and the corresponding LSB, CSB, MSB or TSB;

[0033] Determining the offset snapshot based on the target order matrix includes:

[0034] Based on the target order matrix, the planes where multiple physical block addresses are located, as well as their respective LSBs, CSBs, MSBs, or TSBs, are determined. Each physical block address corresponds to an allocation order, and the planes of physical block addresses with adjacent allocation orders are different, and the LSBs, CSBs, MSBs, or TSBs of physical block addresses with adjacent allocation orders are different.

[0035] In the above scheme, allocating the physical block address corresponding to the logical block address of at least one data item on each multi-word line using the snapshot information includes:

[0036] The multi-word line is assigned an index set, the index set including at least one index of a physical block address, the index representing the allocation order of the physical block addresses;

[0037] The first physical block address corresponding to the first logical block address is allocated according to the index set, where the first logical block address is the logical block address of the starting data on the multiword line;

[0038] Based on the physical block address corresponding to the first logical block address, the difference between the first physical block address and the second physical block address, and the offset snapshot, a second physical block address corresponding to the second logical block address is allocated; the second logical block address is the logical block address of data other than the non-starting data on the multi-word line; the index of the first physical block address takes precedence over the index of the second physical block address.

[0039] The method in the above scheme further includes:

[0040] Check if the block containing the physical block address is a bad block;

[0041] If the block containing the physical block address is a bad block, update the index set to delete or skip the physical block addresses associated with the bad block.

[0042] The method in the above scheme further includes:

[0043] A mapping table is determined based on the logical block address of each piece of data and its physical block address in the solid-state storage unit. The mapping table is used to record the mapping relationship between the logical block address and the physical block address of each piece of data.

[0044] Upon receiving a read request, the system queries the mapping table based on the logical block address carried in the read request to determine the physical block address corresponding to the read request.

[0045] In the above solution, the solid-state drive is a QLC solid-state drive, which includes multiple planes, each plane includes multiple blocks, each block includes multiple pages, and the multiple pages include: LSB, CSB, MSB, and TSB;

[0046] The physical block addresses within the different regions include:

[0047] The planes of the physical block addresses are different, and the LSB, CSB, MSB, or TSB of the physical block addresses are different.

[0048] Secondly, embodiments of this disclosure provide an address allocation device applied to a solid-state drive, the device comprising:

[0049] The acquisition module is used to retrieve snapshot information in response to write requests;

[0050] The processing module is used to allocate physical block addresses corresponding to logical block addresses of at least one piece of data using the snapshot information according to the mapping rules; wherein the snapshot information is used to allocate adjacent logical block addresses to physical block addresses located in different regions.

[0051] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform any of the address allocation methods described above.

[0052] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform an address allocation method according to any one of the claims.

[0053] The embodiments disclosed herein have the following beneficial effects:

[0054] The address allocation method, apparatus, storage medium, and electronic device provided in this disclosure, in response to a write request, acquire snapshot information; according to mapping rules, allocate physical block addresses corresponding to the logical block addresses of at least one piece of data using the snapshot information; wherein, the snapshot information is used to allocate adjacent logical block addresses to physical block addresses located in different regions. Thus, by allocating adjacent logical block addresses to different physical regions, the situation where some data is concentrated in high-page areas (such as MSB, TSB) is avoided, thereby improving read performance and user experience.

[0055] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0056] Figure 1 This is a schematic diagram illustrating a flash memory organization method and a traditional physical address allocation method.

[0057] Figure 2 A flowchart illustrating an address allocation method provided in an embodiment of this disclosure;

[0058] Figure 3 A comparative diagram illustrating the allocation order of MWL physical block addresses provided in this embodiment of the disclosure;

[0059] Figure 4 A flowchart illustrating a PBA allocation method for QLC solid-state storage provided in this embodiment of the disclosure;

[0060] Figure 5 This is a schematic diagram of the structure of a solid-state drive provided in an embodiment of the present disclosure;

[0061] Figure 6 This is a schematic diagram of the structure of an address allocation device provided in an embodiment of the present disclosure;

[0062] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0063] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0064] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0065] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0067] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms involved in the embodiments of this disclosure will be explained, and the nouns and terms involved in the embodiments of this disclosure shall be interpreted as follows.

[0068] Solid-state drives (SSDs) are hard drives based on flash memory technology, using electric flash storage units instead of the spinning disks of traditional hard disk drives (HDDs). The advantages of SSDs include faster read and write speeds, lower power consumption, and higher shock resistance. The core storage area of ​​an SSD is typically flash memory.

[0069] QLC (Quad-Level Cell) solid-state drives are a type of storage where each cell can store 4 bits of data. Compared to other types of solid-state drives (such as Single-Level Cell (SLC), Multi-Level Cell (MLC), and Trinary-Level Cell (TLC), QLC offers higher storage density, thereby reducing storage costs).

[0070] The storage area is divided into multiple planes, each plane contains multiple blocks, and each block contains multiple pages.

[0071] Plane: A unit of storage in a solid-state drive. Multiple Planes (usually 4, 6, or 8) form a LUN (Logical Unit Number). Multiple LUNs can form a storage chip. Each Plane has an independent cache register and page register, and can perform read and write operations independently.

[0072] Block: In an SSD, storage units are further divided into multiple blocks, and each block consists of multiple pages. Each block is the smallest unit for erasing on a solid-state drive.

[0073] Word Line (WL): Each block is usually composed of multiple WLs, and WL is the smallest unit of writing.

[0074] Page: The smallest unit of data storage in each block, typically between 2KB and 16KB in size. SSD read operations are usually performed on a page basis.

[0075] Logical Block Address (LBA): This is a virtual address used by the operating system or storage controller when interacting with storage devices (such as SSD controllers to SSDs). It is a logical address and a data mapping method between the operating system and the hard drive. Users and the operating system typically use logical block addresses to specify the location of data.

[0076] Physical Block Address (PBA): This is the actual physical address inside the storage device, representing the physical location of data on the storage medium (such as a solid-state drive). It is the address that the storage controller actually uses to access the data.

[0077] Figure 1 This is a schematic diagram illustrating a flash memory organization method and a traditional physical address allocation method, such as... Figure 1 As shown, during the write operation, LBA0 to LBA3 are assigned to WL0 and Page0 of Plane0 to Plane3 respectively; when transferring data from LBA0 to the page register, data transfer to LBA1 can be initiated simultaneously; similarly, when reading from LBA0 to LBA3, the read operation of Plane1 can be started immediately when the page register of Plane0 transfers data to the bus.

[0078] It can be seen that if we adopt Figure 1 The method shown, which processes host data in QLC solid-state storage using the ordinary address allocation method, may result in some data being concentrated in high pages (such as MSB, TSB). Because the page size is high, the bit error rate is high, and the read latency of high pages is large, which seriously affects read performance and user experience.

[0079] Based on this, embodiments of this disclosure provide an address allocation method, apparatus, storage medium, and electronic device. In response to a write request, snapshot information is acquired; according to mapping rules, the snapshot information is used to allocate physical block addresses corresponding to logical block addresses of at least one piece of data; wherein the snapshot information is used to allocate adjacent logical block addresses to physical block addresses located in different regions. Thus, by allocating adjacent logical block addresses to different physical regions, the situation where some data is concentrated in high-page areas (such as MSB, TSB) is avoided, thereby improving read performance and user experience.

[0080] Figure 2 This is a flowchart illustrating an address allocation method provided in an embodiment of the present disclosure, as shown below. Figure 1 As shown, the method is applied to a solid-state drive, and the address allocation method includes:

[0081] Step 201: In response to the write request, obtain snapshot information;

[0082] Step 202: According to the mapping rules, allocate the physical block address corresponding to the logical block address of at least one piece of data using the snapshot information; wherein, the snapshot information is used to allocate adjacent logical block addresses to physical block addresses located in different regions.

[0083] Here, the solid-state drive can receive I / O commands from the host, such as read requests and write requests;

[0084] The snapshot information records information that provides the physical block address corresponding to the allocated logical block address, and the mapping rules specify how to map the logical block address to the physical block address. This can be implemented through the FTL (Flash Translation Layer).

[0085] Using snapshot information to allocate adjacent logical block addresses to physical block addresses located in different regions means that although some logical block addresses are adjacent, these adjacent logical block addresses will be allocated to different physical regions (such as different types of pages). In this way, they are distributed in high pages (such as MSB, TSB) and low pages (such as LSB, CSB) in sequence, avoiding the situation where some data is concentrated in high pages (such as MSB, TSB), thereby improving read performance and user experience.

[0086] In some embodiments, the method further includes:

[0087] Snapshot information is generated, including: offset snapshots; the offset snapshots are used to record the offset relationships between physical block addresses.

[0088] Specifically, snapshot information is a backup of the storage system's state at a specific point in time, used to track changes in stored data. It can contain various information to provide guidance during writes or reads, saving computation time. In practice, snapshot information can include several different types of snapshots; for example, in addition to offset snapshots, it can also include Plane snapshots.

[0089] Offset snapshots are used to record the offset relationships between different physical block addresses. An offset relationship refers to the relative position or difference between physical block addresses. For example, an offset snapshot can describe the distance between one physical block address and another, or their offset within the storage medium. Thus, when a new physical block address needs to be mapped, the offset relationship between the allocated physical block address and the new physical block address can be referenced to determine the new physical block address.

[0090] Regarding Plane snapshots, a Plane refers to a hierarchical structure in a storage device (such as a solid-state drive) used to represent the physical hierarchy on the storage medium. In a solid-state drive, it can be divided into multiple Planes, each Plane containing multiple blocks, and each block containing multiple Work Levels (WLs). Figure 1 WL1, WL2, etc.), each WL can include multiple Pages (e.g. Figure 1 (Page 0, Page 1, etc.). Plane snapshots are used to record information related to the physical storage hierarchy, such as details about storage area distribution and management.

[0091] For example, a Plane snapshot is denoted as Plane_snapshot;

[0092] Plane_snapshot={0,1,2,3,1,2,3,0,2,3,0,1,3,0,1,2};

[0093] This indicates the presence of four Planes: Plane0, Plane1, Plane2, and Plane3. During sequential allocation of physical block addresses, the physical block addresses are located sequentially in Plane0, Plane1, Plane2, and Plane3. Then, they are allocated sequentially to Plane1, Plane2, Plane3, and Plane0, and so on. Subsequent allocations are Plane2, Plane3, Plane0, and Plane1, and then Plane3, Plane0, Plane1, and Plane2. This describes the allocation of physical block addresses for different Planes.

[0094] In some embodiments, the physical block address corresponding to the logical block address of at least one piece of data allocated using the snapshot information includes:

[0095] The physical block address corresponding to the logical block address of at least one data item on each Multi-Word Line (MWL) is allocated using the snapshot information.

[0096] Here, to improve data transfer rates and the parallelism of storage operations, multi-word-line technology allows multiple word lines to be activated simultaneously within a single clock cycle. Solid-state drives (SSDs) utilize multi-word lines to read or write multiple pages at the same time, thereby improving data access speed.

[0097] Specifically, each multiword line corresponds to multiple data blocks. A corresponding physical block address can be assigned to the logical block address of each data block on the multiword line. This physical block address refers to the specific address on the Plane, Block, or Page.

[0098] In some embodiments, generating the offset snapshot includes:

[0099] Obtain a first number and a second number of word lines, where the first number is the number of page layers per word line and the second number is the number of planes involved in the parallel storage operation of the word line;

[0100] Construct a first matrix, a second matrix, and a third matrix based on the first quantity and the second quantity;

[0101] Based on the first matrix, the second matrix, and the third matrix, an offset snapshot is obtained;

[0102] The first matrix is ​​used to record pages with allocable physical block addresses using diagonal lines;

[0103] The second matrix is ​​used to shift the allocation order of the pages;

[0104] The third matrix is ​​used to accumulate the number of pages with allocable physical block addresses.

[0105] Specifically, the first quantity represents the number of page layers in each character line, that is, the number of Page layers in each character line, such as... Figure 1 WL0 contains 4 Pages, with the first number being 4;

[0106] The second quantity is the number of planes involved in the parallel storage operations of word lines, i.e., the number of planes, such as... Figure 1 The first part contains Plane0, Plane1, Plane2, Plane3, and the second part has 4.

[0107] In some embodiments, the number of rows in the first matrix is ​​related to the first quantity, and the number of columns in the first matrix is ​​related to the second quantity;

[0108] The number of rows in the second matrix is ​​related to the second quantity, and the number of columns in the second matrix is ​​related to the second quantity;

[0109] The number of rows in the third matrix is ​​related to the first quantity, and the number of columns in the third matrix is ​​related to the second quantity.

[0110] Here, a first matrix (denoted as A), a second matrix (denoted as T), and a third matrix (denoted as D) are designed based on the first quantity and the second quantity.

[0111] In one example, each word line in a multi-word line has 4 pages and 4 planes, and the corresponding first matrix (denoted as A), second matrix (denoted as T), and third matrix (denoted as D) are as follows:

[0112]

[0113]

[0114]

[0115] In another example, each word line in a multi-word line has 4 pages and 8 planes, and the corresponding first matrix (denoted as A), second matrix (denoted as T), and third matrix (denoted as D) are as follows:

[0116]

[0117]

[0118]

[0119] In some embodiments, obtaining the offset snapshot based on the first matrix, the second matrix, and the third matrix includes:

[0120] The total number of iterations is determined based on the second quantity;

[0121] The order matrix is ​​processed sequentially according to the total number of iterations to obtain the target order matrix. Each process includes: determining the product of the iteration number and the third matrix, adding the product to the first matrix to obtain the translation result, multiplying the translation result by the second matrix, and then adding it to the order matrix of the previous round.

[0122] The offset snapshot is determined based on the target order matrix.

[0123] Specifically, based on the example above where each word line has 4 pages and 8 planes, and the initial value of U is A, the target order matrix is ​​calculated using the following formula:

[0124]

[0125] Where i is the iteration number, adjusted based on the actual second number. When i=0, initialization is performed, at which point U=A, and subsequently... When calculating, use the formula above; This represents the product of the iteration number and the third matrix; This means that the product is added to the first matrix to obtain the translation result, that is, the first matrix (A) is translated using the second matrix (D).

[0126] Based on the above example, for 4 Pages and 4 Planes, the target order matrix U is calculated as follows:

[0127]

[0128] For a 4-layer Page and 8 Planes, the target order matrix U is calculated as follows:

[0129]

[0130] In some embodiments, the target order matrix is ​​used to indicate the planes corresponding to the multiple physical block addresses, and the corresponding LSB, CSB, MSB or TSB;

[0131] Determining the offset snapshot based on the target order matrix includes:

[0132] Based on the target order matrix, the planes where multiple physical block addresses are located, as well as their respective LSBs, CSBs, MSBs, or TSBs, are determined. Each physical block address corresponds to an allocation order, and the planes of physical block addresses with adjacent allocation orders are different, and the LSBs, CSBs, MSBs, or TSBs of physical block addresses with adjacent allocation orders are different.

[0133] Here, the QLC solid-state drive uses four-level cell storage technology. The four pages of each word line in the QLC chip, from bottom to top, are:

[0134] LSB (Least Significant Bit): This is the least significant bit stored, representing the part of the data that has the least impact.

[0135] CSB (Central Significant Bit): Located between LSB and MSB, it represents the middle significant bit. In QLC particles, it represents the second page out of four, with the affected data portion positioned in the middle.

[0136] MSB (Most Significant Bit): In QLC granules, MSB corresponds to the third page out of four pages and has a higher significance bit weight.

[0137] TSB (Top Significant Bit): The topmost bit in the QLC granular structure, representing the most important data bit. In the four pages, the TSB is the topmost page and has the highest significance.

[0138] The physical block addresses allocated in adjacent orders are all on different planes, meaning that when data is allocated in an adjacent order, adjacent physical blocks (memory units) will differ in both the plane and the page. For example, the first physical block address and the second physical block address will not both be located on the same plane.

[0139] The LSB, CSB, MSB, or TSB of adjacent physical block addresses are different, indicating that when physical block addresses are allocated sequentially, the storage bits (LSB, CSB, MSB, TSB) of adjacent physical block addresses will not be the same. For example, the first physical block address and the second physical block address will not be of the same type of Page, that is, they will not have the same LSB, CSB, MSB, or TSB.

[0140] In some embodiments, allocating the physical block address corresponding to the logical block address of at least one data item on each multiword line using the snapshot information includes:

[0141] The multi-word line is assigned an index set, the index set including at least one index of a physical block address, the index representing the allocation order of the physical block addresses;

[0142] The first physical block address corresponding to the first logical block address is allocated according to the index set, where the first logical block address is the logical block address of the starting data on the multiword line;

[0143] Based on the physical block address corresponding to the first logical block address, the difference between the first physical block address and the second physical block address, and the offset snapshot, a second physical block address corresponding to the second logical block address is allocated; the second logical block address is the logical block address of data other than the non-starting data on the multi-word line; the index of the first physical block address takes precedence over the index of the second physical block address.

[0144] Here, the index set includes multiple indexes. For example, 4 levels of Pages and 4 Planes can be allocated 16 indexes, denoted as 0-15; 4 levels of Pages and 8 Planes can be allocated 32 indexes, denoted as 0-31.

[0145] The index represents the allocation order of physical block addresses, and physical block addresses are allocated according to this order. For example, the index set includes 0-15, and when allocating physical block addresses, the physical block addresses indexed as 0, 1...15 are allocated according to the index order.

[0146] For example, define the pba_offset_snapshot array variable to represent the PBA offset snapshot, which is used to record the offset of each physical block address index relative to the starting physical block address in the multiword line.

[0147] Index refers to the position in an allocation sequence, and the corresponding PBA offset is the offset relative to the starting physical block address of the multiword line. Assuming the starting physical block address is s_pba, the pba corresponding to the Index-th allocation sequence is pba = s_pba + pba_offset_snapshot[Index], where pba_offset_snapshot[Index] represents the PBA offset in the offset snapshot.

[0148] by Figure 3 For example, Figure 3This diagram illustrates a comparative analysis of the allocation order of MWL (Multi-Plane Library) physical block addresses, as provided in an embodiment of this disclosure. It shows the page distribution of a 4-Plane, 4-Page QLC (Quadrature-Limited Library) type MWL, representing the smallest unit of a multi-Plane program commonly used in the industry. The diagram assumes each Page corresponds to one PBA (Physical Block Address). Typically, a QLC Page is 16 KiB in size. Considering that QLC is often used for high-capacity storage, designers usually set the mapping granularity to be greater than or equal to 16 KiB to reduce DRAM resource costs. Figure 3 In the diagram, the horizontal axis represents the increasing direction of Planes, corresponding to different blocks within different Planes; the vertical axis represents the increasing direction of Pages, indicating the LSB, CSB, MSB, and TSB of the QLC. Numbers represent the allocation order of PBAs and the PBA index.

[0149] Figure 3 The diagram on the left shows an example of the allocation order using the traditional allocation method. As can be seen, the allocation order follows the Page order of the MWL.

[0150] Figure 3 The diagram on the right is an example of the allocation order using the method provided in the embodiments of this disclosure. It can be seen that the allocation order is based on the plane and the LSB, CSB, MSB, TSB of the page. The planes of the physical block addresses of adjacent allocation orders (such as 0 and 1, 1 and 2, and so on) are not the same, and the LSB, CSB, MSB or TSB of the physical block addresses of adjacent allocation orders are not the same (such as 0 and 1 being located in Page0 of Plane0 and Page1 of Plane1, respectively).

[0151] by Figure 3 Taking the right image as an example, it is generated based on the case of 4Page and 4Plane.

[0152] Correspondingly, when the host re-initiates reads of LBA0, LBA1, LAB2, and LAB3, PBA indexes 12-15 are located on different planes and different pages. The example on the left shows indexes 12-15 concentrated on high pages (TSBs), which can easily lead to longer error correction times. The example on the right avoids the long error correction delays caused by data being concentrated on high pages, thus improving read performance and user experience.

[0153] In some embodiments, the method further includes:

[0154] Check if the block containing the physical block address is a bad block;

[0155] If the block containing the physical block address is a bad block, update the index set to delete or skip the physical block addresses associated with the bad block.

[0156] Here, if the block is a bad block, all physical block addresses in the block need to be processed, that is, the physical block address indices of all bad blocks in the index set need to be deleted.

[0157] In this way, subsequent data access will not attempt to write to or read from bad blocks, thus avoiding data loss or read failures caused by bad blocks.

[0158] In some embodiments, the method further includes:

[0159] A mapping table is determined based on the logical block address of each piece of data and its physical block address in the solid-state storage unit. The mapping table is used to record the mapping relationship between the logical block address and the physical block address of each piece of data.

[0160] Upon receiving a read request, the system queries the mapping table based on the logical block address carried in the read request to determine the physical block address corresponding to the read request.

[0161] Here, each piece of data has a logical block address, which is an abstract address assigned by the operating system or file system. The actual physical block location where the data is stored is provided by the solid-state drive (SSD). To ensure that data can be read correctly, the system maintains a mapping table that records the relationship between logical block addresses and physical block addresses.

[0162] In actual read operations, upon receiving a read request containing the logical block address, the mapping table is consulted based on the logical block address to find the corresponding physical block address. Then, data is read from the corresponding physical block address.

[0163] In this way, the storage system can effectively manage data storage and access, hiding the complexity of the underlying hardware and allowing applications to focus only on the management of logical addresses.

[0164] In some embodiments, the solid-state drive is a QLC solid-state drive, which includes multiple planes, each plane including multiple blocks, each block including multiple pages, and the multiple pages including: LSB, CSB, MSB, and TSB;

[0165] The physical block addresses within the different regions include:

[0166] The planes of the physical block addresses are different, and the LSB, CSB, MSB, or TSB of the physical block addresses are different.

[0167] Here, physical block addresses are allocated based on the error characteristics of different pages (LSB, CSB, MSB, TSB) of the QLC granules. While taking into account the parallelism of the plane, it is necessary to ensure that adjacent logical block addresses are on different types of pages as much as possible, thereby reducing the latency caused by read error correction and improving the user experience.

[0168] The method provided in this disclosure solves the performance bottleneck problem in QLC solid-state storage where some data is concentrated in high pages (such as MSB and TSB) due to ordinary address allocation methods. By allocating adjacent logical blocks to different physical regions, it avoids concentrated storage in high-page areas. In this way, the storage system can evenly distribute read and write loads, effectively avoiding overuse of hotspot areas and significantly improving read performance and system response speed.

[0169] First, by distributing data storage, frequent access to the same high-page area is avoided, reducing the pressure on a single area from high-frequency read / write operations and thus preventing performance bottlenecks. This allows the system to achieve higher parallel read capabilities, improving overall data read speed, reducing access latency, and resulting in a smoother user experience when using the storage device.

[0170] Secondly, by distributing data evenly, the lifespan of storage devices can be effectively extended. In traditional storage allocation methods, frequent read / write operations concentrated in certain areas accelerate wear and tear on those areas, especially in flash memory. Due to the limited number of write cycles, excessive erasing and writing can lead to premature aging of the device. A reasonable allocation method can balance the load across different areas, avoiding excessive erasing and writing in certain areas, reducing the device's failure rate, and thus extending the overall lifespan of the device.

[0171] Furthermore, by optimizing data allocation, storage space is utilized more efficiently. Evenly distributed data reduces waste in certain areas, improves the overall utilization of storage resources, and further optimizes the working efficiency of storage devices.

[0172] In summary, by avoiding data concentration in high-page areas, the performance bottleneck caused by high-frequency read / write operations is resolved, achieving the effects of improving read performance, extending device lifespan, and optimizing storage space utilization.

[0173] Figure 4 This is a flowchart illustrating a PBA allocation method for QLC solid-state storage provided in an embodiment of this disclosure; as shown below. Figure 4 As shown, the method is applied to QLC solid-state drives, and the method includes:

[0174] Step 401: Initialize snapshot information;

[0175] Here, the snapshot information includes: offset snapshot and Plane snapshot.

[0176] Offset snapshots are used to record the offset relationship between different physical block addresses. The offset relationship refers to the relative position or difference between physical block addresses.

[0177] Plane snapshots are used to record information related to the physical storage hierarchy, such as the distribution of storage areas and specific management details.

[0178] Step 402: In response to the write request, set the index set, and set the starting index to 0;

[0179] Here, upon receiving a write request, the snapshot information is used to allocate a corresponding physical block address for the logical block address of at least one piece of data carried in the write request. Specifically, an index set is defined, including multiple indices, specifically indices of physical block addresses, where each index can represent the allocation order of physical block addresses. The initial index is set to 0, such as... Figure 3 The example shown includes 16 indices from 0 to 15.

[0180] Step 403: Determine if the Index is less than the total number of Pages; if the Index is less than the total number of Pages, proceed to step 404; otherwise, proceed to step 406.

[0181] Here, the total number of Pages is the total number of pages that can be allocated. If the total number of Pages is less than or equal to the Index, it indicates that there are no more Pages available for allocation, or that allocation has been completed.

[0182] Step 404: Determine if the block is valid. If valid, proceed to step 405; otherwise, update Index = Index + 1 and proceed to step 403.

[0183] Here, determining whether a block is valid specifically refers to determining whether the block containing the physical block address corresponding to the Index is valid (whether it is a bad block).

[0184] Step 405: Allocate physical block addresses and update the mapping table;

[0185] Here, if the block containing the physical block address corresponding to the Index is valid, the corresponding physical block address is allocated, and the mapping relationship between the allocated physical block address and the corresponding logical block address is saved to the mapping table.

[0186] Step 406: Determine the physical block address allocation for each piece of data in the write request;

[0187] Here, adjacent logical block addresses in each data in the write request are assigned to physical block addresses located in different regions. For example, adjacent logical block addresses are assigned to physical block addresses on different planes, and the LSB, CSB, MSB, or TSB of the physical block addresses are different.

[0188] By using the above method, during data writing, adjacent logical block addresses are evenly distributed to physical block addresses located on different Planes and different types of Pages (specifically, four Pages: LSB, CSB, MSB, and TSB). This approach balances read parallelism while avoiding long error correction delays caused by data being concentrated in high-page areas, thereby improving read performance and user experience.

[0189] Figure 5 This is a schematic diagram of the structure of a solid-state drive provided in an embodiment of this disclosure; as shown below. Figure 5 As shown, the solid-state drive includes: an IO command pre-processing unit, an FTL PBA allocation module, an IO command post-processing unit, and flash memory (QLC flash memory shown in the figure).

[0190] Here, the IO command preprocessing unit is used to perform front-end processing and FTL preprocessing on commands from the host, including command parsing, buffer allocation, data transfer, etc.

[0191] The host can send I / O commands to the solid-state drive (SSD) via the I / O interface. These commands can include read and write operations. Command parsing involves resolving these I / O commands. During parsing, the File Transfer Layer (FTL) extracts the target logical block address (LBA) and data content from the I / O command. Then, the FTL uses a stored mapping table to convert the logical address (LBA) to a physical address (PBA). For example, if the I / O command is a read command, the FTL checks the LBA to see if the data is already stored in the QLC flash memory. If the I / O command is a write command, the FTL ensures that the data can be effectively written to the QLC flash memory and allocates an appropriate physical block location for the data.

[0192] Before performing a write operation, FTL needs to allocate a buffer to temporarily store the data to be written. This is because flash memory write operations must follow specific rules; for example, existing data cannot be directly overwritten during writing, but must be written to a new free area. Due to the limitations of flash memory's erase / write cycles, FTL also considers data validity and available space when allocating the buffer. If invalid data is found in the target storage area, FTL will migrate or clean up this invalid data first to make room for new data. Buffer allocation also involves data persistence and sequential writing. FTL will manage the data storage location reasonably according to the SSD's internal structure to optimize write performance and extend the lifespan of the flash memory.

[0193] Data migration refers to the process of moving data from one location to another in flash memory. This typically occurs when new data is written, especially when data at the original location needs to be updated or replaced. The Flash Scrolling Layer (FTL) selects an appropriate location for writing data based on demand. When writing new data, the FTL migrates the original data to a new location and then stores the new data at the target location. Data migration should ideally occur during small-granularity writes. For example, if the flash memory's mapping granularity is 16 KiB, and a 4 KiB needs to be updated, the remaining 12 KiB is combined with the 4 KiB containing the updated data to form a new 16 KiB, which is then written to the new physical block address. In this case, the 12 KiB of data has been migrated.

[0194] Here, the FTL PBA allocation module includes:

[0195] The snapshot calculation unit is used to calculate the offset snapshot and Plane snapshot during firmware initialization and store the snapshot calculation results in the snapshot storage unit;

[0196] A snapshot storage unit is used to store the snapshot calculation results mentioned above;

[0197] The PBA allocation unit is used to allocate PBAs for MWLs one by one based on snapshot information.

[0198] Here, the IO command post-processing unit performs FTL post-processing and back-end processing on the IO commands, including PBA information configuration and programming message configuration, and sends the programming message to the flash memory, completing the processing of a write command issued by the host. That is, the write operation request sent by the host has been correctly processed and written to the QLC flash memory.

[0199] In an SSD, IO commands (such as read and write commands) are first issued by the host and then enter the solid-state drive.

[0200] Post-processing refers to the further operations performed after the FTL has processed the I / O commands. For example, after determining the mapping relationship between logical block addresses and physical block addresses, it performs management of free blocks corresponding to the physical block addresses, garbage collection, etc.

[0201] Back-end processing refers to operations performed inside the flash memory chip, such as data writing and erasing. Back-end processing typically involves interaction with hardware to ensure that data is correctly written to the flash memory.

[0202] Specifically, PBA information configuration refers to associating logical block addresses with actual physical block addresses based on the mapping relationship between logical block addresses and physical block addresses.

[0203] In flash memory, a write operation is actually a programming operation, referring to the storage of data into the flash memory. Programming message configuration refers to configuring the relevant parameters required for the programming operation, such as the data block to be written and the starting address of the data.

[0204] Sending programming messages to flash memory means sending relevant programming information to flash memory when writing data to it, so that the write operation can be performed.

[0205] Figure 6 This is a schematic diagram of the structure of an address allocation device provided in an embodiment of this disclosure; as shown below. Figure 6 As shown, the device is applied to a solid-state drive, and the device includes:

[0206] The acquisition module is used to retrieve snapshot information in response to write requests;

[0207] The processing module is used to allocate physical block addresses corresponding to logical block addresses of at least one piece of data using the snapshot information according to the mapping rules; wherein the snapshot information is used to allocate adjacent logical block addresses to physical block addresses located in different regions.

[0208] In some embodiments, the apparatus further includes: a generation module for generating snapshot information, the snapshot information including: an offset snapshot; the offset snapshot is used to record the offset relationship between physical block addresses.

[0209] In some embodiments, the processing module is configured to use the snapshot information to allocate the physical block address corresponding to the logical block address of at least one data on each multiword line.

[0210] In some embodiments, the generation module is used to obtain a first number and a second number of word lines, wherein the first number is the number of page layers for each word line, and the second number is the number of planes involved in the parallel storage operation of the word line;

[0211] Construct a first matrix, a second matrix, and a third matrix based on the first quantity and the second quantity;

[0212] Based on the first matrix, the second matrix, and the third matrix, an offset snapshot is obtained;

[0213] The first matrix is ​​used to record pages with allocable physical block addresses using diagonal lines;

[0214] The second matrix is ​​used to shift the allocation order of the pages;

[0215] The third matrix is ​​used to accumulate the number of pages with allocable physical block addresses.

[0216] In some embodiments, the number of rows in the first matrix is ​​related to the first quantity, and the number of columns in the first matrix is ​​related to the second quantity;

[0217] The number of rows in the second matrix is ​​related to the second quantity, and the number of columns in the second matrix is ​​related to the second quantity;

[0218] The number of rows in the third matrix is ​​related to the first quantity, and the number of columns in the third matrix is ​​related to the second quantity.

[0219] In some embodiments, the generation module is configured to determine the total number of iterations based on a second quantity;

[0220] The order matrix is ​​processed sequentially according to the total number of iterations to obtain the target order matrix. Each process includes: determining the product of the iteration number and the third matrix, adding the product to the first matrix to obtain the translation result, multiplying the translation result by the second matrix, and then adding it to the order matrix of the previous round.

[0221] The offset snapshot is determined based on the target order matrix.

[0222] In some embodiments, the target order matrix is ​​used to indicate the planes corresponding to the multiple physical block addresses, and the corresponding LSB, CSB, MSB or TSB;

[0223] The generation module is used to determine the plane where multiple physical block addresses are located, and the LSB, CSB, MSB or TSB where they are located, according to the target order matrix; each physical block address corresponds to an allocation order, the planes of physical block addresses with adjacent allocation orders are different, and the LSB, CSB, MSB or TSB of physical block addresses with adjacent allocation orders are different.

[0224] In some embodiments, the logical block address of each data in the multi-word line corresponds to an index;

[0225] The processing module is configured to allocate an index set to the multi-word line, the index set including at least one index of a physical block address, the index representing the allocation order of the physical block addresses;

[0226] The first physical block address corresponding to the first logical block address is allocated according to the index set, where the first logical block address is the logical block address of the starting data on the multiword line;

[0227] Based on the physical block address corresponding to the first logical block address, the difference between the first physical block address and the second physical block address, and the offset snapshot, a second physical block address corresponding to the second logical block address is allocated; the second logical block address is the logical block address of data other than the non-starting data on the multi-word line; the index of the first physical block address takes precedence over the index of the second physical block address.

[0228] In some embodiments, the processing module is further configured to query whether the block containing the physical block address is a bad block;

[0229] If the block containing the physical block address is a bad block, update the index set to delete or skip the physical block addresses associated with the bad block.

[0230] In some embodiments, the processing module is further configured to determine a mapping table based on the logical block address of each piece of data and the physical block address in the solid-state storage unit, wherein the mapping table is used to record the mapping relationship between the logical block address and the physical block address of each piece of data;

[0231] Upon receiving a read request, the system queries the mapping table based on the logical block address carried in the read request to determine the physical block address corresponding to the read request.

[0232] In some embodiments, the solid-state drive is a QLC solid-state drive, which includes multiple planes, each plane including multiple blocks, each block including multiple pages, and the multiple pages including: LSB, CSB, MSB, and TSB;

[0233] The physical block addresses within the different regions include:

[0234] The planes of the physical block addresses are different, and the LSB, CSB, MSB, or TSB of the physical block addresses are different.

[0235] It is understood that, when implementing the corresponding address allocation method, the address allocation apparatus provided in the above embodiments can assign the above processing to different program modules as needed to complete all or part of the processing described above. Furthermore, the apparatus and the corresponding method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0236] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform an address allocation method.

[0237] This application provides a computer-readable storage medium storing executable instructions. When the executable instructions are executed by a processor, the processor will execute the address allocation method provided in this application.

[0238] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0239] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0240] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborating files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0241] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0242] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure; as shown below. Figure 7 As shown, the electronic device 70 includes: a processor 701, and a memory 702 communicatively connected to the processor 701; the memory 702 stores instructions executable by the processor 701. The instructions are executed by the processor 701 to enable the processor 701 to perform:

[0243] In response to a write request, snapshot information is obtained; according to the mapping rules, the physical block address corresponding to the logical block address of at least one piece of data is allocated using the snapshot information; wherein, the snapshot information is used to allocate adjacent logical block addresses to physical block addresses located in different regions.

[0244] The electronic device may be a solid-state drive (SSD), and the processor may be the controller of the SSD, which allocates physical block addresses based on an address allocation method.

[0245] The electronic devices and corresponding address allocation methods provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0246] In practical applications, the electronic device 70 may further include at least one network interface 703. The various components of the electronic device 70 are coupled together via a bus system 704. It is understood that the bus system 704 is used to implement communication between these components. In addition to a data bus, the bus system 704 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 7 All buses are labeled as bus system 704. The number of processors 701 and the number of memories 702 can be at least one. The network interface 703 is used for wired or wireless communication between the electronic device 70 and other devices.

[0247] The memory 702 in this embodiment is used to store various types of data to support the operation of the electronic device 70.

[0248] The methods disclosed in the above embodiments of this disclosure can be applied to processor 701, or implemented by processor 701. Processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 701 or by instructions in the form of software. The processor 701 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 701 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 702. Processor 701 reads the information in memory 702 and, in conjunction with its hardware, completes the steps of the aforementioned address allocation method.

[0249] In some embodiments, the electronic device 70 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned methods.

[0250] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0251] In the above description, the term "some embodiments" refers to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0252] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0253] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0254] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0255] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An address allocation method characterized by, The method is applied to a solid state disk, and the method comprises: In response to a write request, snapshot information is obtained; According to a mapping rule, a physical block address corresponding to a logical block address of at least one data is allocated by using the snapshot information; wherein the snapshot information is used to allocate adjacent logical block addresses to physical block addresses in different areas; the physical block addresses in the different areas include: the planes of the physical block addresses are different, and the LSB, CSB, MSB or TSB of the physical block addresses are different; The method further comprises: generating snapshot information, the snapshot information comprising: an offset snapshot; the offset snapshot is used to record the offset relationship between the physical block addresses; The offset snapshot is generated, comprising: A first number and a second number of multiple word lines are obtained, the first number being the number of pages that each word line has, and the second number being the number of planes involved in parallel storage operation of the word lines; A first matrix, a second matrix and a third matrix are constructed according to the first number and the second number; According to the first matrix, the second matrix and the third matrix, an offset snapshot is obtained; The first matrix is used to record the pages of the allocable physical block addresses by using the diagonal lines; The second matrix is used to shift the allocation order of the pages; The third matrix is used to accumulate the number of pages of the allocable physical block addresses.

2. The method of claim 1, wherein, The allocation of the physical block address corresponding to the logical block address of at least one data by using the snapshot information comprises: The allocation of the physical block address corresponding to the logical block address of at least one data on each multiple word line by using the snapshot information.

3. The method of claim 1, wherein, The number of rows of the first matrix is related to the first number, and the number of columns of the first matrix is related to the second number; The number of rows of the second matrix is related to the second number, and the number of columns of the second matrix is related to the second number; The number of rows of the third matrix is related to the first number, and the number of columns of the third matrix is related to the second number.

4. The method of claim 1, wherein, The obtaining of the offset snapshot according to the first matrix, the second matrix and the third matrix comprises: The total number of iterations is determined according to the second number; The target order matrix is obtained by processing the order matrix according to the total number of iterations, each processing comprising: determining the product of the iteration number and the third matrix, adding the product and the first matrix to obtain a shift result, and adding the shift result and the second matrix to the order matrix of the last round; The offset snapshot is determined according to the target order matrix.

5. The method of claim 4, wherein, The target order matrix is used to indicate the planes to which a plurality of physical block addresses correspond respectively, and the corresponding LSB, CSB, MSB or TSB; The determination of the offset snapshot according to the target order matrix comprises: According to the target order matrix, the planes where a plurality of physical block addresses are located, and the LSB, CSB, MSB or TSB are determined; each physical block address corresponds to an allocation order, the planes of the physical block addresses of adjacent allocation orders are different, and the LSB, CSB, MSB or TSB of the physical block addresses of adjacent allocation orders are different.

6. The method of claim 2, wherein, Distributing, by using the snapshot information, a physical block address corresponding to a logical block address of at least one data on each multi-word line, comprises: allocating an index set to the multi-word line, the index set comprising indexes of at least one physical block address, the indexes representing an allocation sequence of the physical block addresses; allocating a first physical block address corresponding to a first logical block address according to the index set, the first logical block address being a logical block address of starting data on the multi-word line; allocating a second physical block address corresponding to a second logical block address according to a difference between the first physical block address and a second physical block address, the second logical block address being a logical block address of other data than the starting data on the multi-word line, and an offset snapshot, the index of the first physical block address being prior to the index of the second physical block address.

7. The method of claim 6, wherein, The method further comprises: inquiring whether a block where the physical block address is located is a bad block; if the block where the physical block address is located is the bad block, updating the index set to delete or skip the physical block address related to the bad block.

8. The method of claim 1, wherein, The method further comprises: determining a mapping table according to the logical block address of each data and the physical block address in the solid-state storage unit, the mapping table being used to record a mapping relationship between the logical block address of each data and the physical block address; receiving a read request, and inquiring the mapping table according to a logical block address carried by the read request to determine a physical block address corresponding to the read request.

9. The method of claim 1, wherein, The solid-state drive is a four-bit storage unit QLC solid-state drive, the QLC solid-state drive comprising a plurality of planes, each plane comprising a plurality of blocks, and each block comprising a plurality of pages, the plurality of pages comprising: LSB, CSB, MSB, and TSB.

10. An address allocation apparatus characterized by comprising: The device is applied to a solid-state drive, and the device comprises: an acquisition module configured to acquire snapshot information in response to a write request; a processing module configured to distribute, according to a mapping rule, a physical block address corresponding to a logical block address of at least one data by using the snapshot information, wherein the snapshot information is used to distribute adjacent logical block addresses to physical block addresses located in different areas, and the physical block addresses in the different areas comprise different planes of physical block addresses and different LSBs, CSBs, MSBs, or TSBs of physical block addresses; the device further comprises a generation module configured to generate snapshot information, the snapshot information comprising an offset snapshot used to record an offset relationship between physical block addresses; the generation module is configured to acquire a first number and a second number of multi-word lines, the first number being a number of page layers possessed by each word line, and the second number being a number of planes involved in parallel storage operations of the word lines; constructing a first matrix, a second matrix, and a third matrix according to the first number and the second number; obtaining an offset snapshot according to the first matrix, the second matrix, and the third matrix; wherein the first matrix is used to record pages of allocable physical block addresses by using diagonal lines; the second matrix is used to translate an allocation sequence of the pages; and the third matrix is used to accumulate a number of pages of allocable physical block addresses.

11. The apparatus of claim 10, wherein, The solid state disk is a QLC solid state disk, the QLC solid state disk comprises a plurality of planes, each of the planes comprises a plurality of blocks, each of the blocks comprises a plurality of pages, and the plurality of pages comprises an LSB, a CSB, an MSB and a TSB.

12. An electronic device, comprising: Comprise: At least one processor; And a memory connected in communication with the at least one processor; wherein The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method of any one of claims 1 to 9.

13. A non-transitory computer-readable storage medium having stored thereon computer instructions, wherein, The computer instructions are used to enable the computer to execute the method of any one of claims 1 to 9.

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