A low-power arbitration module

Abstract

The present invention discloses a low-power arbitration module, comprising an arbitration unit, which includes a request arbitration result unit, a response unit, a request output unit, an arbitration update unit, an arbitration result register, and a two-way selector. The arbitration update unit obtains the current arbitration result and sends the current arbitration result of the successful arbitration to the arbitration result register for storage, so that it can be output by the arbitration result register during the next data transmission. The two-way selector selects one of the arbitration results stored in the arbitration result register and the arbitration result signal output by the request arbitration result unit according to the request arbitration signal and outputs it to the data multiplexer, so that the data multiplexer selects one of all the data to be transmitted for output. When all the request signals are invalid requests, the two-way selector selects the arbitration result stored in the arbitration result register for output to prevent the output of invalid data. The present invention solves the problem of invalid flipping caused by outputting invalid data, thereby reducing power consumption.

Description

Technical Field

[0001] The present invention relates to an arbitration module, in particular to an arbitration module with low power consumption. Background Art

[0002] The arbitration module (also known as the arbiter) is a key component within the chip. It is responsible for data arbitration, that is, it arbitrates multiple data channels and selects one data output. It is used to manage competing signals for access to shared resources. Different arbitration strategies are available, suitable for different scenarios, such as fixed priority and round-robin scheduling.

[0003] like Figure 1 and Figure 2 The figure shows the structure of the traditional arbitration module 60 by taking 3 input fixed priority as an example, which includes an arbitration unit 10 and a data multiplexer 20. The arbitration unit 10 is used to receive a request signal (such as Figure 1 The arbitration module 60 receives the three request signals valid_0, valid_1, and valid_2 shown in the figure and processes the request signals, transmits the request arbitration signal valid_arb obtained after the processing to a subsequent module (not shown in the figure, any logic circuit can be used without limitation) located after the arbitration module 60, and receives the response arbitration signal ready_arb made by the subsequent module according to the request arbitration signal valid_arb and feeds back a response signal (such as the response arbitration signal ready_arb and the arbitration result signal arb_result made according to the request signals) based on the response arbitration signal ready_arb. Figure 1 The data multiplexer 20 is used to receive data (such as 3 response signals ready_0, ready_1, and ready_2). The response signals ready_0, ready_1, and ready_2 are paired with the request signals valid_0, valid_1, and valid_2 respectively. Figure 1 (The three data items (payload_0, payload_1, and payload_2) shown correspond to request signals valid_0, valid_1, and valid_2, respectively.) Based on the arbitration result signal arb_result generated by arbitration unit 10, the corresponding data item is selected from all the data items and output as data arbitration signal payload_arb to the subsequent module. For example, when the pair of signals valid_0 and ready_0 are both high, it indicates successful arbitration. The corresponding data item payload_0 is then output as data arbitration signal payload_arb via data multiplexer 20 to the subsequent module by selecting the corresponding arbitration result signal arb_result.

[0004] by Figure 2The control logic diagram further illustrates that the arbitration unit 10 includes a request arbitration result unit 15, a response unit 16, and a request output unit 17. The request signal is input to the request arbitration result unit 15 to generate an arbitration result signal arb_result. The request signal is input to the request output unit 17 to generate a request arbitration signal valid_arb. The arbitration result signal arb_result output by the request arbitration result unit 15 and the response arbitration signal ready_arb generated by the subsequent module are input to the response unit 16 to generate a response signal. Generally, the request arbitration result unit 15 is composed of a first AND gate 11 and a NOT gate 12, the response unit 16 is composed of a second AND gate 13, and the request output unit 17 is composed of an OR gate 14. Figure 2 The data multiplexer 20 is composed of an AND gate group 21 and an OR gate group 22. The data and the arbitration result signal arb_result are input into the data multiplexer 20 to select one of the multiple data for output. Here, the priority relationship of each data is set as: payload_0>payload_1>payload_2. Take the arbitration transmission data payload_1 as an example, see Figure 2 As shown by the red dotted line in the figure, since data payload_0 has a higher priority than data payload_1, the request signal valid_0 must be low at this time (if valid_0 is not low, data payload_0 will successfully arbitrate, not data payload_1). Therefore, when the request signal valid_0 is low and valid_1 is high, the first AND gate 11 indicated by label 71 will output a high level. This high level will cause the AND gate group 21 indicated by label 72 and the second AND gate 13 indicated by label 73 to output a high level. In other words, data payload_1 is selected and output as the data arbitration signal payload_arb. At the same time, the response arbitration signal ready_arb is output through the response signal ready_1 to respond to the request signal valid_1.

[0005] From the above control logic, we can see that when there is no valid request signal, that is, the request signals valid_0, valid_1 and valid_2 are all low, the data arbitration signal payload_arb is output as 0. In other words, every time a batch of data is transmitted, the data arbitration signal payload_arb will output invalid data (that is, not the data to be output), that is, an invalid flip occurs. Figure 3 In the interface timing diagram shown, the data marked with a red circle is invalid data, which leads to invalid flipping. In actual operation, invalid flipping means waste of chip power consumption.

[0006] Furthermore, assuming the response arbitration signal ready_arb is constantly high, two extreme scenarios arise for conventional arbitration module 60: Scenario 1 involves continuous data transmission, meaning a valid request signal is always present. In this case, invalid data and no invalid flips will occur in the data arbitration signal payload_arb. Scenario 2 involves transmitting only one data item at a time. In this case, invalid data will occur in the data arbitration signal payload_arb after each data item is transmitted, resulting in a doubling of the total invalid data output, i.e., a doubling of invalid flips. As can be seen, the larger the data transmission bandwidth, the greater the number of data items transmitted continuously each time, approaching scenario 1, and the invalid flip rate approaches 0%. Conversely, the smaller the data transmission bandwidth, the smaller the number of data items transmitted continuously each time, approaching scenario 2, and the invalid flip rate approaches 100%. Here, the invalid flip rate is defined as the number of invalid flips divided by the number of valid flips. Outputting an invalid data item necessitates an invalid flip, while a flip occurring when valid data is output is considered a valid flip.

[0007] As can be seen from the above, no matter the application scenario is large or small in data transmission bandwidth (unless the theoretical maximum bandwidth is reached), there is a problem of outputting invalid data leading to invalid flipping. Therefore, how to solve the problem of invalid data output is currently in urgent need of solution. Summary of the Invention

[0008] The object of the present invention is to provide a low-power arbitration module, which solves the problem of invalid flipping caused by outputting invalid data, thereby reducing power consumption.

[0009] In order to achieve the above object, the present invention adopts the following technical solutions:

[0010] A low-power arbitration module includes an arbitration unit and a data multiplexer. The arbitration unit includes a request arbitration result unit, a response unit, and a request output unit. The request arbitration result unit is used to receive a request signal and output an arbitration result signal. The request output unit is used to receive a request signal and output a request arbitration signal. The response unit is used to receive the arbitration result signal and a response arbitration signal output by a subsequent module and output a response signal. In particular, the arbitration unit also includes an arbitration update unit, an arbitration result register, and a two-way selector. The arbitration update unit is used to receive the arbitration result signal, the request arbitration signal, and the response arbitration signal to obtain a current arbitration result, and send the current arbitration result determined to be successful to the arbitration result register. The arbitration result register is used to store the current arbitration result of the received successful arbitration and output it during the next data transmission; the two-way selector is used to select one of the arbitration result stored in the arbitration result register and the arbitration result signal output by the request arbitration result unit according to the request arbitration signal and output it to the data multiplexer, so that the data multiplexer selects one from all the data to be transmitted and outputs it, thereby completing the data transmission operation. When each of the request signals is an invalid request, the two-way selector selects the arbitration result stored in the arbitration result register for output according to the request arbitration signal, so that the data multiplexer selects one from all the data according to the arbitration result output by the arbitration result register and outputs it, thereby preventing the output of invalid data.

[0011] The advantages of the present invention are:

[0012] The present invention adds an arbitration update unit and an arbitration result register to the arbitration unit, thereby eliminating the output of invalid data, avoiding invalid flips, and eliminating the problem of chip power consumption waste caused by invalid flips. The present invention is suitable for both applications with large data transmission bandwidth and applications with small data transmission bandwidth. In addition, the present invention has little new control logic and will not affect the total chip area, and the chip performance is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a block diagram of a traditional arbitration module.

[0014] Figure 2 It is the control logic diagram of the traditional arbitration module.

[0015] Figure 3 This is the interface timing diagram of the traditional arbitration module.

[0016] Figure 4 This is a control logic diagram of the low-power arbitration module of the present invention.

[0017] Figure 5 This is an interface timing diagram of the low-power arbitration module of the present invention. DETAILED DESCRIPTION

[0018] like Figure 4 and Figure 5As shown, the present invention proposes a low-power arbitration module 60', which is an improvement on the traditional arbitration module 60. Specifically, the low-power arbitration module 60' of the present invention includes an arbitration unit 10' and a data multiplexer 20. The arbitration unit 10' includes a request arbitration result unit 15, a response unit 16, and a request output unit 17. The request arbitration result unit 15 is used to receive a request signal and output an arbitration result signal arb_result. The request output unit 17 is used to receive a request signal and output a request arbitration signal valid_arb. The response unit 16 is used to receive the arbitration result signal arb_result output by the request arbitration result unit 15 and the response arbitration signal output by the subsequent module. ready_arb and outputs a response signal. Specifically, the arbitration unit 10' further includes an arbitration update unit 30, an arbitration result register 40, and a dual selector 50, wherein: the arbitration update unit 30 is used to receive the arbitration result signal arb_result output by the arbitration result request unit 15, the request arbitration signal valid_arb output by the request output unit 17, and the response arbitration signal ready_arb output by the subsequent module, so as to obtain the current arbitration result based on the arbitration result signal arb_result, the request arbitration signal valid_arb, and the response arbitration signal ready_arb, and send the current arbitration result determined to be successful to the arbitration result register. The arbitration result register 40 is used to store the current arbitration result of the arbitration success received and output it during the next data transmission; the dual selector 50 is used to select one of the arbitration result stored in the arbitration result register 40 and the arbitration result signal arb_result output by the arbitration result request unit 15 according to the arbitration request signal valid_arb and output it to the data multiplexer 20, so that the data multiplexer 20 selects one from all the data to be transmitted to output, that is, outputs the data arbitration signal payload_arb to complete the data transmission operation, wherein, when the request signals received by the request output unit 17 are all invalid requests, the dual selector 50 selects one from the arbitration result stored in the arbitration result register 40 and the arbitration result signal arb_result output by the arbitration result request unit 15 according to the arbitration request signal valid_arb valid_arb selects the arbitration result stored in the arbitration result register 40 (the arbitration result of the most recent successful arbitration) for output, so that the data multiplexer 20 selects one from all the data for output according to the arbitration result output by the arbitration result register 40, that is, continues to output the original valid data to prevent the output of invalid data. Conversely, when there is a valid request among the request signals received by the request output unit 17, the dual selector 50 selects the arbitration result signal arb_result output by the request arbitration result unit 15 for output according to the request arbitration signal valid_arb, so that the data multiplexer 20 selects one from all the data for output according to the arbitration result signal arb_result.

[0019] In the present invention, the arbitration result is divided into successful arbitration or unsuccessful arbitration. When the request arbitration signal valid_arb output by the request output unit 17 and the response arbitration signal ready_arb output by the subsequent module are both high, it indicates that the arbitration is successful. Otherwise, it indicates that the arbitration is unsuccessful. In addition, the arbitration result of successful arbitration stored in the arbitration result register 40 is the arbitration result signal arb_result output by the request arbitration result unit 15.

[0020] In actual implementation, when the request arbitration signal valid_arb output by the request output unit 17 is at a low level, it indicates that all request signals are invalid requests, that is, there are no valid requests. Conversely, when the request arbitration signal valid_arb is at a high level, it indicates that there are valid requests among all request signals.

[0021] Furthermore, when there is a valid request among the request signals received by the request output unit 17, that is, when the request arbitration signal valid_arb is at a high level (a valid request signal is present), the dual selector 50 outputs the arbitration result signal arb_result to the data multiplexer 20, so that the data multiplexer 20 outputs the corresponding valid data according to the current arbitration result (arbitration result signal arb_result).

[0022] In the present invention, when no valid request signals are present (i.e., when request signals valid_0, valid_1, and valid_2 are all low), the arbitration request signal valid_arb is low, and the dual selector 50 outputs the arbitration result (arbitration success) stored in the arbitration result register 40. Then, the data multiplexer 20 continues to output the original valid data, preventing the output of invalid data. Furthermore, this avoids the situation in which, as in conventional arbitration module 60, the data arbitration signal payload_arb outputted by the data multiplexer 20 is 0, which is invalid data and not the data actually intended to be output, resulting in an invalid flip.

[0023] like Figure 4 The arbitration result request unit 15 includes a first AND gate 11 and a NOT gate 12 . The arbitration result request unit 15 is configured to output an arbitration result signal arb_result for each request signal.

[0024] In the present invention, the arbitration result request unit 15 can be reasonably designed according to a set arbitration strategy, which is a well-known technique in the art. The arbitration strategy may be, for example, fixed priority or round-robin. Figure 4The composition of the request arbitration result unit 15 is illustrated using a three-input fixed priority level as an example. Specifically, the request signal with the highest priority is directly output as the arbitration result signal arb_result. Request signals with other priorities are each provided with a first AND gate 11. Specifically, the first AND gate 11 receives the request signal corresponding to it and the signals output by all request signals with higher priority than that request signal after passing through a NOT gate 12. The AND operation is then performed on these signals to output the arbitration result signal arb_result.

[0025] like Figure 4 The response unit 16 includes a plurality of second AND gates 13 in parallel, each second AND gate 13 is used to receive the response arbitration signal ready_arb and the corresponding arbitration result signal arb_result to output a response signal, wherein each response signal output by the response unit 16 corresponds to each request signal one by one, forming a pair.

[0026] like Figure 4 The request output unit 17 includes an OR gate 14 , which is used to perform an OR calculation on each request signal and output the calculation result to the arbitration update unit 30 and each dual selector 50 .

[0027] like Figure 4 Each arbitration result signal arb_result output by the arbitration result request unit 15 is input into a corresponding dual-way selector 50 .

[0028] like Figure 4 The data multiplexer 20 includes an AND gate group 21 and an OR gate group 22. Each dual-way selector 50 is set corresponding to an AND gate group 21. The AND gate group 21 is used to receive the selection signal output by the corresponding dual-way selector 50 and the corresponding data. The OR gate group 22 is used to receive the calculation signal of each AND gate group 21 and perform OR calculation to select one from all the data for output, that is, to output the data arbitration signal payload_arb, where: each data corresponds to a request signal.

[0029] In the present invention, the AND gate group 21 is composed of a plurality of parallel AND gates, and the number of AND gates is equal to the bit width of the data. Similarly, the OR gate group 22 is composed of a plurality of parallel OR gates, and the number of OR gates is equal to the bit width of the data. For example, if the input data is binary data with a width of n bits, the number of AND gates in each AND gate group 21 and the number of OR gates in each OR gate group 22 are n, as shown in FIG. Figure 4 , the figure shows the composition of the AND gate group 21 and the OR gate group 22 with n bits width.

[0030] In the present invention, some contents in the module structure of the chip are represented in a simplified manner, for example, the slash on the signal line and the number on it (such as Figure 4The 3 or n) in the 10-bit 10-bit 0-bit 0-bit 1-bit 0 ...

[0031] In the present invention, the request arbitration result unit 15, response unit 16, request output unit 17, and data multiplexer 20 are identical to conventional arbitration module 60. The arbitration update unit 30 is comprised of well-known logic components such as AND gates and OR gates. This is well-known technology, and its specific structure is not limited and will not be described in detail here. The arbitration result register 40 is a register that only buffers the value of an arbitration result. The bit width of the arbitration result is the same as the bit width of the data to be transmitted. The dual selector 50 is a mux device well-known in the art.

[0032] The new control logic of the present invention effectively solves the problem of invalid data causing invalid flipping in the above scenario 2.

[0033] like Figure 4 , Figure 4The structure of arbitration module 60' is illustrated using a three-input fixed priority system as an example. The data priority relationship among the three inputs is set as: payload_0 > payload_1 > payload_2. The request arbitration result unit 15 receives three request signals, valid_0, valid_1, and valid_2, and outputs three arbitration result signals, arb_result. These three request signals, valid_0, valid_1, and valid_2, are transmitted to the subsequent module via the request output unit 17 (which is an OR gate 14) as a request arbitration signal, valid_arb. The three arbitration result signals, arb_result, are split into two paths: one path, along with the response arbitration signal, ready_arb, from the subsequent module, is input to the response unit 16 (which includes three parallel second AND gates 13). The response unit 16 then outputs three response signals, ready_0, ready_1, and ready_2. The request signals valid_0, valid_1, and valid_2 correspond to the three input data payload_0, payload_1, and payload_2 respectively, and the three response signals ready_0, ready_1, and ready_2 correspond to the request signals valid_0, valid_1, and valid_2 respectively, forming a pair. The other input corresponds to the dual-way selector 50. The arbitration result signal arb_result output by the request arbitration result unit 15, the request arbitration signal valid_arb output by the request output unit 17, and the response arbitration signal ready_arb output by the subsequent module are sent to the arbitration update unit 30. The arbitration update unit 30 performs relevant logical calculations to obtain the current arbitration result. If the current arbitration result is a successful arbitration result, the current arbitration result is sent to the arbitration result register 40. The arbitration result register 40 updates its content to the current arbitration result and outputs it to each dual-way selector 50 during the next data transmission. As Figure 4There are three dual selectors 50, one corresponding to each arbitration result signal arb_result. The data multiplexer 20 is equipped with three AND gate groups 21 and one OR gate group 22. Each AND gate group 21 is associated with a dual selector 50. Each dual selector 50 receives a corresponding arbitration result signal arb_result and a corresponding bit value in the arbitration result output by the arbitration result register 40. Based on the arbitration request signal valid_arb, it selects and outputs either the arbitration result output by the arbitration result register 40 or the arbitration result signal arb_result. Each AND gate group 21 receives a select signal output by the corresponding dual selector 50 and a corresponding piece of data. Each AND gate performs an AND operation on each bit of the data and the select signal. The calculated signal output by each AND gate group 21 is input to the OR gate group 22, which then performs the OR operation and outputs the data arbitration signal payload_arb, which represents the data requested for transmission (valid data) to implement the data transmission operation.

[0034] Here, when the three request signals valid_0, valid_1, and valid_2 are all invalid requests, the dual selector 50 outputs the arbitration result of the most recent successful arbitration stored in the arbitration result register 40 (i.e., the arbitration result signal arb_result output by the request arbitration result unit 15 when the most recent arbitration is determined to be successful). Otherwise, it outputs the arbitration result signal arb_result currently output by the request arbitration result unit 15. In this way, when there are no valid request signals, the dual selector 50 outputs the arbitration result output by the arbitration result register 40 as the selection signal, that is, causes the data multiplexer 20 to continue outputting the valid data transmitted most recently. This effectively prevents the output of invalid data, avoids the situation in which the output of invalid data causes invalid flipping as occurs in the conventional arbitration module 60, and solves the problem of wasted chip power consumption.

[0035] like Figure 5 , Figure 5 The interface timing diagram of the arbitration module 60' of the present invention after improving the traditional arbitration module 60 is shown. Figure 3 , Figure 5 The data arbitration signal payload_arb in the FPGA no longer has invalid data, eliminating invalid flips and avoiding waste of chip power consumption.

[0036] Generally speaking, the data bit width is much larger than the arbitration result bit width (i.e., the number of request signals). For example, the input data bit width is 128, while the arbitration result bit width for a 3-input fixed priority is 3. Therefore, the power savings from the addition of arbitration update unit 30, arbitration result register 40, and dual selector 50 far outweigh the power consumption they generate. Therefore, as long as the actual data transmission bandwidth is less than the theoretical bandwidth and the data is not constantly zero, the present invention can achieve the effect of reducing power consumption. Furthermore, the smaller the bandwidth and the greater the input data variability, the greater the power reduction effect. In the special case where the actual bandwidth equals the theoretical bandwidth, the total module power consumption is very high, so the power consumption overhead caused by the addition of arbitration update unit 30, arbitration result register 40, and dual selector 50 is very small and negligible.

[0037] In summary, the present invention eliminates the waste of chip power consumption caused by invalid flipping. In addition, the newly added device of the present invention basically does not increase power consumption at high bandwidth, and is suitable for applications with large data transmission bandwidth. It can save power consumption at low bandwidth and is more suitable for applications with small data transmission bandwidth. Moreover, the present invention has little new control logic, will not affect the total chip area, and the chip performance can be maintained well.

[0038] The above are preferred embodiments of the present invention and the technical principles used therein. For those skilled in the art, any obvious changes such as equivalent transformations, simple replacements, etc. based on the technical solution of the present invention, without departing from the spirit and scope of the present invention, are within the scope of protection of the present invention.

Claims

1. A low-power arbitration module, comprising an arbitration unit and a data multiplexer, wherein the arbitration unit comprises a request arbitration result unit, a response unit, and a request output unit, wherein the request arbitration result unit is configured to receive a request signal and output an arbitration result signal, the request output unit is configured to receive a request signal and output a request arbitration signal, and the response unit is configured to receive the arbitration result signal and a response arbitration signal output by a subsequent module and output a response signal, characterized in that: The arbitration unit further includes an arbitration update unit, an arbitration result register, and a two-way selector, wherein: the arbitration update unit is used to receive an arbitration result signal, an arbitration request signal, and an arbitration response signal to obtain a current arbitration result, and send the current arbitration result determined to be successful to the arbitration result register; the arbitration result register is used to store the received current arbitration result of successful arbitration and output it during the next data transmission; the two-way selector is used to select one of the arbitration result stored in the arbitration result register and the arbitration result signal output by the arbitration request signal and output it to the data multiplexer, so that the arbitration result is received. The data multiplexer selects one data from all data to be transmitted and outputs it, completing the data transmission operation. When each of the request signals is an invalid request, the dual-way selector selects the arbitration result stored in the arbitration result register for output according to the request arbitration signal, so that the data multiplexer selects one data from all data for output according to the arbitration result output by the arbitration result register, thereby preventing the output of invalid data. When a valid request is present among the request signals received by the request output unit, the dual-way selector outputs the arbitration result signal to the data multiplexer, so that the data multiplexer outputs the corresponding valid data according to the current arbitration result.

2. The low-power arbitration module according to claim 1, wherein: The arbitration result is divided into successful arbitration or unsuccessful arbitration, wherein when the request arbitration signal and the response arbitration signal are both at a high level, it indicates that the arbitration is successful, and the arbitration result of successful arbitration stored in the arbitration result register is the arbitration result signal output by the request arbitration result unit.

3. The low-power arbitration module according to claim 2, wherein: When the request arbitration signal is at a low level, it indicates that all the request signals are invalid requests. Conversely, when the request arbitration signal is at a high level, it indicates that there are valid requests among all the request signals.

4. The low-power arbitration module according to claim 3, wherein: The request arbitration result unit includes a first AND gate and a NOT gate, and is configured to output an arbitration result signal for each request signal.

5. The low-power arbitration module according to claim 4, wherein: The response unit includes a plurality of second AND gates in parallel, each of the second AND gates is used to receive the response arbitration signal and the corresponding arbitration result signal to output a response signal, wherein each response signal output by the response unit corresponds to each request signal one by one.

6. The low-power arbitration module according to claim 3, wherein: The request output unit includes an OR gate, and the OR gate is used to perform an OR calculation on each request signal and output the calculation result to the arbitration update unit and each of the two-way selectors.

7. The low-power arbitration module according to claim 6, wherein: Each arbitration result signal output by the arbitration result request unit is input into a corresponding dual-way selector.

8. The low-power arbitration module according to claim 7, wherein: The data multiplexer includes an AND gate group and an OR gate group. Each of the two-way selectors is arranged corresponding to an AND gate group. The AND gate group is used to receive the selection signal output by the corresponding two-way selector and the corresponding data. The OR gate group is used to receive the calculation signal of each AND gate group and perform OR calculation to select one from all the data for output, wherein: each data corresponds to a request signal.

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