A method for storing test data

Abstract

The present application discloses a method for storing test data, which belongs to the field of chip production and manufacturing technology. The method for storing test data includes: providing a wafer to be tested, on which there are multiple die to be tested, and each die to be tested includes multiple light-emitting channels; performing wafer-level testing on the wafer to be tested to obtain test data of the wafer to be tested; wherein, the order of wafer-level testing is to test all light-emitting channels of a die to be tested in sequence, and then switch to the next die to be tested; and storing the test data; wherein, the stored test data carries a position label of each light-emitting channel on the die to be tested to which it belongs. In this way, when there are many chip channels, the wafer performance test data of each channel is associated with the position label of each channel on the die to be tested to which it belongs, and then stored, so that the test data is clear and easy to find, and the storage accuracy of the test data is also improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip production and manufacturing, and in particular to a method for storing test data. Background Art

[0002] Wafers are the starting material for semiconductor chip manufacturing and carry the entire chip manufacturing process. They primarily include: GaAs (gallium arsenide), InGaAs (indium gallium arsenide), GaN (gallium nitride), InGaN (indium gallium nitride), and AlInGaP (aluminum indium gallium phosphide). During the semiconductor manufacturing process, multiple die (DIEs) are formed on the wafer. Dies are then separated into individual dies through a cutting process (such as scribing or laser cutting). Dies typically appear as tiny rectangular or square slices, ranging in size from a few millimeters to tens of millimeters depending on the application. A chip typically refers to the packaged die. Common chips include 2DMA (Direct Memory Access) two-dimensional addressable arrays.

[0003] The entire wafer undergoes post-process WT (Wafer Test) testing, specifically testing the electrical characteristics of each die on the wafer, such as power, to ensure that the die that pass the process enters the packaging stage. The chip undergoes post-process FT (Final Test) testing, specifically performing electrical connectivity tests, functional tests, and parameter tests on the chip to screen out chips that meet the design specifications.

[0004] Whether testing wafers or chips, testing is performed on a channel-by-channel basis. Each chip has many channels, and each channel generates a large amount of data. For example, the data volume from spectral testing and LIV (Light-Current-Voltage) testing is enormous. Therefore, with so many channels, the question of how to store test data in a clear and easy-to-search manner is a pressing technical challenge. Summary of the Invention

[0005] The main technical problem solved by the present invention is how to improve the convenience of test data search when there are many wafers and chip channels.

[0006] According to the first aspect, an embodiment provides a method for storing test data, the method comprising:

[0007] Providing a wafer to be tested, wherein the wafer to be tested has a plurality of dies to be tested, and each dies to be tested includes a plurality of light emitting channels;

[0008] Performing wafer-level testing on the wafer to be tested to obtain test data of the wafer to be tested; wherein the order of the wafer-level testing is to test all light-emitting channels of a wafer to be tested in sequence and then switch to the next wafer to be tested; and

[0009] The test data is stored; wherein the stored test data carries a position label of each light-emitting channel on the die to be tested to which it belongs.

[0010] According to a test data storage method of the above embodiment, when there are many chip channels, the convenience of test data search is further improved by associating the wafer performance test data of each channel with the position label of each channel on the die to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A flow chart of a test data storage method provided in this embodiment;

[0012] Figure 2 A chip direction identification bit provided in this embodiment;

[0013] Figure 3 This is a schematic diagram of the data levels after the FT test is performed on the chip provided in this embodiment. DETAILED DESCRIPTION

[0014] The present invention will be further described in detail below by means of specific embodiments in conjunction with the accompanying drawings. Similar elements in different embodiments are numbered with associated similar elements. In the following embodiments, many detailed descriptions are provided to enable the present application to be better understood. However, those skilled in the art will readily appreciate that some of the features may be omitted in different circumstances, or may be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification. This is to avoid the core portion of the present application being overwhelmed by excessive descriptions, and for those skilled in the art, it is not necessary to describe these related operations in detail. They will fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0015] In addition, the features, operations, or characteristics described in the specification may be combined in any appropriate manner to form various embodiments. Furthermore, the steps or actions in the method description may be reordered or adjusted in a manner readily apparent to those skilled in the art. Therefore, the various sequences in the specification and drawings are provided solely for the purpose of clearly describing a particular embodiment and are not intended to be mandatory, unless otherwise specified.

[0016] The information association form of conventional raw test data at each stage is as follows:

[0017] During front-end testing, wafers have a unique wafer number, represented by Wafer1. Front-end test parameters are associated with the wafer form of Wafer1. During back-end WT testing, WT test parameters are represented by the wafer number (Wafer2) + chip ID (die ID). In other words, during back-end WT testing, test data is associated with both the wafer and the individual die. During WT testing, the wafers are still in wafer form before being diced, and test data is still associated with a specific individual die. During back-end FT testing, FT test parameters are represented by the package lot number (PackageID) + chip ID (ChipID). During FT testing, the wafers are diced, and the individual die are present. Test data is associated with the package lot number and chip ID. There is a clear correspondence between Wafer1, Wafer2, and PackageID in the front-end, WT, and FT stages. All the Die IDs or Chip IDs that appear indicate the coordinate information of the chip on the wafer. For example, Die ID = (123, 456) means that the X coordinate of this die on the wafer is 123 and the Y coordinate is 456.

[0018] In the front-end testing phase, the test data contains the information shown in Table 1:

[0019]

[0020] In the WT test phase, the test data contains the information shown in Table 2:

[0021]

[0022] In the FT test phase, the test data contains the information shown in Table 3:

[0023]

[0024] The coordinate information of the chip coordinates in the packaging stage is the Chip ID. Moreover, the Chip ID in the packaging stage must correspond to the Die ID in the wafer stage. In other words, the Wafer Die ID can be found through the packaging Chip ID.

[0025] The existing WT and FT data formats mainly associate test parameters through "wafer number + chip coordinates". For two-dimensional 2DMA chips, there are hundreds of channels on a chip, and each channel generates a large amount of data. For example, spectral testing and LIV testing, the amount of data is very large. When performing front-end and back-end testing, the 2DMA channels are tested in turn by switching switches, and each channel generates separate measurement data. However, it is difficult to associate 2DMA test data with the existing data format, or the data format will be very complicated when associating 2DMA test data with the existing data format. So, when there are many channels, what kind of data structure should be used to store the original test data so that it is clear and easy to view, and to associate it with the data of each link is a technical problem that needs to be solved urgently.

[0026] In order to solve the above technical problems, the present application proposes that in the WT test link, the physical object of 2DMA is in the form of a wafer, and the data of each link of the WT test is associated in the form of "wafer number + chip coordinates + channel coordinates". In the WT test link, the object to be tested is the wafer, and the test data is accurate to the channel level. In the FT test link, the data of each link of the FT test is associated in the form of "package batch number + chip coordinates + channel coordinates". In the FT test link, the object to be tested is a single chip, and the test data is also accurate to the channel level. In this way, storing the test data in a channel-level data format can make the original test data clear and easy to view, and establish an association relationship with the data of each link.

[0027] Please refer to Figure 1 , Figure 1 FIG. 1 is a flow chart of a test data storage method provided in this embodiment. The method is applied to a wafer. The method specifically includes the following steps S101-S103:

[0028] S101 , providing a wafer to be tested, wherein the wafer to be tested has a plurality of dies to be tested, and each dies to be tested includes a plurality of light emitting channels.

[0029] S102 , performing wafer-level testing on the wafer to be tested to obtain test data of the wafer to be tested; wherein, the order of the wafer-level testing is to test all light-emitting channels of a wafer to be tested in sequence and then switch to the next wafer to be tested.

[0030] In this embodiment, wafer-level testing is performed on the wafer to be tested, including:

[0031] A plurality of different item tests are respectively performed on each light emitting channel of the same die to be tested to obtain test data of each light emitting channel under different item tests.

[0032] That is, wafer-level testing of the wafer to be tested includes: performing multiple test items associated with wafer-level testing on multiple light-emitting channels of multiple test dies on the wafer to be tested, so that test data of the wafer to be tested in each channel can be obtained.

[0033] It should be noted that the wafers to be tested include but are not limited to silicon wafers, SOI wafers, and compound semiconductor wafers.

[0034] It should be noted that wafer-level testing of the wafer under test can be performed as a back-end WT (Wafer Test) test on the entire wafer. This involves performing multiple tests related to back-end wafer testing on multiple light-emitting channels of multiple test dies on the wafer under test. For example, electrical performance testing aims to screen out chips that do not meet specification requirements during the production process, thereby determining the wafer yield.

[0035] It should be noted that WT testing generally includes voltage, current, timing, and functional verification, such as threshold voltage, on-resistance, source-drain breakdown voltage, gate-source leakage current, drain-source leakage current, etc. These test items can be used to determine the yield of wafers.

[0036] It should be noted that the test data of the wafer to be tested may be the electrical performance data of each channel (such as circuit connection channel, data transmission channel, etc.) obtained through performance testing (such as wafer testing, i.e. WT testing) of the wafer to be tested.

[0037] S103, storing the test data; wherein the stored test data carries a position label of each light-emitting channel on the die to be tested to which it belongs.

[0038] It should be noted that the position label of each light emitting channel on the die to be measured reflects the position of the light emitting channel on the die to be measured.

[0039] In this embodiment, the stored test data also carries the position coordinates of the die to be tested and / or the wafer number identification of the die to be tested; wherein the position coordinates of the die to be tested reflect the position of the die to be tested on the wafer to be tested.

[0040] In this embodiment, the test data of the wafer to be tested of each light-emitting channel is numbered according to the position label of each light-emitting channel on the crystal to be tested, the position coordinates of the crystal to be tested and the piece number identification of the wafer to be tested. A unique number of the test data of each light-emitting channel can be obtained, and the number is unique, so as to clearly indicate which channel of which crystal on which wafer the test data corresponds to.

[0041] In this embodiment, the test data of the wafer to be tested includes test sub-data of each test item of each light-emitting channel.

[0042] It should be noted that the test sub-data includes but is not limited to voltage, current, resistance, capacitance, electrostatic immunity, power consumption, signal integrity, logic function, timing, and interface function.

[0043] In this embodiment, the stored test data also has a project test tag.

[0044] In this embodiment, for the test sub-data of the wafer to be tested for each test item of each light-emitting channel, the test sub-data of the wafer to be tested is associated with the item test label, the position label of the light-emitting channel on the crystal grain to be tested to which it belongs, the position coordinates of the crystal grain to be tested to which it belongs, and the piece number identification of the wafer to be tested and then stored.

[0045] It should be noted that associating the test sub-data of the wafer to be tested with the project test label, the position label of the light-emitting channel on the die to be tested to which it belongs, the position coordinates of the die to be tested to which it belongs, and the chip number identification of the wafer to be tested means using the project test label, the position label of the light-emitting channel on the die to be tested to which it belongs, the position coordinates of the die to be tested to which it belongs, and the chip number identification of the wafer to be tested to number the test sub-data of the light-emitting channel of the wafer to be tested corresponding to the test project, and the number is unique to clarify which channel of which die on which wafer the test sub-data corresponds to. The associated test sub-data is stored for subsequent analysis, query, and tracing.

[0046] It should be noted that each wafer under test is uniquely identified by a wafer number, allowing for accurate identification and tracking throughout the manufacturing, testing, and packaging stages. Specifically, this wafer number allows for the traceability of the wafer's production history, test data, and packaging information, facilitating quality control and troubleshooting.

[0047] It should be noted that the wafer ID of the wafer under test typically includes the following information: the fab ID, which identifies the wafer manufacturer or foundry; the batch number, which identifies the wafer's production batch and helps track the production status and quality of wafers within the same batch; and the wafer number, which is a unique number assigned to each wafer within the same batch to distinguish between different wafers. The wafer ID may also include other information such as production date, wafer size, and process node.

[0048] It should be noted that each die on the wafer has unique position coordinates, which reflect the location of the die on the wafer. For example, during the wafer testing phase, by obtaining the position coordinates of the die, each die on the wafer can be accurately probed to ensure that the quality and performance of the die meet the specification requirements. During the packaging phase, this position information helps to accurately place the die on the lead frame or substrate, ensuring good electrical and mechanical connections between the chip and the substrate.

[0049] It's important to note that each channel of each die on the wafer has a unique location label. This label reflects the channel's location on the die. For example, during wafer testing, this label helps accurately test each channel to ensure proper functionality. During the packaging process, this label helps accurately place the die on the lead frame or substrate to ensure a good electrical and mechanical connection.

[0050] It should be noted that storing the test data of the wafer to be tested in the luminous channel after associating it with its position label can make the test data clear and easy to find, and at the same time, it also increases the storage level of the test data from the grain level to the channel level, thereby improving the storage accuracy of the test data.

[0051] In this embodiment, each light-emitting channel is numbered to obtain an index value corresponding to each light-emitting channel; the index values ​​of each light-emitting channel are arranged in a preset order to construct a channel index table; wherein the channel index table has a corresponding index relationship with the stored test data.

[0052] It should be noted that the channel index table includes the unique index value of each light-emitting channel. Through the index value in the channel index table, you can quickly find and access the information of each channel, which is helpful for chip testing, fault diagnosis, and performance optimization.

[0053] It should be noted that by numbering each lighting channel, an index value corresponding to each lighting channel can be obtained. Then, by arranging the index values ​​of each lighting channel in a predetermined order (e.g., from bottom to top and from left to right), a channel index table can be constructed. Because the channel index table has a corresponding index relationship with the stored test data, the channel index table can be used to accurately locate the position of each lighting channel and thus find the test data stored for each lighting channel.

[0054] In actual applications, during the WT test phase, the wafer performance test data contains the information shown in Table 4:

[0055]

[0056] In Table 4, WaferID2, DieID, and ChannelID represent the wafer number, die location coordinates, and channel coordinates (location labels), respectively. DATA1 through DATAn represent the test data for Test Items 1 through n for a specific wafer number, die, and channel. The first three columns represent the actual object, while Test Items 1 through 1 are the test data corresponding to the first three items. The die coordinates are 1015, meaning the die is located in row 10 and column 15 on the wafer. WaferID2 is W123456-01, meaning the lot number for this wafer is W123456, with 01 being the first wafer in this lot. ChannelID is 43, meaning the channel coordinates are 43.

[0057] In practical applications, the encoding of channel coordinates is taken from the encoding form of Table 5, that is, the channel index table is shown in Table 5:

[0058]

[0059] Table 5 numbers all the light-emitting channels of all the dies to be tested on the wafer to be tested, and uses the index values ​​as the position labels of the corresponding light-emitting channels.

[0060] It should be noted that if Figure 2 Each chip has an identification bit for the correct orientation. For example, during WT and FT tests, the chip is aligned with this identifier. The aligned die can then be searched by channel number.

[0061] In this embodiment, all light-emitting channels of all dies to be tested on the wafer to be tested may be column-indexed and row-indexed, and the column index and row index of the same light-emitting channel may be combined into a position label corresponding to the light-emitting channel, as shown in Table 6:

[0062]

[0063] It should be noted that this application specifies test data accuracy down to the channel level because the oxide aperture test, LIV (Light-Current-Voltage) test, NF (Near Field) test, FF (Far Field) test, and reverse voltage test in the 2DMA test are all performed on a channel-by-channel basis. In other words, this application specifies data structure accuracy down to the channel level, which aligns with the actual requirement for 2DMA testing to be accurate to the channel level in practice.

[0064] It should be noted that this application uses location tags (channel coordinates) as the associated information for WT testing and FT testing in order to convert the level of a single test data from the chip level to the channel level, thereby accurately storing the data at the channel level and achieving the purpose of optimizing the data structure.

[0065] In this embodiment, before performing wafer-level testing on the wafer to be tested, the method further includes:

[0066] The plurality of dies to be tested on the wafer to be tested are packaged separately to obtain a plurality of chips to be tested; performing wafer-level testing on the wafer to be tested is performing wafer-level testing on each chip to be tested on the wafer to be tested to obtain test data of the chip to be tested.

[0067] It should be noted that the chips to be tested include but are not limited to logic chips, memory chips, analog chips, digital chips, microprocessor chips, graphics processor chips, sensor chips, and communication chips. This embodiment is described using a two-dimensional addressable chip as an example.

[0068] It should be noted that packaging multiple test dies on a test wafer separately means wrapping a single test die (also called a chip die) on the test wafer in a supporting frame or housing to protect the chip and provide an interface for connecting to an external circuit.

[0069] In practical applications, after packaging multiple test dies on a test wafer, a packaged chip is obtained. The corresponding relationship between the package chip ID and the wafer die ID of the chip is shown in Table 7:

[0070]

[0071] In this embodiment, the stored test data also carries the package number of the wafer to be tested and the package position information of the chip to be tested.

[0072] In this embodiment, the test data of the chip to be tested includes test sub-data of each test item of each light-emitting channel.

[0073] Store test data, including:

[0074] The test sub-data are stored; wherein the stored test sub-data include a project test label, a position label of each light-emitting channel on the chip to be tested, packaging position information of the chip to be tested, and a packaging number of the wafer to be tested.

[0075] It's important to note that the package number of the wafer under test for a specific luminescence channel is a unique number associated with the packaged chip under test or the packaging batch. This number is typically used to track and manage the packaged chips under test. Specifically, the package number can be used to trace the wafer's production history, test data, packaging information, and more, facilitating quality control and troubleshooting.

[0076] It should be noted that the package number of the wafer to be tested to which the light-emitting channel belongs usually includes the following information: package type identification, which may include the package type code, such as DIP (dual in-line package), SOP (small outline package), QFP (quad flat package), BGA (ball grid array package), etc. The package type identification is used to indicate the packaging form used by the chip.

[0077] It should be noted that the package number of the wafer to be tested and the chip number identification of the wafer to be tested exist independently, but both are used to track and identify chips in the semiconductor manufacturing process.

[0078] It should be noted that the package location information of the chip under test refers to the information used to identify the specific location of the chip on the package carrier (such as the lead frame, substrate, or package shell) during the packaging process. Each chip under test has unique package location information. This package location information helps track the location and status of the chip during the production process, ensuring a smooth and efficient production process. It also facilitates quality inspection and troubleshooting of chips in specific locations. It also helps quickly locate and replace faulty chips when they fail or need replacement.

[0079] It should be noted that each light channel on each chip under test has a unique location tag. This location tag reflects the location of the light channel on the chip under test. During the wafer testing phase, this location tag helps quickly locate the fault point and improve repair efficiency.

[0080] It should be noted that the light-emitting channels of the chip to be tested include but are not limited to microchannels, memory channels, data buses and address buses, and I / O interfaces. Among them, the microchannels are located in the internal structure of the chip and are usually designed as a fine pipeline network that runs through the entire chip. In a memory chip, multiple memory channels may be composed of multiple memory modules with the same capacity, speed, and timing. The data bus and address bus are between the CPU and memory and I / O devices, and the data bus and address bus are used to transmit data information and address information. The I / O interface is the external interface of the chip, which is used for data transmission and communication with external devices or systems.

[0081] It should be noted that the test sub-data of the chip to be tested include but are not limited to current, electrostatic immunity, power consumption, logic function, interface function, package integrity, and pin coplanarity.

[0082] It should be noted that the stored test sub-data of the chip to be tested carries the project test label, the position label of each light-emitting channel on the chip to be tested to which it belongs, the packaging position information of the chip to be tested to which it belongs, and the packaging number of the wafer to be tested to which it belongs. This means that the test sub-data of the channel corresponding to the test item is numbered using the project test label, the position label of each light-emitting channel on the chip to which it belongs, the packaging position information of the chip to be tested to which it belongs, and the packaging number of the wafer to be tested to which it belongs, and the number is unique, so as to clarify which channel of which chip the test sub-data corresponds to, so as to achieve fast query and retrieval.

[0083] In this embodiment, the package number of the wafer to which the chip to be tested belongs is associated with the wafer number identifier of the wafer to be tested and stored, and the package position information of the chip to be tested is associated with the position information of the die to which the chip to be tested belongs before packaging and stored.

[0084] It should be noted that the package number of the wafer to which the chip to be tested belongs is associated with the wafer number identification of the wafer to be tested, that is, an association is established between the package number and the wafer number identification. In this way, when a quality problem occurs in the chip to be tested, this association information can be quickly traced back to the wafer to which the problem chip belongs, as well as the specific situation of the wafer during the manufacturing process. This association information can also be used to understand the output of each wafer, including the number and quality of chips. This association information can be used as one of the unique identification identifiers of the chip for anti-counterfeiting and traceability.

[0085] It should be noted that the package location information of the chip under test is associated with the location information of the die to which the chip under test belongs before packaging. In other words, a correlation is established between the package location information and the location information of the die under test. In this way, if the chip under test has quality problems or fails, this correlation information can be quickly traced back to the die to which the problematic chip belongs and its location on the wafer. This correlation information can be used to understand the position of each die after packaging, as well as the impact of the packaging process on the die position. This correlation information can also serve as a unique identifier for the chip, used for anti-counterfeiting and traceability.

[0086] In this embodiment, the test data of the wafer under test for the light emitting channel of the die under test is correlated with the test data of the chip under test for the light emitting channel obtained after the die under test is packaged to obtain correlated data of the light emitting channels; and the performance of the chip under test is evaluated based on the correlated data of each light emitting channel of the chip under test.

[0087] It should be noted that, by matching and associating the test data of the wafer to be tested and the test data of the chip to be tested of the light emitting channel according to the position tag of the light emitting channel, the associated data of the light emitting channel can be obtained.

[0088] It should be noted that by comparing the test data of the wafer to be tested with the test data of the chip to be tested, the performance changes of the light-emitting channel before and after packaging can be analyzed. For example, the differences in channel parameters such as resistance, capacitance, and transmission speed before and after packaging can be compared to evaluate the impact of the packaging process on channel performance. For example, if a chip has performance issues after packaging, the problem can be quickly located through the correlation data. For example, if the test data of a light-emitting channel after packaging is abnormal, the test data of the wafer to be tested and the test data of the chip to be tested can be compared to determine whether the problem is introduced by the packaging process or a problem with the die itself.

[0089] In practical applications, such as Figure 3 As shown in the figure, during the FT test phase, the 2DMA is physically a wafer, and data from each phase of the FT test is linked using the "package lot number + chip coordinates + channel coordinates" format. During the FT test phase, although the test object is a single chip, the test data is accurate to the channel level.

[0090] In actual applications, during the FT test phase, the chip performance test data contains the information shown in Table 8:

[0091] Packaging batch number Chip coordinates Channel coordinates Test Item 1 Test Project 2 … Test Item PackageID Chip ID ChannelID DATA1 DATA2 … DATAn 230620-F03-002-PKG56789 2116 43 8.6 12.8 15.9

[0092] The chip coordinates correspond to the packaging position information of the chip belonging to the test channel; the packaging batch number corresponds to the packaging number of the wafer belonging to the test channel.

[0093] This embodiment provides a method for storing test data, comprising providing a wafer to be tested, on which are multiple die to be tested, each die to be tested including multiple light-emitting channels; performing wafer-level testing on the wafer to be tested to obtain test data of the wafer to be tested; wherein the order of the wafer-level testing is to test all light-emitting channels of a die to be tested in sequence, and then switch to the next die to be tested; and storing the test data; wherein the stored test data carries a location label of each light-emitting channel on the die to be tested to which it belongs. In this way, when there are many chip channels, the wafer performance test data of each channel is associated with the location label of each channel on the die to be tested to which it belongs, and then stored, so that the test data is clear and easy to find, while also improving the storage accuracy of the test data.

[0094] Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer program. When all or part of the functions in the above embodiments are implemented by computer program, the program can be stored in a computer-readable storage medium, and the storage medium can include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to implement the above functions. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor, all or part of the above functions can be implemented. In addition, when all or part of the functions in the above embodiments are implemented by computer program, the program can also be stored in a storage medium such as a server, another computer, disk, optical disk, flash disk or mobile hard disk, and saved in the memory of the local device by downloading or copying, or the system of the local device is updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be implemented.

[0095] The above examples are used to illustrate the present invention, which are only used to help understand the present invention and are not intended to limit the present invention. Those skilled in the art can make several simple deductions, modifications or substitutions based on the concept of the present invention.

Claims

1. A method for storing test data, characterized in that: The method comprises: Providing a wafer to be tested, wherein the wafer to be tested has a plurality of dies to be tested, and each dies to be tested includes a plurality of light-emitting channels; Performing wafer-level testing on the wafer to be tested to obtain test data of the wafer to be tested; wherein the order of the wafer-level testing is to test all light-emitting channels of a die to be tested in sequence and then switch to the next die to be tested; and The test data is stored in a channel-level data format; wherein the stored test data carries a position label of each light-emitting channel on the die to be tested to which it belongs, the position coordinates of the die to be tested and / or the wafer number identification of the wafer to be tested; wherein the position coordinates of the die to be tested reflect the position of the die to be tested on the wafer to be tested.

2. The method according to claim 1, wherein The performing wafer-level testing on the wafer to be tested includes: A plurality of different item tests are respectively performed on each of the light emitting channels of the same die to be tested to obtain test data of each of the light emitting channels under different item tests.

3. The method according to claim 2, wherein The stored test data also has a project test tag.

4. The method according to claim 1, wherein Before performing wafer-level testing on the wafer to be tested, the method further includes: Packaging the plurality of dies to be tested on the wafer to be tested respectively to obtain a plurality of chips to be tested; The performing wafer-level test on the wafer to be tested is performing wafer-level test on each chip to be tested on the wafer to be tested to obtain test data of the chip to be tested.

5. The method according to claim 4, wherein The stored test data also carries the package number of the wafer to be tested.

6. The method according to claim 5, wherein The stored test data also carries the packaging location information of the chip to be tested.

7. The method according to claim 4, wherein The test data of the chip to be tested includes: test sub-data of each test item of each light-emitting channel; The storing of the test data includes: The test sub-data are stored; wherein the stored test sub-data carry a project test label, a position label of each light-emitting channel on the chip to be tested, packaging position information of the chip to be tested, and a packaging number of the wafer to be tested.

8. The method according to claim 7, wherein The method further comprises: Correlating the test data of the wafer to be tested in the light emitting channel of the die to be tested with the test data of the chip to be tested in the light emitting channel obtained after the die to be tested is packaged, to obtain correlated data of the light emitting channels; The performance of the chip to be tested is evaluated according to the associated data of each light emitting channel of the chip to be tested.

9. The method according to claim 1, wherein The method further comprises: Numbering the light-emitting channels to obtain an index value corresponding to each light-emitting channel; The index values ​​of the light-emitting channels are arranged in a preset order to construct a channel index table; wherein the channel index table has a corresponding index relationship with the stored test data.

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