Scan chain reordering method, computer device and storage medium

Abstract

The present disclosure provides a scan chain reordering method, computer device, and storage medium. The method includes: obtaining a chip design layout; determining multiple first scan chains based on the chip design layout, merging the multiple first scan chains into a second scan chain; reordering the second scan chains to generate a third scan chain; determining the number of elements in each first scan chain, dividing the third scan chain according to the number of elements, and generating a plurality of reordered fourth scan chains with the same number as the multiple first scan chains.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip layout planning, and in particular to a scan chain reordering method, a computer device, and a storage medium. Background Art

[0002] Scan chain is a commonly used digital integrated circuit (IC) testing technology, falling under the umbrella of Design for Testability (DFT). Scan chain reordering refers to the process of reorganizing scan chains during chip design.

[0003] During chip design, multiple scan chains may be configured. When reordering these scan chains, if reordering a single scan chain fails to meet overall line length requirements, further consideration is given to reordering by swapping components between multiple scan chains. However, currently, this reordering method is limited and crude. As the number of scan chains increases, the time consumption becomes significant, significantly impacting overall efficiency.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present disclosure proposes a scan chain reordering method, a computer device, and a storage medium to solve or partially solve the above-mentioned problem.

[0006] Based on the above objectives, in a first aspect, the present disclosure provides a scan chain reordering method, comprising:

[0007] Obtain chip design layout;

[0008] Determining a plurality of first scan chains according to the chip design layout, and merging the plurality of first scan chains into a second scan chain;

[0009] reordering the second scan chains to generate a third scan chain;

[0010] The number of elements in each of the first scan chains is determined, and the third scan chain is divided according to the number of elements to generate a plurality of reordered fourth scan chains having the same number as the plurality of first scan chains.

[0011] In a second aspect, the present disclosure provides a computer device comprising one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to the first aspect.

[0012] In a third aspect, the present disclosure provides a non-volatile computer-readable storage medium containing a computer program, which, when executed by one or more processors, causes the processors to perform the method described in the first aspect.

[0013] As can be seen from the above, the present disclosure provides a scan chain reordering method, computer device, and storage medium. The present disclosure first determines multiple first scan chains based on a chip design layout, then merges these scan chains into a single second scan chain using a certain merging rule. This allows for a comprehensive reordering of the single scan chain without restricting components to different scan chains. After the reordering is completed to form a third scan chain, the scan chain needs to be restored to have the same number as the multiple first scan chains. During the restoration, the third scan chain is directly divided according to the number of components in each first scan chain. This not only ensures that the number of fourth scan chains formed by the division is the same as the number of first scan chains, but also ensures that the number of components contained in each fourth scan chain corresponds to the number of components contained in a first scan chain, thereby ensuring the correct length of the reordered multiple scan chains. During the entire reordering process, obstructions between different scan chains are avoided. Furthermore, the reordering efficiency for a single scan chain is generally high, which can significantly optimize the runtime of the scan chain reordering and improve overall efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] Figure 1 A schematic diagram of the hardware structure of an exemplary computer device provided by an embodiment of the present disclosure is shown.

[0016] Figure 2 A basic structural diagram of the EDA tool provided by an embodiment of the present disclosure is shown.

[0017] Figure 3 A schematic diagram showing a basic execution flow of a calculation command of an EDA tool provided by an embodiment of the present disclosure is shown.

[0018] Figure 4 A flowchart of an exemplary method provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of this specification more clear, this specification is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0020] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements, objects or method steps appearing before the word include the elements, objects or method steps listed after the word and their equivalents, without excluding other elements, objects or method steps. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0021] Figure 1 The following is a schematic diagram of the structure of a computer device 100 provided by an embodiment of the present disclosure. The computer device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. The processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are connected to each other within the device via the bus 110.

[0022] The processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or one or more integrated circuits. The processor 102 may be used to perform functions related to the technology described in this disclosure. In some embodiments, the processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0023] The memory 104 may be configured to store data (eg, instruction sets, computer code, intermediate data, etc.). Figure 1 As shown, the stored data may include program instructions (e.g., program instructions for implementing the technical solutions of the present disclosure) and data to be processed. The processor 102 may also access the stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include random access memory (RAM), read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0024] The network interface 106 can be configured to provide the computer device 100 with communication with other external devices via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near-field communication (NFC)), a cellular network, the Internet, or a combination thereof. It will be appreciated that the type of network is not limited to the specific examples above. In some embodiments, the network interface 106 can include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.

[0025] The peripheral interface 108 can be configured to connect the computer device 100 to one or more peripheral devices to enable information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touchpad, a touch screen, a microphone, and various sensors, as well as output devices such as a display, a speaker, a vibrator, and an indicator light.

[0026] The bus 110 may be configured to transmit information between various components of the computer device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0027] It should be noted that although the above device only shows the processor 102, memory 104, network interface 106, peripheral interface 108 and bus 110, in a specific implementation, the device may also include other components necessary for normal operation. In addition, those skilled in the art will understand that the above device may only include the components necessary to implement the embodiments of the present disclosure, and does not necessarily include all the components shown in the figure.

[0028] Figure 2 FIG. 2 shows a basic structural diagram of an EDA tool 200 according to an embodiment of the present disclosure.

[0029] like Figure 2 As shown, the part above the dotted line is the user part; the part below the dotted line is the EDA tool 200, which can be Figure 1 The device 100 shown is implemented. In some embodiments, the EDA tool 200 can be implemented as EDA software. More specifically, the EDA tool 200 can be software that performs placement and routing based on chip designs. The EDA tool 200 can include a Tcl command (or graphical / window interface) module 204, various calculation modules (e.g., a Placement calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc.), and a database system 212. A user 202 can operate the EDA tool 200 by entering relevant commands in the Tcl command (or graphical / window interface) module 204.

[0030] The Tcl command module 204 mainly performs the function of message transmission or command transmission. The Tcl command module 204 can read the instructions input by the user 202 to the simulation tool 200, and can distribute and transmit the instructions to the corresponding computing modules to perform specific tasks according to the specific content of the instructions.

[0031] Depending on the calculation task, each calculation module can be divided into, for example, a Place calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc. The Place calculation module 206 can be used to calculate a reasonable placement position for all components, the Route calculation module 208 can be used to calculate a reasonable wire connection method between each component, and the Optimization calculation module 210 can be used to optimize the placement position and wire connection method between each component. The calculation process of these calculation modules can be, for example, Figure 1 is performed in the processor 102.

[0032] The database system 212 can be used to completely and comprehensively record and store all information of the chip being simulated or designed (such as location, direction, size, structure, wire connection method, etc.). This information can be stored in, for example, Figure 1 in the memory 104.

[0033] Figure 3 FIG. 3 shows a basic execution flow 300 of a calculation command of the EDA tool 200 according to an embodiment of the present disclosure. Figure 3As shown, in step 302, user 202 can issue a command (e.g., the do_place command) to the EDA tool 200 via the command interface or graphical user interface (GUI) provided by the Tcl command module 204. Then, in step 304, the Tcl command module 204 parses the command and dispatches it to the corresponding computation module (e.g., the Place computation module 206). In step 306, each computation module performs its required calculations. During this process, as shown in step 308, each computation module needs to frequently and repeatedly access data from the database system 212 to perform its calculations. After the calculations are complete, as shown in step 310, each computation module can write the results to the database system 212 and return the results to the Tcl command module 204. In step 312, the Tcl command module 204 returns the results to user 202 via the command interface or graphical user interface (GUI), concluding the processing of the computation command by the EDA tool 200. In step 314, the user can evaluate the results and determine the next steps.

[0034] In some embodiments, a scan chain is a design-for-test (DFT) technique that, by embedding shift registers, allows testers to externally control and observe the signal values ​​of internal flip-flops. The basic principle is to connect all flip-flops in the design into a chain, drive them with a unified scan clk, and shift them bit by bit into the chip using a pre-designed scan pattern. Capture is then enabled, and the Q output of each flip-flop is fed into the combinational circuit it drives. The D input of the next-level flip-flop captures the output of this combinational circuit. The resulting vector of results is compared with the tool's pre-calculated expectations to determine if there are any manufacturing errors in the chip. Scan chain reordering refers to the process of reordering the scan chain during chip design. A scan chain is a design technique in Design for Testability (DFT). By replacing ordinary registers with registers with scan functionality and connecting them into a chain through specific input and output ports, these registers can be shifted under external control during testing, enabling testing of the chip's internal logic. The main function of scan chain reordering is to optimize the connection mode of scan chains to ensure that data can flow quickly and safely.

[0035] As chip design becomes more complex, multiple scan chains are involved in some scenarios. Corresponding scan chain reordering (Scan Reorder) can be performed for each of these scan chains. If the reordering effect does not meet the requirements, the components (insts) between the scan chains can be further interchanged and reordered. That is, the scan_reorder -repartition true instruction is executed using the EDA tool to divide the multiple scan chains into at least one repartition group, and the components in the scan chains within a repartition group are interchanged and the component connection relationships are rearranged. However, when this instruction is currently executed, the corresponding reordering method is relatively rough, has many loopholes, and is highly dependent on human intervention. Moreover, once the number of scan chains in the group increases, the corresponding reordering time will increase exponentially, seriously affecting the overall efficiency.

[0036] In view of this, the present disclosure proposes a scan chain reordering method. The present disclosure first determines multiple first scan chains based on the chip design layout. Then, these scan chains can be merged into a whole second scan chain using a certain merging rule. In this way, a single whole scan chain can be reordered as a whole without restricting the components to different scan chains. After the reordering is completed to form a third scan chain, the scan chain needs to be restored to the same number as the multiple first scan chains. During the restoration, the third scan chain is directly divided according to the number of components in each first scan chain. In this way, not only the number of fourth scan chains formed by the division is ensured to be the same as the number of first scan chains, but also the number of components contained in each fourth scan chain can correspond to the number of components contained in a first scan chain, thereby ensuring the correctness of the chain length after the reordering of the multiple scan chains. In the entire reordering process, the obstruction between different scan chains is avoided. At the same time, the reordering efficiency for a single scan chain is generally high. Ultimately, the running time of the scan chain reordering can be greatly optimized, and the overall efficiency can be improved.

[0037] Figure 4 The flow chart of the exemplary method 400 provided by the embodiment of the present disclosure is shown. The method 400 may be Figure 1 The computer device 100 is implemented and can be implemented as Figure 2 A portion of the functionality of the EDA tool 200. Figure 4 As shown, the method 400 may further include the following steps.

[0038] Step 402: Obtain chip design layout.

[0039] Typically, a chip design layout includes every layer of chip fabrication, including transistor layout, wiring, routing, and inter-layer connection locations for channels and vias. Based on this chip design layout, chip fabrication service providers can directly execute and mass-produce the chips. Furthermore, the chip design layout itself is drawn step by step, accompanied by various optimizations, ultimately completing the entire chip design layout. In the initial stages of a chip design layout, it may only indicate hierarchical functional information, such as which layer is a routing layer or an insulation layer; or it may simply list individual functional components, indicating their location, size, and other information. Subsequently, EDA tools are used for step-by-step design and optimization, ultimately resulting in a complete version of the chip design layout. Here, components (inst) can refer to standard processing units, modules or hard cores, input / output ports, registers, and so on within the chip.

[0040] In this step, since this embodiment involves operations related to the scan chain, it is generally necessary to obtain a chip design layout with the relevant scan chain drawn. This chip design layout can be used to determine the specific form of the current scan chain and related attribute data, such as the scan chain's starting position (which can be represented by coordinates, etc.), the ending position, the connection relationship between each component in the scan chain, the location of these components (which can be represented by coordinates, etc.), etc. In specific application scenarios, initial data information such as scan chain data and component positions can be obtained through DEF (Design Exchange File, physical information of the design library) files and / or LEF (Library Exchange File, physical information of the process library) files of the chip design layout.

[0041] It should be noted that scan chain reordering generally redefines the connection relationship between components. During the entire process, the physical positions of the components generally do not change. What changes are only the connection relationships between different components or the scan chains to which the components belong.

[0042] In addition, in this step, the chip design layout can be local (for example, the entire design layout is divided into a large number of sub-areas) or overall.

[0043] Step 404 : determining a plurality of first scan chains according to the chip design layout, and merging the plurality of first scan chains into a second scan chain.

[0044] In this step, after obtaining the chip design layout, at least one scan chain is determined based on the records therein. These scan chains are generally set with a starting position and then reach the ending position after passing through multiple components connected in series and / or parallel. The at least one scan chain determined here is the first scan chain.

[0045] After determining multiple first scan chains, these scan chains can be merged into a whole, that is, a second scan chain is generated. The merging process here can be to directly connect these first scan chains end to end to form a whole second scan chain; or it can be to break up the components contained in each first scan chain and then reconstruct a complete second scan chain; it can also be directly determining the components contained in these first scan chains, and then directly connecting them into a second scan chain according to specific connection rules, etc. That is, in some embodiments, the merging of the multiple first scan chains into the second scan chain includes: splicing the multiple first scan chains according to the set rules to generate the second scan chain; or splitting the components of the multiple first scan chains and reorganizing the split components into the second scan chain. The set rules can be the aforementioned end-to-end connection rules, or can be specifically set according to the specific application scenario.

[0046] In a more specific application scenario, when the first scan chain is determined, other relevant properties of the first scan chain can generally be determined, such as the starting position of the scan chain, the setting position of each component, etc. In this scenario, these properties generally do not change and can be regarded as fixed properties.

[0047] Step 406: reorder the second scan chains to generate a third scan chain.

[0048] In this step, the second scan chain needs to be reordered. This can be done directly using conventional reordering methods. For example, a full reordering calculation can be performed on the components of the entire second scan chain, and then the components are reconnected in series based on the reordering results to form the third scan chain.

[0049] However, due to the complexity of chip design, the merged second scan chain may contain a large number of components. If ordinary reordering is performed directly, it may consume too much time and be inefficient. In order to improve efficiency, the reordering process can be further optimized. First, the multiple components contained in the second scan chain can be determined. After determining the multiple components contained in the second scan chain, the number of components contained in the scan chain can be determined by reading the chip design layout data or by statistical methods. These components can then be grouped according to this number to generate at least one component set.

[0050] In some embodiments, the number of groups to be divided can be preset and used to group the components. For example, if five groups are desired, after determining the number of components, the components can be divided into five groups using methods such as randomization, equal division, or proximity clustering (clustering components that are close to each other based on distance), generating five component sets. In other embodiments, the components can be grouped by setting a maximum number of components per group. For example, if the number of components is 200 and the maximum number of components per group is 20, the components can be divided into 10 groups, generating 10 component sets.

[0051] After the component sets are determined, since these component sets are essentially part of the scan chain, these component sets can be reordered according to the original reordering rules for the scan chain. This can be understood as dividing the scan chain into multiple sub-chains and reordering these sub-chains. The specific reordering rules can be set according to the specific application scenario, and its main purpose is to optimize the connection relationship of the components. By reordering at least one group of component sets, adjusting the connection relationship of the components in each group of component sets, and optimizing the connection relationship, at least one reordered sub-chain can be generated, where one sub-chain corresponds to one group of component sets. After completing the reordering of each sub-chain, these sub-chains need to be spliced ​​together to restore them to a complete scan chain, that is, to form a third scan chain. For splicing, splicing can be performed according to pre-set settings. For example, the order of the sub-chains corresponding to each component set when splicing is determined before reordering. This order can be set manually or determined according to other requirements. That is, in some embodiments, the reordering of the second scan chain includes: determining a plurality of elements included in the second scan chain; grouping the plurality of elements according to the number of the plurality of elements to generate at least one set of element sets; reordering the at least one set of element sets to generate at least one sub-chain corresponding to the at least one set of element sets; and splicing the at least one sub-chain.

[0052] Furthermore, when arranging and connecting components in chip design, there is a more important parameter that needs to be considered, namely, wire length gain. Every time the connection method of the components is adjusted, it is expected that the loss of wire length gain will be minimized. For the scenario of this embodiment, if the loss of wire length gain is minimized, it is necessary to try to rearrange components with close distances together or group them in the same group during the reordering process. In this way, in a specific application scenario, the distance between each component in the scan chain can be determined based on the chip design layout, and then these components can be clustered using a clustering algorithm based on these distances to complete the grouping of these components, so as to finally make the components in each group of components as close as possible, thereby reducing the global optimization loss of wire length gain. For example, assuming that 100 components need to be divided into 5 groups of component sets, a clustering algorithm can be used to first randomly select 5 origins. Then, based on the distance between the components, clustering can be performed with these 5 origins as the center. After the initial clustering is completed, the center origin is re-determined for each cluster set, and clustering is performed again. This iterative process is repeated until a set termination condition is met, and the 5 groups of component sets are completed. That is, in some embodiments, grouping based on the number of the multiple components includes: determining the distance between the multiple components; clustering the multiple components using a clustering algorithm based on the distance; and performing the grouping based on the clustering results.

[0053] Furthermore, in some more specific application scenarios, among the various clustering algorithms, the K-means clustering algorithm can be selected for clustering, taking into account the application scenario of this embodiment and the requirements for convergence speed, scalability, etc. That is, in some embodiments, the clustering algorithm includes the K-means clustering algorithm.

[0054] Furthermore, in specific application scenarios, when clustering components in a scan chain using a clustering algorithm, the clustering convergence process can sometimes take a long time due to factors such as the excessive number of clustering objects (components), the specificity of the clustering objects (components), or the specificity of the connection relationships between the clustering objects (components), which can also affect overall efficiency. Therefore, it is possible to consider accelerating the clustering algorithm, for example, by reducing dimensionality (such as principal component analysis (PCA)), using efficient databases (such as the NumPy library), and locality-sensitive hashing (LSH). Due to its outstanding performance in optimizing data structures and automatic vectorization, the Eigen template library can be used to accelerate the clustering algorithm. The Eigen template library also demonstrates significant advantages in the specific application scenarios of this embodiment, significantly reducing the clustering process for components. The Eigen template library is a C++ template library for linear algebra: for matrices, vectors, numerical solvers, and related algorithms. That is, in some embodiments, clustering the plurality of elements using a clustering algorithm according to the distance includes: accelerating the clustering algorithm using an Eigen template library.

[0055] Step 408 : Determine the number of components in each of the first scan chains, divide the third scan chain according to the number of components, and generate a plurality of reordered fourth scan chains having the same number as the plurality of first scan chains.

[0056] In this step, after the reordered third scan chain is formed, according to relevant chip design rules, the number of scan chains needs to be restored to the same as before the reordering. That is, before the reordering, there were 50 scan chains in a repartition group, and after the reordering, there still needs to be 50 scan chains in a repartition group. Therefore, in this embodiment, the third scan chain needs to be divided.

[0057] In this embodiment, the number of elements in each of the first scan chains is first determined, and then the third scan chain is directly divided based on these element numbers. For example, if the first scan chain consists of four chains: chain 1, chain 2, chain 3, and chain 4, containing 10, 20, 20, and 30 elements, respectively, and the second and third scan chains each contain 80 elements according to the aforementioned steps, they can be directly divided according to the order of "10, 20, 20, and 30," generating four fourth scan chains: chain 1' with 10 elements, chain 2' with 20 elements, chain 3' with 20 elements, and chain 4' with 30 elements. This ensures that the number of generated fourth scan chains is the same as the number of first scan chains and that any first scan chain can find a fourth scan chain with the same number of elements. This also facilitates connecting each scan chain to the starting and ending positions of the corresponding scan chain. For example, if chain 1' corresponds to chain 1, it can be connected based on the starting and ending positions of chain 1. This improves connection efficiency. At the same time, in a more specific application scenario, when executing the scan_reorder -repartition true instruction, the maxbit attribute needs to be considered, that is, the number of elements contained in each scan chain after reordering cannot exceed a corresponding threshold value, which is the maxbit. The maxbit of a scan chain is generally greater than or equal to the number of elements contained in the scan chain before reordering. For example, if scan chain A contains 10 elements before reordering, then the maxbit of scan chain A is generally greater than or equal to 10. Returning to this embodiment, the fourth scan chain is directly divided based on the number of elements of the first scan chain. According to the aforementioned division method, the fourth scan chain after division not only has the same number as the first scan chain, but each first scan chain can correspond to a fourth scan chain with the same number of elements, which also necessarily meets the relevant reordering requirements. In this way, while improving the reordering efficiency, the relevant detection process can also be further simplified, the detection efficiency can be improved, and the overall efficiency can be further improved.

[0058] In some embodiments, to further improve the efficiency of the slicing process, the slicing process can be further refined. Based on the number of components in different first scan chains, a corresponding set of quantities can be generated. For example, the corresponding set of quantities for chains 1 through 4 is {10, 20, 20, 30}. The number types contained in this set can then be counted. For example, the set {10, 20, 20, 30} contains three quantities: 10, 20, and 30. A slicing scheme can then be determined based on these three quantities. A slicing scheme here refers to a single cut. Simply put, it determines how the "first cut" or "second cut" will be performed. Based on the above example, the generated slicing schemes are for slicing 10, 20, or 30 components. Slicing simulations can then be performed on the third scan chain based on these slicing schemes. For the "first cut" example, Scheme A slices out the first 10 components, Scheme B slices out the first 20 components, and Scheme C slices out the first 30 components, generating three simulation results. Afterwards, these simulation results can be screened based on line length requirements, gain requirements, and other requirements in specific application scenarios, and a target simulation result can be selected, and a target segmentation scheme corresponding to the target simulation result can be determined. The third scan chain can then be segmented directly based on the target segmentation scheme; or the next segmentation scheme can be determined until all segmentation schemes are determined, and then the third scan chain can be segmented. That is, in some embodiments, segmenting the third scan chain based on the number of elements includes: generating a quantity set based on the number of elements of different first scan chains; determining the number types included in the quantity set, and determining at least one segmentation scheme based on the number types; wherein the at least one segmentation scheme is a scheme for segmenting the third scan chain once; performing segmentation simulation on the third scan chain based on the at least one segmentation scheme, and generating at least one simulation result corresponding to the at least one segmentation scheme; screening the at least one simulation result based on set requirements, determining a target simulation result and a target segmentation scheme corresponding to the target simulation result; and segmenting the third scan chain based on the target segmentation scheme.

[0059] Furthermore, according to the aforementioned embodiments, wirelength gain is prioritized during the reordering process. Therefore, during the slicing process, this factor can also be used to optimize the slicing process, particularly the aforementioned screening process. As previously mentioned, the starting and ending positions of a scan chain generally remain unchanged before and after reordering, and the positions of the components involved in the reordering generally remain unchanged. This can be used as a basis for screening during slicing. Taking chains 1 to 4 as an example, during the first slicing determination, three slicing results are generated: Result A, which slicing 10 components, corresponds to chain 1; Result B, which slicing 20 components, corresponds to chains 2 and 3; and Result C, which slicing 30 components, corresponds to chain 4. In this case, the component closest to the starting position of chain 1 can be found in Result A as the starting component. Since the 10 components in Result A can be connected end-to-end, after determining the starting component, Result A can be expanded to determine the ending component within Result A. After that, the first distance from the starting element to the starting position of chain 1 and the second distance from the ending element to the ending position of chain 1 can be calculated. The sum of the first and second distances can then be used as the filtering condition for chain 1 corresponding to result A. Repeating the above process can determine the filtering conditions for chain 2 corresponding to result B, chain 3 corresponding to result B, and chain 4 corresponding to result C. Ultimately, based on the size of these four filtering conditions (the smallest filtering condition can be selected), the specific result to be used for the first split can be determined, and the split scan chain can correspond to which first scan chain. That is, in some embodiments, the filtering of the at least one simulation result according to the set requirements includes: determining multiple attribute information corresponding to the multiple first scan chains; wherein each of the attribute information includes at least a starting position, an ending position and a first number of elements; for any simulation result, determining the second number of elements of the any simulation result, and selecting at least one target attribute information in which the first number of elements is equal to the second number of elements from the multiple attribute information; for any target attribute information, determining the starting element closest to the starting position of the any target attribute information in the any simulation result, and determining the ending element of the any cutting result based on the starting element; calculating a first distance between the starting element and the starting position of the any target attribute information, and a second distance between the ending element and the ending position of the any target attribute information, and generating a filtering condition for the any simulation result for the any target attribute information based on the first distance and the second distance; counting and sorting all the filtering conditions of the at least one simulation result, and filtering based on the sorting result.

[0060] Furthermore, in order to reduce the process of repeated calculation or repeated determination. After determining a segmentation scheme, when determining the next segmentation scheme, first determine whether a segmentation scheme already exists before. If so, then all the segmentation schemes previously carried out can be counted to determine which attribute information corresponds to each segmentation scheme. Here, the attribute information corresponding to each segmentation scheme determined can be referred to as segmentation attribute information. Later, when determining the current segmentation scheme, after determining multiple attribute information, the segmentation attribute information can be removed from these attribute information. For example, based on the above example, assuming the "first cut", the first segmentation scheme is finally determined to segment chain2 according to result B, that is, first cut 20 elements of the third scan chain, and these elements will be connected to the starting position and end position of chain2 to form chain2'. In the second cut, when determining the second splitting plan, the splitting attribute information corresponding to the first splitting plan (here, the relevant information corresponding to chain2 or chain2') can be excluded from the attribute information. Only three sets of corresponding filtering conditions are generated (the filtering conditions for result A corresponding to chain1, the filtering conditions for result B corresponding to chain3, and the filtering conditions for result C corresponding to chain4). Selection is then made between these three sets of filtering conditions. Assuming that the second splitting plan is ultimately determined to be based on result B corresponding to chain3, the third cut follows a similar process, ultimately generating only two sets of corresponding filtering conditions (the filtering conditions for result A corresponding to chain1 and the filtering conditions for result C corresponding to chain4). Selection is then made between these two sets of filtering conditions, and so on. That is, in some embodiments, after determining the multiple pieces of attribute information corresponding to the multiple first scan chains, the method further includes: determining whether there is a previous segmentation scheme; in response to the existence of the previous segmentation scheme, performing statistics on the previous segmentation schemes to determine the segmentation attribute information of each segmentation scheme; and removing the attribute information corresponding to the segmentation attribute information from the multiple pieces of attribute information.

[0061] As can be seen from the above, the embodiments of the present disclosure provide a scan chain reordering method. The present disclosure first determines multiple first scan chains based on a chip design layout. These scan chains can then be merged into a single second scan chain using certain merging rules. This allows for a comprehensive reordering of the single scan chain without restricting components to different scan chains. After the reordering is completed to form a third scan chain, the scan chain needs to be restored to a number that is the same as the number of the multiple first scan chains. During the restoration process, the third scan chain is directly divided according to the number of components in each first scan chain. This ensures that the number of fourth scan chains formed by the division is the same as the number of first scan chains, and that the number of components in each fourth scan chain corresponds to the number of components in a first scan chain. This ensures the correct length of the reordered scan chains, avoids interference between different scan chains, and generally results in higher reordering efficiency for a single scan chain. This significantly optimizes the runtime of the scan chain reordering and improves overall efficiency.

[0062] It should be noted that the methods of the embodiments of the present disclosure can be performed by a single device, such as a computer or server. The methods of the embodiments of the present disclosure can also be applied in a distributed scenario, performed by multiple devices working together. In such a distributed scenario, one of the multiple devices may only perform one or more steps of the methods of the embodiments of the present disclosure, and the multiple devices will interact with each other to complete the described method.

[0063] It should be noted that the above description is of specific embodiments of the present disclosure. In some cases, the actions or steps described in the above embodiments of the present disclosure can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0064] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides a non-volatile computer-readable storage medium containing a computer program, wherein the non-volatile computer-readable storage medium containing a computer program stores computer instructions, and the computer instructions are used to enable the computer to execute method 400 described in any of the above embodiments.

[0065] The computer-readable storage media of this embodiment includes permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0066] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the method 400 described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0067] Based on the same inventive concept, corresponding to method 400 in any of the above embodiments, this application also provides a computer program product comprising a computer program. In some embodiments, the computer program is executable by one or more processors to cause the processors to perform method 400. For the execution entities corresponding to the steps in each embodiment of method 400, the processors executing the corresponding steps may belong to the corresponding execution entities.

[0068] The computer program product of the above embodiment is used to enable a processor to execute the method 400 described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0069] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application is limited to these examples. In line with the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0070] In addition, to simplify the description and discussion, and to avoid obscuring the understanding of the embodiments of the present application, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided figures. Furthermore, devices may be shown in block diagram form to avoid obscuring the understanding of the embodiments of the present application, and this also takes into account the fact that the implementation details of these block diagram devices are highly dependent on the platform on which the embodiments of the present application will be implemented (i.e., these details should be fully understood by those skilled in the art). Where specific details (e.g., circuits) are set forth to describe the exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application can be implemented without these specific details or with variations therefrom. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0071] Although the present invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may utilize the discussed embodiments.

[0072] The embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the above-described embodiments. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of this application.

Claims

1. A scan chain reordering method, characterized in that: include: Obtain chip design layout; Determining a plurality of first scan chains according to the chip design layout, and merging the plurality of first scan chains into a second scan chain; reordering the second scan chains to generate a third scan chain; The number of elements in each of the first scan chains is determined, and the third scan chain is divided according to the number of elements to generate a plurality of reordered fourth scan chains having the same number as the plurality of first scan chains; wherein, when dividing the third scan chain, a dividing scheme for each dividing is determined according to the number of elements, and the dividing of the third scan chain is completed according to the dividing scheme.

2. The method according to claim 1, characterized in that The dividing the third scan chain according to the number of components includes: generating a quantity set according to the quantity of the components of different first scan chains; Determining the quantity types included in the quantity set, and determining at least one segmentation scheme according to the quantity types; wherein the at least one segmentation scheme is a scheme for segmenting the third scan chain once; Performing a segmentation simulation on the third scan chain according to the at least one segmentation scheme, and generating at least one simulation result corresponding to the at least one segmentation scheme; Screening the at least one simulation result according to set requirements to determine a target simulation result and a target segmentation scheme corresponding to the target simulation result; The third scan chain is divided according to the target division scheme.

3. The method according to claim 2, characterized in that The screening of the at least one simulation result according to the set requirements includes: Determining a plurality of pieces of attribute information corresponding to the plurality of first scan chains; wherein each piece of attribute information at least includes a starting position, an ending position, and the number of first elements; For any simulation result, determining the second number of elements in the simulation result, and selecting at least one target attribute information in which the first number of elements is equal to the second number of elements from the multiple attribute information; For any target attribute information, determining a starting element in any simulation result that is closest to a starting position of the target attribute information, and determining an ending element of the simulation result according to the starting element; calculating a first distance between the starting element and a starting position of the any target attribute information, and a second distance between the ending element and an ending position of the any target attribute information, and generating a screening condition for the any simulation result for the any target attribute information based on the first distance and the second distance; All screening conditions of the at least one simulation result are counted and sorted, and screening is performed according to the sorting results.

4. The method according to claim 3, characterized in that After determining the plurality of pieces of attribute information corresponding to the plurality of first scan chains, the method further includes: Determine whether there is a previous segmentation plan; In response to the existence of the previous segmentation scheme, statistics are collected on the previous segmentation schemes to determine segmentation attribute information of each segmentation scheme; Attribute information corresponding to the segmented attribute information is removed from the plurality of pieces of attribute information.

5. The method according to claim 1, wherein The reordering of the second scan chain includes: determining a plurality of elements included in the second scan chain; Grouping the plurality of components according to the number of components to generate at least one component set; reordering the at least one set of component sets to generate at least one subchain corresponding to the at least one set of component sets; The at least one daughter strand is spliced.

6. The method according to claim 5, characterized in that The grouping according to the number of the plurality of elements comprises: determining distances between the plurality of elements; clustering the plurality of elements using a clustering algorithm according to the distance; The grouping is performed according to the clustering result.

7. The method according to claim 6, characterized in that Clustering the plurality of elements using a clustering algorithm according to the distance includes: The clustering algorithm is accelerated using the Eigen template library.

8. The method according to claim 1, characterized in that The merging of the plurality of first scan chains into a second scan chain comprises: splicing the plurality of first scan chains according to a set rule to generate the second scan chain; Alternatively, the plurality of first scan chains are split into components, and the split components are reassembled into the second scan chains.

9. A computer device, characterized in that: The method comprises one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to any one of claims 1 to 8.

10. A non-volatile computer-readable storage medium containing a computer program, characterized in that When the computer program is executed by one or more processors, the processors are caused to perform the method according to any one of claims 1 to 8.

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