Chip Layout Model Training Method, Device, Storage Medium and Electronic Device

Abstract

The present application provides a chip layout model training method, device, storage medium and electronic device, which relate to the field of circuit electronic design automation. The electronic device obtains a fine-tuning sample set of a large language model, wherein the fine-tuning sample set includes layout process information of multiple reference layouts; for the layout process information of each reference layout, the phased requirements in the layout process information are input into the large language model to obtain a predicted layout suggestion generated by the large language model; according to the phased layout suggestion and the predicted layout suggestion, the model loss of the large language model is obtained; the large language model is updated by adjusting the model loss with the pros and cons factor to obtain a chip layout model. In this way, based on the chip design-related professional knowledge that the large language model has learned, the large language model is further trained through the pros and cons factor to learn the pros and cons of different chip layouts, so that the trained chip layout model can simulate human experts and provide high-quality chip layout suggestions.

Description

Technical Field

[0001] The present application relates to the field of electronic design automation (EDA), and more specifically, to a chip layout model training method, device, storage medium, and electronic device. Background Art

[0002] During chip design, netlist nodes must be properly placed on the chip canvas to meet chip performance requirements. Therefore, chip layout becomes a crucial step in chip design. Traditional chip design layout optimization methods are typically based on rules and experience, making them inadequate for addressing the increasingly complex demands of chip design. In recent years, the development of artificial intelligence (AI), particularly large language models (LLMs), has provided new insights into chip design layout optimization due to their powerful natural language understanding and generation capabilities. However, effectively training LLMs to optimize chip design layout remains an unresolved issue. Summary of the Invention

[0003] To overcome at least one shortcoming of the prior art, this application provides a chip layout model training method, apparatus, storage medium, and electronic device. These methods, based on the chip design expertise already learned by a large language model, further train the large language model using pros and cons factors to learn the pros and cons of different chip layouts. This allows the trained chip layout model to simulate human experts and provide high-quality chip layout recommendations. Specifically, these methods include:

[0004] In a first aspect, the present application provides a chip layout model training method, the method comprising:

[0005] Obtaining a fine-tuning sample set for a large language model, wherein the fine-tuning sample set includes chip design requirements and layout process information of multiple reference layouts that meet the chip design requirements, each reference layout must be obtained through at least one round of layout, and the layout process information of each reference layout includes phased requirements corresponding to each round of layout and phased layout suggestions for the phased requirements;

[0006] For each reference layout, inputting the phased requirements in the layout process information into the large language model to obtain a predicted layout suggestion generated by the large language model;

[0007] Obtaining a model loss of the large language model according to the phased layout suggestion and the predicted layout suggestion;

[0008] The model loss is adjusted by a pros and cons factor to obtain an optimized model loss, and the large language model is updated according to the optimized model loss to obtain a chip layout model, wherein the pros and cons factor characterizes the difference in layout effect between the reference layout and other reference layouts.

[0009] In a second aspect, the present application provides a chip layout model training device, the device comprising:

[0010] A sample preparation module is configured to obtain a fine-tuning sample set for a large language model, wherein the fine-tuning sample set includes chip design requirements and layout process information of multiple reference layouts that meet the chip design requirements. Each reference layout must be obtained through at least one round of layout. The layout process information of each reference layout includes the phased requirements corresponding to each round of layout and phased layout suggestions for the phased requirements.

[0011] A model training module 12 is configured to input the phased requirements in the layout process information of each reference layout into the large language model to obtain a predicted layout suggestion generated by the large language model;

[0012] The model training module 12 is further configured to obtain a model loss of the large language model based on the phased layout suggestions and the predicted layout suggestions;

[0013] The model training module 12 is further configured to adjust the model loss by a pros and cons factor to obtain an optimized model loss, and update the large language model according to the optimized model loss to obtain a chip layout model, wherein the pros and cons factor characterizes the difference in layout effect between the reference layout and other reference layouts.

[0014] In a third aspect, the present application provides a storage medium storing a computer program, which implements the chip layout model training method when executed by a processor.

[0015] In a fourth aspect, the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores a computer program, and the computer program implements the chip layout model training method when executed by the processor.

[0016] Compared with the prior art, this application has the following beneficial effects:

[0017] The present application provides a chip layout model training method, device, storage medium and electronic device. The electronic device obtains a fine-tuning sample set of a large language model, wherein the fine-tuning sample set includes chip design requirements and layout process information of multiple reference layouts that meet the chip design requirements, each reference layout needs to be obtained through at least one round of layout, and the layout process information of each reference layout includes the phased requirements corresponding to each round of layout and the phased layout suggestions for the phased requirements; for the layout process information of each reference layout, the phased requirements in the layout process information are input into the large language model to obtain the predicted layout suggestions generated by the large language model; based on the phased layout suggestions and the predicted layout suggestions, the model loss of the large language model is obtained; the model loss is adjusted by a quality factor to obtain an optimized model loss, and the large language model is updated according to the optimized model loss to obtain a chip layout model, wherein the quality factor represents the difference in layout effect between the reference layout and other reference layouts.

[0018] In this way, based on the chip design-related professional knowledge that the large language model has already learned, the large language model is further trained through pros and cons factors to learn the pros and cons of different chip layouts, so that the trained chip layout model can simulate human experts and provide high-quality chip layout recommendations. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A flowchart of a chip layout model training method provided in an embodiment of the present application;

[0021] Figure 2 Schematic diagram of input and output of the large language model provided in the embodiment of the present application;

[0022] Figure 3 A schematic diagram of a single layout of a chip layout model provided in an embodiment of the present application;

[0023] Figure 4 A schematic diagram of multiple layouts of a chip layout model provided in an embodiment of the present application;

[0024] Figure 5 One of the detailed schematic diagrams of the chip layout model training method provided in an embodiment of the present application;

[0025] Figure 6A second detailed schematic diagram of the chip layout model training method provided in an embodiment of the present application;

[0026] Figure 7 A second detailed schematic diagram of the chip layout model training method provided in an embodiment of the present application;

[0027] Figure 8 A schematic diagram of the principle of reinforcement learning provided in an embodiment of the present application;

[0028] Figure 9 A schematic diagram of the structure of a chip layout model training device provided in an embodiment of the present application;

[0029] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present application (hereinafter referred to as the embodiments) more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0032] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0033] In the description of this application, it should be noted that the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be understood as indicating or implying relative importance. In addition, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0034] Based on the above statement, as introduced in the background technology, how to effectively train large language models to optimize chip design layout is still a problem to be solved.

[0035] Based on the discovery of the above technical problems, the inventors have proposed the following technical solutions after creative work to solve or improve the above problems. It should be noted that the defects existing in the solutions in the above prior art are the results obtained by the inventors after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed in the embodiments of this application below for the above problems should all be the contributions made by the inventors to this application in the process of invention and creation, and should not be understood as technical contents known to those skilled in the art.

[0036] In view of the technical problems discovered above, this embodiment provides a chip layout model training method. Before explaining this method, the following first explains the relevant professional terms that may be involved in this embodiment to make the subsequent description of the chip layout model training method easier to understand.

[0037] A macro library is a collection of predefined functional modules or circuit units, each of which is called a macrocell. Each macrocell is carefully designed and optimized, allowing for reuse in different chip designs. Each macrocell in a macro library typically provides a specific function, such as a memory cell, logic gate, or arithmetic unit. Therefore, macrocells exist in a standardized form with fixed interfaces and performance parameters, allowing designers to select appropriate macrocells and combine them into complex chip architectures, just like building blocks.

[0038] A netlist is a file that describes the interconnections between circuit components and contains information about the connections between every component in a chip. A netlist details the logical connections of a circuit through components such as instances, ports, nets, and properties. Therefore, a netlist allows designers to clearly understand how each component in a circuit is connected, enabling them to achieve the desired circuit logic and functionality during chip manufacturing.

[0039] The canvas is used to describe the two-dimensional spatial layout of a chip's physical design and represents the actual available area on the silicon wafer during chip manufacturing. During chip design, designers need to rationally arrange various circuit components, including standard cells, macro cells, input / output (I / O) ports, and other functional modules, within the canvas. The size and shape of the canvas are typically determined by the chip's manufacturing process and design goals. For example, the chip's area, power consumption, and performance requirements all influence canvas planning. Therefore, designers need to map the logic circuits described in the netlist onto the canvas and determine the specific location of each component (e.g., logic gates, registers, macro cells, etc.). Designers need to comprehensively consider multiple constraints during this process, so a reasonable canvas design is crucial for meeting multiple chip objectives, including performance, power consumption, timing, and manufacturability.

[0040] A large language model is a natural language processing (NLP) technology based on deep learning. It requires training a model based on a specific architecture using large amounts of data. During training, a large language model learns the statistical patterns, semantic relationships, and contextual associations of language from massive amounts of text data, enabling efficient processing and generation of human language. Consequently, large language models possess powerful natural language understanding and generation capabilities. For example, well-known large language models include the ChatGPT-4o model released by OpenAI, the Claude 3 series of models released by Anthropic, and the Gemini series of models released by Google.

[0041] Multimodality refers to techniques or methods that combine different types of data or information modalities (such as text, images, audio, and video) for processing and analysis. Compared to single-modality analysis, multimodality can more comprehensively capture and understand the connections between multiple data types, thereby creating complementary information between different modalities and improving the reliability of model processing results.

[0042] Supervised fine-tuning (SFT) is a key step in the training of large language models. It is used to adapt a pre-trained model to a specific task or domain, thereby improving its performance on that task. The principle is to use supervised learning based on the pre-trained model, using labeled task-specific data and loss functions (such as cross-entropy loss) to guide the model to learn task-related patterns and regularities. For example, by using labeled task data (such as question-answer pairs and classification labels), the model's parameters can be further optimized, enabling it to more accurately understand and generate task-related outputs.

[0043] Reinforcement learning (RL) is a machine learning method that learns optimal policies through the interaction between an agent and its environment. Its core principle is based on a trial-and-error mechanism: the agent influences the environment by performing actions and receives feedback from the environment, with the goal of maximizing cumulative rewards. During the learning process, the agent observes the current state at each time step and selects an action based on the policy. After executing the action, the environment transitions to a new state and returns the corresponding reward. In this way, by continuously trying and adjusting its policy, the agent gradually learns how to make optimal decisions in a specific environment.

[0044] The Library Exchange Format (LEF) file is a standard format for describing integrated circuit physical design information. It primarily defines the physical characteristics of library cells, such as macro cell size, pin locations, metal layer information, and obstacles. Therefore, this file provides the necessary physical cell information for placement and routing tools, enabling these tools to correctly perform automatic placement and routing operations. LEF files are often used in conjunction with Design Exchange Format (DEF) files. The former provides a physical description of library cells, while the latter describes the physical layout and connectivity of the entire chip, jointly supporting the back-end process of integrated circuit design.

[0045] A Design Exchange Format file is a file used to describe the physical design layout of an integrated circuit. It primarily records the physical implementation details of the chip, including the location of macrocells, network connectivity, routing information, and hierarchical structure. Therefore, this file provides complete physical design data to layout and routing tools, allowing designs to be exchanged and optimized between different tools.

[0046] Based on the above explanations of relevant professional terms, such as Figure 1 As shown, the chip layout model training method provided in this embodiment includes:

[0047] S1, obtain the fine-tuning sample set of the large language model.

[0048] The fine-tuning sample set includes chip design requirements and layout process information for multiple reference layouts that meet these requirements. Each reference layout must be obtained through at least one round of layout. The layout process information for each reference layout includes the phased requirements corresponding to each round of layout and phased layout recommendations for these phased requirements. It should be noted that because fine-tuning large language models requires a large number of samples, the fine-tuning sample set can contain multiple chip design requirements, each of which corresponds to multiple reference layouts.

[0049] It should also be understood that in order to be able to process professional files in the EDA field such as netlists and macro libraries, the large language model in this embodiment also supports multi-modal processing capabilities. Figure 2 The multimodal capabilities of large language models are more intuitively demonstrated. Figure 2 As shown, the layout optimization input file for the large language model includes a LEF file that records the netlist, a DEF file that records the macro library, and user instructions in natural language. The user instructions are used to inform the large language model designer of their needs. For example, the user instruction could be "Please describe the input file information and perform phased layout optimization for the current layout."

[0050] Continue to see Figure 2 For LEF files and DEF files, in order to enable the large language model to process them like text, it is necessary to extract the encoding features of these files through a file encoder, and further convert the extracted encoding features into text encoding that can be processed by the large language model. Figure 2 The large language model shown is trained so that the trained chip layout model can convert the input LEF file, DEF file, and user instructions into chip layout suggestions. The chip layout suggestions may include the placement order of multiple macro units in the canvas and the placement position of each macro unit.

[0051] In addition, it should be understood that the number of layout operations required for different LEF files, DEF files, and user instructions may vary significantly. Figure 3 As shown (user instructions are not shown), in some application scenarios, the trained chip layout model can obtain the final layout through only a single layout. Figure 4 As shown (user instructions are not shown), in other complex scenarios, the trained chip layout model may need to go through multiple rounds of iterative layout to obtain the final layout. Therefore, in this implementation, the layout process information of each reference layout in the sample set needs to be fine-tuned, including the phased requirements corresponding to each round of layout and the phased layout suggestions for each phased requirement, so that the large language model can learn the skills of phased layout.

[0052] For example, consider a layout task involving 10 macrocells. In the first round of layout, only 4 of the macrocells can be laid out, resulting in a phased layout of 4 macrocells. In the second round of layout, 3 of the remaining 6 macrocells can be selected and collaboratively laid out with the 4 macrocells already laid out in the first round, resulting in a phased layout of 7 macrocells. In the third round of layout, the remaining 3 macrocells are combined with the 7 macrocells already laid out in the first two rounds for an overall optimized layout, resulting in a final layout of 10 macrocells. In this way, a progressive layout strategy can effectively improve layout quality and optimization efficiency.

[0053] Because in some complex scenarios, multiple rounds of iterative layout are required to achieve the expected goals, this embodiment refers to the data input into the large language model during each round of layout as phased requirements. Among them, compared with the phased requirements, the chip design requirements are similar in data structure, both of which include netlists, macro units to be laid out, the current canvas status, and user instructions; the difference is that the chip design requirements are original requirements, and their corresponding canvas status is blank, while the phased requirements will change dynamically with the layout process. Specifically, except for the first round of layout, the chip design requirements are used as the phased requirements for that round of layout, and the canvas status of each subsequent round of layout is the layout status of the existing macro units in the canvas.

[0054] Furthermore, user instructions in each layout round can be implicitly reflected through context during interaction with the large language model. For example, explicit input can be performed only in the first layout round, and the user instructions can be captured through the context in subsequent rounds. Of course, explicit input can also be performed in each round, that is, user instructions are entered once in each layout round to prevent the large language model from missing user instructions.

[0055] Based on the explanation of the fine-tuning sample set in step S1 in the above embodiment, the following is Figure 1 Explanation of step S2 in FIG.

[0056] S2: For the layout process information of each reference layout, the phased requirements in the layout process information are input into the large language model to obtain the predicted layout suggestions generated by the large language model.

[0057] In this embodiment, for multiple sets of layout process information corresponding to multiple reference layouts, the phased requirements within each set of layout process information can be sequentially input into the large language model for fine-tuning. Alternatively, the phased requirements within multiple sets of layout process information can be randomly input into the large language model for fine-tuning. This embodiment does not specifically limit the method for inputting multiple sets of layout process information.

[0058] S3, based on the staged layout suggestions and the predicted layout suggestions, obtains the model loss of the large language model.

[0059] This embodiment uses supervised fine-tuning to fine-tune the large language model. It can be understood that when the large language model is first trained, the predicted layout suggestions it outputs are not reasonable and differ significantly from the staged layout suggestions. The difference between the two is measured using model loss, and the large language model is fine-tuned using this model loss, so that the predicted suggestions output by the large language model approach the reference suggestions. Details on the calculation of model loss can be found in the relevant description of SFT and will not be elaborated on in this embodiment.

[0060] S4, adjusts the model loss by the pros and cons factor to obtain the optimized model loss, and updates the large language model according to the optimized model loss to obtain the chip layout model.

[0061] The performance factor characterizes the difference in layout performance between a reference layout and other reference layouts. It should be understood that while multiple reference layouts can meet chip design requirements, there are relative advantages and disadvantages between the multiple reference layouts. Therefore, this embodiment quantifies this using the performance factor and applies it to the model loss when fine-tuning the large language model. This allows the large language model to learn the advantages and disadvantages of multiple reference layouts from the optimized model loss.

[0062] In this way, based on the chip design-related professional knowledge that the large language model has already learned, the large language model is further trained through pros and cons factors to learn the pros and cons of different chip layouts, so that the trained chip layout model can simulate human experts and provide high-quality chip layout recommendations.

[0063] For the chip layout model training method provided in this embodiment, the electronic device implementing the method may be, but is not limited to, a mobile terminal, a tablet computer, a laptop computer, a desktop computer, and a server, etc., as long as it can provide sufficient computing power for model training. When the electronic device is a server, the server may be a single server or a server group. The server group may be centralized or distributed (for example, the server may be a distributed system). In some embodiments, the server may be local or remote relative to the user terminal. In some embodiments, the server may be implemented on a cloud platform; as an example only, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud (Community Cloud), a distributed cloud, an inter-cloud (Inter-Cloud), a multi-cloud (Multi-Cloud), etc., or any combination thereof. In some embodiments, the server may be implemented on an electronic device having one or more components.

[0064] In order to make the solution provided by this embodiment clearer, the following uses a server as an electronic device to implement the method. Figure 1Each step in the method shown is described in detail. However, it should be understood that the operations in the flowchart may not be performed in order, and steps that have no logical contextual relationship may be reversed or performed simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more additional operations to the flowchart or remove one or more operations from the flowchart.

[0065] In this embodiment, the phased layout suggestions for each round of layout include descriptive information of the phased layout and reasoning information for obtaining the phased layout, wherein the phased layout refers to the chip layout that meets the phased requirements. For each chip design requirement, multiple reference layouts can be generated with the help of currently available chip layout tools. For example, multiple reference layouts that meet the chip layout suggestions can be generated by Alphachip. As for the reasoning information in the phased layout suggestions, this embodiment uses a third-party large language model to analyze the chip design requirements and the reference layout, and infers the number of layout rounds required to obtain the reference layout from the chip design requirements, the phased layout after each round of layout, and the reasoning information required to obtain each phased layout. For example, the third large language model can be a ChatGPT-4o model.

[0066] Compared to fine-tuning samples that directly generate chip layout recommendations all at once, each training sample in this implementation is stage-by-stage, including stage-by-stage requirements, reasoning information, and descriptions of the stage-by-stage layout. This allows the large language model to learn human layout methods, such as categorizing and grouping macrocells for placement, and to backtrack to a previous node and re-explore the search tree when necessary.

[0067] Therefore, in this embodiment, the description information of the phased requirements, reasoning information, and phased layout is combined into a training sample. For the convenience of description, this embodiment represents each training sample as<input,think+answer> In the form of, input represents the stage demand, think represents the reasoning information, and answer represents the description information of the stage layout. Based on the above invention concept, as Figure 5 As shown, this embodiment provides Figure 1 The following optional implementations of step S1 are shown:

[0068] S1-1, obtain multiple reference layouts that meet chip design requirements.

[0069] S1-2: For each reference layout, a third-party large language model is called to process the chip design requirements and the description information of the reference layout to obtain layout process information of the reference layout.

[0070] Exemplarily, let’s continue to take the multiple reference layouts generated by Alphachip as an example. First of all, it should be understood that the reference layout output by AlphaChip is usually not in text form, but in the form of technical data, graphical layout or structured file, including the placement of each component on the chip, connection relationship and performance indicators (such as power consumption, timing, area, etc.). Therefore, the server needs to first convert the reference layout output by AlphaChip into natural language form, and combine it with the original chip design requirements to generate a prompt word (Prompt) for training samples. This prompt word is input into ChatGPT-4o to instruct ChatGPT-4o to generate the number of layout rounds required to obtain the reference layout based on the chip design requirements, the stage layout after each round of layout, and the reasoning information required to obtain each stage layout. Finally, the generated reasoning information is verified, and only the information corresponding to each round of layout is verified.<input,think> Can be perfectly inferred <answer>After that, you can<input, think+answer> Used for fine-tuning large language models.

[0071] In this way, by using a third-party large language model to generate the samples required for fine-tuning, a large number of high-quality samples can be generated for model fine-tuning when there is a lack of fine-tuning samples.

[0072] Based on the above description of the method for obtaining the fine-tuning sample set, in order to obtain the pros and cons factor of each reference layout and characterize the differences in layout effects between multiple reference layouts, this embodiment compares the layout scores of multiple reference layouts to obtain the pros and cons factor of each reference layout. Figure 6 As shown, in Figure 5 Before step S3, the chip layout model training method further includes:

[0073] S2.1, obtain layout scores for multiple reference layouts.

[0074] S2.2, compare the layout scores of multiple reference layouts to obtain the pros and cons factor of each reference layout.

[0075] In this way, by comparing the layout scores of multiple reference layouts, the pros and cons factor of each reference layout can be obtained, so that the pros and cons factor can characterize the difference in layout effects between the reference layout and other reference layouts.

[0076] From the above implementation, it can be seen that the quality factor depends on the layout score. For each reference layout, this implementation evaluates the three aspects of line length, congestion level, and density. It should be understood that these evaluation factors are the inventor's experience summary in practice.

[0077] Specifically, the length of the interconnection lines between macro units has a significant impact on the timing performance and power consumption of the chip. Specifically, a shorter interconnection line length can effectively reduce signal transmission delay and reduce power loss, thereby improving the overall performance of the chip; on the contrary, an excessively long interconnection line length will not only increase signal delay, but also increase power consumption, ultimately affecting chip performance. In addition, the study also found that some chip layout methods will lead to signal line congestion, which is specifically manifested in the excessive occupation of wiring resources in specific areas, and dense interweaving of signal lines, resulting in insufficient available wiring channels. When congestion occurs, it will not only increase the difficulty of wiring, but may also cause signal delays, increased power consumption, and even make it impossible to complete wiring in some areas, thereby affecting the overall performance and function realization of the chip. In addition, some chip layout methods will cause the macro units to be too dense, and too high a density may lead to poor heat dissipation and poor signal integrity, affecting the stability and reliability of the chip. Based on the above findings, the layout score in this embodiment integrates factors such as the reference layout in terms of line length, congestion level, and density. Therefore, this embodiment also provides Figure 6 The following implementation of step S2.1 is shown in:

[0078] S2.1-1. For each reference layout, obtain the line length, congestion level, and density of the reference layout.

[0079] In this embodiment, macro cells may be arranged in a canvas according to a reference layout, and then the line length, congestion level, and density under the reference layout may be obtained from the canvas.

[0080] S2.1-2, obtain a layout score of the reference layout based on the line length, congestion level, and density of the reference layout.

[0081] In this embodiment, the server can weight the line length, congestion level, and density with a preset weight to obtain a layout score of the reference layout. Therefore, the layout score objectively evaluates the layout effect of the reference layout from multiple aspects.

[0082] The layout score of the reference layout in the above implementation is an absolute score. In practice, it is found that there are certain limitations in directly applying it to the model loss. Specifically, the absolute score is usually calculated based on specific indicators or standards and cannot directly reflect the relative advantages and disadvantages of different layout schemes. For example, a certain layout is scored 80 points and another layout is scored 85 points. Although the latter is higher in terms of numerical value, this difference cannot explain the position of the latter among multiple reference layouts. Therefore, this embodiment needs to convert the absolute score into a relative advantage score, that is, Figure 6 Step S2.2 in may include:

[0083] S2.2-1, obtaining an average layout score among the multiple reference layouts based on the layout scores of each of the multiple reference layouts.

[0084] S2.2-2, respectively determine the ratio between the layout score of each reference layout and the average layout score as the quality factor of each reference layout.

[0085] To do this, the server first quantifies the overall layout performance by calculating the average layout score of multiple reference layouts. It should be understood that this average layout score serves as a baseline, reflecting the overall performance of all reference layouts. The server then calculates the ratio of each reference layout's layout score to the average layout score, accurately assessing the degree to which each reference layout deviates from the overall level. This ratio not only intuitively reflects each reference layout's relative position within the overall layout, but also quantitatively indicates the degree to which it performs better or worse than the average level.

[0086] In the above implementation, after fine-tuning the large language model using the fine-tuning sample set, the fine-tuned chip layout model can infer a chip layout that at least meets some of the requirements of the chip to be processed, and can also evaluate the effects of different chip layouts. On this basis, this embodiment also performs reinforcement learning on the chip layout model to further improve the chip layout capability of the chip layout model. Therefore, Figure 7 As shown, in Figure 6 Based on this, the chip layout model training method also includes:

[0087] S5, obtaining chip requirements to be processed.

[0088] Similar to the fine-tuning phase of the chip layout model, the chip requirements to be processed may include a netlist, a macro library, user instructions, and the current canvas status.

[0089] Based on the description of the chip requirements to be processed in step S5 in the above embodiment, the following Figure 7 Step S6 in the following is explained:

[0090] S6, processing the chip requirements to be processed through the chip layout model to obtain multiple candidate chip layouts.

[0091] It should be understood that, similar to the fine-tuning phase, the chip layout model also needs to output a chip layout after processing the chip requirements. However, unlike the fine-tuning phase, it no longer outputs layout suggestions for just one chip layout, but rather for multiple chip layouts. In this embodiment, the multiple chip layouts in the reinforcement learning phase are referred to as multiple candidate chip layouts. Within-group comparison is used to strengthen the chip layout model, making the model more inclined to select layouts with higher relative advantages and less inclined to select layouts with lower relative advantages.

[0092] Based on the above description of the various candidate chip layouts in step S6, we will continue to Figure 7 Step S7 in the following is explained:

[0093] S7, compares the layout rewards of multiple candidate chip layouts to obtain a relative advantage score of each candidate chip layout.

[0094] In this embodiment, the server can evaluate the layout effects of multiple candidate chip layouts separately. If the layout effect is good, a higher layout reward is given, otherwise, a lower layout reward is given. In a specific implementation, the server can calculate the layout score of each candidate chip layout, and then map the layout score of each chip to the layout reward, where the layout score is positively correlated with the layout reward. Based on the layout reward of each candidate chip layout, the relative advantage scores between the multiple candidate chip layouts can be calculated in the following way:

[0095]

[0096] Where, Indicates the The relative advantage scores of the candidate layouts, Indicates the Layout rewards for candidate layouts, represents the average of the layout rewards of multiple candidate chip layouts, Represents the variance between placement rewards for multiple candidate chip placements.

[0097] S8, using the relative advantage scores of multiple candidate chip layouts as reward signals, updates the chip layout model through reinforcement learning to obtain a reinforced chip layout model.

[0098] For example, the following is combined Figure 8 A more intuitive demonstration of how to enhance the above chip layout model is provided. Figure 8 The server is at time The netlist, macro library, current layout and user instructions are input into the chip layout model. After multiple rounds of layout (each round of layout is output as an action list), the chip layout model is Output multiple candidate chip layouts, then compare the layout rewards of the multiple candidate chip layouts to obtain the relative advantage score of each candidate layout; finally, the reward signal is fed back to the model output of each round, causing the model to increase the generation probability of those layouts with higher relative advantages, while reducing the generation probability of those layouts with lower relative advantages.

[0099] In this way, after reinforcement learning, the model will increase the generation probability of those layout methods with higher relative advantages, while reducing the generation probability of those layout methods with lower relative advantages; through this reinforcement learning method, the model can gradually learn which layout methods are better.

[0100] Compared to traditional deep reinforcement learning, the chip layout model based on a large language model, after reinforcement learning, has a larger number of parameters and stronger reasoning capabilities. It can better focus on the context of the search and perform a more flexible layout strategy search with backtracking. Actual testing has shown that the enhanced chip layout model is no longer restricted to a sequential, one-by-one placement strategy when placing macro units. Instead, it can place macro units in groups and categories, similar to humans. It can even backtrack to a previous node and explore another search tree when necessary, fully leveraging the reasoning capabilities of large reinforcement learning models.

[0101] Based on the same inventive concept as the chip layout model training method provided in this embodiment, this embodiment also provides a chip layout model training device, which includes at least one software function module that can be stored in a memory or fixed in an electronic device in the form of software. The processor in the electronic device is used to execute the executable module stored in the memory. For example, the software function module and computer program included in the device. Please refer to Figure 9 Functionally, the device can include:

[0102] A sample preparation module 11 is configured to obtain a fine-tuning sample set for a large language model. The fine-tuning sample set includes chip design requirements and layout process information for multiple reference layouts that meet the chip design requirements. Each reference layout must be obtained through at least one layout round. The layout process information for each reference layout includes the phased requirements corresponding to each layout round and phased layout suggestions for the phased requirements.

[0103] A model training module 12 is configured to input the phased requirements in the layout process information of each reference layout into a large language model to obtain a predicted layout suggestion generated by the large language model;

[0104] The model training module 12 is further configured to obtain a model loss of the large language model based on the staged layout suggestions and the predicted layout suggestions;

[0105] The model training module 12 is also used to adjust the model loss through the pros and cons factor to obtain an optimized model loss, and update the large language model according to the optimized model loss to obtain a chip layout model, wherein the pros and cons factor represents the difference in layout effect between the reference layout and other reference layouts.

[0106] Therefore, in this embodiment, the sample preparation module 11 is used to implement Figure 1 In step S1, the model training module 12 is used to implement Figure 1 Therefore, for the detailed description of each of the above modules, please refer to the specific implementation of the corresponding steps.

[0107] In addition, it should be understood that since the chip layout model training method has the same inventive concept, the chip layout model training device can also implement other steps or sub-steps of the method through the above modules.

[0108] Optionally, before adjusting the model loss by the pros and cons factor to obtain the optimized model loss, the sample preparation module 11 is further configured to:

[0109] Obtain layout scores for multiple reference layouts;

[0110] The layout scores of multiple reference layouts are compared to obtain the pros and cons factor of each reference layout.

[0111] Optionally, the sample preparation module 11 is further specifically configured to:

[0112] For each reference layout, obtain the line length, congestion level, and density of the reference layout;

[0113] A layout score of the reference layout is obtained according to the line length, congestion level, and density of the reference layout.

[0114] Optionally, the sample preparation module 11 is further specifically configured to:

[0115] Obtaining an average layout score among the multiple reference layouts according to the respective layout scores of the multiple reference layouts;

[0116] The ratio between the layout score of each reference layout and the average layout score is determined as the quality factor of each reference layout.

[0117] Optionally, the sample preparation module 11 is further specifically configured to:

[0118] Get multiple reference layouts that meet chip design needs;

[0119] For each reference layout, a third-party large language model is called to process the chip design requirements and the description information of the reference layout to obtain the layout process information of the reference layout.

[0120] Optionally, the model training module 12 is further configured to:

[0121] Obtain chip requirements to be processed;

[0122] Processing the chip requirements to be processed by the chip layout model to obtain multiple candidate chip layouts;

[0123] Compare the layout rewards of multiple candidate chip layouts to obtain a relative advantage score for each candidate chip layout;

[0124] The relative advantage scores of multiple candidate chip layouts are used as reward signals, and the chip layout model is updated through reinforcement learning to obtain a reinforced chip layout model.

[0125] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0126] It should also be understood that if the above embodiments are implemented in the form of software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the portion that contributes to the prior art, or the portion of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0127] Therefore, this embodiment further provides a storage medium that is computer-readable. The storage medium stores a computer program that, when executed by a processor, implements the chip layout model training method provided in this embodiment. The storage medium can be any medium capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0128] This embodiment provides an electronic device for implementing a chip layout model training method. Figure 10 As shown, the electronic device includes a processor 22 and a memory 21. In addition, the memory 21 stores a computer program, and the processor implements the chip layout model training method provided in this embodiment by reading and executing the computer program corresponding to the above embodiment in the memory 21.

[0129] Continue to see Figure 10 The electronic device further includes a communication unit 23. The memory 21, the processor 22 and the communication unit 23 are electrically connected to each other directly or indirectly via a system bus 24 to achieve data transmission or interaction.

[0130] The memory 21 may be an information recording device based on any electronic, magnetic, optical or other physical principles, for recording execution instructions, data, etc. In some embodiments, the memory 21 may be, but is not limited to, a volatile memory, a non-volatile memory, a storage drive, etc.

[0131] In some embodiments, the volatile memory may be a random access memory (RAM); in some embodiments, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, etc.; in some embodiments, the storage drive may be a magnetic disk drive, a solid-state drive, any type of storage disk (such as a CD, DVD, etc.), or a similar storage medium, or a combination thereof.

[0132] The communication unit 23 is configured to transmit and receive data via a network. In some embodiments, the network may include a wired network, a wireless network, a fiber optic network, a telecommunications network, an intranet, the Internet, a local area network (LAN), a wide area network (WAN), a wireless local area network (WLAN), a metropolitan area network (MAN), a wide area network (WAN), a public switched telephone network (PSTN), a Bluetooth network, a ZigBee network, or a near field communication (NFC) network, or any combination thereof. In some embodiments, the network may include one or more network access points. For example, the network may include a wired or wireless network access point, such as a base station and / or a network switching node, through which one or more components of the service request processing system may connect to the network to exchange data and / or information.

[0133] The processor 22 may be an integrated circuit chip having signal processing capabilities, and the processor may include one or more processing cores (e.g., a single-core processor or a multi-core processor). By way of example only, the processor may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), an application-specific instruction-set processor (ASIP), a graphics processing unit (GPU), a physical processing unit (PPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a microcontroller unit, a reduced instruction set computer (RISC), or a microprocessor, or any combination thereof.

[0134] I understand. Figure 10 The structure shown is for reference only. Figure 10 More or fewer components than shown, or with Figure 10 Different configurations shown. Figure 10 The components shown may be implemented in hardware, software, or a combination thereof.

[0135] It should be understood that the devices and methods disclosed in the above embodiments may also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the devices, methods, and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram may represent a module, a program segment, or a portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes may actually be executed substantially in parallel, or they may sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, may be implemented using a dedicated hardware-based system that performs a specified function or action, or may be implemented using a combination of dedicated hardware and computer instructions.

[0136] The above descriptions are merely examples of various embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.< / answer>

Claims

1. A chip layout model training method, characterized in that: The method comprises: Obtaining a fine-tuning sample set for a large language model, wherein the fine-tuning sample set includes chip design requirements and layout process information of multiple reference layouts that meet the chip design requirements, each reference layout must be obtained through at least one round of layout, and the layout process information of each reference layout includes phased requirements corresponding to each round of layout and phased layout suggestions for the phased requirements; Obtaining layout scores of the multiple reference layouts; Obtaining an average layout score among the multiple reference layouts according to the layout scores of each of the multiple reference layouts; Determining the ratio between the layout score of each reference layout and the average layout score as the quality factor of each reference layout; For each reference layout, inputting the phased requirements in the layout process information into the large language model to obtain a predicted layout suggestion generated by the large language model; Obtaining a model loss of the large language model according to the phased layout suggestion and the predicted layout suggestion; The model loss is adjusted by the pros and cons factor of the reference layout to obtain an optimized model loss, and the large language model is updated according to the optimized model loss to obtain a chip layout model, wherein the pros and cons factor represents the difference in layout effect between the reference layout and other reference layouts.

2. The chip layout model training method according to claim 1, characterized in that: Obtain scores for each of the multiple reference layouts, including: For each of the reference layouts, obtaining the line length, congestion level, and density of the reference layout; A layout score of the reference layout is obtained according to the line length, congestion level, and density of the reference layout.

3. The chip layout model training method according to claim 1, characterized in that: Obtain a fine-tuning sample set for a large language model, including: Acquire multiple reference layouts that meet the chip design requirements; For each reference layout, a third-party large language model is called to process the chip design requirements and the description information of the reference layout to obtain layout process information of the reference layout.

4. The chip layout model training method according to any one of claims 1 to 3, characterized in that: The phased layout suggestion includes description information of the phased layout and reasoning information for obtaining the phased layout, and the phased layout is a chip layout that meets the phased requirements.

5. The chip layout model training method according to any one of claims 1 to 3, characterized in that: The method further comprises: Obtain chip requirements to be processed; Processing the chip requirements to be processed by using the chip layout model to obtain multiple candidate chip layouts; Comparing the layout rewards of the multiple candidate chip layouts to obtain a relative advantage score for each candidate chip layout; The relative advantage scores of the multiple candidate chip layouts are used as reward signals, and the chip layout model is updated through reinforcement learning to obtain a reinforced chip layout model.

6. A chip layout model training device, characterized in that: The device comprises: A sample preparation module is configured to obtain a fine-tuning sample set for a large language model, wherein the fine-tuning sample set includes chip design requirements and layout process information of multiple reference layouts that meet the chip design requirements. Each reference layout must be obtained through at least one round of layout. The layout process information of each reference layout includes the phased requirements corresponding to each round of layout and phased layout suggestions for the phased requirements. The sample preparation module is further configured to obtain layout scores of the multiple reference layouts; obtain an average layout score among the multiple reference layouts based on the layout scores of the multiple reference layouts; and determine the ratio between the layout score of each reference layout and the average layout score as a quality factor of each reference layout; a model training module, configured to input the phased requirements in the layout process information of each reference layout into the large language model to obtain a predicted layout suggestion generated by the large language model; The model training module is further configured to obtain a model loss of the large language model based on the phased layout suggestion and the predicted layout suggestion; The model training module is further configured to adjust the model loss according to the pros and cons factor of the reference layout to obtain an optimized model loss, and update the large language model according to the optimized model loss to obtain a chip layout model, wherein the pros and cons factor characterizes the difference in layout effect between the reference layout and other reference layouts.

7. A storage medium, characterized in that: The storage medium stores a computer program, and the computer program, when executed by a processor, implements the chip layout model training method according to any one of claims 1 to 5.

8. An electronic device, characterized in that: The electronic device includes a processor and a memory, the memory stores a computer program, and the computer program, when executed by the processor, implements the chip layout model training method according to any one of claims 1 to 5.

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