Shift register, gate drive circuit and display device

Abstract

The invention provides a shift register, a gate drive circuit and a display device, belongs to the technical field of display, and can solve the problem that a part of transistors in an existing shift register are prone to breakdown, and the display effect is affected. The shifting register comprises a first output sub-circuit, a second output sub-circuit and a first adjusting sub-circuit, the first output sub-circuit is configured to respond to the voltage of the pull-up node, transmit a clock signal of a clock signal end to a first node, and output the clock signal through a current-stage signal output end; the second output sub-circuit is configured to respond to the voltage of the pull-down node, transmit a non-working level signal of a non-working level signal end to a second node, and output the non-working level signal through a current-stage signal output end; the first adjusting sub-circuit is configured to control the voltage of the first node when the current-stage signal output end outputs a non-working level signal and the clock signal of the clock signal end is a working level signal, so as to adjust the voltage difference between the first node and the current-stage signal output end.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a shift register, a gate driving circuit, and a display device. Background Art

[0002] With the continuous development of display technology, in recent years, the development of displays has gradually shown a trend of high integration and low cost. One of the very important technologies is the mass production implementation of the Gate Driver on Array (GOA) technology. By using the GOA technology, the gate switch circuit composed of thin film transistors (TFTs) is integrated on the array substrate of the display panel to form a scan drive for the display panel, thereby eliminating the gate driver integrated circuit part. This can not only reduce the product cost in terms of both material cost and manufacturing process, but also enable the display panel to achieve a beautiful design with symmetry on both sides and narrow borders. Summary of the Invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a shift register, a gate driving circuit, and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a shift register, which includes: a first output sub-circuit, a second output sub-circuit, and a first adjustment sub-circuit;

[0005] The first output sub-circuit is configured to transmit the clock signal at the clock signal terminal to the first node in response to the voltage at the pull-up node, and output it through the signal output terminal of the current stage;

[0006] The second output sub-circuit is configured to transmit the non-operating level signal at the non-operating level signal terminal to the second node in response to the voltage at the pull-down node, and output it through the signal output terminal of the current stage;

[0007] The first adjustment sub-circuit is configured to control the voltage of the first node to adjust the voltage difference between the first node and the signal output terminal of the current stage when the non-operating level signal is output at the signal output terminal of the current stage and the clock signal at the clock signal terminal is a working level signal.

[0008] In some embodiments, the first adjustment sub-circuit includes: a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;

[0009] The control electrode and the first electrode of the fourteenth transistor are connected to the clock signal terminal, and the second electrode is connected to the first electrode of the fifteenth transistor;

[0010] The control electrode of the fifteenth transistor is connected to the pull-up node, the first electrode is connected to the second electrode of the fourteenth transistor, and the second electrode is connected to the control electrode of the sixteenth transistor;

[0011] The control electrode of the sixteenth transistor is connected to the second electrode of the fifteenth transistor, the first electrode is connected to the first auxiliary node, and the second electrode is connected to the second auxiliary node; the first auxiliary node and the second auxiliary node are two nodes formed after the disconnection at the first node.

[0012] In some embodiments, the first adjustment sub-circuit includes: a seventeenth transistor;

[0013] The control electrode and the first electrode of the seventeenth transistor are connected to the first auxiliary node, and the second electrode is connected to the second auxiliary node; the first auxiliary node and the second auxiliary node are two nodes formed after the disconnection at the first node.

[0014] In some embodiments, the first adjustment sub-circuit includes: an eighteenth transistor and a nineteenth transistor;

[0015] The control electrode and the first electrode of the eighteenth transistor are connected to the clock signal terminal, and the second electrode is connected to the first electrode and the control electrode of the nineteenth transistor;

[0016] The control electrode and the first electrode of the nineteenth transistor are connected to the second electrode of the eighteenth transistor, and the second electrode is connected to the first node.

[0017] In some embodiments, the shift register further includes: a second adjustment sub-circuit;

[0018] The second adjustment sub-circuit is configured to control the voltage of the second node when the clock signal output at the current stage signal output terminal is a working level signal, so as to adjust the voltage difference between the second node and the current stage signal output terminal.

[0019] In some embodiments, the second adjustment sub-circuit includes: a twentieth transistor, a twenty-first transistor, and a twenty-second transistor;

[0020] The control electrode and the first electrode of the twentieth transistor are connected to the clock signal terminal, and the second electrode is connected to the first electrode of the twenty-first transistor;

[0021] The control electrode of the twenty-first transistor is connected to the pull-down node, the first electrode is connected to the second electrode of the twentieth transistor, and the second electrode is connected to the control electrode of the twenty-second transistor;

[0022] The control electrode of the twenty-second transistor is connected to the second electrode of the twentieth transistor, the first electrode is connected to the third auxiliary node, and the second electrode is connected to the fourth auxiliary node; the third auxiliary node and the fourth auxiliary node are two nodes formed after the second node is disconnected.

[0023] In some embodiments, the second adjustment sub-circuit includes: a twenty-third transistor;

[0024] The control electrode and the first electrode of the twenty-third transistor are connected to the third auxiliary node, and the second electrode is connected to the fourth auxiliary node; the third auxiliary node and the fourth auxiliary node are two nodes formed after the second node is disconnected.

[0025] In some embodiments, the second adjustment sub-circuit includes: a twenty-fourth transistor and a twenty-fifth transistor;

[0026] The control electrode and the first electrode of the twenty-fourth transistor are connected to the non-operating level signal terminal, and the second electrode is connected to the first electrode and the control electrode of the twenty-fifth transistor;

[0027] The control electrode and the first electrode of the twenty-fifth transistor are connected to the second electrode of the twenty-fourth transistor, and the second electrode is connected to the second node.

[0028] In some embodiments, the first output sub-circuit includes: a tenth transistor, an eleventh transistor, and a storage capacitor;

[0029] The control electrode of the tenth transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the first node;

[0030] The control electrode of the eleventh transistor is connected to the pull-up node, the first electrode is connected to the first node, and the second electrode is connected to the local signal output terminal;

[0031] One end of the storage capacitor is connected to the pull-up node, and the other end is connected to the local signal output terminal;

[0032] The second output sub-circuit includes: a twelfth transistor and a thirteenth transistor;

[0033] The control electrode of the twelfth transistor is connected to the pull-down node, the first electrode is connected to the non-operating level signal terminal, and the second electrode is connected to the second node;

[0034] The control electrode of the thirteenth transistor is connected to the pull-down node, the first electrode is connected to the second node, and the second electrode is connected to the local signal output terminal.

[0035] In some embodiments, the shift register further includes: an input sub-circuit, a reset sub-circuit, a discharge sub-circuit, a first pull-down control sub-circuit, a second pull-down control sub-circuit, a first pull-down sub-circuit, and a second pull-down sub-circuit;

[0036] The input sub-circuit is configured to transmit the voltage of the upper-stage signal output terminal to the pull-up node in response to the voltage of the upper-stage signal output terminal, so as to charge the pull-up node;

[0037] The reset sub-circuit is configured to transmit the non-operating level signal of the non-operating level signal terminal to the pull-up node in response to the voltage of the lower-stage signal output terminal, so as to reset the pull-up node;

[0038] The discharge sub-circuit is configured to transmit the non-operating level signal of the non-operating level signal terminal to the pull-up node in response to the voltage of the pull-down node, so as to discharge the pull-up node;

[0039] The first pull-down control sub-circuit is configured to transmit the first power signal of the first power signal terminal to the pull-down node in response to the voltage of the first power signal terminal, so as to control the voltage of the pull-down node;

[0040] The second pull-down control sub-circuit is configured to transmit the second power signal of the second power signal terminal to the pull-down node in response to the voltage of the second power signal terminal, so as to control the voltage of the pull-down node;

[0041] The first pull-down sub-circuit is configured to transmit the non-operating level signal of the non-operating level signal terminal to the pull-down node in response to the voltage of the pull-up node, so as to pull down the voltage of the pull-down node;

[0042] The second pull-down sub-circuit is configured to transmit the non-operating level signal of the non-operating level signal terminal to the pull-down node in response to the voltage of the pull-up node, so as to pull down the voltage of the pull-down node.

[0043] In some embodiments, the input sub-circuit includes: a first transistor; the control electrode and the first electrode of the first transistor are connected to the upper-stage signal output terminal;

[0044] The reset sub-circuit includes: a second transistor; the control electrode of the second transistor is connected to the lower-stage signal output terminal, the first electrode is connected to the non-operating level signal terminal, and the second electrode is connected to the pull-up node;

[0045] The discharge sub-circuit includes: a third transistor; the control electrode of the third transistor is connected to the pull-down node, the first electrode is connected to the non-operating level signal terminal, and the second electrode is connected to the pull-up node;

[0046] The first pull-down control sub-circuit includes: a fourth transistor; a control electrode and a first electrode of the fourth transistor are connected to a first power signal terminal, and a second electrode is connected to the pull-down node;

[0047] The first pull-down sub-circuit includes: a fifth transistor and a sixth transistor; a control electrode of the fifth transistor is connected to the pull-up node, a first electrode is connected to a second electrode of the sixth transistor, and a second electrode is connected to the pull-down node; a control electrode of the sixth transistor is connected to the pull-up node, a first electrode is connected to the non-operating level signal terminal, and a second electrode is connected to the first electrode of the fifth transistor;

[0048] The second pull-down control sub-circuit includes: a seventh transistor; a control electrode and a first electrode of the seventh transistor are connected to a second power signal terminal, and a second electrode is connected to the pull-down node;

[0049] The second pull-down sub-circuit includes: an eighth transistor and a ninth transistor; a control electrode of the eighth transistor is connected to the pull-up node, a first electrode is connected to a second electrode of the ninth transistor, and a second electrode is connected to the pull-down node; a control electrode of the ninth transistor is connected to the pull-up node, a first electrode is connected to the non-operating level signal terminal, and a second electrode is connected to the first electrode of the eighth transistor.

[0050] In a second aspect, an embodiment of the present disclosure provides a gate driving circuit, which includes a plurality of cascaded shift registers as provided in the first aspect above.

[0051] In a third aspect, an embodiment of the present disclosure provides a display device, which includes the gate driving circuit as provided in the second aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a schematic structural diagram of some devices in an exemplary gate driving circuit.

[0053] Figure 2 It is a schematic structural diagram of the first shift register provided by an embodiment of the present disclosure.

[0054] Figure 3 For Figure 2 The timing diagram of the shift register shown.

[0055] Figure 4 It is a schematic structural diagram of the second shift register provided by an embodiment of the present disclosure.

[0056] Figure 5 It is a schematic structural diagram of the third shift register provided by an embodiment of the present disclosure.

[0057] Figure 6Schematic diagram of the fourth shift register provided by the embodiments of the present disclosure.

[0058] Figure 7 Schematic diagram of the fifth shift register provided by the embodiments of the present disclosure.

[0059] Figure 8 Schematic diagram of the sixth shift register provided by the embodiments of the present disclosure. Detailed implementation manners

[0060] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part rather than all of the embodiments of the present disclosure. Components of the embodiments of the present disclosure generally described and illustrated in the accompanying drawings herein can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the claimed present disclosure, but merely represents selected embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure. Without conflict, the various embodiments of the present disclosure and the features in the embodiments can be combined with each other.

[0061] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "include" or "comprise" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items.

[0062] The term "a plurality of or several" mentioned in the present disclosure means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0063] It should be noted here that the transistors used in the embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetric, there is no difference between the source and drain. In the embodiments of the present disclosure, to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. In the following embodiments, the N-type transistor is used for illustration. When the N-type transistor is used, the first electrode is the source of the N-type transistor, the second electrode is the drain of the N-type transistor, and when a high-level signal is input to the gate, the source-drain is turned on, and the P-type is the opposite. It can be imagined that implementing with a P-type transistor can be easily thought of by those skilled in the art without creative labor, and therefore it is also within the protection scope of the embodiments of the present disclosure.

[0064] Among them, since the transistor used in the embodiments of the present disclosure is an N-type transistor, the working level signal in the embodiments of the present disclosure refers to a high-level signal, and the non-working level signal is a low-level signal; correspondingly, the working level terminal is a high-level signal terminal, and the non-working level terminal is a low-level signal terminal.

[0065] An electronic ink screen, also known as an electronic paper display screen, is composed of many electronic inks. The electronic inks can be regarded as microcapsules, and there are liquid charges in each microcapsule. Among them, the positive charges are white and the negative charges are black. When positive and negative voltages are applied on one side, the charged liquid will be attracted and repelled respectively. In this way, each pixel can display white or black. Since the electronic ink has a bistable hysteresis effect, even if the power is turned off, the microcapsules will not return to their original state or enter a random chaotic state, but will maintain the state of the last picture, and the power consumption is 0 at this time.

[0066] The electronic ink screen includes multiple gate lines and multiple data lines. The gate lines and data lines are arranged crosswise to define multiple pixel areas, and each pixel area is provided with a pixel unit. Among them, taking the extension direction of each gate line as the row direction and the extension direction of each data line as the column direction as an example to illustrate the structure of the display panel. When driving the display panel to display, according to the picture to be displayed, a scan signal can be written to the gate line row by row, and a data voltage signal can be written to each data line at the same time, so that the pixel units in the electronic ink screen are lit row by row.

[0067] Among them, the scan signal is provided by the gate driving circuit, and the data voltage signal is provided by the source driving circuit. In the related art, the gate driving circuit can be integrated in the gate driving chip, and the source driving circuit can be integrated in the source driving chip. At present, in order to reduce the number of chips and achieve a narrow border or borderless design, a technology of integrating the gate driving circuit on the array substrate (Gate On Array, GOA) is provided. Among them, the gate driving circuit includes a plurality of cascaded shift registers integrated on the array substrate, and each shift register is connected to a gate line one by one, and is used to provide a scan signal for the gate line connected thereto.

[0068] The GOA output voltage of the electronic ink screen is relatively high, such as +20v, -20v, +15v, -15v, etc. When outputting a signal with a relatively high voltage, the voltage difference between the source and drain of some transistors in the GOA is relatively large. For example, Figure 1 FIG. is a schematic structural diagram of some devices in an exemplary gate driving circuit, such as Figure 1 As shown, the eleventh transistor T11 can output the clock signal of the clock signal terminal CLK through the local signal output terminal Gate(n) with the cooperation of the storage capacitor Cst. The thirteenth transistor T13 can output the low-level signal of the low-level signal terminal VGL through the local signal output terminal Gate(n). The two work in a time-sharing manner to output an effective scan signal to the corresponding gate line within the time of one frame of display screen. When the GOA outputs a low-level signal (-15v) and the clock signal is a high-level signal (+20v), the voltage difference between the source and drain of the eleventh transistor T11 responsible for signal output can reach 35v, which easily causes the transistor therein to be broken down and fail, affecting the display effect.

[0069] In order to solve one of the above technical problems, the present disclosure provides a shift register, a gate driving circuit and a display device. The shift register, the gate driving circuit and the display device provided by the embodiments of the present disclosure will be further described in detail below with reference to the drawings and specific embodiments.

[0070] In a first aspect, an embodiment of the present disclosure provides a shift register. Figure 2 FIG. is a schematic structural diagram of the first shift register provided by the embodiment of the present disclosure, such as Figure 2As shown, the shift register includes: a first output sub-circuit 101, a second output sub-circuit 102, and a first adjustment sub-circuit 103; the first output sub-circuit 101 is configured to transmit the clock signal of the clock signal terminal CLK to the first node N1 in response to the voltage of the pull-up node PU, and output it through the signal output terminal Gate(n) of this stage; the second output sub-circuit 102 is configured to transmit the low-level signal of the low-level signal terminal VGL to the second node N2 in response to the voltage of the pull-down node PD, and output it through the signal output terminal Gate(n) of this stage; the first adjustment sub-circuit 103 is configured to control the voltage of the first node N1 when the signal output through the signal output terminal Gate(n) of this stage is a low-level signal and the clock signal of the clock signal terminal CLK is a high-level signal, so as to adjust the voltage difference between the first node N1 and the signal output terminal Gate(n) of this stage.

[0071] It should be noted here that the first node N1 is a node between the clock signal terminal CLK and the signal output terminal Gate(n) of this stage. When only one transistor (for example, Figure 1 the eleventh transistor T11 shown) is provided in the first output sub-circuit 101, the first node N1 does not actually exist, and it can be the same node as the clock signal terminal CLK or the signal output terminal Gate(n) of this stage. Similarly, the second node N2 is a node between the low-level signal terminal VGL and the signal output terminal Gate(n) of this stage. When only one transistor (for example, Figure 1 the thirteenth transistor T13 shown in ) is provided in the second output sub-circuit 102, the second node N2 does not actually exist, and it can be the same node as the low-level signal terminal VGL or the signal output terminal Gate(n) of this stage.

[0072] In the shift register provided by the embodiment of the present disclosure, the first output sub-circuit 101 can output the clock signal through the local signal output terminal Gate(n), and the second output sub-circuit 102 can output the low-level signal through the local signal output terminal Gate(n). The two work in a time-sharing manner to output an effective scanning signal to the corresponding gate line within the time of one frame of display screen. When a low-level signal is output at the local signal output terminal Gate(n) and the clock signal at the clock signal terminal CLK is a high-level signal, the signal transmitted by the first node N1 is a high-level signal, and there is a large voltage difference between the first node N1 and the local signal output terminal Gate(n). The first adjustment sub-circuit 103 can control the voltage of the first node N1 (for example, reduce the voltage of the first node N1) to reduce the voltage difference between the first node N1 and the local signal output terminal Gate(n). In this way, during the transmission of the clock signal from the first node N1 to the local signal output terminal Gate(n), it is possible to avoid excessive voltage difference between the source and drain of the corresponding transistor, which may cause the transistor to be broken down and fail, thereby improving the display effect.

[0073] Specifically, as Figure 2 shown, the first adjustment sub-circuit 103 includes: a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16; the gate and source of the fourteenth transistor T14 are connected to the clock signal terminal, and the drain is connected to the source of the fifteenth transistor T15; the gate of the fifteenth transistor T15 is connected to the pull-up node, the source is connected to the drain of the fourteenth transistor T14, and the drain is connected to the gate of the sixteenth transistor T16; the gate of the sixteenth transistor T16 is connected to the drain of the fifteenth transistor T15, the source is connected to the first auxiliary node N11, and the drain is connected to the second auxiliary node N12; the first auxiliary node N11 and the second auxiliary node N12 are two nodes formed after the first node N1 is disconnected.

[0074] More specifically, the first output sub-circuit 101 includes: a tenth transistor T10, an eleventh transistor T11, and a storage capacitor Cst; the gate of the tenth transistor T10 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the first node N1 (the first auxiliary node N11); the gate of the eleventh transistor T11 is connected to the pull-up node PU, the source is connected to the first node N1 (the second auxiliary node N12), and the drain is connected to the signal output terminal Gate(n) of this stage; one end of the storage capacitor Cst is connected to the pull-up node PU, and the other end is connected to the signal output terminal Gate(n) of this stage; the second output sub-circuit 102 includes: a twelfth transistor T12 and a thirteenth transistor T13; the gate of the twelfth transistor T12 is connected to the pull-down node PD, the source is connected to the low-level signal terminal VGL, and the drain is connected to the second node N2; the gate of the thirteenth transistor T13 is connected to the pull-down node PD, the source is connected to the second node N2, and the drain is connected to the signal output terminal Gate(n) of this stage.

[0075] In some embodiments, as Figure 2 shown, the shift register further includes: an input sub-circuit 104, a reset sub-circuit 105, a discharge sub-circuit 106, a first pull-down control sub-circuit 107, a second pull-down control sub-circuit 108, a first pull-down sub-circuit 109, and a second pull-down sub-circuit 110; the input sub-circuit 104 is configured to transmit the voltage of the signal output terminal Gate(n - 1) of the previous stage to the pull-up node PU in response to the voltage of the signal output terminal Gate(n - 1) of the previous stage, so as to charge the pull-up node PU; the reset sub-circuit 105 is configured to transmit the non-operating level signal of the low-level signal terminal VGL to the pull-up node PU in response to the voltage of the signal output terminal Gate(n + 1) of the next stage, so as to reset the pull-up node PU; the discharge sub-circuit 106 is configured to transmit the non-operating level signal of the low-level signal terminal VGL to the pull-up node PU in response to the voltage of the pull-down node PD, so as to discharge the pull-up node PU; the first pull-down control sub-circuit 107 is configured to transmit the first power signal of the first power signal terminal Vdd1 to the pull-down node PD in response to the voltage of the first power signal terminal Vdd1, so as to control the voltage of the pull-down node PD; the second pull-down control sub-circuit 108 is configured to transmit the second power signal of the second power signal terminal Vdd2 to the pull-down node PD in response to the voltage of the second power signal terminal Vdd2, so as to control the voltage of the pull-down node PD; the first pull-down sub-circuit 109 is configured to transmit the non-operating level signal of the low-level signal terminal VGL to the pull-down node PD in response to the voltage of the pull-up node PU, so as to pull down the voltage of the pull-down node PD; the second pull-down sub-circuit 110 is configured to transmit the non-operating level signal of the low-level signal terminal VGL to the pull-down node PD in response to the voltage of the pull-up node PU, so as to pull down the voltage of the pull-down node PD.

[0076] Specifically, the input sub-circuit 104 includes: a first transistor T1; the gate and source of the first transistor T1 are connected to the previous-stage signal output terminal Gate(n - 1); the reset sub-circuit 105 includes: a second transistor T2; the gate of the second transistor T2 is connected to the next-stage signal output terminal Gate(n + 1), the source is connected to the low-level signal terminal VGL, and the drain is connected to the pull-up node PU; the discharge sub-circuit 106 includes: a third transistor T3; the gate of the third transistor T3 is connected to the pull-down node PD, the source is connected to the low-level signal terminal VGL, and the drain is connected to the pull-up node PU; the first pull-down control sub-circuit 107 includes: a fourth transistor T4; the gate and source of the fourth transistor T4 are connected to the first power signal terminal Vdd1, and the drain is connected to the pull-down node PD; the first pull-down sub-circuit 109 includes: a fifth transistor T5 and a sixth transistor T6; the gate of the fifth transistor T5 is connected to the pull-up node PU, the source is connected to the drain of the sixth transistor T6, and the drain is connected to the pull-down node PD; the gate of the sixth transistor T6 is connected to the pull-up node PU, the source is connected to the low-level signal terminal VGL, and the drain is connected to the source of the fifth transistor T5; the second pull-down control sub-circuit 108 includes: a seventh transistor T7; the gate and source of the seventh transistor T7 are connected to the second power signal terminal Vdd2, and the drain is connected to the pull-down node PD; the second pull-down sub-circuit 110 includes: an eighth transistor T8 and a ninth transistor T9; the gate of the eighth transistor T8 is connected to the pull-up node PU, the source is connected to the drain of the ninth transistor T9, and the drain is connected to the pull-down node PD; the gate of the ninth transistor T9 is connected to the pull-up node PU, the source is connected to the low-level signal terminal VGL, and the drain is connected to the source of the eighth transistor T8.

[0077] It should be noted here that the functions of the first pull-down control sub-circuit 107 and the second pull-down control sub-circuit 108 are the same, the functions of the first pull-down sub-circuit 109 and the second pull-down sub-circuit 110 are the same, the first pull-down control sub-circuit 107 and the second pull-down control sub-circuit 108 are respectively connected to the first power signal terminal Vdd1 and the second power signal terminal Vdd2, and the signals of the first power signal terminal Vdd1 and the second power signal terminal Vdd2 are opposite, so that the first pull-down control sub-circuit 107 and the second pull-down control sub-circuit 108 work alternately to improve the service life of the transistors therein. Similarly, the first pull-down sub-circuit 109 and the second pull-down sub-circuit 110 also work alternately.

[0078] Figure 3 For Figure 2 the timing diagram of the shift register shown below, the working principle of the shift register shown will be further described in detail in conjunction with Figure 3 the timing diagram shown, for Figure 2 the working principle of the shift register shown will be further described in detail.

[0079] ​In the first stage t1, the previous stage signal output terminal Gate(n-1) is a high level signal, the first transistor T1 is turned on, the pull-up node PU is a high level signal, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11 and the fifteenth transistor T15 are turned on, the pull-down node PD is a low level signal, the third transistor T3, the twelfth transistor T12 and the thirteenth transistor T13 are turned off, the clock signal terminal CLK is a low level signal, the fourteenth transistor T14 is turned off, and accordingly, the sixteenth transistor T16 is turned off, the next stage signal output terminal Gate(n+1) is a low level signal, and the second transistor T2 is turned off. In this stage, the current stage signal output terminal Gate(n) maintains outputting a low level signal.

[0080] In the second stage t2, the previous stage signal output terminal Gate(n-1) is a low level signal, the first transistor T1 is turned off, under the action of the storage capacitor Cst, the pull-up node PU maintains a high level signal, the pull-down node PD maintains a low level signal, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11 and the fifteenth transistor T15 are turned on, the third transistor T3, the twelfth transistor T12 and the thirteenth transistor T13 are turned off, the clock signal terminal CLK is a high level signal, the fourteenth transistor T14 and the fifteenth transistor T15 are turned on, and accordingly, the sixteenth transistor T16 is turned on, the next stage signal output terminal Gate(n+1) is a low level signal, and the second transistor T2 is turned off. In this stage, the current stage signal output terminal Gate(n) outputs a high level signal.

[0081] In the third stage t3, the next-stage signal output terminal Gate(n+1) is a high-level signal, the second transistor T2 is turned on, the pull-up node PU is a low-level signal, the tenth transistor T10 and the eleventh transistor T11 are turned off, at this time, the fourth transistor T4 is turned on, the pull-down node PD is a high-level signal, the third transistor T3, the twelfth transistor T12 and the thirteenth transistor T13 are turned on. In this stage, the signal output terminal Gate(n) of this stage outputs a low-level signal. The first auxiliary node N11 and the second auxiliary node N12 are both in a floating state, and the connection between the tenth transistor T10 and the eleventh transistor T11 is disconnected.

[0082] In the fourth stage t4, the next-stage signal output terminal Gate(n+1) is a low-level signal, the second transistor T2 is turned off, and under the action of the storage capacitor Cst, the pull-up node PU maintains a low-level signal, the pull-down node PD maintains a high-level signal, the tenth transistor T10, the eleventh transistor T11 and the fifteenth transistor T15 are turned off, and the twelfth transistor T12 and the thirteenth transistor T13 are turned on. In this stage, the signal output terminal Gate(n) of this stage outputs a low-level signal. T12 is turned on and outputs a low level. The first auxiliary node N11 and the second auxiliary node N12 are both in a floating state, and the connection between the tenth transistor T10 and the eleventh transistor T11 is disconnected.

[0083] It can be seen from the working process of the shift register described above that when the current signal output terminal Gate(n) outputs a low level signal and the clock signal of the clock signal terminal CLK is a high level signal, the signal transmitted by the first node N1 is a high level signal, and the first regulating subcircuit 103 composed of the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 can disconnect the first auxiliary node N11 and the second auxiliary node N12, so that the drain of the tenth transistor T10 and the source of the eleventh transistor T11 are in a floating state, and the connection between the tenth transistor T10 and the eleventh transistor T11 is disconnected to reduce the voltage difference between the first node N1 (the second auxiliary node N12) and the current signal output terminal Gate(n). In this way, in the process of transmitting the clock signal from the first node N1 (the second auxiliary node N12) to the current signal output terminal Gate(n), the voltage difference between the source and the drain of the eleventh transistor T11 can be avoided to be too large, causing the transistor to be broken down and fail, thereby improving the display effect.

[0084] Figure 4 A schematic diagram of the structure of a second shift register provided in an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the first regulating subcircuit 103 includes: a seventeenth transistor T17; the gate and source of the seventeenth transistor T17 are connected to the first auxiliary node N11, and the drain is connected to the second auxiliary node N12; the first auxiliary node N11 and the second auxiliary node N12 are two nodes formed after the first node N1 is disconnected.

[0085] Figure 4 The shift register in Figure 2 The shift register shown differs in that Figure 2In the shift register shown, in the fourth stage t4, through the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16, the connection between the first auxiliary node N11 and the second auxiliary node N12 is disconnected, so that the source of the eleventh transistor T11 is in a floating state, and the drain of the tenth transistor T10 and the source of the eleventh transistor T11 are in a floating state, disconnecting the connection between the tenth transistor T10 and the eleventh transistor T11 to reduce the voltage difference between the first node N1 (the second auxiliary node N12) and the signal output terminal Gate(n) of this stage. Figure 4 In the shift register shown, the source and gate of the seventeenth transistor T17 are short-circuited to the first auxiliary node N11, and the drain is connected to the second auxiliary node N12. At this time, the seventeenth transistor T17 is equivalent to a resistor. In the fourth stage t4, the seventeenth transistor T17 can divide the voltage transmitted from the clock signal terminal CLK to the first node N1 (the first auxiliary node N11 and the second auxiliary node N12), so that the voltage of the first node N1 (the second auxiliary node N12) is reduced to reduce the voltage difference between the first node N1 (the second auxiliary node N12) and the signal output terminal Gate(n) of this stage. In this way, during the transmission of the clock signal from the first node N1 (the second auxiliary node N12) to the signal output terminal Gate(n) of this stage, it is possible to avoid the voltage difference between the source and drain of the eleventh transistor T11 being too large, causing the transistor to be broken down and fail, thereby improving the display effect.

[0086] Figure 5 FIG. is a schematic structural diagram of a third shift register provided by an embodiment of the present disclosure, as Figure 5 shown, the first adjustment sub-circuit 103 includes: an eighteenth transistor T18 and a nineteenth transistor T19; the gate and source of the eighteenth transistor T18 are connected to the clock signal terminal CLK, and the drain is connected to the source and control electrode of the nineteenth transistor T19; the gate and source of the nineteenth transistor T19 are connected to the drain of the eighteenth transistor T18, and the drain is connected to the first node N1.

[0087] Figure 5 The shift register shown in Figure 4 is different from the shift register shown in Figure 4 In the shift register shown, the source and gate of the seventeenth transistor T17 are short-circuited to the first auxiliary node N11, and the drain is connected to the second auxiliary node N12. At this time, the seventeenth transistor T17 is equivalent to a resistor. It is necessary to disconnect the first node N1 in the original circuit structure to form the first auxiliary node N11 and the second auxiliary node N12. Figure 5In the shift register shown, the gate and source of the eighteenth transistor T18 are connected to the clock signal terminal CLK, and the drain is connected to the source and gate of the nineteenth transistor T19; the gate and source of the nineteenth transistor T19 are connected to the drain of the eighteenth transistor T18, and the drain is connected to the first node N1. The eighteenth transistor T18 and the nineteenth transistor T19 are connected in series and are equivalent to a resistor, which has no impact on the original circuit structure. In the fourth stage t4, the eighteenth transistor T18 and the nineteenth transistor T19 can divide the voltage transmitted from the clock signal terminal CLK to the first node N1, so that the voltage of the first node N1 is reduced, in order to reduce the voltage difference between the first node N1 and the signal output terminal Gate(n) of this stage. In this way, during the transmission of the clock signal from the first node N1 to the signal output terminal Gate(n) of this stage, it is possible to avoid the voltage difference between the source and drain of the eleventh transistor T11 from being too large, which may cause the transistor to be broken down and fail, thereby improving the display effect.

[0088] Figure 6 FIG. is a schematic structural diagram of a fourth shift register provided by an embodiment of the present disclosure. As Figure 6 shown, the shift register further includes: a second adjustment sub-circuit 111; the second adjustment sub-circuit 111 is configured to control the voltage of the second node N2 when the clock signal output from the signal output terminal Gate(n) of this stage is a high-level signal, so as to adjust the voltage difference between the second node N2 and the signal output terminal Gate(n) of this stage.

[0089] In the shift register provided by the embodiment of the present disclosure, the first output sub-circuit 101 can output the clock signal through the signal output terminal Gate(n) of this stage, and the second output sub-circuit 102 can output the low-level signal through the signal output terminal Gate(n) of this stage. The two work in a time-sharing manner to output an effective scanning signal to the corresponding gate line within the time of one frame of the display screen. When the clock signal output from the signal output terminal Gate(n) of this stage is a high-level signal, the low-level signal terminal VGL always maintains a low-level signal, and the signal transmitted by the second node N2 is a low-level signal. There is a large voltage difference between the second node N2 and the signal output terminal Gate(n) of this stage. The second adjustment sub-circuit 111 can control the voltage of the second node N2 (for example, reduce the voltage of the second node N2) to reduce the voltage difference between the second node N2 and the signal output terminal Gate(n) of this stage. In this way, during the transmission of the low-level signal from the second node N2 to the signal output terminal Gate(n) of this stage, it is possible to avoid the voltage difference between the source and drain of the corresponding transistor from being too large, which may cause the transistor therein to be broken down and fail, thereby improving the display effect.

[0090] Specifically, as Figure 6As shown, the second regulator circuit 111 includes: a twentieth transistor T20, a twenty-first transistor T21, and a twenty-second transistor T22; the gate and source of the twentieth transistor T20 are connected to the clock signal terminal CLK, and the drain is connected to the source of the twenty-first transistor T21; the gate of the twenty-first transistor T21 is connected to the pull-down node PD, the source is connected to the drain of the twentieth transistor T20, and the drain is connected to the gate of the twenty-second transistor T22; the gate of the twenty-second transistor T22 is connected to the drain of the twentieth transistor T20, the source is connected to the third auxiliary node N21, and the drain is connected to the fourth auxiliary node N22; the third auxiliary node N21 and the fourth auxiliary node N22 are two nodes formed after the second node N2 is disconnected.

[0091] Figure 6 The structure of the second regulator circuit 111 in the shift register shown is similar to Figure 2 the structure of the first regulator circuit 103 in the shift register shown, Figure 6 In the shift register shown, the second regulator circuit 103 formed by the twentieth transistor T20, the twenty-first transistor T21, and the twenty-second transistor T22 can disconnect the third auxiliary node N21 and the fourth auxiliary node N22, so that the drain of the twelfth transistor T12 and the source of the thirteenth transistor T13 are in a floating state, disconnecting the connection between the twelfth transistor T12 and the thirteenth transistor T13 to reduce the voltage difference between the second node N2 (the fourth auxiliary node N22) and the signal output terminal Gate(n) of this stage. In this way, during the transmission of the low-level signal from the second node N2 (the fourth auxiliary node N22) to the signal output terminal Gate(n) of this stage, it is possible to avoid the voltage difference between the source and drain of the thirteenth transistor T13 from being too large, causing the transistor to be broken down and fail, thereby improving the display effect.

[0092] Figure 7 FIG. is a schematic structural diagram of a fifth shift register provided by an embodiment of the present disclosure. As Figure 7 shown, the second regulator circuit 111 includes: a twenty-third transistor T23; the gate and source of the twenty-third transistor T23 are connected to the third auxiliary node N21, and the drain is connected to the fourth auxiliary node N22; the third auxiliary node N21 and the fourth auxiliary node N22 are two nodes formed after the second node N2 is disconnected.

[0093] Figure 7 The structure of the second regulator circuit 111 in the shift register shown is similar to Figure 4 the structure of the first regulator circuit 103 in the shift register shown, Figure 7In the shift register shown, the source and gate of the twenty-third transistor T23 are shorted to the third auxiliary node N21, and the drain is connected to the fourth auxiliary node N22. At this time, the twenty-third transistor T23 is equivalent to a resistor. In the second stage t2, the twenty-third transistor T23 can divide the voltage transmitted from the low-level signal terminal VGL to the second node N2 (the third auxiliary node N21 and the fourth auxiliary node N22), so that the voltage of the second node N2 (the fourth auxiliary node N22) decreases, in order to reduce the voltage difference between the second node N2 (the fourth auxiliary node N22) and the signal output terminal Gate(n) of this stage. In this way, during the transmission of the low-level signal from the second node N2 (the fourth auxiliary node N22) to the signal output terminal Gate(n) of this stage, it is possible to avoid the transistor being broken down and failing due to an excessive voltage difference between the source and drain of the thirteenth transistor T13, thereby improving the display effect.

[0094] Figure 8 FIG. is a schematic structural diagram of a sixth shift register provided by the present disclosure, as Figure 8 shown, the second adjustment sub-circuit 111 includes: a twenty-fourth transistor T24 and a twenty-fifth transistor T25; the gate and source of the twenty-fourth transistor T24 are connected to the low-level signal terminal, and the drain is connected to the source and gate of the twenty-fifth transistor T25; the gate and source of the twenty-fifth transistor T25 are connected to the drain of the twenty-fourth transistor T24, and the drain is connected to the second node N2.

[0095] Figure 8 The structure of the second adjustment sub-circuit 111 in the shift register shown is similar to Figure 5 the structure of the first adjustment sub-circuit 103 in the shift register shown, Figure 8 In the shift register shown, the gate and source of the twenty-fourth transistor T24 are connected to the low-level signal terminal, and the drain is connected to the source and gate of the twenty-fifth transistor T25; the gate and source of the twenty-fifth transistor T25 are connected to the drain of the twenty-fourth transistor T24, and the drain is connected to the second node N2. The twenty-fourth transistor T24 and the twenty-fifth transistor T25 are connected in series and are equivalent to a resistor, which does not affect the original circuit structure. In the second stage t2, the twenty-fourth transistor T24 and the twenty-fifth transistor T25 can divide the voltage transmitted from the signal output terminal Gate(n) to the second node N2, so that the voltage of the second node N2 decreases, in order to reduce the voltage difference between the second node N2 and the signal output terminal Gate(n) of this stage. In this way, during the transmission of the high-level signal from the signal output terminal Gate(n) of this stage to the second node N2, it is possible to avoid the transistor being broken down and failing due to an excessive voltage difference between the source and drain of the thirteenth transistor T13, thereby improving the display effect.

[0096] Second aspect, embodiments of the present disclosure provide a gate driving circuit, which includes a plurality of cascaded shift registers provided in any of the above embodiments. For the description of the specific structure of the shift register, reference may be made to the detailed description of the above shift register, and the repeated parts will not be elaborated.

[0097] Third aspect, embodiments of the present disclosure provide a display device, which includes the gate driving circuit provided in any of the above embodiments. The display device may specifically be a mobile phone, a wireless device, a personal data assistant, a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an automotive display (e.g., an odometer display, etc.), a navigator, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rear view camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, etc. The implementation principle and beneficial effects thereof are the same as those of the above gate driving circuit and shift register, and will not be elaborated herein.

[0098] It should be noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Moreover, it can be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be an intermediate layer. Additionally, it can be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or there may be more than one intermediate layer or element. Additionally, it can also be understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Like reference numerals throughout indicate like elements.

[0099] In several embodiments provided by the embodiments of the present disclosure, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the positions of the illustrated components are only for a logical functional position, and there may be other position arrangements in actual implementation.

[0100] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present disclosure, and the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered within the protection scope of the present disclosure.

Claims

1. A shift register, characterized in that: The shift register comprises: a first output subcircuit, a second output subcircuit and a first regulating subcircuit; The first output subcircuit is configured to transmit the clock signal of the clock signal terminal to the first node in response to the voltage of the pull-up node, and output it through the signal output terminal of this stage; The second output subcircuit is configured to transmit the non-operating level signal of the non-operating level signal terminal to the second node in response to the voltage of the pull-down node, and output it through the signal output terminal of this stage; The first regulating subcircuit is configured to output the non-working level signal at the signal output terminal of the current stage, and when the clock signal at the clock signal terminal is a working level signal, control the voltage of the first node to adjust the voltage difference between the first node and the signal output terminal of the current stage.

2. The shift register according to claim 1, characterized in that: The first regulating subcircuit includes: a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; The control electrode and the first electrode of the fourteenth transistor are connected to the clock signal terminal, and the second electrode is connected to the first electrode of the fifteenth transistor; The control electrode of the fifteenth transistor is connected to the pull-up node, the first electrode is connected to the second electrode of the fourteenth transistor, and the second electrode is connected to the control electrode of the sixteenth transistor; The control electrode of the sixteenth transistor is connected to the second electrode of the fifteenth transistor, the first electrode is connected to the first auxiliary node, and the second electrode is connected to the second auxiliary node; the first auxiliary node and the second auxiliary node are two nodes formed after the first node is disconnected.

3. The shift register according to claim 1, characterized in that: The first regulating subcircuit comprises: a seventeenth transistor; The control electrode and the first electrode of the seventeenth transistor are connected to the first auxiliary node, and the second electrode is connected to the second auxiliary node; the first auxiliary node and the second auxiliary node are two nodes formed after the first node is disconnected.

4. The shift register according to claim 1, wherein: The first regulating subcircuit includes: an eighteenth transistor and a nineteenth transistor; The control electrode and the first electrode of the eighteenth transistor are connected to the clock signal terminal, and the second electrode is connected to the first electrode and the control electrode of the nineteenth transistor; The control electrode and the first electrode of the nineteenth transistor are connected to the second electrode of the eighteenth transistor, and the second electrode is connected to the first node.

5. The shift register according to claim 1, characterized in that: The shift register further includes: a second regulating subcircuit; The second regulating subcircuit is configured to control the voltage of the second node when the clock signal output at the current stage signal output terminal is a working level signal, so as to adjust the voltage difference between the second node and the current stage signal output terminal.

6. The shift register according to claim 5, characterized in that: The second regulating subcircuit comprises: a twentieth transistor, a twenty-first transistor and a twenty-second transistor; The control electrode and the first electrode of the 20th transistor are connected to the clock signal terminal, and the second electrode is connected to the first electrode of the 21st transistor; The control electrode of the 21st transistor is connected to the pull-down node, the first electrode is connected to the second electrode of the 20th transistor, and the second electrode is connected to the control electrode of the 22nd transistor; The control electrode of the 22nd transistor is connected to the second electrode of the 20th transistor, the first electrode is connected to the third auxiliary node, and the second electrode is connected to the fourth auxiliary node; the third auxiliary node and the fourth auxiliary node are two nodes formed after the second node is disconnected.

7. The shift register according to claim 5, characterized in that: The second regulating subcircuit comprises: a twenty-third transistor; The control electrode and the first electrode of the twenty-third transistor are connected to the third auxiliary node, and the second electrode is connected to the fourth auxiliary node; the third auxiliary node and the fourth auxiliary node are two nodes formed after the second node is disconnected.

8. The shift register according to claim 5, characterized in that: The second regulating subcircuit includes: a twenty-fourth transistor and a twenty-fifth transistor; The control electrode and the first electrode of the twenty-fourth transistor are connected to the non-working level signal terminal, and the second electrode is connected to the first electrode and the control electrode of the twenty-fifth transistor; The control electrode and the first electrode of the 25th transistor are connected to the second electrode of the 24th transistor, and the second electrode is connected to the second node.

9. The shift register according to claim 1, characterized in that: The first output sub-circuit comprises: a tenth transistor, an eleventh transistor and a storage capacitor; The control electrode of the tenth transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the first node; The control electrode of the eleventh transistor is connected to the pull-up node, the first electrode is connected to the first node, and the second electrode is connected to the current-stage signal output terminal; One end of the storage capacitor is connected to the pull-up node, and the other end is connected to the current-stage signal output terminal; The second output sub-circuit comprises: a twelfth transistor and a thirteenth transistor; The control electrode of the twelfth transistor is connected to the pull-down node, the first electrode is connected to the non-working level signal terminal, and the second electrode is connected to the second node; The control electrode of the thirteenth transistor is connected to the pull-down node, the first electrode is connected to the second node, and the second electrode is connected to the signal output terminal of this stage.

10. The shift register according to claim 1, characterized in that: The shift register further includes: an input subcircuit, a reset subcircuit, a discharge subcircuit, a first pull-down control subcircuit, a second pull-down control subcircuit, a first pull-down subcircuit, and a second pull-down subcircuit; The input subcircuit is configured to transmit the voltage of the previous stage signal output terminal to the pull-up node in response to the voltage of the previous stage signal output terminal, so as to charge the pull-up node; The reset subcircuit is configured to transmit the non-operating level signal of the non-operating level signal terminal to the pull-up node in response to the voltage of the next-stage signal output terminal, so as to reset the pull-up node; The discharge subcircuit is configured to transmit the non-operating level signal of the non-operating level signal terminal to the pull-up node in response to the voltage of the pull-down node, so as to discharge the pull-up node; The first pull-down control subcircuit is configured to transmit the first power signal of the first power signal terminal to the pull-down node in response to the voltage of the first power signal terminal to control the voltage of the pull-down node; The second pull-down control subcircuit is configured to transmit the second power signal of the second power signal terminal to the pull-down node in response to the voltage of the second power signal terminal to control the voltage of the pull-down node; The first pull-down subcircuit is configured to transmit the non-operating level signal of the non-operating level signal terminal to the pull-down node in response to the voltage of the pull-up node, so as to pull down the voltage of the pull-down node; The second pull-down sub-circuit is configured to transmit the non-operating level signal of the non-operating level signal terminal to the pull-down node in response to the voltage of the pull-up node, so as to pull down the voltage of the pull-down node.

11. The shift register according to claim 10, characterized in that: The input subcircuit comprises: a first transistor; the control electrode and the first electrode of the first transistor are connected to the signal output terminal of the previous stage; The reset subcircuit comprises: a second transistor; the control electrode of the second transistor is connected to the next stage signal output terminal, the first electrode is connected to the non-working level signal terminal, and the second electrode is connected to the pull-up node; The discharge subcircuit comprises: a third transistor; the control electrode of the third transistor is connected to the pull-down node, the first electrode is connected to the non-working level signal terminal, and the second electrode is connected to the pull-up node; The first pull-down control subcircuit comprises: a fourth transistor; the control electrode and the first electrode of the fourth transistor are connected to the first power signal terminal, and the second electrode is connected to the pull-down node; The first pull-down subcircuit comprises: a fifth transistor and a sixth transistor; the control electrode of the fifth transistor is connected to the pull-up node, the first electrode is connected to the second electrode of the sixth transistor, and the second electrode is connected to the pull-down node; the control electrode of the sixth transistor is connected to the pull-up node, the first electrode is connected to the non-working level signal terminal, and the second electrode is connected to the first electrode of the fifth transistor; The second pull-down control subcircuit comprises: a seventh transistor; the control electrode and the first electrode of the seventh transistor are connected to the second power signal terminal, and the second electrode is connected to the pull-down node; The second pull-down sub-circuit includes: an eighth transistor and a ninth transistor; the control electrode of the eighth transistor is connected to the pull-up node, the first electrode is connected to the second electrode of the ninth transistor, and the second electrode is connected to the pull-down node; the control electrode of the ninth transistor is connected to the pull-up node, the first electrode is connected to the non-working level signal terminal, and the second electrode is connected to the first electrode of the eighth transistor.

12. A gate drive circuit, characterized in that: The gate driving circuit includes a plurality of shift registers according to any one of claims 1 to 11 connected in cascade.

13. A display device, characterized in that: The display device comprises the gate driving circuit as claimed in claim 12.

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