Metal-insulator-metal capacitor structure

Abstract

A metal-insulator-metal capacitor structure includes a semiconductor substrate having a capacitor forming region; a first trench and a second trench disposed in the semiconductor substrate in the capacitance formation region, where the second trench is adjacent to the first trench, and where the depth of the second trench is greater than that of the first trench; a dielectric liner layer conformally covering a top surface of the semiconductor substrate, an inner surface of the first trench, and an inner surface of the second trench; a bottom electrode layer conformally covering the dielectric liner layer, the bottom electrode layer extending to the top surface of the semiconductor substrate; the capacitor dielectric layer is arranged on the bottom electrode layer in the first groove and the second groove; and the top electrode layer is arranged on the capacitor dielectric layer in the first groove and the second groove, and the top surface of the top electrode layer and the top surface of the bottom electrode layer are coplanar.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a deep trench metal-insulator-metal (MIM) capacitor structure. Background Art

[0002] To meet the stringent power integrity (PI) requirements of advanced artificial intelligence (AI) and high-performance computing (HPC) components, high-k (HK) deep trench capacitors (DTCs) have been integrated into silicon interposers with through-silicon vias (TSVs) and fine-pitch interconnect structures and applied to CoWoS packaging.

[0003] Since a capacitor structure with a high capacitance value requires multiple metal electrodes and high-k thin film layers, vias usually connect to electrodes located on different horizontal planes, forming a height difference, which poses a risk of via open or short circuit. Summary of the Invention

[0004] The main object of the present invention is to provide an improved metal-insulator-metal (MIM) capacitor structure to solve the deficiencies or drawbacks of the prior art.

[0005] One aspect of the present invention provides an MIM capacitor structure, comprising a semiconductor substrate having a capacitor formation region thereon; a first trench having a first depth and disposed in the semiconductor substrate within the capacitor formation region; a second trench having a second depth and disposed in the semiconductor substrate within the capacitor formation region, wherein the second trench is adjacent to the first trench and wherein the second depth is greater than the first depth; a dielectric liner layer conformally covering the top surface of the semiconductor substrate, the inner surfaces of the first trench, and the inner surfaces of the second trench; a bottom electrode layer conformally covering the dielectric liner layer, wherein the bottom electrode layer extends onto the top surface of the semiconductor substrate; a capacitor dielectric layer disposed on the bottom electrode layer within the first trench and the second trench; and a top electrode layer disposed on the capacitor dielectric layer within the first trench and the second trench, wherein the top surface of the top electrode layer is coplanar with the top surface of the bottom electrode layer.

[0006] According to an embodiment of the present invention, the first depth ranges from 5 nm to 5 μm, and the second depth ranges from 100 nm to 50 μm.

[0007] According to an embodiment of the present invention, the dielectric liner layer comprises silicon oxide.

[0008] According to an embodiment of the present invention, the bottom electrode layer comprises TiN.

[0009] According to an embodiment of the present invention, the top electrode layer comprises TiN.

[0010] According to an embodiment of the present invention, the capacitive dielectric layer includes a ZrO2 / Al2O3 / ZrO2 (ZAZ) film.

[0011] According to an embodiment of the present invention, the capacitive dielectric layer does not extend to the top surface of the semiconductor substrate.

[0012] According to an embodiment of the present invention, the top electrode layer does not extend to the top surface of the semiconductor substrate.

[0013] According to an embodiment of the present invention, the MIM capacitor structure further includes: a trench filling material layer filling the second trench; a dielectric layer covering the trench filling material layer, the top electrode layer, the bottom electrode layer, and the capacitive dielectric layer; a first contact disposed in the dielectric layer and electrically connected to the bottom electrode layer; and a second contact disposed in the dielectric layer and electrically connected to a portion of the top electrode layer directly above the first trench.

[0014] According to an embodiment of the present invention, the MIM capacitor structure further includes: a through-silicon via penetrating the entire thickness of the dielectric layer and the semiconductor substrate.

[0015] On the other hand, the present invention provides a MIM capacitor structure, including a semiconductor substrate having a capacitor formation region thereon; a first trench having a first depth and disposed in the semiconductor substrate within the capacitor formation region; a second trench having a second depth and disposed in the semiconductor substrate within the capacitor formation region, wherein the second trench is adjacent to the first trench, and wherein the second depth is greater than the first depth; a dielectric liner layer conformally covering the top surface of the semiconductor substrate, the inner surfaces of the first trench, and the inner surfaces of the second trench; a first electrode layer conformally covering the dielectric liner layer, wherein the first electrode layer extends to the top surface of the semiconductor substrate; a first capacitive dielectric layer disposed on the first electrode layer; a second electrode layer disposed on the first capacitive dielectric layer; a second capacitive dielectric layer disposed on the second electrode layer; and a third electrode layer disposed on the second capacitive dielectric layer, wherein the top surface of the second electrode layer is coplanar with the top surface of the first electrode layer.

[0016] According to an embodiment of the present invention, the first depth ranges from 5 nm to 5 μm, and the second depth ranges from 100 nm to 50 μm.

[0017] According to an embodiment of the present invention, the dielectric liner layer includes silicon oxide.

[0018] According to an embodiment of the present invention, the first electrode layer, the second electrode layer, and the third electrode layer include TiN.

[0019] According to an embodiment of the present invention, the first capacitive dielectric layer and the second capacitive dielectric layer include a ZrO2 / Al2O3 / ZrO2 (ZAZ) film.

[0020] According to an embodiment of the present invention, the third electrode layer includes a through hole directly above the first trench.

[0021] According to an embodiment of the present invention, the MIM capacitor structure further includes: a dielectric layer covering the third electrode layer and the second capacitor dielectric layer; a first contact penetrating the dielectric layer, the third electrode layer, the second capacitor dielectric layer, and the first capacitor dielectric layer, wherein the first contact is electrically connected to the first electrode layer and the third electrode layer; and a second contact penetrating the dielectric layer, the through hole of the third electrode layer, and the second capacitor dielectric layer, wherein the second contact is electrically connected to a portion of the second electrode layer directly above the first trench.

[0022] According to an embodiment of the present invention, the MIM capacitor structure further includes: a through-silicon via penetrating the entire thickness of the dielectric layer, the dielectric liner layer, and the semiconductor substrate.

[0023] According to an embodiment of the present invention, the first contact penetrates the first electrode layer.

[0024] According to an embodiment of the present invention, the first contact and the second contact include tungsten. Description of the Drawings

[0025] Figures 1 to 6 Schematic diagram of a method for manufacturing the MIM capacitor structure illustrated in an embodiment of the present invention;

[0026] Figures 7 to 14 which is a schematic diagram of a method for manufacturing the MIM capacitor structure illustrated in another embodiment of the present invention.

[0027] Symbol Description

[0028] 100 Semiconductor substrate

[0029] 100a Top surface

[0030] 102 First trench

[0031] 104 Second trench

[0032] 110 Dielectric liner layer

[0033] 120 Capacitor stack structure

[0034] 121 Bottom electrode layer, first electrode layer

[0035] 121a Top surface

[0036] 122 Capacitor dielectric layer, first capacitor dielectric layer

[0037] 123 Top electrode layer, second electrode layer

[0038] 123a top surface

[0039] 124 second capacitive dielectric layer

[0040] 125 third electrode layer

[0041] 125t via hole

[0042] 130 trench filling material layer

[0043] 140 dielectric layer

[0044] CS multi - electrode capacitor structure

[0045] CT1 first contact

[0046] CT2 second contact

[0047] DA capacitor formation region

[0048] d1 first depth

[0049] d2 second depth

[0050] TV through - silicon via Detailed implementation manners

[0051] In the following, details will be described with reference to the accompanying drawings, the content of which also constitutes a part of the detailed description of the specification and is shown in a special description manner for implementing this embodiment. The following embodiments have described sufficient details for those of ordinary skill in the art to implement accordingly.

[0052] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as a limitation. On the contrary, the embodiments included therein will be defined by the appended claims.

[0053] Please refer to Figures 1 to 6 , which is a schematic diagram of the manufacturing method of a metal - insulator - metal (MIM) capacitor structure illustrated according to an embodiment of the present invention. As Figure 1 shown, first, a semiconductor substrate 100 is provided, for example, a silicon substrate. According to an embodiment of the present invention, a capacitor formation region DA is provided on the semiconductor substrate 100. Then, a photolithography manufacturing process and an etching manufacturing process are performed to form a first trench 102 in the semiconductor substrate 100 within the capacitor formation region DA. According to an embodiment of the present invention, the first trench 102 has a first depth d1.

[0054] As Figure 2As shown, next, the photolithography process and the etching process are continued to form a second trench 104 in the semiconductor substrate 100 within the capacitor formation region DA. According to an embodiment of the present invention, the second trench 104 may be adjacent to or connected to the first trench 102.

[0055] According to an embodiment of the present invention, the second trench 104 has a second depth d2, where the second depth d2 is greater than the first depth d1. According to an embodiment of the present invention, the first depth d1 is, for example, between 5 nm and 5 μm, and the second depth d2 is, for example, between 100 nm and 50 μm.

[0056] As Figure 3 shown, next, a chemical vapor deposition (CVD) process, for example, an atomic layer deposition (ALD) process, is performed to conformally deposit a dielectric liner layer 110 on the top surface 100a of the semiconductor substrate 100, the inner surface of the first trench 102, and the inner surface of the second trench 104. According to an embodiment of the present invention, for example, the dielectric liner layer 110 may include silicon oxide. Then, a bottom electrode layer 121, a capacitor dielectric layer 122, and a top electrode layer 123 are sequentially formed on the dielectric liner layer 110. The bottom electrode layer 121, the capacitor dielectric layer 122, and the top electrode layer 123 constitute a capacitor stack structure 120.

[0057] According to an embodiment of the present invention, for example, the bottom electrode layer 121 includes TiN. According to an embodiment of the present invention, for example, the top electrode layer 123 includes TiN. According to an embodiment of the present invention, for example, the thicknesses of the bottom electrode layer 121 and the top electrode layer 123 are between 200 and 300 angstroms, for example, 250 angstroms. According to an embodiment of the present invention, for example, the capacitor dielectric layer 122 includes a ZrO2 / Al2O3 / ZrO2 (ZAZ) film or other suitable high-k materials. According to an embodiment of the present invention, the first depth d1 of the first trench 102 may be equal to the thickness of the capacitor dielectric layer 122. According to an embodiment of the present invention, the thickness of the capacitor dielectric layer 122 is, for example, between 40 and 80 angstroms, for example, 60 angstroms.

[0058] As Figure 4 shown, next, a trench filling material layer 130 is deposited over the entire semiconductor substrate 100. According to an embodiment of the present invention, the trench filling material layer 130 fills the second trench 104 and the first trench 102. According to an embodiment of the present invention, for example, the trench filling material layer 130 may include silicon oxide.

[0059] As Figure 5As shown, next, a chemical mechanical polish (CMP) manufacturing process is performed to grind away part of the trench fill material layer 130, the top electrode layer 123, and the capacitor dielectric layer 122 until the bottom electrode layer 121 on the top surface 100a of the semiconductor substrate 100 is exposed. At this time, the trench fill material layer 130, the top electrode layer 123, and the capacitor dielectric layer 122 on the top surface 100a of the semiconductor substrate 100 have been removed, exposing the top surface 121a of the bottom electrode layer 121, and the top surface 123a of the top electrode layer 123 located in the first trench 102 is coplanar with the top surface 121a of the bottom electrode layer 121 on the top surface 100a of the semiconductor substrate 100.

[0060] As Figure 6 shown, next, a dielectric layer 140 is deposited over the entire semiconductor substrate 100, covering the trench fill material layer 130 in the second trench 104, the top electrode layer 123 in the first trench 102, the bottom electrode layer 121 on the top surface of the semiconductor substrate 100, and part of the capacitor dielectric layer 122. Then, a metallization manufacturing process is performed to form a first contact CT1 and a second contact CT2 in the dielectric layer 140, for example, tungsten contacts, wherein the first contact CT1 is electrically connected to the bottom electrode layer 121, and the second contact CT2 is electrically connected to the part of the top electrode layer 123 directly above the first trench 102. Next, a through-silicon via TV can be formed in the dielectric layer 140 and the semiconductor substrate 100, penetrating the entire thickness of the dielectric layer 140 and the semiconductor substrate 100.

[0061] Structurally, as Figure 6 shown, the bottom electrode layer 121 conformally covers the dielectric liner layer 110. The bottom electrode layer 121 extends onto the top surface 100a of the semiconductor substrate 100. The capacitor dielectric layer 122 is disposed on the bottom electrode layer 121 within the first trench 102 and the second trench 104. The top electrode layer 123 is disposed on the capacitor dielectric layer 122 within the first trench 102 and the second trench 104. The top surface 123a of the top electrode layer 123 is coplanar with the top surface 121a of the bottom electrode layer 121. According to an embodiment of the present invention, the capacitor dielectric layer 122 does not extend onto the top surface 100a of the semiconductor substrate 100. According to an embodiment of the present invention, the top electrode layer 123 does not extend onto the top surface 100a of the semiconductor substrate 100.

[0062] Please refer to Figures 7 to 14 , which is a schematic diagram of a manufacturing method of a MIM capacitor structure according to another embodiment of the present invention, wherein the same regions, elements, or layers still use the same symbols to represent. As Figure 7As shown, a semiconductor substrate 100 is first provided, for example, a silicon substrate. According to an embodiment of the present invention, a capacitance formation region DA is provided on the semiconductor substrate 100. Then, a photolithography process and an etching process are performed to form a first trench 102 in the semiconductor substrate 100 within the capacitance formation region DA. According to an embodiment of the present invention, the first trench 102 has a first depth d1.

[0063] Next, the photolithography process and the etching process are continued to form a second trench 104 in the semiconductor substrate 100 within the capacitance formation region DA. According to an embodiment of the present invention, the second trench 104 may be adjacent to or connected to the first trench 102. According to an embodiment of the present invention, the second trench 104 has a second depth d2, where the second depth d2 is greater than the first depth d1. According to an embodiment of the present invention, the first depth d1 is, for example, between 5 nm and 5 μm, and the second depth d2 is, for example, between 100 nm and 50 μm.

[0064] As Figure 8 shown, next, a chemical vapor deposition (CVD) process is performed, for example, an atomic layer deposition (ALD) process, to conformally deposit a dielectric liner layer 110 on the top surface 100a of the semiconductor substrate 100, the inner surface of the first trench 102, and the inner surface of the second trench 104. According to an embodiment of the present invention, for example, the dielectric liner layer 110 may comprise silicon oxide. Then, a first electrode layer 121, a first capacitance dielectric layer 122, and a second electrode layer 123 are sequentially formed on the dielectric liner layer 110.

[0065] As Figure 9 shown, next, a photolithography process and an etching process are performed to remove a portion of the second electrode layer 123 on the top surface 100a of the semiconductor substrate 100, exposing a portion of the first capacitance dielectric layer 122 on the top surface 100a of the semiconductor substrate 100.

[0066] As Figure 10 shown, a second capacitance dielectric layer 124 and a third electrode layer 125 are deposited over the entire semiconductor substrate 100. According to an embodiment of the present invention, for example, the first electrode layer 121, the second electrode layer 123, and the third electrode layer 125 may comprise TiN. According to an embodiment of the present invention, for example, the thickness of the first electrode layer 121, the second electrode layer 123, and the third electrode layer 125 may be between 200 and 300 angstroms, for example, 250 angstroms. According to an embodiment of the present invention, for example, the first capacitance dielectric layer 122 and the second capacitance dielectric layer 124 may comprise a ZrO2 / Al2O3 / ZrO2 (ZAZ) film or other suitable high dielectric constant materials. According to an embodiment of the present invention, the first depth d1 of the first trench 102 may be equal to the thickness of the first capacitance dielectric layer 122. According to an embodiment of the present invention, the thickness of the first capacitance dielectric layer 122 is, for example, between 40 and 80 angstroms, for example, 60 angstroms.

[0067] As shown Figure 11 in, a photolithography process and an etching process are then performed to remove the third electrode layer 125 on the top surface 100a of the semiconductor substrate 100 and on the first trench 102. At this time, a via hole 125t is formed in the third electrode layer 125 directly above the first trench 102, exposing a part of the second capacitive dielectric layer 124.

[0068] As shown Figure 12 in, then, a photolithography process and an etching process are performed to remove the second capacitive dielectric layer 124, the first capacitive dielectric layer 122, and the first electrode layer 121 on the top surface 100a of the semiconductor substrate 100, exposing a part of the dielectric liner layer 110. Thus, a multi-electrode capacitor structure CS is formed.

[0069] As shown Figure 13 in, a dielectric layer 140 is deposited over the entire semiconductor substrate 100, covering the multi-electrode capacitor structure CS. According to an embodiment of the present invention, the dielectric layer 140 covers and directly contacts the third electrode layer 125 and the second capacitive dielectric layer 124. A metallization process is then performed to form a first contact CT1 and a second contact CT2 in the dielectric layer 140, for example, tungsten contacts.

[0070] According to an embodiment of the present invention, the first contact CT1 penetrates through the dielectric layer 140, the third electrode layer 125, the second capacitive dielectric layer 124, and the first capacitive dielectric layer 122, wherein the first contact CT1 is electrically connected to the first electrode layer 121 and the third electrode layer 125.

[0071] According to an embodiment of the present invention, the second contact CT2 penetrates through the dielectric layer 140, the via hole 125t of the third electrode layer 125, and the second capacitive dielectric layer 124, wherein the second contact CT2 is electrically connected to a portion of the second electrode layer 123 directly above the first trench 102.

[0072] As shown Figure 14 in, then, a through-silicon via TV can be formed to penetrate through the entire thickness of the dielectric layer 140, the dielectric liner layer 110, and the semiconductor substrate 100. Subsequently, a metallization process can be continued to form an interconnect structure on the dielectric layer 140. For simplicity of illustration, it will not be described further.

[0073] Structurally, as shown Figure 14As shown, the first electrode layer 121 conformally covers the dielectric cushion layer 110, wherein the first electrode layer 110 extends onto the top surface 100a of the semiconductor substrate 100. The first capacitive dielectric layer 122 is disposed on the first electrode layer 121. The second electrode layer 123 is disposed on the first capacitive dielectric layer 122. The second capacitive dielectric layer 124 is disposed on the second electrode layer 123. The third electrode layer 125 is disposed on the second capacitive dielectric layer 124. The top surface of the second electrode layer 123 is coplanar with the top surface of the first electrode layer 121. According to an embodiment of the present invention, the first contact CT1 can penetrate the first electrode layer 121.

[0074] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A metal-insulator-metal (MIM) capacitor structure, comprising: a semiconductor substrate having a capacitor forming region thereon; A first trench having a first depth and disposed in the semiconductor substrate within the capacitor forming region; A second trench having a second depth, disposed in the semiconductor substrate in the capacitor forming region, wherein the second trench is adjacent to the first trench, and wherein the second depth is greater than the first depth; A dielectric liner layer conformally covers the top surface of the semiconductor substrate, the inner surface of the first trench and the inner surface of the second trench; A bottom electrode layer conformally covers the dielectric liner layer, wherein the bottom electrode layer extends onto the top surface of the semiconductor substrate; A capacitor dielectric layer is disposed on the bottom electrode layer in the first trench and the second trench; and The top electrode layer is disposed on the capacitor dielectric layer in the first trench and the second trench, wherein the top surface of the top electrode layer is coplanar with the top surface of the bottom electrode layer.

2. The metal-insulator-metal capacitor structure according to claim 1, wherein: The first depth is between 5 nm and 5 μm, and the second depth is between 100 nm and 50 μm.

3. The metal-insulator-metal capacitor structure according to claim 1, wherein: The dielectric liner layer includes silicon oxide.

4. The metal-insulator-metal capacitor structure according to claim 1, wherein: The bottom electrode layer includes TiN.

5. The metal-insulator-metal capacitor structure according to claim 1, wherein: The top electrode layer includes TiN.

6. The metal-insulator-metal capacitor structure according to claim 1, wherein: The capacitor dielectric layer includes a ZrO2 / Al2O3 / ZrO2 (ZAZ) film.

7. The metal-insulator-metal capacitor structure according to claim 1, wherein: The capacitor dielectric layer does not extend onto the top surface of the semiconductor substrate.

8. The metal-insulator-metal capacitor structure according to claim 1, wherein: The top electrode layer does not extend onto the top surface of the semiconductor substrate.

9. The metal-insulator-metal capacitor structure according to claim 1, wherein: Also includes: A trench filling material layer is filled into the second trench; A dielectric layer covering the trench filling material layer, the top electrode layer, the bottom electrode layer and the capacitor dielectric layer; a first contact disposed in the dielectric layer and electrically connected to the bottom electrode layer; as well as A second contact is disposed in the dielectric layer and electrically connected to a portion of the top electrode layer directly above the first trench.

10. The metal-insulator-metal capacitor structure according to claim 9, wherein: Also includes: The through silicon via penetrates the entire thickness of the dielectric layer and the semiconductor substrate.

11. A metal-insulator-metal (MIM) capacitor structure, comprising: a semiconductor substrate having a capacitor forming region thereon; A first trench having a first depth and disposed in the semiconductor substrate within the capacitor forming region; A second trench having a second depth is disposed in the semiconductor substrate in the capacitor forming region, wherein the second trench is adjacent to the first trench, and wherein the second depth is greater than the first depth; A dielectric liner layer conformally covers the top surface of the semiconductor substrate, the inner surface of the first trench and the inner surface of the second trench; A first electrode layer conformally covers the dielectric liner layer, wherein the first electrode layer extends onto the top surface of the semiconductor substrate; A first capacitor dielectric layer is disposed on the first electrode layer; A second electrode layer is disposed on the first capacitor dielectric layer; A second capacitor dielectric layer is disposed on the second electrode layer; and The third electrode layer is disposed on the second capacitor dielectric layer, wherein the top surface of the second electrode layer is coplanar with the top surface of the first electrode layer.

12. The metal-insulator-metal capacitor structure according to claim 11, wherein: The first depth is between 5 nm and 5 μm, and the second depth is between 100 nm and 50 μm.

13. The metal-insulator-metal capacitor structure according to claim 11, wherein: The dielectric liner layer includes silicon oxide.

14. The metal-insulator-metal capacitor structure according to claim 11, wherein: The first electrode layer, the second electrode layer, and the third electrode layer include TiN.

15. The metal-insulator-metal capacitor structure according to claim 11, wherein: The first capacitor dielectric layer and the second capacitor dielectric layer include ZrO2 / Al2O3 / ZrO2 (ZAZ) films.

16. The metal-insulator-metal capacitor structure according to claim 11, wherein: The third electrode layer includes a through hole located directly above the first trench.

17. The metal-insulator-metal capacitor structure according to claim 11, wherein: Also includes: A dielectric layer covering the third electrode layer and the second capacitor dielectric layer; A first contact member, which penetrates the dielectric layer, the third electrode layer, the second capacitor dielectric layer and the first capacitor dielectric layer, wherein the first contact member is electrically connected to the first electrode layer and the third electrode layer; and The second contact member penetrates the dielectric layer, the through hole of the third electrode layer and the second capacitor dielectric layer, wherein the second contact member is electrically connected to a portion of the second electrode layer directly above the first trench.

18. The metal-insulator-metal capacitor structure according to claim 17, wherein: Also includes: The through silicon via penetrates the entire thickness of the dielectric layer, the dielectric liner layer and the semiconductor substrate.

19. The metal-insulator-metal capacitor structure of claim 17, wherein: The first contact penetrates the first electrode layer.

20. The metal-insulator-metal capacitor structure of claim 17, wherein: The first contact and the second contact include tungsten.

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