Multi-stage multi-path power amplifier

Abstract

A packaged semiconductor device includes a substrate, an interface for signal communication with an external power divider, and first and second stages of a multi-stage amplifier. The interface includes a first lead, a second lead, and a third lead coupled to the substrate. The first amplifier stage includes a first amplifier die having a first input, a first output, and a first power transistor acting as a driver amplifier. The second amplifier stage includes a first amplifier path and a second amplifier path. The first amplifier path has a second amplifier die having a second input, a second output, and a second transistor acting as a first final amplifier. The second amplifier path has a third amplifier die having a third input, a third output, and a third transistor acting as a second final amplifier. The first output, the second input, and the third input are coupled to the first lead, the second lead, and the third lead, respectively.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to radio frequency (RF) amplifiers, and more particularly, to multi-path amplifiers (e.g., Doherty amplifiers) and amplifier modules. Background Art

[0002] Doherty power amplifiers are widespread in cellular base station transmitters because the Doherty power amplifier architecture is known to improve the back-off efficiency of spectrally efficient modulation compared to other types of amplifiers. The high efficiency of Doherty power amplifiers makes this architecture desirable for current and next-generation wireless systems. However, the trend towards increasingly high operating frequencies (e.g., in the gigahertz (GHz) range) and increased system miniaturization poses challenges to conventional Doherty power amplifier architectures, particularly in the area of semiconductor package design. As frequencies continue to increase, effective Doherty power amplifier implementations that can achieve efficient operation in low-cost, small footprint solutions are needed. Summary of the Invention

[0003] According to a first aspect of the present invention, there is provided a packaged semiconductor device, comprising:

[0004] A device substrate having a mounting surface and a bottom surface;

[0005] An interface for signal communication with an external power divider, wherein the interface includes a first lead, a second lead, and a third lead coupled to the device substrate;

[0006] A first stage of a multi-stage amplifier, the first stage including a first amplifier die having a first input, a first output, and a first power transistor serving as a driver amplifier, wherein the first output is coupled to the first lead; and

[0007] A second stage of a multi-stage amplifier, the second stage including:

[0008] A first amplifier path having a second amplifier die having a second input, a second output, and a second transistor serving as a first final-stage amplifier, wherein the second input is coupled to the second lead, and

[0009] A second amplifier path having a third amplifier die having a third input, a third output, and a third transistor serving as a second final-stage amplifier, wherein the third input is coupled to the third lead.

[0010] In one or more embodiments, the packaged semiconductor device further includes:

[0011] A first heat dissipation structure that extends between the mounting surface and the bottom surface of the device substrate, wherein a first surface of the first heat dissipation structure is exposed at the mounting surface of the device substrate, and the second amplifier die is coupled to the first surface of the first heat dissipation structure; and

[0012] A second heat dissipation structure that extends between the mounting surface and the bottom surface of the device substrate, wherein a first surface of the second heat dissipation structure is exposed at the mounting surface of the device substrate, and the third amplifier die is coupled to the first surface of the second heat dissipation structure.

[0013] In one or more embodiments, the first amplifier die is also coupled to the first surface of the second heat dissipation structure.

[0014] In one or more embodiments, the first lead is characterized by a first inductance forming part of a first impedance transformation circuit;

[0015] The second lead is characterized by a second inductance forming part of a second impedance transformation circuit; and

[0016] The third lead is characterized by a third inductance forming part of a third impedance transformation circuit.

[0017] In one or more embodiments, the first inductance, the second inductance, and the third inductance are in the range of 0.25 nanohenries to 0.75 nanohenries.

[0018] In one or more embodiments, the first lead, the second lead, and the third lead have proximal ends coupled to the mounting surface of the device substrate, and the first lead, the second lead, and the third lead extend perpendicularly from the mounting surface towards the distal ends of the first lead, the second lead, and the third lead.

[0019] In one or more embodiments, the packaged semiconductor device further includes:

[0020] A non-conductive encapsulant above the mounting surface of the device substrate, wherein the non-conductive encapsulant covers the first amplifier die, the second amplifier die, and the third amplifier die, wherein the upper surface of the non-conductive encapsulant at least partially defines a contact surface of the packaged semiconductor device, and wherein the distal ends of the first lead, the second lead, and the third lead are exposed at the contact surface of the packaged semiconductor device.

[0021] In one or more embodiments, the encapsulated semiconductor device further includes:

[0022] A fourth lead coupled to the device substrate and to the first input of the first amplifier die.

[0023] In one or more embodiments, the encapsulated semiconductor device further includes:

[0024] At least a portion of a first-stage input impedance matching circuit coupled between the fourth lead and the first input of the first amplifier die; and

[0025] At least a portion of a first-stage output impedance matching circuit coupled between the first output of the first amplifier die and the first lead.

[0026] In one or more embodiments, the encapsulated semiconductor device further includes:

[0027] At least a portion of a first final-stage input impedance matching circuit coupled between the second lead and the second input of the second amplifier die; and

[0028] At least a portion of a second final-stage input impedance matching circuit coupled between the third lead and the third input of the third amplifier die.

[0029] In one or more embodiments, the multi-stage amplifier is a Doherty power amplifier,

[0030] The first amplifier die is a driver amplifier die;

[0031] The second amplifier die is a carrier amplifier die; and

[0032] The third amplifier die is a peak amplifier die.

[0033] In one or more embodiments, the encapsulated semiconductor device further includes:

[0034] A fourth lead coupled to the device substrate; and

[0035] An output combining network having:

[0036] A first transmission line having a proximal end and a distal end, wherein the proximal end is coupled to the second output of the second amplifier die, and

[0037] A combining node coupled to the third output of the third amplifier die, to the distal end of a first phase shift and impedance transformation section, and to the fourth lead.

[0038] In one or more embodiments, the output combining network further includes:

[0039] A second transmission line coupled between the combining node and the third output of the third amplifier die.

[0040] In one or more embodiments, the first lead, the second lead, and the third lead are selected from conductive posts, quad flat no-lead (QFN) package leads, gull-wing leads, land grid array (LGA) package leads, and ball grid array (BGA) package leads.

[0041] According to a second aspect of the present invention, there is provided a multi-stage multi-path power amplifier, comprising:

[0042] An amplifier substrate having a top substrate surface and first device interconnects, second device interconnects, and third device interconnects at the top substrate surface;

[0043] A packaged semiconductor device coupled to the top substrate surface, wherein the packaged semiconductor device includes:

[0044] A device substrate having a mounting surface and a bottom surface,

[0045] An interface for signal communication with a power divider, wherein the interface includes a first lead, a second lead, and a third lead, and the first lead, the second lead, and the third lead are coupled to the device substrate and respectively coupled to the first device interconnect, the second device interconnect, and the third device interconnect,

[0046] A first stage of a multi-stage amplifier, the first stage including a first amplifier die having a first input, a first output, and a first power transistor serving as a driver amplifier, wherein the first output is coupled to the first lead, and

[0047] A second stage of a multi-stage amplifier, the second stage including:

[0048] A first amplifier path having a second amplifier die having a second input, a second output, and a second transistor serving as a first final stage amplifier, wherein the second input is coupled to the second lead, and

[0049] A second amplifier path having a third amplifier die having a third input, a third output, and a third transistor serving as a second final stage amplifier, wherein the third input is coupled to the third lead; and

[0050] The power splitter, the power splitter being coupled to the top substrate surface, wherein the power splitter has a splitter input coupled to the first device interconnect, a first splitter output coupled to the second device interconnect, and a second splitter output coupled to the third device interconnect, and wherein the power splitter is configured to receive a first signal characterized by a first signal power at the splitter input, provide a first portion of the first signal power at the first splitter output, and provide a second portion of the first signal power at the second splitter output.

[0051] In one or more embodiments, the multi-stage multi-path power amplifier is a Doherty power amplifier,

[0052] The first amplifier die is a driver amplifier die;

[0053] The second amplifier die is a carrier amplifier die; and

[0054] The third amplifier die is a peak amplifier die.

[0055] In one or more embodiments, the packaged semiconductor device further comprises:

[0056] A first heat sink structure extending between the mounting surface and the bottom surface of the device substrate, wherein a first surface of the first heat sink structure is exposed at the mounting surface of the device substrate, and the second amplifier die is coupled to the first surface of the first heat sink structure; and

[0057] A second heat sink structure extending between the mounting surface and the bottom surface of the device substrate, wherein a first surface of the second heat sink structure is exposed at the mounting surface of the device substrate, and the first amplifier die and the third amplifier die are coupled to the first surface of the second heat sink structure.

[0058] In one or more embodiments, the packaged semiconductor device further comprises:

[0059] A fourth lead coupled to the device substrate; and

[0060] An output combining network having:

[0061] A first transmission line having a proximal end and a distal end, wherein the proximal end is coupled to the second output of the second amplifier die, and

[0062] A combined node, the combined node being coupled to the third output of the third amplifier die, coupled to the distal end of the first phase shift and impedance transformation section, and coupled to the fourth lead.

[0063] In one or more embodiments, the output combining network further includes:

[0064] A second transmission line, the second transmission line being coupled between the combined node and the third output of the third amplifier die.

[0065] These and other aspects of the present invention will be apparent from the embodiments described hereinafter and will be elucidated with reference to these embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In conjunction with the following drawings, a more complete understanding of the subject matter can be obtained by referring to the detailed description and the claims, in which like reference numerals refer to like elements throughout the drawings.

[0067] Figure 1 is a schematic diagram of a Doherty power amplifier according to an exemplary embodiment;

[0068] Figure 2 is a schematic diagram of a Doherty power amplifier according to another exemplary embodiment;

[0069] Figure 3 is a top view of a power amplifier device accommodating Figure 2 a driver amplifier, a carrier amplifier, and a peak amplifier according to an exemplary embodiment;

[0070] Figure 4 is Figure 3 a cross-sectional side view of the power amplifier device along line 4-4;

[0071] Figure 5 is Figure 3 a cross-sectional side view of the power amplifier device along line 5-5;

[0072] Figure 6 is a top view of a power amplifier system of a power amplifier device according to an exemplary embodiment having Figure 3 mounted on an amplifier substrate including a power divider and other amplifier features;

[0073] Figure 7 is a schematic diagram of a portion between the driver stage output and the divider input of a Doherty power amplifier according to an exemplary embodiment;

[0074] Figure 8 is a schematic diagram of a portion between the divider output and the inputs of the carrier amplifier and the peak amplifier of a Doherty power amplifier according to an exemplary embodiment;

[0075] Figure 9 is Figure 6 a side cross-sectional view of a power amplifier system along line 9-9; and

[0076] Figure 10 is a side cross-sectional view of an amplifier system of an alternative embodiment of a power amplifier device including Figure 3 coupled to a system substrate according to another exemplary embodiment. DETAILED DESCRIPTION

[0077] Embodiments of the inventive subject matter described herein include a multi-stage multi-path power amplifier (e.g., including but not limited to a Doherty amplifier) configured to amplify a radio frequency (RF) signal. According to one or more embodiments, the multi-stage multi-path power amplifier includes an amplifier substrate and a packaged power amplifier device (or more generally, a "packaged semiconductor device") coupled to a top surface of the amplifier substrate. The packaged power amplifier device includes a first amplifier die (e.g., a driver amplifier die) corresponding to a first amplification stage (e.g., a driver stage), and a set of second amplifier dies (e.g., a carrier amplifier die and a peak amplifier die) corresponding together to a second amplification stage. The packaged power amplifier device also includes an interface for signal communication with an external power divider coupled to the top surface of the amplifier substrate. More specifically, the package interface includes a plurality of leads, where a first one of the leads is coupled to an output of the first amplifier die (e.g., an output of the driver amplifier die). A second lead and a third lead of the leads are coupled to inputs of the second amplifier dies (e.g., inputs of the carrier die and the peak die). On the amplifier substrate, an input of the power divider is coupled to the first lead, and outputs of the power divider are coupled to the second lead and the third lead, respectively.

[0078] Thus, this arrangement can provide a power amplifier lineup with an in-package driver amplifier that provides a pre-amplified signal to the divider input via the first lead. The divider divides the power of the pre-amplified signal into a first signal and a second signal (e.g., a carrier signal and a peak signal) and provides these signals to the in-package carrier amplifier and the in-package peak amplifier via the second lead and the third lead. Thus, because the first amplification stage and the second amplification stage (or the driver die, the carrier die, and the peak die) are all integrated within a single packaged semiconductor device, while the inter-stage power divider is located external to the packaged semiconductor device and accessible via the leads of the packaged semiconductor device, the power amplifier lineup is "partially integrated". In some embodiments, an output transformer at the output of the amplifier may also be located external to the packaged semiconductor device on the amplifier substrate.

[0079] Compared with a power amplifier integrated in a power amplifier package together with a power divider and / or an output converter and driver amplifier die, carrier amplifier die, and peak amplifier die, this arrangement enables the size of the packaged power amplifier device to be reduced (e.g., reduced by about 30%, more or less). By moving the power divider and / or output converter outside the power amplifier package, the cost of the packaged power amplifier device is also reduced.

[0080] The multi-stage power amplifier embodiments described herein can be used to implement any of a variety of different types of power amplifiers. To provide a specific example that will help convey details of the subject matter of the present invention, two examples of Doherty power amplifiers are described herein. Each Doherty amplifier embodiment includes a driver amplifier stage within a package, the driver amplifier stage within the package being coupled to a final carrier amplifier stage within the package and a final peak amplifier stage within the package via an external power divider. However, based on the description herein, those skilled in the art will understand that the subject matter of the present invention can also be used in systems implementing other types of multi-stage amplifiers. Thus, the use of Doherty power amplifiers in the following example embodiments does not mean that the application of the subject matter of the present invention is limited to Doherty power amplifiers, since the subject matter of the present invention can also be used in other types of multi-stage power amplifiers.

[0081] Before describing various physical implementations of the power amplifier, reference is made to Figure 1 and 2 , Figure 1 and 2 which are schematic diagrams of a first example embodiment and a second example embodiment of Doherty power amplifiers 100, 200. Except for output combining networks 170 ( Figure 1 ) and 270 ( Figure 2 ), Doherty power amplifiers 100 and 200 are substantially similar. For the sake of concise description, the same reference numerals are used for Figure 1 and 2 substantially the same elements. Figure 1 and 2 The differences between the embodiments shown in Figure 1 and 2 are indicated by different reference numerals, and these differences will be explained in detail below. To better describe the relative orientation of the various elements of the embodiments shown, a Cartesian coordinate system 194 with orthogonal axes 195, 196, 197 is depicted in the lower right corner of Figure 1 and 2 and in other figures.

[0082] Power amplifiers 100, 200 each substantially include an amplifier substrate 180 (e.g., Figure 6The multi-stage Doherty amplifiers 100, 200 are implemented on an amplifier substrate 680 of FIG. 1 . The Doherty amplifiers 100, 200 are "multi-stage multi-path" amplifiers because each amplifier 100, 200 includes a driver stage (e.g., implemented with driver amplifier 114) and a parallel-coupled final stage (e.g., implemented with carrier amplifier 132 and peaking amplifier 152).

[0083] As will be discussed in more detail later, each Doherty amplifier 100, 200 includes circuitry disposed on an amplifier substrate 180 or disposed within a packaged power amplifier device 182, 282. Importantly, in accordance with one or more embodiments, the amplification components (e.g., driver die 114, carrier die 132, and peak die 152) of the Doherty amplifier 100, 200 are included within the packaged power amplifier device 182, 282, while the interstage power divider 120 is disposed on the amplifier substrate 180. As will be explained in more detail later, the external interstage power divider 120 is electrically coupled to the amplification components via an interface for signal communication, the interface including a plurality of device terminals (e.g., Figure 1-3 Device ends 104-108, 302, 304-308).

[0084] The amplifier substrate 180 may include, for example, a printed circuit board (PCB) or other suitable substrate. The packaged power amplifier device 182, 282 may be a discrete surface-mountable device configured to be coupled to a mounting surface of the amplifier substrate 180. More specifically, the conductive device leads 104-109 (e.g., Figure 3 The distal ends of the leads 302, 304-312 of the amplifier substrate 180 are physically and electrically coupled to conductive bonding pads (e.g., Figure 6 As will be discussed in more detail later, the packaged power amplifier device 182, 282 includes a device substrate 183 (e.g., Figure 3-5 The device substrate 301), the device leads 104-109 (for example, Figure 3-5 leads 302, 304-312), one or more heat dissipation structures 161, 162 (e.g., Figure 3-5 structures 361, 362), multiple power amplifier dies 114, 132, 152 coupled to the heat dissipation structures 161, 162 (e.g., Figure 3-5 dies 314, 332, 352) and additional circuit systems as described below.

[0085] In an embodiment, each Doherty amplifier 100, 200 includes an amplifier input terminal 101 on an amplifier substrate 180, an amplifier output terminal 102 on the amplifier substrate 180, a driver amplifier including a driver amplifier die 114 (e.g., Figure 3 die 314) in the packaged power amplifier devices 182, 282, a power divider 120 on the amplifier substrate 180, a carrier amplifier path 130 including a carrier amplifier die 132 (e.g., Figure 3 die 332) in the packaged power amplifier devices 182, 282, a peak amplifier path 150 including a peak amplifier die 152 (e.g., Figure 3 die 352) in the packaged power amplifier devices 182, 282, an output combining network 170 or 270 in the packaged power amplifier devices 182, 282, a combining node 176 or 276 in the packaged power amplifier devices 182, 282, and an output impedance transformer 178 on the amplifier substrate 180. A significant difference between the Doherty amplifiers 100, 200 and a conventional Doherty amplifier is that in the Doherty amplifiers 100, 200, the driver amplifier die 114, the carrier amplifier die 132, and the peak amplifier die 152 are implemented within the packaged power amplifier devices 182, 282, while the power divider 120 is implemented external to the packaged power amplifier devices 182, 282 on the amplifier substrate 180. By pulling the power divider 120 out of the packaged power amplifier devices 182, 282, the size of the packaged power amplifier devices 182, 282 can be made smaller compared to a conventional Doherty amplifier device.

[0086] When incorporated into a larger RF system, the amplifier input terminal 101 is coupled to an RF signal source, and the amplifier output terminal 102 is coupled to a load 190 (e.g., an antenna or other load). The RF signal source provides an input RF signal, which is an analog signal that includes spectral energy typically centered around one or more carrier frequencies. Basically, the Doherty amplifier is configured to amplify the input RF signal received at the amplifier input terminal 101 and produce an amplified output RF signal at the amplifier output terminal 102.

[0087] According to an embodiment, the input RF signal received at the amplifier input terminal 101 is transmitted through a first impedance matching circuit 110 on the amplifier substrate 180 to a device input lead 104 of the packaged power amplifier devices 182, 282. Then, the input RF signal is amplified by a driver amplifier within the packaged power amplifier devices 182, 282. The driver amplifier corresponds to a first amplifier stage of the Doherty amplifiers 100, 200.

[0088] The driver amplifier includes a driver input impedance matching circuit 113, a driver amplifier die 114, and a driver output impedance matching circuit 117. The driver input impedance matching circuit 113 is coupled to the device substrate 183 between the device input lead 104 and the input terminal 115 (e.g., the gate terminal) of the driver amplifier die 114. The first impedance matching circuit 110, the smaller inductance provided by the device input lead 104, and the driver input impedance matching circuit 113 (collectively referred to as the "driver input impedance matching circuit") are configured to transform the gate impedance of the power transistor within the die 114 into a more desirable system-level impedance (e.g., 50 ohms).

[0089] According to one or more embodiments, the driver amplifier die 114 is coupled to a first heat sink structure 161 (e.g., Figure 3-5 the heat sink structure 361), and the first heat sink structure 161 is configured to transfer heat generated by the driver amplifier die 114 to a system heat sink (e.g., Figure 9 , 10 the heat sink 916 or 1016) during the operation of the Doherty amplifiers 100, 200. The driver amplifier die 114 is configured to amplify an input RF signal received from the input impedance matching circuit 113 to produce a pre-amplified RF signal at the output terminal 116 (e.g., the drain terminal) of the driver amplifier die 114. According to one or more embodiments, the pre-amplified RF signal is then transmitted through the driver output impedance matching circuit 117 to the driver output lead 105 of the packaged power amplifier devices 182, 282.

[0090] Returning now to the amplifier substrate 180, the pre-amplified RF signal is transmitted through an additional impedance matching circuit 118 on the amplifier substrate 180 to the input 121 of the power divider 120. The power divider 120 is configured to divide the pre-amplified RF signal received at the input 121 into a first pre-amplified RF signal and a second pre-amplified RF signal (or a carrier signal and a peak signal), which are provided at the power divider outputs 122, 123, respectively. According to an embodiment, the power divider 120 is configured to apply a phase difference (e.g., a phase difference of about 90 degrees) between the first pre-amplified RF signal and the second pre-amplified RF signal. In such embodiments, at the outputs 122 and 123, the carrier signal and the peak signal may be out of phase with each other by about 90 degrees.

[0091] When the Doherty amplifier has a symmetric configuration (i.e., a configuration in which the power transistors in die 132, 152 have substantially the same size), the power splitter 120 can divide or allocate the input RF signal received at input 121 into two signals having very similar power and, in some embodiments, equal power. Conversely, when the Doherty amplifier has an asymmetric configuration (i.e., a configuration in which one of the power transistors, typically the power transistor in the peaking amplifier die 152, is significantly larger), the power splitter 120 can output a carrier signal and a peaking signal having unequal power.

[0092] The outputs 122, 123 of the power splitter 120 are connected via phase shift circuits 124, 126 on the amplifier substrate 180 to the carrier input lead 106 and the peaking input lead 107 of the packaged power amplifier devices 182, 282. Now turning back inside the packaged power amplifier devices 182, 282, the carrier input lead 106 is coupled to the carrier amplifier path 130, and the peaking input lead 107 is coupled to the peaking amplifier path 150. As will be described in more detail below, the carrier amplifier path 130 is configured to amplify the pre-amplified carrier signal from the power splitter 120 to produce an amplified carrier signal. Similarly, the peaking amplifier path 150 is configured to amplify the pre-amplified peaking signal from the power splitter 120 to produce an amplified peaking signal. The carrier amplifier and the peaking amplifier correspond to the second amplifier stage of the Doherty amplifiers 100, 200.

[0093] The carrier amplifier path 130 includes a first carrier impedance matching circuit 127 and a second carrier impedance matching circuit 131 and a carrier amplifier die 132. The first carrier impedance matching circuit 127 and the second carrier impedance matching circuit 131 are coupled between the carrier input lead 106 and the input terminal 138 (e.g., the gate terminal) of the carrier amplifier die 132. More specifically, the first carrier impedance matching circuit 127 coupled to the device substrate 183 represents the first part of the total input impedance matching circuit of the carrier amplifier die 132, and the second carrier impedance matching circuit 131 coupled to the second heat sink structure 162 (e.g., Figure 3-5 the heat sink structure 362) represents the second part of the total input impedance matching circuit of the carrier amplifier die 132.

[0094] According to one or more embodiments, the carrier amplifier die 132 is also coupled to the second heat sink structure 162, which is configured to transfer the heat generated by the carrier amplifier die 132 to the aforementioned system heat sink during operation of the Doherty amplifiers 100, 200 (e.g., Figure 9 , 10a radiator 916 or 1016). The carrier amplifier die 132 is configured to amplify the pre-amplified carrier signal received from the carrier input impedance matching circuits 127, 131 so as to generate an amplified carrier signal at the output terminal 139 (e.g., drain terminal) of the carrier amplifier die 132.

[0095] The peak amplifier path 150 includes a first peak impedance matching circuit 128 and a second peak impedance matching circuit 151 and a peak amplifier die 152. The first peak impedance matching circuit 128 and the second peak impedance matching circuit 151 are coupled between the peak input lead 107 and the input terminal 158 (e.g., gate terminal) of the peak amplifier die 152. More specifically, the first peak impedance matching circuit 128 coupled to the device substrate 183 represents the first part of the total input impedance matching circuit of the peak amplifier die 152, and the second peak impedance matching circuit 151 coupled to the first heat sink structure 161 (e.g., Figure 3-5 a heat sink structure 361) represents the second part of the total input impedance matching circuit of the peak amplifier die 152.

[0096] According to one or more embodiments, the peak amplifier die 152 is also coupled to the first heat sink structure 161, and the first heat sink structure 161 is configured to transfer the heat generated by the peak amplifier die 152 during the operation of the Doherty amplifier 100, 200 to the aforementioned system radiator (e.g., Figure 9 , 10 a radiator 916 or 1016). The peak amplifier die 152 is configured to amplify the pre-amplified peak signal received from the peak input impedance matching circuits 128, 151 so as to generate an amplified carrier signal at the output terminal 159 (e.g., drain terminal) of the peak amplifier die 152.

[0097] According to an embodiment, the peak amplifier die 152 and the carrier amplifier die 132 are coupled to the first heat sink structure 161 and the second heat sink structure 162 such that the signal paths through the peak amplifier die 152 and the carrier amplifier die 132 extend in a first direction indicated by arrows 130 and 150, and the first direction is parallel to the first axis 197 of the Cartesian coordinate system 194. Conversely, the driver amplifier die 114 can be coupled to the first heat sink structure 161 such that the signal path through the driver amplifier die 114 extends in a second direction parallel to the second axis 195 (i.e., an axis orthogonal to the first axis 197) of the Cartesian coordinate system 194. Such an arrangement of the dies 114, 132, 152 facilitates a compact arrangement of the components of the packaged power amplifier devices 182, 282. Additionally, coupling the driver amplifier die 114 and the peak amplifier die 152 to the same heat sink structure 161 achieves a relatively compact device by eliminating the need for such dies to have separate heat sink structures.

[0098] Each amplifier die 114, 132, 152 includes one or more integrated power transistors, where each power transistor includes a control terminal (e.g., a gate terminal) and first and second current-carrying terminals (e.g., a drain terminal and a source terminal). In a single-stage device including a single power transistor, the control terminal is electrically connected to the input terminals 115, 138, 158, one current-carrying terminal (e.g., the drain terminal) is electrically connected to the output terminals 116, 139, 159, and the other current-carrying terminal (e.g., the source terminal) is electrically connected to a ground reference (or another voltage reference) through the first heat dissipation structure 161 or the second heat dissipation structure 162. Conversely, a two-stage amplifier will include two power transistors serially coupled between each input terminal 115, 138, 158 and each output terminal 116, 139, 159.

[0099] According to various embodiments, in Doherty power amplifiers 100 and 200, the output terminal 139 of the carrier amplifier die 132 and the output terminal 159 of the peak amplifier die 152 are coupled to the power combining node 176 or 276 through the output combining network 170 or 270. Referring first to Figure 1 amplifier 100 in, the first end of the output combining network 170 is connected to the output terminal 139 of the carrier amplifier die 132, and the second end of the output combining network 170 is connected to the power combining node 176.

[0100] According to an embodiment, the output combining network 170 includes one or more transmission lines 172 formed on or within the device substrate 183, and connectors 171 between the opposite ends of the transmission line 172 and the carrier output terminal 139 and connectors 175 between the opposite ends of the transmission line 172 and the peak output terminal 159. For example, the total electrical length of the output combining network 170 may be about lambda / 4 (λ / 4) (i.e., about 90 degrees) at the fundamental operating frequency f0 of the amplifier 100. Thus, the output combining network 170 is configured to apply a relative phase shift of about 90 degrees to the amplified carrier signal between the RF output terminal 139 and the power combining node 176 at the fundamental frequency.

[0101] According to Figure 1In the illustrated embodiment, the output terminal 159 of the peak amplifier die 152 and the combining node 176 can be implemented with common physical elements. More specifically, in the embodiment, the output terminal 159 of the peak amplifier die 152 is configured to serve as both the combining node 176 and the output terminal 159 of the peak amplifier die 152. To facilitate the combining of the amplified carrier signal and the amplified peak signal, and as mentioned above, the output terminal 159 (and thus the combining node 176) is connected to the second end of the output combining network 170. In other embodiments, the combining node 176 can be an element separate from the output terminal 159. In summary, in amplifier 100, the amplified carrier RF signal and the amplified peak RF signal are combined in-phase at the combining node 176. Since the output combining network 170 applies a relative phase shift of approximately 90 degrees to the amplified carrier signal between the carrier output terminal 139 and the combining node 176, while substantially no phase shift is applied to the amplified peak signal between the peak output terminal 159 and the combining node 176, so Figure 1 the illustrated combining topology can be referred to as a 90 / 0 combining topology.

[0102] Now referring to Figure 2 amplifier 200 in, a different combining topology is shown. More specifically, the output combining network 270 is configured to apply a phase delay to both the amplified carrier signal and the amplified peak signal before they reach the combining node 276. More specifically, according to an embodiment, the output combining network 270 includes a carrier-side phase delay circuit and a peak-side phase delay circuit.

[0103] The carrier-side phase delay circuit includes a connection 271 between the carrier output terminal 139 and the combining node 276 and one or more first transmission lines 272. Similarly, the peak-side phase delay circuit includes a connection 274 between the peak output terminal 159 and the combining node 276 and one or more second transmission lines 273. The first transmission lines 272 and the second transmission lines 273 are formed on or within the device substrate 183. According to an embodiment, the total electrical length of the carrier-side phase delay circuit can be approximately lambda / 4 (λ / 4) (i.e., approximately 90 degrees) at the fundamental operating frequency f0 of the amplifier 200. Thus, the carrier-side phase delay circuit is configured to apply a relative phase shift of approximately 90 degrees to the amplified carrier signal between the RF output terminal 139 and the power combining node 276 at the fundamental frequency. Conversely, the total electrical length of the peak-side phase delay circuit can be approximately lambda / 2 (λ / 2) (i.e., approximately 180 degrees) at the fundamental operating frequency f0 of the amplifier 200. Thus, the peak-side phase delay circuit is configured to apply a relative phase shift of approximately 180 degrees to the amplified peak signal between the RF output terminal 159 and the power combining node 276 at the fundamental frequency.

[0104] Similarly, in amplifier 200, output combining network 270 is configured such that the amplified carrier RF signal and the amplified peak RF signal are combined in-phase at combining node 276. Since output combining network 270 applies a relative phase shift of approximately 90 degrees to the amplified carrier signal between carrier output terminal 139 and combining node 276, and also applies a relative phase shift of approximately 180 degrees to the amplified peak signal between peak output terminal 159 and combining node 276, Figure 2 the combining topology shown can be referred to as a 90 / 180 combining topology. Although the 90 / 180 output combining network 270 in amplifier 200 is larger in size than the 90 / 0 output combining network 170 in amplifier 100, it may have certain performance advantages. More specifically, compared to the 90 / 0 combining topology included in amplifier 100, including the 90 / 180 combining topology in amplifier 200 can improve Doherty performance and bandwidth.

[0105] According to one or more alternative embodiments, in amplifier 200, alternatively, at the fundamental operating frequency f0 of amplifier 200, output combining network 270 can be configured such that the total electrical length of the carrier-side phase delay circuit (e.g., interconnect 271 and transmission line 272) can be between approximately lambda / 8 (λ / 8) (i.e., approximately 45 degrees) and approximately lambda / 4 (λ / 4) (i.e., approximately 90 degrees), and the total electrical length of the peak-side phase delay circuit (e.g., interconnect 274 and transmission line 273) can be between approximately 3 times lambda / 2 (3λ / 4) (i.e., approximately 145 degrees) and lambda / 2 (λ / 2) (i.e., approximately 180 degrees). In such embodiments, the combining node impedance can be complex. This topology can be referred to as an A-CCL topology. Compared to the 90 / 0 topology described above, this topology can exhibit better broadband performance while maintaining the footprint of amplifier 200 to be smaller than the 90 / 180 topology described above.

[0106] In both Doherty power amplifiers 100, 200, combining nodes 176, 276 are electrically coupled to output leads 108 of packaged power amplifier devices 182, 282. Returning to amplifier substrate 180, output impedance transformer 178 is coupled between output lead 108 and RF output terminal 102. Finally, output transformer 178 is used to present an appropriate load impedance to each of carrier amplifier die 132 and peak amplifier die 152. The resulting amplified RF output signal is generated at RF output terminal 102, and output load 190 (e.g., an antenna) is connected to the RF output terminal 102.

[0107] In addition to the components described and shown above, the power amplifier 100 may further include gate and / or drain bias circuitry 192 on the amplifier substrate 180. The gate and / or drain bias circuitry 192 may receive bias voltages from an external source via additional *103 on the amplifier substrate 180 and may transfer those bias voltages to additional leads 109 of the packaged power amplifier devices 182, 282. Although Figure 1 not shown in FIGS. 1 or 2, additional conductive traces and bond wires within the packaged power amplifier devices 182, 282 may further transfer those bias voltages to the gates and / or drains of the power transistors within the driver amplifier die 114, the carrier amplifier die 132, and the peaking amplifier die 152.

[0108] Each Doherty power amplifier 100, 200 is configured such that the carrier amplifier path 130 provides amplification of a relatively low-level input signal, and both the carrier amplification path 130 and the peaking amplification path 150 operate in combination to provide amplification of a relatively high-level input signal. This may be achieved, for example, by biasing the carrier amplifier 132 such that the carrier amplifier 132 operates in class AB mode and biasing the peaking amplifier 152 such that the peaking amplifier 152 operates in class C mode. Thus, the bias voltages provided to the gates and / or drains of the driver amplifier die 114 may configure the driver amplifier to operate in class AB mode, while the bias voltages provided to the gates and / or drains of the carrier amplifier die 132 and the peaking amplifier die 152 may be provided to configure the carrier amplifier and the peaking amplifier to operate in class AB mode and class C mode, respectively.

[0109] Although Figure 1 not shown in FIGS. 1 or 2, additional circuitry may be included in each of the Doherty power amplifiers 100, 200. For example but not limited to, harmonic termination circuitry (e.g., circuitry that resonates at one or more harmonics of the fundamental operating frequency) may be included in the packaged power amplifier devices 182, 282 at the inputs and / or outputs of the carrier amplifier 132 and the peaking amplifier 152.

[0110] An example of a physical implementation of the packaged power amplifier device 282 will now be described in connection with Figure 3-5 discussion Figure 2 More specifically, Figure 3 is a top view of a power amplifier device 300 that houses Figure 2 the driver amplifier 114, the carrier amplifier 132, and the peaking amplifier 152 according to an example embodiment. For enhanced understanding, Figure 3 should be viewed in conjunction with Figure 4 and 5 whereinFigure 4 is a cross-sectional side view of the power amplifier device 300 along line 4-4, and Figure 5 is a cross-sectional side view of the power amplifier device 300 along line 5-5.

[0111] Figure 3 is an embodiment according to an exemplary embodiment Figure 1 、 2 of a packaged power amplifier device 300 showing the circuitry within the packaged power amplifier device 282. For enhanced understanding, Figure 3 should be viewed in conjunction with Figure 4 and 5 simultaneously. Figure 4 and 5 are, respectively, Figure 3 cross-sectional side views of the device 300 along lines 4-4 and 5-5. Basically, the packaged power amplifier device 300 includes the majority of a Doherty power amplifier coupled to a multi-layer device substrate 383 (or coupled to heat dissipation structures 361, 362 extending through the device substrate 383). The portion of the Doherty power amplifier coupled to the device substrate 383 or coupled to the heat dissipation structures 361, 362 includes a plurality of power transistor dies 314, 332, 352 (e.g., Figure 1 、 2 dies 114, 132, 152), an output combining network 370 (e.g., Figure 1 、 2 network 270, but alternatively could be Figure 1 、 2 network 170), various impedance matching circuits 313, 317, 327, 328, 331, 351 (e.g., circuits 113, 117, 127, 128, 131, 151) and other electrical components. It should be noted that the packaged power amplifier device 282 does not include a power splitter (e.g., Figure 1 、 2 power splitter 120), as the power splitter is instead implemented on an amplifier substrate (e.g., Figure 1 、 2 substrate 180), rather than within the device 300. Additionally, the packaged power amplifier device 300 includes a plurality of conductive leads 302, 304, 305, 306, 307, 308, 309, 310, 311, 312 (e.g., Figure 1 、 2 leads 104 - 108) for transmitting signals or bias voltages or for connection to a ground reference, as will be discussed in detail below.

[0112] The encapsulated power amplifier device 300 includes a device substrate 383 in the form of a multi-layer printed circuit board (PCB) or other suitable substrate (e.g., Figure 1 , 2 substrate 183). The device substrate 383 has a top surface 384 (also referred to as the "front side" or "mounting surface") and a bottom surface 385 (also referred to as the "back side" or "heat dissipation surface"). As used herein, the term "mounting surface 384 of the device substrate 383" includes the top surface of the substrate 383, but does not include the upper surfaces of the first heat dissipation structure 361 and the second heat dissipation structure 362, which may be substantially coplanar with the mounting surface 384 of the device substrate 383.

[0113] As will be described in more detail below, leads 302, 304 - 312 and a plurality of components are coupled to the mounting surface 384 of the device substrate 383, and power amplifier dies 314, 332, 352 are coupled to the heat dissipation structures 361, 362. As Figure 4 and 5 shown, a non-conductive encapsulant material 386 (e.g., plastic encapsulant) is disposed on the mounting surface 384 and above and around the components, dies 314, 332, 352, and leads 302, 304 - 312 so as to define the top surface 381 (also referred to as the "contact surface") of the device 300. Basically, the encapsulant material 386 covers the components and dies 314, 332, 352. As Figure 3 shown, the thickness of the encapsulant material 386 is greater than the maximum height of the components (e.g., power transistor dies 314, 332, 352) covered by the encapsulant material 386, such that the encapsulant material 386 exists between the top surfaces of these components and the top surface 381 of the device 300.

[0114] The lower or proximal ends of the leads 302, 304 - 312 are coupled to conductive features on the mounting surface 384 of the device substrate 383. The leads 302, 304 - 312 extend vertically from the mounting surface 384 towards their upper or distal ends. The upper or distal ends of the leads 302, 304 - 312 are exposed at the contact surface 381 (i.e., the leads 302, 304 - 312 are exposed at the top surface of the encapsulant material 386). A conductive attachment material 399 (e.g., solder balls, solder paste, or conductive adhesive) is disposed on the exposed distal ends of the leads 302, 304 - 312 to facilitate the electrical and mechanical attachment of the device 300 to a system substrate (e.g., Figure 2 , 6 amplifier substrate 180 or 680) as will be described in more detail below.

[0115] In Figure 3-5In the illustrated embodiment, leads 302, 304 - 312 are formed of conductive posts that may be attached to or formed on conductive pads at mounting surface 384 of device substrate 383. In some embodiments, groups of such leads 302, 304 - 312 may be wrapped in a non - conductive holding structure (e.g., a plastic or ceramic structure) prior to attachment to device substrate 383. In other embodiments, leads 302, 304 - 312 may have other forms, such as but not limited to quad flat no - lead (QFN) package leads, gull - wing leads, land grid array (LGA) package leads, and ball grid array (BGA) package leads.

[0116] As Figure 4 and 5 depicted, device substrate 383 includes a plurality of dielectric layers 390, 391, 392, 393 (e.g., formed of FR - 4, ceramic, or other PCB dielectric materials) alternating with a plurality of conductive layers 394, 395, 396, 397, 398. The top surface 384 of device substrate 383 is defined by patterned conductive layer 394, and the bottom surface 385 of device substrate 383 is defined by the bottom surfaces of conductive layer 398 and heat - sink structures 361, 362. In Figure 4 and 5 the illustrated embodiment, layers 394 and 398 do not respectively overlie the top and bottom surfaces of heat - sink structures 361, 362. In other embodiments, layer 394 and / or 398 may overlie the top and / or bottom surfaces of heat - sink structures 361, 362, and / or the top and / or bottom surfaces of heat - sink structures 361, 362 may be electroplated. It should be noted that although device substrate 383 is shown as including four dielectric layers 390 - 393 and five conductive layers 394 - 398, other embodiments of the device substrate may include more or fewer dielectric layers and / or conductive layers.

[0117] Each of the respective conductive layers 394 - 398 may have a primary use and may also include conductive features that facilitate signal and / or voltage / ground routing between other layers. Although the following description may indicate the primary use for each of conductive layers 394 - 398, it should be understood that the layers (or their functionality) may be arranged differently than Figure 4 and 5 shown best in

[0118] For example, in an embodiment, the patterned conductive layer 394 at the mounting surface 384 of the device substrate 383 can primarily function as a signal conduction layer. More specifically, layer 394 includes a plurality of conductive features (e.g., conductive bonding pads and traces) that serve as attachment points for various discrete components and also provide electrical connectivity between the dies 314, 332, 352 and other discrete components. Additionally, layer 394 can include a plurality of conductive bonding pads that are specifically designated for attaching conductive signal leads, bias leads, and / or ground leads (e.g., leads 302, 304 - 312).

[0119] In various embodiments, other patterned conductive layers 395 - 397 can function as an RF ground layer, a signal routing layer, and / or a layer for delivering a bias voltage to power transistors within the dies 314, 332, 352. According to an embodiment, the conductive layer 398 at the bottom surface 385 of the device 300 can function as a system ground layer. Conductive vias extend through the dielectric layers 390 - 393 to electrically connect the respective conductive layers 394 - 398.

[0120] According to an embodiment, the device substrate 383 further includes one or more heat dissipation structures 361, 362 that extend between the top surface 384 and the bottom surface 385 of the device substrate 383. In some embodiments, the heat dissipation structures 361, 362 can be joined together by a heat infrastructure 363 to form a single integrated heat structure 360. In such embodiments, the heat structure 360 includes the heat infrastructure 363 and two pedestals corresponding to two portions of the heat dissipation structures 361, 362 that extend from the infrastructure 363 to the mounting surface 384 of the device substrate 383. In alternative embodiments, the heat dissipation structures 361, 362 can be separate structures (e.g., may not include the heat infrastructure 363), as Figure 4 and 5 indicated by the vertical dashed lines passing through the infrastructure 363 (i.e., the vertical dashed lines represent the sidewalls of the separate heat dissipation structures 361, 362).

[0121] In summary, the first heat dissipation structure 361 has a first heat surface 365 exposed at the mounting surface 384 of the device substrate 383, the second heat dissipation structure 362 has a second heat surface 367 exposed at the mounting surface 384 of the device substrate 383, and the first heat surface 365 and the second heat surface 367 are physically separated by a portion of the mounting surface 384 of the device substrate 383 that exists between the first heat surface 365 and the second heat surface 367. The sidewalls (not numbered) of the heat dissipation structures 361, 362 are formed by portions of the device substrate 383 (e.g., portions of the dielectric layers 390 - 393, as Figure 5As shown, or when the infrastructure 363 is not included, the portions of all the dielectric layers 390 - 393) are separated. The first thermal surface 365 and the second thermal surface 367 may or may not be plated and / or covered by portions of the layer 394.

[0122] According to an embodiment, the driver amplifier die 314 and the peak amplifier die 352 (e.g., Figure 1 , 2 die 114, 152) of) are physically and electrically coupled (or connected) to the surface 365 of the first heat sink structure 361, and the carrier amplifier die 332 (e.g., Figure 1 , 2 die 132) of) is physically and electrically coupled to the surface 367 of the second heat sink structure 362. In some embodiments, the driver amplifier die 314 and the peak amplifier die 352 may be directly connected to the first thermal surface 365, or a portion of the upper conductive layer 394 and / or the plating layer may be located between the dies 314, 352 and the first thermal surface 365. Similarly, in some embodiments, the carrier amplifier die 332 may be directly connected to the second thermal surface 367, or a portion of the upper conductive layer 383 and / or the plating layer may be located between the die 332 and the second thermal surface 367.

[0123] The driver amplifier die 314 includes power transistors that are integrally formed within the die 314 and serve as a driver amplifier. The driver amplifier die 314 has an input terminal 315 coupled to a control terminal (e.g., gate terminal) of the integrated power transistors, and an output terminal 316 coupled to an output terminal (e.g., drain terminal) of the integrated transistors. The driver amplifier die 314 is coupled to the first thermal surface 365 such that a first signal path through the driver amplifier die 314 (i.e., the signal path between terminals 315, 316) extends in a first direction parallel to a first axis 195 of the Cartesian coordinate system 194.

[0124] Additionally, the peak amplifier die 352 includes a power transistor that is integrally formed within the die 352 and serves as a first final stage amplifier. The peak amplifier die 352 has an input terminal 358 coupled to a control terminal (e.g., gate terminal) of the integrated power transistor and an output terminal 359 coupled to an output terminal (e.g., drain terminal) of the integrated power transistor. The peak amplifier die 352 is coupled to the first thermal surface 365 such that the peak signal path through the peak amplifier die 352 (i.e., the signal path between leads 358, 359) extends in a second direction parallel to the second axis 197 of the Cartesian coordinate system 194. As previously mentioned, coupling the driver amplifier die 314 and the peak amplifier die 352 to the same heat sink structure 361 enables a relatively compact module by eliminating the need for such dies to have separate heat sink structures.

[0125] Similarly, the carrier amplifier die 332 includes a power transistor that is integrally formed within the die 332 and serves as a second final stage amplifier, where the first final stage amplifier and the second final stage amplifier are arranged in parallel with each other. The carrier amplifier die 332 has an input terminal 338 coupled to a control terminal (e.g., gate terminal) of the integrated power transistor and an output terminal 339 coupled to an output terminal (e.g., drain terminal) of the integrated power transistor. The carrier amplifier die 352 is coupled to the second thermal surface 367 such that the carrier signal path through the carrier amplifier die 332 (i.e., the signal path between leads 338, 339) can also extend in a second direction parallel to the second axis 197 of the Cartesian coordinate system 194. In an alternative embodiment, the carrier amplifier die 332 can be rotated 90 degrees such that the carrier signal path extends in a first direction (i.e., parallel to the first axis 195).

[0126] According to various embodiments, each of the power transistors integrally formed within the driver amplifier die 314, the carrier amplifier die 332, and the peak amplifier die 352 may be implemented, for example, using a field effect transistor (FET), such as a laterally diffused metal oxide semiconductor (LDMOS) FET or a high electron mobility transistor (HEMT). For example, each of the power transistors within dies 314, 332, 352 may be implemented using a III-V field effect transistor (e.g., HEMT), such as a gallium nitride (GaN) FET (or another type of III-V transistor, including GaAs FET, GaP FET, InP FET, or InSb FET). Additionally or alternatively, in some embodiments, the power transistors within dies 314, 332, 352 may be implemented using a silicon-based FET (e.g., a laterally diffused metal oxide semiconductor (LDMOS) FET) or a silicon germanium (SiGe) FET. Further, the semiconductor technology of the driver amplifier die 314, the carrier amplifier die 332, and the peak amplifier die 352 may be the same, or the driver amplifier die 314 may utilize one semiconductor technology while the carrier amplifier die 332 and the peak amplifier die 352 utilize different semiconductor technologies.

[0127] The specification and claims may refer to each transistor as including a control terminal and two conductive terminals. For example, using terms associated with an FET, the "control terminal" refers to the gate lead of the transistor, and the first and second conductive terminals refer to the drain and source terminals of the transistor (and vice versa). Although the following description may use terms common to FET devices, the various embodiments are not limited to embodiments utilizing FET devices, but rather are meant to also apply to embodiments utilizing bipolar junction transistor (BJT) devices or other suitable types of transistors.

[0128] As described above and best shown in Figure 3 the driver amplifier die 314 and the peak amplifier die 352 are each coupled to the surface 365 of the first heat sink structure 361 such that the direction of the signal path through the driver amplifier die 314 is orthogonal (i.e., angularly offset by 90 degrees) to the direction of the signal path through the peak amplifier die 352. The orthogonal orientation of the driver amplifier die 314 and the peak amplifier die 352 reduces any mutual coupling between the driver amplifier die 314 and the peak amplifier die 352 and also provides the possibility of reducing the module size.

[0129] The bottom surfaces of the heat dissipation structures 361, 362 and the bottom surface of the base structure 363 (when included) are exposed at the bottom surface 385 of the device substrate 383. Alternatively, the bottom surfaces of the heat dissipation structures 361, 362 may be covered by a bottom conductive layer 398 and / or a plating layer. In summary, the heat dissipation structures 361, 362 are configured to provide a thermal path between the die 314, 332, 352 and the bottom surfaces of the heat dissipation structures 361, 362 (and thus the bottom surface 385 of the device substrate 383).

[0130] In some embodiments, and specifically when the base structure 363 is not included, the heat dissipation structures 361, 362 may include separate conductive metal coins that are press-fit and / or attached into vias extending between the surfaces 384, 385 of the device substrate 383. Alternatively, when the base structure 363 is included, the structures 361 - 363 may be integrally formed together and / or machined from a single block of thermally conductive material. In summary, as will be described in more detail Figure 9 when the device 300 is integrated within a larger electrical system, the exposed bottom surfaces 364, 366 of the heat dissipation structures (or the portions of the conductive layer 398 overlying these surfaces) may be physically and thermally coupled to a heat sink (e.g., Figure 9 heat sink 916).

[0131] Now that the general physical construction of the device 300 has been described, the amplifier circuitry embedded within the device 300 will now be described in more detail. Specifically, the packaged power amplifier device 300 includes an RF signal input lead 304 (e.g., Figure 1 , 2 RF input lead 104), a driver amplifier path including a driver amplifier die 314 (e.g., Figure 1 , 2 die 114), a carrier amplifier path including a carrier amplifier die 332 (e.g., Figure 1 , 2 die 132), a peak amplifier path 350 including a peak amplifier die 352 (e.g., Figure 1 , 2 die 152), an output combinational network 370 (e.g., Figure 2 network 270), a combinational node 376 (e.g., Figure 2 combinational node 276), components associated with input and output impedance matching circuits, and an RF signal output lead 308 (e.g., Figure 1 , 2 RF output lead 108).

[0132] The lead 304 serves as the RF input lead of the device 300. According to an embodiment, the lead 304 is coupled to an RF signal input pad (not numbered) at the mounting surface 384 of the device substrate 383. Through one or more conductive structures (e.g., vias, traces, and / or bond wires) of the substrate 383, the RF input lead 304 is electrically coupled to the input terminal 315 (e.g., the gate terminal) of the driver amplifier die 314 through the driver input matching circuit 313 (e.g., Figure 1 , 2 's circuit 113), a conductive pad (not numbered) at the mounting surface 384, and a conductive connection (e.g., a bond wire, not numbered). Although not shown in detail, the input impedance matching circuit 313 may include multiple components to implement, for example, a portion of a low-pass or band-pass filter in the form of a T-matching network or a π-matching network. The multiple impedance matching circuit components may include, for example, various inductors, capacitors, and / or resistors in the form of discrete components mounted to the mounting surface 384 of the device substrate 314. Alternatively, some or all of the multiple impedance matching components may be incorporated into an integrated passive device (IPD) coupled to the mounting surface 384. Regardless of the implementation, the driver input matching circuit 313 is configured to transform the gate impedance of the power transistor within the die 314 to a more desirable system-level impedance (e.g., 50 ohms).

[0133] The driver amplifier die 314 is configured to amplify the input RF signal received from the input matching circuit 313 to produce a pre-amplified RF signal at the output terminal 316 (e.g., the drain terminal) of the driver amplifier die 314. Using terms associated with an FET, the driver amplifier die 314 includes a power transistor having a gate terminal electrically coupled to the input terminal 315, a drain terminal electrically coupled to the output terminal 316, and a source terminal electrically coupled to a conductive layer (not numbered) on the bottom surface of the die 314. Since the conductive layer is connected to the first heat sink structure 361, which in turn may be coupled to the system ground, the conductive layer on the bottom surface of the die 314 can provide a ground node for the source terminal.

[0134] The driver output matching circuit 317 (e.g., Figure 1 , 2 's circuit 117) is coupled to the output terminal 316 of the driver amplifier die 314 through a conductive connection (e.g., a bond wire, not numbered) and a conductive pad (not numbered) at the mounting surface 384 of the device substrate 383. Additionally, the driver output matching circuit 317 is coupled to the driver output terminal 305, which in turn is coupled to a power divider (e.g., Figure 1 , 2 's substrate 180) when the device 300 is coupled to an amplifier substrate (e.g., Figure 1 ,2 input (e.g., of the distributor 120) Figure 1 , 2 input 121). Similar to the matching circuit 313, the driver output matching circuit 317 can include a plurality of components in the form of discrete components (e.g., inductors, capacitors, and / or resistors) and / or an IPD mounted to the mounting surface 384 of the device substrate 383. The driver output matching circuit 317 and the driver output terminal 305 are configured to perform a partial impedance transformation between the output terminal 316 of the driver amplifier die 314 and a power distributor (e.g., Figure 1 , 2 power distributor 120).

[0135] As discussed above, during operation of the device 300, the pre-amplified signal generated by the driver amplifier die 114 is passed out of the device 300 (and onto the amplifier substrate) through the driver output terminal 305. On the amplifier substrate (e.g., Figure 1 , 2 substrate 180), the remainder of the impedance transformation can be performed by a driver input matching circuit (e.g., Figure 1 , 2 circuit 118). The overall impedance transformation between the driver output terminal 316 and the power distributor input (e.g., Figure 7 input 121) will be discussed in more detail in connection with Figure 1 , 2 .

[0136] On the amplifier substrate (e.g., Figure 1 , 2 substrate 183), the power of the pre-amplified signal is divided into a carrier signal and a peak signal by a power distributor (e.g., Figure 1 , 2 power distributor 120). The carrier signal and the peak signal provided at the power distributor output (e.g., Figure 1 , 2 outputs 122, 123) are provided to the carrier input terminal 306 and the peak input terminal 307 of the device 300 (e.g., Figure 1 , 2 terminals 106, 107).

[0137] The carrier amplifier path 330 (e.g., Figure 1 , 2 carrier amplifier path 130) is coupled to the carrier input terminal 306. The carrier amplifier path 330 includes a first carrier input matching circuit 327 and a second carrier input matching circuit 331 (e.g., Figure 1 , 2circuit 127, 131), and a power transistor integrated within carrier amplifier die 332. Carrier input matching circuits 327, 331 are coupled between carrier input terminal 306 (e.g., Figure 1 , 2 terminal 106 of) and input terminal 338 (e.g., the gate terminal) of carrier amplifier die 332. According to an embodiment, the first carrier input matching circuit 327 is implemented using a plurality of components in the form of discrete components (e.g., inductors, capacitors, and / or resistors) and / or an IPD coupled to mounting surface 384 of device substrate 383, and the second carrier input matching circuit 331 is implemented using various inductive connections (e.g., bond wires) and additional components integrally formed within a carrier IPD mounted to heat sink structure 362. In an alternative embodiment, carrier amplifier die 332 may be mounted on heat sink structure 362, and the carrier IPD may be coupled to mounting surface 384 of device substrate 383.

[0138] Regardless of the implementation, carrier input terminal 306 and carrier input matching circuits 327, 331 are configured to transform the impedance between an output (e.g., Figure 1 , 2 output 122 of) of a splitter (e.g., Figure 1 , 2 splitter 120 of) and input terminal 338 of carrier amplifier die 332. A phase shift circuit (e.g., Figure 1 , 2 circuit 124 of) on an amplifier substrate (e.g., Figure 1 , 2 substrate 180 of) allows the phase of a pre-amplified carrier signal to be tuned as needed for modification. The overall impedance transformation between the power splitter output and input terminal 338 of carrier amplifier die 332 will be discussed in more detail later in connection with Figure 8 .

[0139] Carrier amplifier die 332 is configured to receive, at input terminal 338, a first output (e.g., Figure 1 , 2 output 122 of) of a power splitter (e.g., Figure 1 , 2The pre-amplified carrier signal generated at the output 122) and is configured to amplify the pre-amplified carrier signal to generate an amplified carrier signal at the output terminal 339 of the carrier amplifier die 332. Using terms associated with FETs, the carrier amplifier die 332 includes a power transistor having a gate terminal electrically coupled to the input terminal 338, a drain terminal electrically coupled to the output terminal 339, and a source terminal electrically coupled to a conductive layer (not numbered) on the bottom surface of the die 332. Since the conductive layer is connected to the second heat sink structure 362, which in turn can be coupled to ground, the conductive layer on the bottom surface of the die 332 can provide a ground node for the source terminal.

[0140] The peak amplifier path 350 (e.g., Figure 1 , 2 the peak amplifier path 150) is coupled to the peak input terminal 307. The peak amplifier path 350 includes a first peak input matching circuit 328 and a second peak input matching circuit 351 (e.g., Figure 1 , 2 circuits 128, 151) and a power transistor integrated within the peak amplifier die 352. The peak input matching circuits 328, 351 are coupled between the peak input terminal 307 (e.g., Figure 1 , 2 terminal 107) and the input terminal 358 (e.g., gate terminal) of the peak amplifier die 352. According to an embodiment, the first peak input matching circuit 328 is implemented using a plurality of components in the form of discrete components (e.g., inductors, capacitors, and / or resistors) and / or an IPD coupled to the mounting surface 384 of the device substrate 383, and the second peak input matching circuit 351 is implemented using various inductive connectors (e.g., bond wires) and additional components integrally formed within the peak IPD mounted to the heat sink structure 361. In an alternative embodiment, the peak amplifier die 352 can be mounted on the heat sink structure 361, and the peak IPD can be coupled to the mounting surface 384 of the device substrate 383.

[0141] Regardless of the implementation, the peak input terminal 307 and the peak input matching circuits 328, 351 are configured to transform the impedance between the second output of a splitter (e.g., Figure 1 , 2 splitter 120) and the input terminal 358 of the peak amplifier die 352. A phase shift circuit (e.g., Figure 1 , 2 output 123) and the input terminal 358 of the peak amplifier die 352. An amplifier substrate (e.g., Figure 1 , 2 substrate 180) Figure 1 , 2The circuit 126) allows tuning the phase of the pre - amplified peak signal to be modified as needed. This will be discussed in more detail later in connection with Figure 8 the overall impedance transformation between the output of the power splitter and the input terminal 358 of the peak amplifier die 352.

[0142] The peak amplifier die 352 is configured to receive, at the input terminal 358, the pre - amplified peak signal generated at the second output (e.g., Figure 1 , 2 of the power splitter 120) (e.g., Figure 1 , 2 output 123), and is configured to amplify the pre - amplified peak signal to generate an amplified peak signal at the output terminal 359 of the peak amplifier die 352. Using terms associated with FETs, the peak amplifier die 352 includes a power transistor having a gate terminal electrically coupled to the input terminal 358, a drain terminal electrically coupled to the output terminal 359, and a source terminal electrically coupled to a conductive layer (not numbered) on the bottom surface of the die 352. Since the conductive layer is connected to the first heat sink structure 361, which in turn can be coupled to ground, the conductive layer on the bottom surface of the die 352 can provide a ground node for the source terminal.

[0143] The output terminals 339, 359 of the carrier amplifier die 332 and the peak amplifier die 352 are coupled to a power combining node 376 (e.g., Figure 2 network 270) through an output combining network 370 (e.g., Figure 1 , 2 node 176). According to an embodiment, the first part of the output combining network 370 is coupled between the output terminal 339 of the carrier amplifier die 332 and the combining node 376, and the second part of the output combining network 370 is coupled between the output terminal 359 of the peak amplifier die 352 and the combining node 376.

[0144] The first part of the output combining network 370 includes a plurality of elements configured to apply a phase shift of approximately 90 degrees to the amplified carrier signal between the output lead 339 of the carrier amplifier die 332 and the power combining node 376. In other words, the total electrical length of the first part of the output combining network 370 can be approximately lambda / 4 (λ / 4) (i.e., approximately 90 degrees) at the fundamental operating frequency f0 of the amplifier. Thus, the output combining network 370 is configured to apply a relative phase shift of approximately 90 degrees to the amplified carrier signal between the output lead 339 and the power combining node 376 at the fundamental frequency.

[0145] In one or more embodiments, a first portion of the output combining network 370 includes a first interconnect 371 (e.g., a bond wire array) and a first transmission line 372 having a first end and a second end. In the illustrated embodiment, the first interconnect 371 is coupled between the output 339 of the carrier amplifier die 332 and the first end of the first transmission line 372.

[0146] Conversely, a second portion of the output combining network 370 includes a plurality of elements configured to apply a phase shift of approximately 180 degrees to the amplified peak signal between the output lead 359 of the peak amplifier die 352 and the power combining node 376. In other words, the total electrical length of the second portion of the output combining network 370 can be approximately lambda / 2 (λ / 2) (i.e., approximately 180 degrees) at the fundamental operating frequency f0 of the amplifier. Thus, the output combining network 370 is configured to apply a relative phase shift of approximately 180 degrees to the amplified peak signal between the output lead 359 and the power combining node 376 at the fundamental frequency.

[0147] In one or more embodiments, a second portion of the output combining network 370 includes a second interconnect 374 (e.g., a bond wire array) and a second transmission line 373 having a first end and a second end. In the illustrated embodiment, the second interconnect 374 is coupled between the output 359 of the peak amplifier die 352 and the first end of the second transmission line 373. The second end of the second transmission line 373 is coupled to the second end of the first transmission line 372. The intersection of the ends of the first transmission line 372 and the second transmission line 373 corresponds to the power combining node 376. During operation of the device 300, the amplified carrier signal and the amplified peak signal are combined in phase at the power combining node 376.

[0148] The power combining node 376 is electrically coupled to the device output 308 (e.g., Figure 1 、 2 end 108). When the device 300 is coupled to an amplifier substrate (e.g., Figure 1 、 2 substrate 180), the device output 308 is coupled to the proximal end of an output impedance transformer (e.g., Figure 1 、 2 output impedance transformer 178), and the distal end of the output impedance transformer is coupled to an RF output (e.g., Figure 1 、 2 RF output 102). As previously discussed, the output impedance transformer 178 is used to present an appropriate load impedance to each of the carrier amplifier die 332 and the peak amplifier die 352. The resulting amplified RF output signal is generated at the RF output.

[0149] As previously combined with Figure 1, 2 As discussed, the driver amplifier die 314 can be biased to operate in class AB mode. Additionally, to achieve proper Doherty operation, the carrier amplifier die 332 can be biased to operate in class AB mode, and the peak amplifier die 352 can be biased to operate in class C mode. To achieve this biasing, multiple gate bias voltages and drain bias voltages can be provided by an external bias voltage source. According to an embodiment, the gate bias voltage and drain bias voltage of the driver amplifier die 314 are provided through leads 304 and 305, respectively. The gate bias voltage and drain bias voltage of the carrier amplifier die 332 are provided through leads 309 and 310, respectively. Finally, the gate bias voltage and drain bias voltage of the peak amplifier die 352 are provided through leads 311 and 312, respectively. Additionally, although Figure 3-5 not shown in

[0150] and as previously mentioned, additional circuitry (e.g., harmonic termination circuitry) can be included in the packaged power amplifier device 300 at the input and / or output of the carrier amplifier die 332 and the peak amplifier die 352.

[0150] As discussed in connection with Figure 1-5 the packaged power amplifier device 300 can be coupled to an amplifier substrate (e.g., Figure 1 , 2 the amplifier substrate 180). Figure 6 is a top view of a physical implementation of a power amplifier system 600 according to an example embodiment, the power amplifier system 600 having a Figure 3 packaged power amplifier device 300 and a power divider 620 (e.g., Figure 1 , 2 the power divider 120), an output impedance transformer 678 (e.g., Figure 1 , 2 the output impedance transformer 178) and other amplifier features mounted on a mounting surface of an amplifier substrate 680.

[0151] According to one or more embodiments, the packaged power amplifier device 300 is mounted on the amplifier substrate 680 by first applying a conductive attachment material (e.g., Figure 3 ) to the exposed distal ends of leads 302, 304 - 312 ( Figure 4 , 5 the material 399, such as solder balls, solder paste or a conductive adhesive). Next, the device 300 is oriented such that the top device surface (e.g., Figure 4 , Figure 5 the top surface 381) faces the mounting surface of the amplifier substrate 680, and the device leads 302, 304 - 312 ( Figure 3 ​​​​​​​) The distal end of which is aligned with corresponding bonding pads (e.g., Figure 6 's bonding pads 604 - 607) on the mounting surface of the amplifier substrate 680. Then, the distal ends of the device leads 302, 304 - 312 ( Figure 3 ) are attached to the bonding pads with a conductive attachment material. In this orientation, the heat sink structure 360 of the device 300 faces outward. As will be described later in connection with Figure 9 , this allows the heat generated by the die within the device 300 to be removed through the top of the device 300. This is referred to as "top - side cooling" of the device 300.

[0152] As previously indicated, the amplifier substrate 680 can include, for example, a PCB or other suitable substrate. The amplifier input terminal 601 (e.g., Figure 1 , 2 's input terminal 101) and the amplifier output terminal 602 (e.g., Figure 1 , 2 's output terminal 102) are coupled to the amplifier substrate 680. When incorporated into a larger RF system, the amplifier input terminal 601 is coupled to an RF signal source, and the amplifier output terminal 602 is coupled to a load (e.g., Figure 1 , 2 's load 190). The RF signal source provides an input RF signal, which is an analog signal that includes spectral energy typically centered around one or more carrier frequencies. Basically, the power amplifier system 600 is configured to amplify the input RF signal received at the amplifier input terminal 601 and generate an amplified output RF signal at the amplifier output terminal 602.

[0153] According to an embodiment, the input RF signal received at the amplifier input terminal 601 is transmitted through a first impedance - matching circuit 610 (e.g., Figure 1 , 2 's circuit 110) on the amplifier substrate 680 to the substrate bonding pad 604, to which the device input leads (e.g., Figure 1-3 's leads 104, 304) of the packaged power amplifier device 300 are coupled. As described in detail above, the input RF signal then passes through a driver amplifier (e.g., including Figure 3 's driver amplifier die 314) within the packaged power amplifier device 300 and is amplified. The driver amplifier corresponds to the first amplifier stage of the amplifier system 600.

[0154] The driver amplifier die generates a pre - amplified RF signal, which passes through a driver output impedance - matching circuit (e.g., Figure 1-3The circuits 117, 317) are transmitted to the driver output leads (e.g., Figure 1-3 the leads 105, 305) of the packaged power amplifier device 300.

[0155] The driver output leads (e.g., Figure 1-3 the leads 105, 305) are coupled to another substrate bonding pad 605 on the amplifier substrate 680. Now returning to the amplifier substrate 680, the pre-amplified RF signal is transmitted through an additional impedance matching circuit 618 (e.g., Figure 1 the circuit 118) on the amplifier substrate 380 to the input 621 (e.g., Figure 1 、 2 the input 121) of the power divider 620 (e.g., Figure 1 、 2 the divider 120).

[0156] According to one or more embodiments, in the Figure 7 schematic diagram, the output terminal of the driver amplifier die (e.g., Figure 3 the terminal 316 of the die 314) and the input 621 of the power divider 620 (e.g., Figure 1 、 Figure 2 the input 121 of the divider 120) are modeled for the overall impedance matching circuit therebetween. As described above, the overall impedance matching circuit includes a driver output impedance matching circuit 317 ( Figure 3 ) coupled between the output terminal 316 ( Figure 3 ) of the driver amplifier die 314 ( Figure 3 ) and the driver output terminal 305 of the device 300 ( Figure 3 ). According to an embodiment, and also as Figure 3 shown, the driver output impedance matching circuit 317 includes a plurality of serially coupled inductors associated with the bond wires coupled to the output terminal 316, and a series of conductive trace segments between these bond wires and the driver output terminal 305. Additionally, the driver output impedance matching circuit 317 may include one or more shunt capacitors and / or other passive components.

[0157] The overall impedance matching circuit further includes a series inductor associated with the driver output terminal 305. According to an embodiment, the inductance value of the driver output terminal 305 may be in the range of about 0.25 nanohenries (nH) to about 0.75 nH, but the inductance may also be smaller or larger.

[0158] Still further, the overall impedance matching circuit further includes an additional impedance matching circuit 618 (e.g., Figure 1 、 2circuit 118). Also as Figure 6 shown, the additional impedance matching circuit 618 includes a plurality of inductors coupled in series associated with a bond pad 605 to which the driver output 305 is coupled ( Figure 6 ), and a series of conductive transmission segments (schematically represented by inductors in Figure 7 ) between the driver output 305 and the input 621 of the power divider 620 on the amplifier substrate 680. Additionally, the additional impedance matching circuit 618 may include one or more series and / or shunt capacitors and / or other passive components.

[0159] Referring again to Figure 6 , the power divider 620 is configured to divide the pre-amplified RF signal received at the input 621 into a first pre-amplified RF signal and a second pre-amplified RF signal (or a carrier signal and a peak signal), the first pre-amplified RF signal and the second pre-amplified RF signal being provided at the power divider outputs 622, 623 (e.g., Figure 1 , 2 outputs 122, 123) respectively. As previously discussed, the power divider 620 is configured to impose a phase difference (e.g., a phase difference of about 90 degrees) between the first pre-amplified RF signal and the second pre-amplified RF signal. In such embodiments, at the outputs 622 and 623, the carrier signal and the peak signal may be out of phase with each other by about 90 degrees.

[0160] The outputs 622, 623 of the power divider 620 are connected to the substrate bond pads 606 and 607 on the amplifier substrate 680 through phase shift circuits 624, 626 (e.g., Figure 1 , 2 circuits 124, 126) on the amplifier substrate 680. The substrate bond pads 606, 607 are in turn coupled to the carrier input leads (e.g., Figure 1-3 leads 106, 306) and the peak input leads (e.g., Figure 1-3 leads 107, 307) of the packaged power amplifier device 300.

[0161] Now returning to within the packaged power amplifier device 300, the carrier input lead is coupled to a carrier amplifier path (e.g., Figure 1-3 paths 130, 330), and the peak input lead is coupled to a peak amplifier path (e.g., Figure 1-3 paths 150, 350). As previously described, the carrier amplifier and the peak amplifier correspond to the second stage of the power amplifier 600.

[0162] Along the carrier amplifier path, the carrier signal passes through one or more impedance matching circuits (e.g., Figure 1-3The circuits 127, 131, 327, 331) are transmitted from the carrier input leads (e.g., Figure 1-3 the leads 106, 306) to the input terminals (e.g., Figure 1-3 the die 132, 332) of the carrier amplifier die (e.g., Figure 1-3 the terminals 138, 338). Similarly, along the peak amplifier path, the peak signal passes through one or more impedance matching circuits (e.g., Figure 1-3 the circuits 128, 151, 328, 351) from the peak input leads (e.g., Figure 1-3 the leads 107, 307) to the input terminals (e.g., Figure 1-3 the die 152, 352) of the peak amplifier die (e.g., Figure 1-3 the terminals 158, 358).

[0163] According to one or more embodiments, in the Figure 8 schematic diagram, the overall impedance matching circuit between the outputs 622, 623 of the power divider 620 (e.g., Figure 1 , 2 the outputs 122, 123 of the divider 120) and the input terminals of the carrier amplifier die and the peak amplifier die (e.g., Figure 1-3 the terminals 138, 158, 338, 358 of the die 132, 152, 332, 352) is modeled. As described above, the overall impedance matching circuit for the carrier amplifier path includes a first phase shift circuit 627 (e.g., Figure 1 , 2 the circuit 127), and the first phase shift circuit 627 is coupled between the first output 622 of the power divider 620 (e.g., Figure 1 , 2 the output 122) and the carrier input terminal 306 ( Figure 3 ). Also as Figure 6 shown, the first phase shift circuit 627 includes two shunt capacitors separated by a series impedance. Impedance matching is further achieved by additional series inductors and capacitors and the inductance associated with the bond pad 606 to which the carrier input terminal 306 is coupled (not shown separately). At least some of the series-coupled inductors can correspond to the conductive transmission segments on the amplifier substrate 680 between the power divider output 622 and the carrier input terminal 306 (schematically represented by inductance in Figure 8 ).

[0164] The overall impedance matching circuit for the carrier amplifier path also includes a series inductor associated with the carrier input terminal 306. According to an embodiment, the inductance value of the carrier input terminal 306 can be in the range of about 0.25 nH to about 0.75 nH, but the inductance can also be smaller or larger.

[0165] Additionally, the overall impedance matching circuit for the carrier amplifier path includes a first carrier input impedance matching circuit 327 and a second carrier input impedance matching circuit 331( Figure 3 ) coupled between the carrier input 306 and the input 338( Figure 3 ) of the carrier amplifier die 332( Figure 3 ). According to an embodiment, and as also Figure 3 shown, the first carrier input impedance matching circuit 327 includes a plurality of serially coupled inductors associated with a series of conductive trace segments between the carrier input 306 and the second carrier input impedance matching circuit 331. Additionally, the first carrier input impedance matching circuit 327 may include one or more shunt capacitors and / or other passive components. As previously discussed, the second carrier input impedance matching circuit 331 may include inductors associated with various bond wires and inductors and capacitors associated with components integrated on the IPD.

[0166] The overall impedance matching circuit for the peak amplifier path may be substantially similar to the overall impedance matching circuit for the carrier amplifier path. Briefly, and as described above, the overall impedance matching circuit for the peak amplifier path includes a second phase shift circuit 628 (e.g., Figure 1 , 2 circuit 128), the second phase shift circuit 628 being coupled between the second output 623 of the power divider 620 (e.g., Figure 1 , 2 output 123) and the peak input 307( Figure 3 ). Also as Figure 6 shown, the second phase shift circuit 628 includes two shunt capacitors separated by a series impedance. Impedance matching is further achieved by additional series inductors and capacitors and an inductor (not shown separately) associated with the bond pad 607 to which the peak input 307 is coupled. At least some of the serially coupled inductors may correspond to conductive transmission segments on the amplifier substrate 680 between the power divider output 623 and the peak input 307 (schematically represented by an inductor in Figure 8 ).

[0167] The overall impedance matching circuit for the peak amplifier path further includes a series inductor associated with the peak input 307. According to an embodiment, the inductance value of the peak input 307 may be in the range of about 0.25 nH to about 0.75 nH, but the inductance may also be smaller or larger.

[0168] Additionally, the overall impedance matching circuit for the peak amplifier path includes a first peak input impedance matching circuit 357 and a second peak input impedance matching circuit 361( Figure 3 ) coupled between the peak input 307 and the input 358(Figure 3 ) between the first peak input impedance matching circuit 328 and the second peak input impedance matching circuit 351( Figure 3 ). According to an embodiment, and as also Figure 3 shown, the first peak input impedance matching circuit 328 includes a plurality of serially coupled inductors associated with a series of conductive trace segments between the peak input terminal 307 and the second peak input impedance matching circuit 351. Additionally, the first peak input impedance matching circuit 328 may include one or more shunt capacitors and / or other passive components. As previously discussed, the second peak input impedance matching circuit 351 may include inductors associated with various bond wires and inductors and capacitors associated with components integrated on the IPD.

[0169] Within the device 300, the carrier signal and the peak signal are amplified (by Figure 1-3 the carrier die 132, 332 and the peak die 152, 352), combined (at Figure 1-3 the combination nodes 176, 276, 376), and transmitted through RF signal output leads (e.g., Figure 1-3 the leads 108, 308). Referring again to Figure 6 , the RF signal output lead is coupled to the bond pad 608, which in turn is coupled to the amplifier output terminal 602 through an output impedance transformer 678 (e.g., Figure 1 , 2 the output impedance transformer 178).

[0170] In addition to the various features discussed above, the power amplifier system 600 may further include a plurality of additional terminals 611, 612, 613, 614, 615, 616 on the amplifier substrate 680, which are configured to receive the driver amplifier gate bias voltage and the driver amplifier drain bias voltage, the carrier amplifier gate bias voltage and the carrier amplifier drain bias voltage, and the peak amplifier gate bias voltage and the peak amplifier drain bias voltage, respectively. These terminals 611 - 616 are coupled to additional substrate bond pads through additional traces and bias circuitry on the amplifier substrate 680, which in turn are connected to the bias terminals of the packaged power amplifier device 300 (e.g., Figure 1-3 the terminals 109, 304, 305, 309 - 312).

[0171] Now referring to Figure 9 , there is shown Figure 6Cross-sectional side view of power amplifier system 600 along line 9-9. As described above and in accordance with one or more embodiments, the encapsulated power amplifier device 300 may be mounted on the amplifier substrate 680 in an orientation with the top device surface 381 facing the mounting surface of the amplifier substrate 680 to effect "top-side cooling" of the device 300.

[0172] To connect the device 300 to the amplifier substrate 680, each of the ends 302 of the device 300 is aligned with and contacted to a corresponding pad 902 on the mounting surface 909 of the amplifier substrate 680. Then, the conductive attachment material 392 is reflowed or otherwise cured to physically connect the device end 302 to its corresponding pad 902 on the mounting surface 909 of the amplifier substrate 680. In other embodiments, the conductive attachment material is additionally or alternatively disposed on the conductive pads 902 of the amplifier substrate 680, and an appropriate reflow or curing process may be performed to connect the device 300 to the amplifier substrate 680.

[0173] In this orientation, the bottom surface of the heat sink structure 360 of the device 300 faces upward and outward. This allows the heat generated by the die 314, 332, 352 within the device 300 and absorbed by the heat sink structure 360 (including structures 361, 362) to be removed through the top of the system 600. Similarly, this is referred to as "top-side cooling" of the device 300. The top-side cooling topology described and illustrated herein can have significant benefits associated with heat dissipation, as this topology allows the heat generated by both the driver-stage amplifier die (e.g., die 314) and the final-stage carrier amplifier die and final-stage peak amplifier die (e.g., die 332, 352) to be removed through the same heat sink structure, which may not be feasible in a discrete solution where the driver-stage amplifier die is not integrated in the manner described and depicted herein.

[0174] More specifically, the heat sink 916 may be physically and thermally coupled to the upward-facing surface of the encapsulated power amplifier device 300, and specifically to the upward-facing surface of the heat sink structure 360. The heat sink 916 is formed of a thermally conductive material, which may also be conductive. For example, the heat sink 916 may be formed of copper or another bulk conductive material. To couple the heat sink 916 to the encapsulated power amplifier device 300, a thermally conductive material 998 (e.g., thermal grease) may be dispensed on the exposed surface of the heat sink structure 360 (or on the surfaces of structures 361, 362) and / or on the heat sink 916, and the heat sink 916 may be brought into contact with the surface of the heat sink structure 360. Then, the heat sink 916 may be clamped, screwed, or otherwise secured in place.

[0175] During operation of the power amplifier system 600, an input RF signal is provided through the RF input 601 of the amplifier substrate 680 ( Figure 6 ) and then through the RF input 304 of the packaged power amplifier device 300 ( Figure 3 ). As previously discussed, the input RF signal is then amplified. An amplified output RF signal is generated at the output 308 ( Figure 3 ), which is electrically coupled to the RF output 602 on the amplifier substrate 680.

[0176] During operation, a significant amount of heat energy (heat) can be generated by the power transistors within the power transistor die 314, 332, 352. As indicated by arrow 999, the heat energy generated by the power transistor die is transferred to the heat sink 916 through the heat dissipation structure 360 (including Figure 3-5 structures 361, 362), and the heat sink 916 effectively dissipates the heat to the ambient atmosphere. Thus, the heat dissipation structure 360 (including Figure 3-5 structures 361, 362) transfers the heat generated by the power transistor die 314, 332, 352 to the heat sink 916.

[0177] Figure 10 is a cross-sectional side view of an amplifier system 1000 according to another exemplary embodiment, the amplifier system 1000 including a Figure 3-5 package power amplifier device 300 alternative embodiment coupled to the system substrate 1080 and the heat sink 1016. Specifically, the power amplifier 300' differs from the power amplifier 300 in that the power amplifier 300' does not include leads 302, 304 - 312 coupled to the mounting surface of the device substrate 383. Instead, the packaged power amplifier device 300' includes RF input, output, and other terminals 302' exposed at the bottom surface 385 of the modified device substrate 383'. The RF input and output terminals 302' are electrically coupled to the power amplifier die 314, 332, 352 of the device 300' through patterned conductive layers of the device substrate 383'. Except for the configuration of the input, output, and other terminals 302', the other components of the packaged power amplifier device 300' can be substantially the same as the components of the packaged power amplifier device 300, and the details described above in connection with Figure 3-5 apply equally to the device 300'.

[0178] Amplifier system 1000 generally includes an amplifier substrate 1080, a packaged power amplifier device 300', and a heat sink 1016. According to an embodiment, the amplifier substrate 1080 includes a multi-layer PCB or other suitable substrate. The amplifier substrate 1080 has a mounting surface 1009 and an opposite bottom surface. The amplifier substrate 1080 also includes a plurality of dielectric layers (e.g., formed of FR-4, ceramic, or other PCB dielectric material) alternating with a plurality of conductive layers.

[0179] The packaged power amplifier device 300' is coupled to the mounting surface 1009 of the amplifier substrate 1080 in an orientation Figure 4 identical to 5 the depicted orientation. More specifically, the device 300' is coupled to the amplifier substrate 1080 such that the lower surface of the device substrate 383' and the mounting surface 1009 of the amplifier substrate 1080 face each other. To connect the device 300' to the amplifier substrate 1080, each of the ends 302' of the device 300' is aligned with and contacted to a corresponding pad 1002 on the mounting surface 1009 of the amplifier substrate 1080. Then, the conductive attachment material 392 is reflowed or otherwise cured to physically connect the device end 302' to its corresponding pad 1002 on the mounting surface 1009 of the amplifier substrate 1080. In other embodiments, the conductive attachment material is additionally or alternatively disposed on the conductive pads 1002 of the amplifier substrate 1080, and an appropriate reflow or curing process may be performed to connect the device 300' to the amplifier substrate 1080.

[0180] According to one embodiment, the heat sink 1016 is embedded in the amplifier substrate 1080, and when the device 300' is coupled to the amplifier substrate 1080, the heat sink 1016 is physically and thermally coupled to the bottom surface 385 of the packaged power amplifier device 300', and more specifically to the exposed surface of the embedded heat sink structure 360 (including structures 361, 362) of the device 300'. The heat sink 1016 is formed of a thermally conductive material, which may also be conductive. For example, the heat sink 1016 may be formed of copper or another bulk conductive material. To couple the heat sink 1016 to the packaged power amplifier device 300', a thermally conductive material 1098 (e.g., thermal grease) may be dispensed on the surface of the heat sink structure 360 (or the surface of structures 361, 362) and / or on the heat sink 1016, and the heat sink 1016 may be brought into contact with the device 300'.

[0181] During operation of the power amplifier system 1000, an input RF signal is provided through an RF input of the amplifier substrate 1080 (not shown) and then through an RF input of the packaged power amplifier device 300' (one of the terminals 302', not shown). As previously discussed, the input RF signal is then amplified. An amplified output RF signal is generated at an RF output of the packaged power amplifier device 300' (the other of the terminals 302', not shown), which is electrically coupled to an RF output on the amplifier substrate 1080 (not shown).

[0182] Also during operation, a large amount of thermal energy (heat) can be generated by the power transistors within the power transistor dies 314, 332, 352. As indicated by arrow 1099, the thermal energy generated by the power transistor dies is transferred to the heat sink 1016 through a heat dissipation structure 360 (including Figure 3-5 structures 361, 362), and the heat sink 1016 effectively dissipates the heat to the bottom of the amplifier substrate 1080 and, through additional heat sinks (not shown), ultimately to the ambient atmosphere. Thus, the heat dissipation structure 360 (including Figure 3-5 structures 361, 362) transfers the heat generated by the power transistor dies 314, 332, 352 to the heat sink 1016. This configuration is referred to as "bottom-side cooling" of the device 300'.

[0183] An embodiment of a packaged semiconductor device includes a device substrate, an interface for signal communication with an external power distributor, and a first stage and a second stage of a multi-stage amplifier. The device substrate has a mounting surface and a bottom surface. The interface for signal communication with the external power distributor includes a first lead, a second lead, and a third lead coupled to the device substrate. The first stage of the multi-stage amplifier includes a first amplifier die having a first input, a first output, and a first power transistor serving as a driver amplifier. The first output is coupled to the first lead. The second stage of the multi-stage amplifier includes a first amplifier path and a second amplifier path. The first amplifier path has a second amplifier die having a second input, a second output, and a second transistor serving as a first final amplifier. The second input is coupled to the second lead. The second amplifier path has a third amplifier die having a third input, a third output, and a third transistor serving as a second final amplifier. The third input is coupled to the third lead.

[0184] An embodiment of a multi-stage multi-path power amplifier includes an amplifier substrate, a packaged semiconductor device, and a power divider. The amplifier substrate has a top substrate surface and a first device interconnect, a second device interconnect, and a third device interconnect at the top substrate surface. The packaged semiconductor device is coupled to the top substrate surface, and the packaged semiconductor device includes a device substrate, an interface for signal communication with the power divider, and a first stage and a second stage of a multi-stage amplifier. The device substrate has a mounting surface and a bottom surface. The interface for signal communication with the power divider includes a first lead, a second lead, and a third lead, the first lead, the second lead, and the third lead being coupled to the device substrate and respectively coupled to the first device interconnect, the second device interconnect, and the third device interconnect. The first stage of the multi-stage amplifier includes a first amplifier die having a first input, a first output, and a first power transistor serving as a driver amplifier. The first output is coupled to the first lead. The second stage of the multi-stage amplifier includes a first amplifier path and a second amplifier path. The first amplifier path has a second amplifier die having a second input, a second output, and a second transistor serving as a first final stage amplifier. The second input is coupled to the second lead. The second amplifier path has a third amplifier die having a third input, a third output, and a third transistor serving as a second final stage amplifier. The third input is coupled to the third lead. The power divider is coupled to the top substrate surface. The power divider has a divider input coupled to the first device interconnect, a first divider output coupled to the second device interconnect, and a second divider output coupled to the third device interconnect. The power divider is configured to receive a first signal characterized by a first signal power at the divider input, provide a first portion of the first signal power at the first divider output, and provide a second portion of the first signal power at the second divider output.

[0185] The foregoing detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as exemplary is not necessarily to be construed as preferred or advantageous over other embodiments. Further, there is no intention to be bound by any theory presented in the foregoing technical field, background, or detailed description.

[0186] The connecting lines shown in the various figures included in this document are intended to represent exemplary functional relationships and / or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in embodiments of the subject matter. In addition, certain terms may be used herein for reference purposes only, and thus these terms are not intended to be restrictive, and unless the context clearly indicates otherwise, the terms "first", "second", and other such numerical terms referring to structures do not imply order or sequence.

[0187] As used herein, "node" means any internal or external reference point, connection point, junction point, signal line, conductive element, etc., at which a given signal, logic level, voltage, data pattern, current, or quantity exists. In addition, two or more than two nodes may be implemented by a single physical element (and although received or output at a common node, two or more signals may still be multiplexed, modulated, or differentiated).

[0188] The foregoing description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise explicitly stated, "connected" means that one element is directly joined to another element (or directly in communication with another element), and not necessarily in a mechanical manner. Similarly, unless otherwise explicitly stated, "coupled" means that one element is directly or indirectly joined to another element (or directly or indirectly in electrical or other communication with another element), and not necessarily in a mechanical manner. Thus, while the schematic diagrams shown in the figures depict an exemplary arrangement of elements, additional intervening elements, devices, features, or components may exist in embodiments of the subject matter being depicted.

[0189] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that there are numerous variations. It should also be understood that the exemplary embodiments described herein are not intended to limit in any way the scope, applicability, or configuration of the claimed subject matter. Indeed, the foregoing detailed description will provide those skilled in the art with a convenient guide for implementing the described embodiments. It should be understood that various changes may be made to the functions and arrangements of the elements without departing from the scope defined by the claims, which include equivalents known at the time of filing this patent application and equivalents that are foreseeable.

Claims

1. A packaged semiconductor device, characterized in that: include: a device substrate having a mounting surface and a bottom surface; an interface for signal communication with an external power distributor, wherein the interface comprises a first lead, a second lead, and a third lead coupled to a substrate of the device; a first stage of a multi-stage amplifier, the first stage comprising a first amplifier die having a first input, a first output, and a first power transistor used as a driver amplifier, wherein the first output is coupled to the first lead; as well as A second stage of a multi-stage amplifier, the second stage comprising: a first amplifier path having a second amplifier die having a second input, a second output, and a second transistor used as a first final amplifier, wherein the second input is coupled to the second lead, and A second amplifier path has a third amplifier die having a third input, a third output, and a third transistor used as a second final amplifier, wherein the third input is coupled to the third lead.

2. The packaged semiconductor device according to claim 1, wherein: Also includes: a first heat dissipation structure extending between the mounting surface and the bottom surface of the device substrate, wherein a first surface of the first heat dissipation structure is exposed at the mounting surface of the device substrate and the second amplifier die is coupled to the first surface of the first heat dissipation structure; as well as A second heat dissipation structure extends between the mounting surface and the bottom surface of the device substrate, wherein a first surface of the second heat dissipation structure is exposed at the mounting surface of the device substrate and the third amplifier die is coupled to the first surface of the second heat dissipation structure.

3. The packaged semiconductor device according to claim 2, wherein: The first amplifier die is also coupled to the first surface of the second heat dissipation structure.

4. The packaged semiconductor device according to claim 1, wherein: The first lead is characterized by a first inductance forming part of a first impedance transformation circuit; The second lead is characterized by a second inductance forming part of a second impedance transformation circuit; and The third lead is characterized by a third inductance forming part of a third impedance transformation circuit.

5. The packaged semiconductor device according to claim 1, wherein: The first lead, the second lead, and the third lead have proximal ends coupled to the mounting surface of the device substrate, and the first lead, the second lead, and the third lead extend vertically from the mounting surface to distal ends of the first lead, the second lead, and the third lead.

6. The packaged semiconductor device according to claim 1, wherein: Also includes: A fourth lead is coupled to the device substrate and to the first input of the first amplifier die.

7. The packaged semiconductor device according to claim 1, wherein: Also includes: at least a portion of a first final input impedance matching circuit coupled between the second lead and the second input of the second amplifier die; as well as At least a portion of a second final stage input impedance matching circuit is coupled between the third lead and the third input of the third amplifier die.

8. The packaged semiconductor device according to claim 1, wherein: The multi-stage amplifier is a Doherty power amplifier, The first amplifier die is a driver amplifier die; The second amplifier die is a carrier amplifier die; and The third amplifier die is a peak amplifier die.

9. The packaged semiconductor device according to claim 1, wherein: The first lead, the second lead and the third lead are selected from conductive pillars, quad flat no-lead (QFN) package leads, gull-wing leads, land grid array (LGA) package leads and ball grid array (BGA) package leads.

10. A multi-stage multi-path power amplifier, characterized in that: include: an amplifier substrate having a top substrate surface and first, second, and third device interconnects at the top substrate surface; a packaged semiconductor device coupled to the top substrate surface, wherein the packaged semiconductor device comprises: a device substrate having a mounting surface and a bottom surface, an interface for signal communication with a power divider, wherein the interface comprises a first lead, a second lead, and a third lead, the first lead, the second lead, and the third lead being coupled to the device substrate and respectively coupled to the first device interconnect, the second device interconnect, and the third device interconnect, a first stage of a multi-stage amplifier, the first stage comprising a first amplifier die having a first input, a first output, and a first power transistor used as a driver amplifier, wherein the first output is coupled to the first lead, and A second stage of a multi-stage amplifier, the second stage comprising: a first amplifier path having a second amplifier die having a second input, a second output, and a second transistor used as a first final amplifier, wherein the second input is coupled to the second lead, and a second amplifier path having a third amplifier die having a third input, a third output, and a third transistor used as a second final amplifier, wherein the third input is coupled to the third lead; and The power divider is coupled to the top substrate surface, wherein the power divider has a divider input coupled to the first device interconnect, a first divider output coupled to the second device interconnect, and a second divider output coupled to the third device interconnect, and wherein the power divider is configured to receive a first signal characterized by a first signal power at the divider input, provide a first portion of the first signal power at the first divider output, and provide a second portion of the first signal power at the second divider output.

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