Class D amplifier and operation method thereof

Abstract

The invention provides a class D amplifier and an operation method thereof, and the class D amplifier comprises a pulse width modulation signal generator which is configured to generate an input signal; a p-type output transistor; and an n-type output transistor connected in series with the p-type output transistor at an output terminal; and an output monitor connected to the output and configured to detect a duty cycle of an output signal at the output. The amplifier comprises a pre-driving circuit which is provided with a first input end, a second input end, a first output end and a second output end. The first input terminal is connected to the PWM signal generator to receive the input signal, the second input terminal is connected to the output monitor to receive the duty cycle, the first output terminal is connected to a gate of the p-type output transistor, and the second output terminal is connected to a gate of the n-type output transistor.

Description

Technical Field

[0001] This application relates to the field of electronic circuits in audio systems, and more particularly to class-D amplifiers and methods of operating the same. More specifically, this application is directed to automatic calibration control of a class-D amplifier driver circuit. Background Art

[0002] A class-D amplifier (also known as a switching amplifier) is an electronic amplifier in which transistors act as binary switches. These switches are either fully on or fully off. Class-D amplifiers employ rail-to-rail output switching, where, ideally, the output transistors of these class-D amplifiers actually always carry zero current or zero voltage. Thus, these class-D amplifiers have extremely low power dissipation and provide high efficiency over a wide range of power levels. The favorable high efficiency of these class-D amplifiers has driven their use in various audio applications from cellular phones to flat screen televisions and home theater receivers. Class-D audio power amplifiers are more efficient than class-AB audio power amplifiers. Because class-D amplifiers are more efficient, they require a smaller power supply and do not require a heat sink, thus significantly reducing the overall system cost, size, and weight. Summary of the Invention

[0003] One general aspect includes a class-D amplifier. The class-D amplifier includes a pulse width modulation (PWM) signal generator configured to generate an input signal. The amplifier also includes a p-type output transistor. The amplifier also includes an n-type output transistor serially connected to the p-type output transistor at an output terminal. The amplifier also includes an output monitor connected to the output terminal and configured to detect a duty cycle of an output signal at the output terminal. The amplifier also includes a pre-driver circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is connected to the PWM signal generator to receive the input signal, the second input terminal is connected to the output monitor to receive the duty cycle of the output signal, the first output terminal is connected to a gate of the p-type output transistor to provide a first gate voltage, and the second output terminal is connected to a gate of the n-type output transistor to provide a second gate voltage.

[0004] Implementations may include one or more of the following features. In some embodiments, the pre-driver circuit determines the first gate voltage and the second gate voltage based on the duty cycle of the output signal. In some embodiments, the first gate voltage and the second gate voltage are complementary to each other.

[0005] In some embodiments, in a first phase, the second gate voltage is at a logic low level and the first gate voltage is at a logic high level.

[0006] In some embodiments, in a second stage, the second gate voltage is increased to a first voltage level close to a threshold voltage of the n-type output transistor. In some embodiments, the first voltage level deviates from the threshold voltage of the n-type output transistor by a value greater than or less than 200 mV. In some embodiments, the pre-drive circuit includes a slew rate controller enabled in the second stage, and a slew rate of the class-D amplifier is adjusted by the slew rate controller in the second stage. In some embodiments, the slew rate controller may include a first current-output digital-to-analog converter (DAC) connected between ground and the n-type output transistor, and an output current at an output terminal of the first current-output DAC is adjusted based on a duty cycle of the output signal. In some embodiments, the output terminal is connected to a source of the n-type output transistor, and a gate-source voltage of the n-type output transistor is adjusted by the output current.

[0007] In some embodiments, in a third stage, the second gate voltage is increased to a second voltage level higher than the first voltage level. In some embodiments, the n-type output transistor is fully turned on at the second voltage level. In some embodiments, the pre-drive circuit includes a bias voltage controller enabled in the third stage, and a bias voltage of the n-type output transistor is adjusted by the bias voltage controller in the third stage. In some embodiments, the bias voltage controller may include a second current-output DAC connected in series with a resistor, and an output current at an output terminal of the second current-output DAC is adjusted based on the duty cycle of the output signal.

[0008] In some embodiments, the output monitor may include a duty cycle detector configured to detect the duty cycle. In some embodiments, the output monitor may further include a steady-state detector, and the steady-state detector is configured to sense the output signal at the output terminal and generate a current signal, and compare the current signal with a reference current. In some embodiments, when the current signal is higher than a reference current, the slew rate controller is deactivated.

[0009] Another general aspect includes a method of operating a class-D amplifier. The method includes receiving an input signal by means of a pulse-width modulation (PWM) signal generator of the class-D amplifier. The method also includes detecting a duty cycle of an output signal at an output terminal of the class-D amplifier by means of an output monitor of the class-D amplifier. The method also includes determining, by means of a pre-drive circuit of the class-D amplifier, a first gate voltage to be applied to a gate of a p-type output transistor based on the duty cycle and the input signal. The method also includes determining, by means of the pre-drive circuit of the class-D amplifier, a second gate voltage to be applied to a gate of an n-type output transistor based on the duty cycle and the input signal. The n-type output transistor is connected in series with the p-type output transistor at the output terminal. The method also includes applying the first gate voltage to the gate of the p-type output transistor. The method also includes applying the second gate voltage to the gate of the n-type output transistor.

[0010] Implementations may include one or more of the following features. In some implementations, in a first stage, the second gate voltage is configured to a logic low level, and the first gate voltage is configured to a logic high level. In some implementations, in a second stage, the second gate voltage is configured to increase to a first voltage level close to a threshold voltage of the n-type output transistor. In some implementations, in a third stage, the second gate voltage is configured to increase to a second voltage level higher than the first voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Aspects of the present application are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or reduced.

[0012] Figure 1A FIG. 12 is a simplified schematic diagram of a class-D amplifier 100 as an existing class-D amplifier.

[0013] Figure 1B FIG. Figure 1A 13 is a waveform diagram showing modulation of signals in the class-D amplifier 100.

[0014] Figure 2 FIG. 14 is a block diagram of a class-D amplifier having an automatic calibration drive circuit according to some embodiments.

[0015] Figure 3 FIG. Figure 2 15 is a diagram showing operation of the class-D amplifier 200 according to some embodiments.

[0016] Figure 4 FIG. 16 is a diagram showing the relationship between the inductor current at the output terminal and the duty cycle according to some embodiments.

[0017] Figure 5 A diagram illustrating the operation of a duty cycle detector according to some embodiments.

[0018] Figure 6 A diagram illustrating an example of a steady state detector according to some embodiments.

[0019] Figure 7 A diagram illustrating an example of a conversion rate controller according to some embodiments.

[0020] Figure 8 A diagram illustrating an example of a bias voltage controller according to some embodiments.

[0021] Figure 9 A diagram illustrating the adaptive gate voltage of a class D amplifier according to some embodiments.

[0022] Figure 10 A diagram illustrating the voltage at the gate terminal in different stages according to some embodiments.

[0023] Figure 11 A flowchart illustrating an example method of operating a class D amplifier according to some embodiments.

[0024] Symbol Explanation

[0025] 100: Class D amplifier; 101: First comparator; 102: Second comparator; 103: Oscillator; 106: First PWM signal; 107: Second PWM signal; 110: Speaker load; 191: Output transistor; 192: Output transistor; 193: Output transistor; 194: Output transistor; 200: Class D amplifier; 210: PWM signal generator; 220: p-type pre-driver circuit; 222: p-type slew rate controller; 224: p-type bias voltage controller; 230: n-type pre-driver circuit; 232: n-type slew rate controller; 234: n-type bias voltage controller; 280: Output monitor; 282: Duty cycle detector; 284: Steady state detector; 290: Output stage; 291: p-type output transistor; 292: n-type output transistor; 402: Duty cycle; 404: Inductor current; 502: Output PWM signal; 504: Counter clock pulse signal; 506: Reset signal; 602: Current mirror; 604: Detector circuit; 606: Output buffer; 702: NAND gate; 704: First inverter; 706: Second inverter; 708: Third inverter; 710: Current output DAC; 810: Current output DAC; 820: Resistor; 1100: Method; 1102: Operation / Step; 1104: Operation / Step; 1106: Operation / Step; 1108: Operation / Step; 1110: Operation / Step; 1112: Operation / Step; DutyCycle_in: Input terminal; GATEN: Terminal; GATEN_in: First input terminal; I1: First input current; I2: Second input current; I3: Third current; I4: Fourth current; IN: Input node; INM: Second audio input signal; INP: First audio input signal; I r : Reference current; L1: Inductor; ND: Node; NDET: Node; OUT: Output terminal; OUTM: First output signal; OUTP: Second output signal; PD: Node; PDET: Node; R1: Resistor; t1: Time; t2: Time; t6: Time; t7: Time; t8: Time; V1: Raised level; V GS : Gate-source voltage; VREF: Triangular wave signal; V t : Threshold voltage. Detailed implementation

[0026] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present application. Of course, these components and configurations are only examples and are not intended to be restrictive. Additionally, the present application may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity purposes and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] In addition, for ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one device or feature depicted in the figure with another device or feature. In addition to the orientation depicted in the figure, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0028] In addition, the source / drain ("S / D") region may refer to the source or the drain individually or jointly depending on the context. For example, a device may include a first source / drain region and a second source / drain region, as well as other components. The first source / drain region may be the source region, and the second source / drain region may be the drain region, or vice versa. Those of ordinary skill in the art should recognize many variations, modifications, and alternatives.

[0029] Some embodiments of the present application are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be replaced or eliminated. For different embodiments, some of the features described below may be replaced or eliminated, and additional features may be added. Although some embodiments are discussed in connection with operations performed in a specific order, these operations may be performed in another logical order.

[0030] A class-D audio power amplifier converts an audio input signal into high-frequency pulses that switch an output transistor according to the audio input signal. Some class-D amplifiers use a pulse width modulator (PWM) to generate a series of modulation pulses whose widths vary according to the amplitude of the audio input signal. The pulses of varying width switch the output transistor at a fixed frequency. Other class-D amplifiers may rely on other types of pulse modulators. The following discussion will mainly refer to the pulse width modulator, but those of ordinary skill in the art should recognize that class-D amplifiers can be configured with other types of modulators.

[0031] As will be discussed in more detail below, the present application is related to improving the slew rate of a class-D amplifier during switching when the class-D amplifier employs a rail-to-rail output voltage swing. The slew rate is the change in voltage (or current) per unit time. The unit of measurement is usually expressed, for example, in volts per microsecond (V / μs). When the output of a given class-D amplifier is given, the slew rate specification guarantees that the output signal will change at a speed of at least a given minimum value or at most a given maximum value. If these limits are violated, some errors may occur and correct operation is no longer guaranteed. As an example, when the input signal of a class-D amplifier is a square wave, the output signal is required to be a corresponding square wave. However, the actual output signal is not an ideal square wave, and the rising edge has a slew rate.

[0032] The disclosed technology can minimize overshoot and undershoot, which reduces the power efficiency of a class-D amplifier. Typically, a class-D amplifier provides a power efficiency of more than 90%. To keep the power efficiency as high as possible, the slew rate of the output transistor gates must be carefully controlled.

[0033] Figure 1A FIG. 6 is a simplified schematic diagram of a class-D amplifier 100 as an existing class-D amplifier. As Figure 1A shown, the class-D amplifier 100 is a differential amplifier. A pair of differential audio input signals INP and INM (i.e., a first audio input signal INP and a second audio input signal INM) are respectively input to a first comparator 101 and a second comparator 102. Each of the pair of differential audio input signals INP and INM is compared with a triangular signal (i.e., a signal having a triangular waveform) VREF generated from an oscillator 103 to respectively generate a first PWM signal 106 and a second PWM signal 107. Since the first audio input signal INP and the second audio input signal INM are differential signals and the same triangular signal VREF is used as a reference signal, the first PWM signal and the second PWM signal 107 are also differential signals (i.e., inverse to each other).

[0034] The first PWM signal 106 is coupled to the gates of output transistors 191 and 192 that are electrically connected together. Thus, the first PWM signal 106 controls the conduction and disconnection of the output transistors 191 and 192. The second PWM signal 107 is coupled to the gates of output transistors 193 and 194 that are electrically connected together. Thus, the second PWM signal 107 controls the conduction and disconnection of the output transistors 193 and 194. Thus, the first output signal OUTM and the second output signal OUTP of the class-D amplifier 100 are also differential output signals. As Figure 1A shown, the first output signal OUTM and the second output signal OUTP are applied to both ends of a speaker load 110, which is represented by an inductor L1 and a resistor R1 in Figure 1A FIG. 6.

[0035] Figure 1B FIG. 7 is a waveform diagram showing the modulation of signals in the class-D amplifier 100 of Figure 1A FIG. 6. As Figure 1B shown, the first audio input signal INP and the second audio input signal INM are compared with the triangular signal VREF, as described above in connection with Figure 1Aand described. The output signals of the first comparator 101 and the second comparator 102 are pulse signals at a fixed frequency (i.e., fixed period), and the pulse widths of these pulse signals are proportional to their corresponding audio input signals. Therefore, the first output signal OUTM and the second output signal OUTP are two PWM signals, as Figure 1B shown.

[0036] Figure 2 FIG. is a block diagram illustrating a class D amplifier 200 having an automatic calibration drive circuit according to some embodiments. Figure 3 FIG. is for illustrating according to some embodiments Figure 2 operation of the class D amplifier 200.

[0037] In Figure 2 the example shown, the output terminal of the class D amplifier 200 (labeled "OUT" in Figure 2 ) is connected to an output load (e.g., a speaker load), such as the load shown in Figure 1A , which is represented by an inductor L1 and a resistor R1.

[0038] In Figure 2 the example shown, the class D amplifier 200 includes a PWM signal generator 210, a p-type pre-drive circuit 220, an n-type pre-drive circuit 230, a p-type output transistor 291, an n-type output transistor 292, and an output monitor 280, as well as other components.

[0039] The p-type output transistor 291 and the n-type output transistor 292 can be regarded as an output stage 290. The p-type output transistor 291 and the n-type output transistor 292 are connected in series between a lower power rail (e.g., ground) and a higher power rail (e.g., V DD ). Compared with other transistors in the class D amplifier 200, the p-type output transistor 291 and the n-type output transistor 292 are characterized by large sizes (e.g., channel length, channel width, etc.) to drive the output load to meet the required power efficiency. Therefore, large parasitic capacitances are associated with the p-type output transistor 291 and the n-type output transistor 292, which will make the conversion rate smaller (i.e., slow down the conversion rate). In one embodiment, the p-type output transistor 291 is a PMOS transistor, and the n-type output transistor 292 is an NMOS transistor. It should be understood that other types of transistors can be used for the p-type output transistor 291 and the n-type output transistor 292. Those of ordinary skill in the art should recognize many variations, modifications, and alternatives.

[0040] The PWM signal generator 210 is at an input node (in Figure 2generate an input signal (labeled as "IN" therein). The PWM signal generator 210 can further generate an input bar signal, which is the complement of the input signal. In one embodiment, the PWM signal generator 210 can include a comparator and an oscillator that generates a triangular wave, as discussed above in connection with Figure 1A and Figure 1B It should be understood that in other embodiments, PWM signal generators of other architectures can be employed.

[0041] The p-type pre-driver circuit 220 and the n-type pre-driver circuit 230 can be regarded as pre-driver circuits connected between the PWM signal generator 210 and the output stage 290. In the example shown in Figure 2 the p-type pre-driver circuit 220 includes a p-type conversion rate controller 222 and a p-type bias voltage controller 224, as well as other components, while the n-type pre-driver circuit 230 includes an n-type conversion rate controller 232 and an n-type bias voltage controller 234, as well as other components.

[0042] The p-type conversion rate controller 222 receives the input signal generated by the PWM signal generator 210 and the feedback signal generated by the output monitor 280, and controls the conversion rate by adjusting the gate voltage of the p-type output transistor 291. Similarly, the n-type conversion rate controller 232 receives the input signal generated by the PWM signal generator 210 and the feedback signal generated by the output monitor 280, and controls the conversion rate by adjusting the gate voltage of the n-type output transistor 292.

[0043] The p-type bias voltage controller 224 receives the input signal generated by the PWM signal generator 210 and the feedback signal generated by the output monitor 280, and adaptively adjusts the bias voltage of the p-type output transistor 291. Similarly, the n-type bias voltage controller 234 receives the input signal generated by the PWM signal generator 210 and the feedback signal generated by the output monitor 280, and adaptively adjusts the bias voltage of the n-type output transistor 292.

[0044] Details of the p-type pre-driver circuit 220 and the n-type pre-driver circuit 230 will be discussed below.

[0045] In Figure 2In the example shown, the output monitor 280 includes a duty cycle detector 282 and a steady state detector 284, among other components. The duty cycle detector 282 is configured to detect the duty cycle of the output signal at the output terminal OUT. The steady state detector 284 is configured to sense the output signal at the output terminal OUT and thus generate a current signal. A comparison between the current signal and a reference current produces an indication of whether the class-D amplifier 200 is in a steady state. Details of the duty cycle detector 282 and the steady state detector 284 will be discussed below.

[0046] Details of the p-type pre-driver circuit 220 and the n-type pre-driver circuit 230 will be discussed below.

[0047] As Figure 2 shown, there is a feedback path from the output terminal OUT through the output monitor 280 to the p-type pre-driver circuit 220 (marked by a dashed line in Figure 2 ). The output monitor 280 senses the output signal at the output terminal OUT and thus generates a feedback signal. There is a corresponding signal path from the PWM signal generator 210 to the p-type pre-driver circuit 220. Then, the p-type pre-driver circuit 220 adaptively adjusts the duty cycle and the bias voltage corresponding to the p-type output transistor 291.

[0048] As Figure 2 shown, there is a feedback path from the output terminal OUT through the output monitor 280 to the n-type pre-driver circuit 230 (marked by a dashed line in Figure 2 ). The output monitor 280 senses the output signal at the output terminal OUT and thus generates a feedback signal. There is a corresponding signal path from the PWM signal generator 210 to the n-type pre-driver circuit 230. Then, the p-type pre-driver circuit 220 adaptively adjusts the duty cycle and the bias voltage corresponding to the n-type output transistor 292.

[0049] As Figure 3 shown, the class-D amplifier 200 operates in three phases. Although Figure 3 shows the gate-source voltage V GS of the n-type output transistor 292, it should be understood that the same principle also applies to the p-type output transistor 291. The gate-source voltage V GS of the p-type output transistor 291 is complementary to the gate-source voltage V GS of the n-type output transistor 292. When the gate-source voltage V GS of the n-type output transistor 292 is at a logic low level, the gate-source voltage V GS of the p-type output transistor 291 is at a logic high level. When the gate-source voltage V GSWhen it is logic high on time, the gate-source voltage V of the p-type output transistor 291 GS is logic low on time.

[0050] In stage 1, the gate-source voltage V of the n-type output transistor 292 GS is 0V (i.e., logic low on time), and the n-type output transistor 292 is turned off. At the same time, the p-type output transistor 291 is turned on.

[0051] In stage 2, the V of the n-type output transistor 292 GS increases to a level close to the threshold voltage V of the n-type output transistor 292 t (i.e., V t ±ΔV, where ±ΔV is the deviation, indicated by the dotted line shown in Figure 3 . In one example, ΔV is 200mV. Of course, in other embodiments, ΔV can be other values. In other words, the V of the n-type output transistor 292 GS deviates from the threshold voltage V of the n-type output transistor 292 by a value of ΔV t . In one example, this value is 200mV. In some examples, this value is less than 200mV. In other examples, this value can be greater than 200mV. Therefore, the n-type output transistor 292 is soft turned on. In stage 2, the switching rate control is turned on (implemented by the n-type switching rate controller 232), while the bias voltage control is turned off (implemented by the n-type bias voltage controller 234). These implementations will be discussed in more detail below.

[0052] In stage 3, the V of the n-type output transistor 292 GS further increases to a level close to the elevated level V1, where the elevated level V1 is higher than the threshold voltage V of the n-type output transistor 292 t . Similarly, the dotted line shown depicts the range close to the elevated level V1. Therefore, the n-type output transistor 292 is completely turned on. In stage 2, the switching rate control is turned off (implemented by the n-type switching rate controller 232), while the bias voltage control is turned on (implemented by the n-type bias voltage controller 234). These implementations will be discussed in more detail below.

[0053] Figure 4 is a graph showing the relationship between the inductor current and the duty cycle at the output terminal according to some embodiments. As Figure 4 shown, the inductor current 404 tracks the duty cycle 402 of the output signal at the output terminal OUT, or vice versa. The inductor current 404 is the current sensed at the output terminal OUT, and can be regarded as, for example, flowing through Figure 1AThe current of inductor L1 of the speaker load 110 shown in. When the inductor current 404 is zero (corresponding to Figure 4 the middle dashed line shown in), the duty cycle 402 is 50%. As the inductor current 404 increases (from zero to Figure 4 a positive value above the dashed line shown in), the duty cycle 402 increases accordingly. As the inductor current 404 decreases (from zero to Figure 4 a negative value below the dashed line shown in), the duty cycle 402 decreases accordingly. Since the duty cycle 402 tracks the inductor current 404, the duty cycle 402 can be used to determine the inductor current 404. This is the operating principle of the duty cycle detector 282.

[0054] Figure 5 is a diagram illustrating the operation of the duty cycle detector 282. In the Figure 5 example shown in, the output PWM signal 502 at the output terminal OUT is in the form of a pulse wave (i.e., a rectangular wave), and the frequency of the output PWM signal 502 is a first frequency (e.g., 500 KHz). The duty cycle detector 282 also includes a counter clock pulse signal generator that generates a counter clock pulse signal 504. In the Figure 5 example shown in, the frequency of the counter clock pulse signal 504 is a second frequency (e.g., 100 MHz). The second frequency is higher than the first frequency. In this example, the second frequency is 200 times higher than the first frequency. It should be noted that in other embodiments, other suitable frequencies can be selected.

[0055] The duty cycle detector 282 counts the number of cycles of the counter clock pulse signal 504 until the reset signal 506 toggles (i.e., the pulse of the reset signal 506 hits). The pulse of the reset signal 506 is aligned with the rising edge of the output PWM signal 502. Thus, when the PWM signal 502 is at the logic low level, the duty cycle detector 282 counts the number of cycles of the counter clock pulse signal 504. Accordingly, the duty cycle 402 is determined.

[0056] In the Figure 5 example shown in, when the count is 200, the duty cycle is 100%; when the count is 150, the duty cycle is 75%; when the count is 100, the duty cycle is 50%; when the count is 50, the duty cycle is 25%.

[0057] Figure 6 is a diagram illustrating an example of the steady state detector 284 according to some embodiments. In the Figure 6 example shown in, the steady state detector 284 includes a current mirror 602, a detector circuit 604, and an output buffer 606, among other components. It should be understood that Figure 6The examples shown are not intended to be restrictive, and in other embodiments, the steady-state detector 284 may have other configurations.

[0058] The current mirror 602 is configured to set a reference current for the detector circuit 604. In some embodiments, the reference current follows the Vbst level, which is the highest output voltage of the class-D amplifier 200. In one example, the Vbst level is approximately 12V. It should be understood that this example is not intended to be restrictive. In one example, the reference current is proportional to the Vbst level. In other words, the reference current changes as the Vbst level changes, and the ratio between them remains constant.

[0059] The detector circuit 604 is connected to Figure 2 the output terminal OUT shown in. The detector circuit 604 senses the output signal to generate a first input current I1 and / or a second input current I2 (based on the logic low level or logic high level of the output signal at the output terminal OUT), as Figure 6 shown in.

[0060] When the output signal at the output terminal OUT is at a logic low level (i.e., "0"), a third current I3 is generated by the detector circuit 604 in response to the first input current I1. The third current I3 is proportional to the first input current I1. When the first input current I1 increases, the third current I3 increases accordingly.

[0061] At Figure 6 the node ND shown in, the third current I3 is compared with the reference current I r generated by the current mirror 602. When the output signal at the output terminal OUT is at a logic low level (i.e., "0") and the third current I3 is greater than the reference current I r , the third current I3 pulls down the output signal, and the signal at the node NDET in the output buffer 606 becomes a logic low level (i.e., "0"). As will be discussed below, the signal at the node NDET is used to control (e.g., by means of an AND gate) the function of the n-type switching rate controller 232. When the third current I3 is greater than the reference current I r , indicating an unstable state, the signal at the node NDET (i.e., the logic low level) deactivates the n-type switching rate controller 232.

[0062] Similarly, when the output signal at the output terminal OUT is at a logic high level (i.e., "1"), a fourth current I4 is generated by the detector circuit 604 in response to the second input current I2. The fourth current I4 is proportional to the second input current I2. When the second input current I2 increases, the fourth current I4 increases accordingly.

[0063] At Figure 6At node PD shown in the figure, the fourth current I4 is compared with the reference current I generated by the current mirror 602. r When the output signal at the output terminal OUT is at the logic high level (i.e., "1") and the fourth current I4 is greater than the reference current I r , the fourth current I4 pulls up the output signal, and the signal at node PDET in the output buffer 606 becomes the logic high level (i.e., "1").

[0064] Figure 7 FIG. is a diagram illustrating an example of the conversion rate controller 232 according to some embodiments. Although Figure 7 shown Figure 2 is an example of the n-type conversion rate controller 232 shown in the figure, the principle also applies to Figure 2 the p-type conversion rate controller 222 shown in the figure. In some embodiments, the p-type conversion rate controller 222 is separated from the n-type conversion rate controller 232. In other embodiments, the p-type conversion rate controller 222 and the n-type conversion rate controller 232 are integrated into one circuit.

[0065] In Figure 7 the example shown in the figure, the n-type conversion rate controller 232 includes a current output digital-to-analog converter (DAC) 710 and other components. In some embodiments, the current output DAC 710 uses a binary weighted current ladder to generate an output current. A digital signal input in binary format is translated into a corresponding analog current output. In one implementation, the current output DAC 710 includes several current branches (e.g., ten current branches), and each current branch includes an access transistor and a current generating transistor (in a common-gate configuration). It should be understood that this is not intended to be restrictive, and in other embodiments, other types of current output DACs may be used. Since the current output DAC 710 is connected between the ground and the n-type output transistor 292, the less current branches are turned on, the higher the V GS of the n-type output transistor 292 becomes, and vice versa.

[0066] The current output DAC 710 has an input terminal ( Figure 7 "DutyCycle_in" shown in the figure). The output signal of the duty cycle detector 282 (i.e., the duty cycle detected by it) is input to the input terminal of the current output DAC 710. Therefore, the output current of the current output DAC 710 changes based on the duty cycle. The output current of the current output DAC 710 flows into the n-type output transistor 292. As the output current changes, the gate voltage of the n-type output transistor 292 changes accordingly, thereby adjusting the conversion rate of the n-type output transistor 292.

[0067] When the inductor current becomes higher (e.g., in the positive direction), the duty cycle becomes larger (e.g., increases beyond 50%), as Figure 4 shown. With the current output DAC 710, the duty cycle correspondingly changes the gate voltage of the n-type output transistor 292 (e.g., by turning on fewer current branches to increase the gate voltage of the n-type output transistor 292), thereby adjusting the switching rate of the n-type output transistor 292. As Figure 3 shown, the change of V GS of the n-type output transistor 292 in stage 2 (close to the threshold voltage V t ) of the n-type output transistor 292 can achieve switching rate control.

[0068] In the Figure 7 shown example, the n-type switching rate controller further includes a NAND gate 702, a first inverter 704, a second inverter 706, and a third inverter 708. The first input terminal (labeled "GATEN_in" in Figure 7 ) is configured to receive an n-type gate control signal that controls the switching of the n-type output transistor 292. The second input terminal is connected to the Figure 6 shown node NDET. Therefore, the n-type gate control signal that controls the switching of the n-type output transistor 292 only takes effect when the signal at the node NDET is at a logic low level (i.e., when the output signal at the output terminal OUT is at a logic low level). The combination of the first inverter 704 and the second inverter 706 and the third inverter 708 generates complementary signals to control the n-type output transistor 292 and the p-type output transistor 291, respectively.

[0069] Figure 8 FIG. is a diagram illustrating an example of a bias voltage controller according to some embodiments. Although Figure 8 shows Figure 2 the example of the n-type bias voltage controller 234 shown in Figure 2 , the principle also applies to the

[0070] shown p-type bias voltage controller 224. In some embodiments, the p-type bias voltage controller 224 is separate from the n-type bias voltage controller 234. In other embodiments, the p-type bias voltage controller 224 and the n-type bias voltage controller 234 are integrated into one circuit. Figure 8 In the

[0071] In some embodiments, the current-output DAC 810 utilizes a binary-weighted current ladder to generate an output current. A digital signal input in binary format is translated into a corresponding analog current output. In one implementation, the current-output DAC 810 includes several current branches (e.g., ten current branches), and each current branch includes an access transistor and a current-generating transistor (in a common-gate configuration). It should be understood that this is not intended to be restrictive, and in other embodiments, other types of current-output DACs may be employed. Since the resistor 820 is connected between the current-output DAC 810 and ground, the fewer current branches that are turned on, the lower the output voltage of the n-type bias voltage controller 234 (at the endpoint labeled "GATEN") becomes. In other words, the output voltage at the endpoint GATEN is controlled by the current-output DAC 810 and the resistor 820.

[0072] The current-output DAC 810 has an input terminal ( Figure 8 "DutyCycle_in" as shown therein). The output signal of the duty cycle detector 282 (i.e., the duty cycle detected by it) is input to the input terminal of the current-output DAC 810. Therefore, the output current of the current-output DAC 810 and thus the output voltage at the endpoint GATEN change based on the duty cycle. When the class D amplifier 200 needs to deliver higher power, the output current of the current-output DAC 810 becomes higher, and the output voltage at the endpoint GATEN becomes correspondingly higher, or vice versa. The output voltage at the endpoint GATEN determines the V of the n-type output transistor 292 GS . As Figure 3 shown therein, the change in V of the n-type output transistor 292 GS in stage 3 can automatically optimize the power efficiency. Thus, depending on the power to be delivered, the bias voltage controller 234 and the bias voltage controller 224 can adaptively adjust the V of the n-type output transistor 292 in stage 3 GS .

[0073] Although Figure 8 one example is shown therein, it should be understood that in other embodiments, other configurations of the n-type bias voltage controller 234 may be employed. In one embodiment, the n-type bias voltage controller may include Figure 8 the n-type bias voltage controller 234 as shown therein, and a source follower circuit. The source follower circuit is connected to Figure 8The node between the current output DAC 810 and the resistor 820 as shown. The source follower circuit (sometimes also referred to as a "common drain amplifier") is one of three basic single-stage FET amplifier topologies commonly used as a voltage buffer. The gate terminal of the transistor acts as the signal input, the source as the output, and the drain is common to both (the input and the output). By adding a source follower circuit, the drive strength becomes greater.

[0074] In another embodiment, the n-type bias voltage controller may include Figure 8 the n-type bias voltage controller 234 as shown in, and a unity gain buffer circuit. The unity gain buffer circuit is connected to Figure 8 the node between the current output DAC 810 and the resistor 820 as shown. A unity gain buffer (also known as a unity gain amplifier) is an operational amplifier (op-amp) circuit with a voltage gain of 1. This means that the operational amplifier does not provide any amplification of the signal. The output voltage signal is the same as the input voltage. Since the operational amplifier circuit is a circuit with a very high input impedance, very little current is drawn from the circuit. Thus, when feeding a high impedance load with current, the power of the circuit is not affected.

[0075] Figure 9 A diagram showing the adaptive gate voltage of a class D amplifier according to some embodiments. Figure 9 Shows the adaptive gate voltage and Figure 4 the duty cycle and the inductor current as shown in. As Figure 9 shown in, when the duty cycle 402 is 50% (e.g., Figure 9 at time t1 as shown in), the inductor current 404 is zero, as explained above with reference to Figure 4 . At time t1, the V of the n-type output transistor 292 GS and the V of the p-type output transistor 291 GS are both at a minimum. When the duty cycle 402 increases to its peak (e.g., Figure 9 at time t2 as shown in), the inductor current 404 correspondingly reaches its peak, as explained above with reference to Figure 4 . At time t2, the V of the n-type output transistor 292 GS and the V of the p-type output transistor 291 GS are both at a maximum. The n-type output transistor 292 and the p-type output transistor 291 conduct more, corresponding to Figure 3 stage 3 as shown in.

[0076] Figure 10A graph showing the voltage at the gate terminal in different stages according to some embodiments. The voltage at the gate terminal of the p-type output transistor 291 is in the upper half, while the voltage at the gate terminal of the n-type output transistor 292 is in the lower half. As Figure 10 shown, when the p-type output transistor 291 transitions from stage 1 to stage 2 (e.g., Figure 10 t7 shown in Figure 10 ), the voltage drops slightly, thereby being in a soft conduction state in stage 2. At the same time, the n-type output transistor 292 transitions from stage 3 to stage 1, and the voltage drops rapidly, thereby being in a fully off state in stage 1. At a later time (e.g., Figure 10 t8 shown in Figure 10 ), the n-type output transistor 292 is still in stage 1, and when the p-type output transistor 291 is fully conducting, the p-type output transistor 291 enters stage 3. This same timing also occurs when the n-type output transistor 292 transitions from stage 1 to stage 2 (e.g.,

[0077] Figure 11 A flowchart illustrating an example method of operating a class D amplifier according to some embodiments. In the Figure 11 example shown, method 1100 includes operations (or steps) 1102, 1104, 1106, 1108, 1110, and 1112. Additional operations may be performed. In addition, it should be understood that the order of the various operations discussed above with reference to Figure 11 is provided for illustrative purposes, and thus, other embodiments may utilize different orders. For example, steps 1106 and 1108 may be performed Figure 11 in the reverse order shown in

[0078] or simultaneously. These various operation orders are included within the scope of the embodiments. Figure 2 At step 1102, a pulse width modulation (PWM) signal generator (e.g., Figure 2 the PWM signal generator 210 shown in

[0079] of a class D amplifier (e.g., Figure 2 the class D amplifier 200 shown in Figure 2 receives an input signal.

[0080] At step 1104, an output monitor (e.g., Figure 2 the pre-drive circuits 220 and 230 shown together inFigure 2 The first gate voltage of the gate of the p-type output transistor 291) shown in

[0081] At step 1108, the pre-drive circuit of the class-D amplifier determines the second gate voltage to be applied to the gate of the n-type output transistor (e.g., Figure 2 the n-type output transistor 292) shown in based on the duty cycle and the input signal. The n-type output transistor is connected in series with the p-type output transistor at the output terminal.

[0082] At step 1110, the first gate voltage is applied to the gate of the p-type output transistor.

[0083] At step 1112, the second gate voltage is applied to the gate of the n-type output transistor.

[0084] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand aspects of the present application. Those skilled in the art should understand that they can readily use the present application as a basis for designing or modifying other processes and structures for achieving the same purposes and / or attaining the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present application, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present application.

Claims

1. A class D amplifier, characterized in that: Include: a pulse width modulation signal generator configured to generate an input signal; p-type output transistor; an n-type output transistor connected in series with the p-type output transistor at an output terminal; an output monitor connected to the output terminal and configured to detect a duty cycle of an output signal at the output terminal; as well as A pre-driver circuit has a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the first input terminal is connected to the pulse width modulation signal generator to receive the input signal, the second input terminal is connected to the output monitor to receive the duty cycle of the output signal, the first output terminal is connected to the gate of the p-type output transistor to provide a first gate voltage, and the second output terminal is connected to the gate of the n-type output transistor to provide a second gate voltage.

2. The class D amplifier according to claim 1, wherein: The pre-driving circuit determines the first gate voltage and the second gate voltage based on the duty cycle of the output signal.

3. The class D amplifier according to claim 2, wherein: The first gate voltage and the second gate voltage are complementary to each other.

4. The class D amplifier according to claim 1, wherein: In a first phase, the second gate voltage is at a logic low level, and the first gate voltage is at a logic high level.

5. The class D amplifier according to claim 4, wherein: In a second phase, the second gate voltage increases to a first voltage level close to a threshold voltage of the n-type output transistor.

6. The class D amplifier according to claim 5, characterized in that The first voltage level deviates from the threshold voltage of the n-type output transistor by a value greater than or less than 200 mV.

7. The class D amplifier according to claim 5, wherein: The pre-driver circuit includes a slew rate controller enabled in the second stage, and a slew rate of the class-D amplifier is adjusted by the slew rate controller in the second stage.

8. The class D amplifier of claim 7, wherein: The conversion rate controller includes a first current output digital-to-analog converter connected between a ground terminal and the n-type output transistor, and an output current of an output terminal of the first current output digital-to-analog converter is adjusted based on the duty cycle of the output signal.

9. The class D amplifier of claim 8, wherein: The output terminal of the first current output digital-to-analog converter is connected to the source of the n-type output transistor, and the gate-source voltage of the n-type output transistor is adjusted by the output current.

10. The class D amplifier according to claim 5, wherein: In a third phase, the second gate voltage increases to a second voltage level higher than the first voltage level.

11. The class D amplifier of claim 10, wherein: The n-type output transistor is fully turned on at the second voltage level.

12. The class D amplifier of claim 10, wherein: The pre-driver circuit includes a bias voltage controller enabled in the third stage, and the bias voltage of the n-type output transistor is adjusted by the bias voltage controller in the third stage.

13. The class D amplifier of claim 12, wherein: The bias voltage controller includes a second current output digital-to-analog converter connected in series with a resistor, and an output current at an output terminal of the second current output digital-to-analog converter is adjusted based on the duty cycle of the output signal.

14. The class D amplifier of claim 1, wherein: The output monitor includes a duty cycle detector configured to detect the duty cycle.

15. The class D amplifier of claim 1, wherein: The output monitor further includes a steady-state detector, and the steady-state detector is configured to sense the output signal at the output terminal and generate a current signal, and compare the current signal with a reference current.

16. The class D amplifier of claim 15, wherein: When the current signal is higher than the reference current, the slew rate controller is disabled.

17. A method for operating a class D amplifier, characterized in that: The method comprises: Receiving an input signal via a pulse width modulation signal generator of the class D amplifier; detecting a duty cycle of an output signal at an output terminal of the class D amplifier by means of an output monitor of the class D amplifier; determining, by a pre-driver circuit of the class-D amplifier, a first gate voltage applied to a gate of a p-type output transistor based on the duty cycle and the input signal; determining, by the pre-driver circuit of the class-D amplifier, a second gate voltage applied to a gate of an n-type output transistor based on the duty cycle and the input signal, wherein the n-type output transistor is connected in series with the p-type output transistor at the output terminal; applying the first gate voltage to the gate of the p-type output transistor; as well as The second gate voltage is applied to the gate of the n-type output transistor.

18. The method according to claim 17, characterized in that In a first stage, the second gate voltage is configured as a logic low level, and the first gate voltage is configured as a logic high level.

19. The method according to claim 18, characterized in that In a second phase, the second gate voltage is configured to increase to a first voltage level close to a threshold voltage of the n-type output transistor.

20. The method of claim 19, wherein: In a third phase, the second gate voltage is configured to increase to a second voltage level higher than the first voltage level.

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