Optical module time sequence signal test system and method
By designing an automated optical module timing signal testing system, the problem of low manual testing efficiency in the existing technology is solved, efficient and accurate optical module timing signal testing is achieved, and multiple packaging types are supported.
Patent Information
- Application Number
- CN202411727026.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-06-20
AI Technical Summary
The existing optical module timing testing technology mainly relies on manual operation, is low in efficiency and has high learning cost, and lacks an automated testing system to improve testing efficiency and accuracy.
An automated optical module timing signal testing system is designed, including a control host, power supply, control test board, oscilloscope, module test board and light source module. Test efficiency and accuracy are improved by automatically performing test operations such as switching of signal channels, generation of trigger signals and analysis of photoelectric timing.
A fully automated test system is realized, which reduces manual intervention, improves testing efficiency and accuracy, supports multiple packaging types of optical modules, and can automatically generate test data reports.
Smart Images
Figure CN120185703A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of optical communication, and particularly relates to an optical module timing signal testing system and method. Background Art
[0002] With the development of optical communication technology, optical modules are increasingly widely used in data transmission. The main function of an optical module is to realize the conversion of optical and electrical signals, and its performance directly affects the stability and reliability of the optical communication system. Therefore, the performance testing of optical modules is crucial. Among them, timing signal testing is an important part of optical module performance testing, which is mainly used to detect the timing characteristics of optical modules, such as overshoot current, laser switching time, communication enable time, reset time and other parameters.
[0003] In the field of electronic packaging technology, packages such as SFP, QSFP, and QSFPDD are currently commonly used packaging forms for optical modules. These packaging forms have the advantages of small size, light weight, and fast transmission speed, and are widely used in equipment such as data centers, servers, and switches.
[0004] Existing optical module timing testing technologies are mostly manual tests by humans, with relatively slow efficiency and high learning costs. In the field of automatic testing systems, in order to improve testing efficiency and accuracy, automated testing systems have been widely used. There is an urgent need for an automated optical module timing signal testing system. Summary of the Invention
[0005] The purpose of the present invention is to overcome at least one defect in the prior art, and provides an optical module timing signal testing system. The automated testing system of the present invention can automatically perform a series of testing operations, including signal channel switching, generation of trigger signals, analysis of optoelectronic timing, etc., greatly improving the testing efficiency and accuracy.
[0006] The technical solution of the present invention is implemented as follows: The present invention discloses an optical module timing signal testing system, including a control host, a power supply, a control test board, an oscilloscope, a module test board, and a light source module. The power supply is used to supply power to the entire testing system. The control host is connected to the oscilloscope and the control test board. The module test board is provided with a first connector for connecting the module under test and a second connector for connecting the control test board. The first connector and the second connector are electrically connected. The optical receiving end of the module under test connected to the module test board is connected through an optical fiber line. The module test board is electrically connected to the control test board. The output port of the control test board is connected to the oscilloscope, and the oscilloscope is used to record test timing waveform data.
[0007] Further, the control test board includes a main control module, a channel selection circuit, and an output port. The main control module is used to provide a trigger source signal, a low-speed control signal, and an IIC signal. The input end of the channel selection circuit is used to receive at least the trigger source signal and the low-speed control signal output by the main control module. The output end of the channel selection circuit is connected to the output port. The main control module is used to control the switching state of the switch of the channel selection circuit to at least select the trigger source signal and the low-speed control signal through channels and output them to the output port.
[0008] The control test board is provided with a communication interface for communicating with a control host, a first IIC signal interface for connecting the IIC signal to an oscilloscope, a second IIC signal interface, and connection ports for connecting the low-speed control signal pins of various optical modules. The connection ports, the first IIC signal interface, and the second IIC signal interface are connected to the main control module.
[0009] Further, the main control module is used to provide at least one of the signals of TRIG, LPMODE, RESELT, MODSELT, TX_DIS, and VCCOUT_EN to the module test board. The main control module is used to detect at least one of the signals of INTL, RX_LOS, MOD_ABS, and ModPrsL output by the module under test.
[0010] The main control module is used to control the switching state of the switch of the channel selection circuit to select the signals of TRIG, TX_DIS, RX_LOS, LPMODE, RESELT, MODSELT, INTL, and VCCOUT through channels and output them to two output ports.
[0011] Further, the channel selection circuit includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, an eighth switch S8, and a ninth switch S9. The second contact of the first switch S1 is connected to the LPMODE signal output end of the main control module. The third contact of the first switch S1 is connected to the third contact of the second switch S2. The first contact of the second switch S2 is connected to the RESELT signal output end of the main control module. The second contact of the second switch S2 is connected to the third contact of the fifth switch S5. The first contact of the fifth switch S5 is connected to the TRIG signal output end of the main control module. The second contact of the fifth switch S5 is connected to the first output port among the two output ports.
[0012] The first contact of the first switch S1 is connected to the third contact of the third switch S3. The first contact of the third switch S3 is connected to the INTL signal output terminal of the main control module. The second contact of the third switch S3 is connected to the first contact of the sixth switch S6. The third contact of the sixth switch S6 is connected to the second contact of the fourth switch S4. The first contact of the fourth switch S4 is connected to the MODSELT signal output terminal of the main control module. The third contact of the fourth switch S4 is connected to the first input port VCCOUT. The second contact of the sixth switch S6 is connected to the second output port among the two output ports;
[0013] The second contact is the common terminal;
[0014] The first input port VCCOUT is used to receive the VCCOUT signal;
[0015] The first output port is connected to the third interface of the oscilloscope;
[0016] The second output port is connected to the fourth interface of the oscilloscope.
[0017] Furthermore, the channel selection circuit further includes an eighth switch S8, and the eighth switch S8 is arranged between the second contact of the fifth switch S5 and the first output port;
[0018] and / or,
[0019] The channel selection circuit further includes a ninth switch S9, and the ninth switch S9 is arranged between the second contact of the sixth switch S6 and the second output port;
[0020] and / or,
[0021] The channel selection circuit further includes a seventh switch S7. The first contact of the seventh switch S7 is connected to the second input port TX. The third contact of the seventh switch S7 is connected to the third input port RX. The second contact of the seventh switch S7 is connected to the second output port among the two output ports.
[0022] Furthermore, the optical module timing signal test system of the present invention further includes an optoelectronic probe, and the optoelectronic probe is used to convert the optical signal at the receiving end of the module to be tested into an electrical signal and transmit it to the sixth interface of the oscilloscope;
[0023] or / and,
[0024] It further includes a current probe, and the current probe is used to collect the current signal provided by the control test board to the module to be tested on the module test board and transmit it to the fifth interface of the oscilloscope.
[0025] Furthermore, the optical module timing signal test system of the present invention further includes an error code tester, and the error code tester is used to provide a modulation signal for the light source module and the module to be tested, so that the light source module and the module to be tested operate in a full working state;
[0026] The error code tester is connected to the control host.
[0027] Furthermore, the control host is used to control the oscilloscope, display the trigger timing waveform, perform data determination, capture and record data, and read the test timing waveform data recorded by the oscilloscope, perform data analysis to obtain the test values of each test item, and compare the test values of each test item with the preset reference values.
[0028] The control host also has the functions of reading and writing the status of module registers of different package types, controlling the power soft switch, and controlling and detecting the status of low-speed pins; the control host also has the function of performing data determination according to the specified timing limit range, and saving the oscilloscope screenshot and outputting the test data report.
[0029] Furthermore, the optical module timing signal test system of the present invention further includes a light source board, on which a third connector for connecting a light source module is provided, and the light source board is connected to the control test board.
[0030] The present invention also discloses an optical module timing signal test method, including the following steps:
[0031] Control the error code tester to provide modulation signals to the light source module and the module under test, so that the light source module and the module under test DUT work in a fully operating state.
[0032] Control the control test board so that its main control module provides a trigger source signal and a low-speed control signal, outputs the low-speed control signal to the module under test, and receives the signal output by the module under test.
[0033] Control the control test board so that its main control module controls the channel selection circuit to at least select channels for the trigger source signal and the low-speed control signal and output them to the output port, and the output port is connected to the oscilloscope.
[0034] Control the oscilloscope to display the trigger timing waveform, capture and record data.
[0035] Read the test timing waveform data recorded by the oscilloscope, perform data analysis to obtain the test values of each test item, and compare the test values of each test item with the preset reference values to obtain the test results.
[0036] Furthermore, the control test board is also provided with a programming interface for the control bottom layer logic code of the main control module and the expansion ability for other package type modules such as DSFP modules and OSFP modules.
[0037] Furthermore, the control test board is also provided with a power supply module, a first power input port for supplying a first voltage input, a second power input port for supplying a second voltage input, and a power output port for supplying power to the module test board. The power supply module includes a switch soft start module. The input end of the switch soft start module is connected to the second power input port, and the output end of the switch soft start module is connected to the power output port. The power output port of the control test board is connected to the first input port VCCOUT.
[0038] The present invention has at least the following beneficial effects:
[0039] 1. Automated test system: Construct a fully automated test system that can automatically complete the tests on the control of the optical module, status signals, and the timing sequence of the two-wire interface. This system can reduce manual intervention and improve test efficiency.
[0040] 2. Precise timing test: In the automated test system, high-precision timing test instruments and methods are adopted to accurately test all the timing characteristics of the optical module. This precise timing test can ensure the accuracy of the test results.
[0041] 3. Support for multiple packages: This technical solution not only supports modules with SFP, QSFP, and QSFPDD type packages, but also can be extended to support other types of optical module packages according to actual needs, with strong adaptability and flexibility.
[0042] 4. Automatically generate test data reports: Improve the ability of the test system to process a large amount of test data, ensure the accuracy of the test results, and automatically complete technical issues such as the output of test reports. This solution can not only capture and save the test results, but also control the test data according to requirements such as SFF-8431 and SFF-8679, and output a complete test report file and a test process LOG file. Description of the Drawings
[0043] Figure 1 It is a schematic diagram of an optical module timing signal test system provided by an embodiment of the present invention;
[0044] Figure 2 It is a schematic diagram of a control test board provided by an embodiment of the present invention;
[0045] Figure 3 It is an enlarged view of the power supply part of the control test board;
[0046] Figure 4 It is an enlarged view of the channel selection circuit part of the control test board;
[0047] Figure 5 It is an enlarged view of the main control module part of the control test board;
[0048] Figure 6 Flow chart of the optical module timing signal test method provided by an embodiment of the present invention;
[0049] Figure 7 Schematic diagram of the test timing waveform data recorded by an oscilloscope according to an embodiment of the present invention;
[0050] Figure 8 Schematic diagram of the test presentation effect according to an embodiment of the present invention. Detailed implementation manners
[0051] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.
[0052] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should have the ordinary meanings understood by those of ordinary skill in the field to which the present disclosure belongs. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "including" or "comprising" mean that the elements or objects appearing before the term cover the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the described target changes, the relative positional relationship may also change accordingly.
[0053] In the respective drawings, the same elements are denoted by similar reference numerals. For the sake of clarity, not all parts in the drawings are drawn to scale. In addition, some well-known parts may not be shown in the figures.
[0054] The present invention relates to an optical module timing signal test system. Specifically, it is an automatic and precise test system for the control, status signals and two-wire interface timing of SFP, QSFP, QSFPDD and other types of packaged modules.
[0055] See Figures 1 to 5, an embodiment of the present invention discloses an optical module timing signal test system, including a control host PC, a power supply, a control test board, an oscilloscope, a module test board MCB, and a light source module. The power supply is used to supply power to the entire test system. The control host is connected to the oscilloscope and the control test board. The module test board is provided with a first connector for connecting a module under test and a second connector for connecting the control test board. The first connector is electrically connected to the second connector. The optical receiving end of the module under test DUT connected to the module test board is connected through an optical fiber line. The module test board is electrically connected to the control test board. The output port of the control test board is connected to the oscilloscope. The oscilloscope is used to record test timing waveform data.
[0056] The system of the present invention takes the control test board as the core.
[0057] Further, the control test board includes a main control module, a channel selection circuit, and an output port. The main control module is used to provide a trigger source signal, a module pin low-speed control signal, and a module communication signal, and generate and capture a specific timing waveform. The input end of the channel selection circuit is used to receive at least the trigger source signal and the low-speed control signal output by the main control module. The output end of the channel selection circuit is connected to the output port. The main control module is used to control the switch state of the switch of the channel selection circuit to at least select the trigger source signal and the module pin low-speed control signal through the channel and output them to the output port. For example, the main control module is used to control the switch state of the switch of the channel selection circuit to select signals such as the trigger source signal, TX_DIS, RX_LOS, LPMODE, RESET, MODSELT, INTL, VCCOUT, etc. through the channel and output them to the output port.
[0058] The low-speed control signals include: TX_DIS, RX_LOS, LPMODE, RESET, MODSELT, INTL, VCCOUT. They are the standard module pin interfaces described in the protocol standards SFF-8431, SFF-8436, QSFP-DD MSA, and CMIS-5.2. The module communication signal is an IIC signal (a standard protocol interface), specifically two lines of SDA and SCL. The trigger source signal refers to the synchronization indication signal TRIG generated by the control test board.
[0059] The control test board is provided with a communication interface for communicating with the control host, a first IIC signal interface and a second IIC signal interface for connecting the IIC signal (i.e., the SDA and SCL signals of IIC) to the oscilloscope, and each connection port for connecting the low-speed control signal pins of various optical modules. The connection port, the first IIC signal interface, and the second IIC signal interface are connected to the main control module.
[0060] Further, the control test board is also provided with a programming interface for the control low-level logic code of the main control module and the expansion ability for other package type modules such as DSFP modules and OSFP modules.
[0061] Further, the main control module is used to provide at least one of the signals of TRIG, LPMODE, RESELT, MODSELT, TX_DIS, and VCCOUT_EN to the module test board, and the main control module is used to detect at least one of the signals of INTL, RX_LOS, MOD_ABS, and ModPrsL output by the module under test.
[0062] The main control module is used to control the switch state of the switch of the channel selection circuit to perform channel selection on TRIG, TX_DIS, RX_LOS, LPMODE, RESELT, MODSELT, INTL, and VCCOUT signals and output them to two output ports.
[0063] The main control module is used to provide signals of TRIG, LPMODE, RESELT, MODSELT, TX_DIS, and VCCOUT_EN, and the working direction of this signal is from the control test board to the module test board. The main control module is used to detect signals such as INTL, RX_LOS (also including MOD_ABS and ModPrsL not mentioned), and the working direction of this signal is from the module under test to the module test board and then to the control test board.
[0064] The TRIG signal is provided for the MCU and is used as the trigger source of the oscilloscope to synchronize the detection of other signals.
[0065] The LPMODE signal is provided for the MCU and is used to control the high and low power consumption of the module.
[0066] The RESELT signal is provided for the MCU and is used to control the restart and reset of the module.
[0067] The MODSELT signal is provided for the MCU and is used to control the switch of the IIC communication function of the module.
[0068] The TX_DIS signal is provided for the MCU and is used to control the switch of the laser of the module.
[0069] The VCCOUT_EN signal is provided for the MCU and is used to control the power signal switch of the bench power supply to the module test board through the module control test board.
[0070] The VCCOUT signal is provided for the bench power supply and is used to power the module on the module test board, and the VCCOUT signal is connected to the oscilloscope to indicate the voltage status of the module VCC.
[0071] The INTL signal is provided for the module output, and the MCU detects the level status to indicate the abnormal problem status of the module.
[0072] The RX_LOS signal is provided for the module output, and the MCU detects the level status to indicate the presence or absence of the modulated optical signal at the receiving end of the module.
[0073] MOD_ABS and ModPrsL are provided for the module output, and the MCU detects the level status to indicate the status of whether the module is normally connected to the first connector (female port of the module test board).
[0074] TX_DIS and LPMODE are multiplexed on the main control module (MCU). The usage principles for SFP and QSFP / QSFP-DD type modules are the same, but the functions are different. RX_LOS and INTL are multiplexed on the MCU. The usage principles for SFP and QSFP / QSFP-DD type modules are the same, but the functions are different.
[0075] Further, the channel selection circuit includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, an eighth switch S8, and a ninth switch S9. The second contact of the first switch S1 is connected to the LPMODE signal output terminal of the main control module. The third contact of the first switch S1 is connected to the third contact of the second switch S2. The first contact of the second switch S2 is connected to the RESELT signal output terminal of the main control module. The second contact of the second switch S2 is connected to the third contact of the fifth switch S5. The first contact of the fifth switch S5 is connected to the TRIG signal output terminal of the main control module. The second contact of the fifth switch S5 is connected to the first output port among the two output ports;
[0076] The first contact of the first switch S1 is connected to the third contact of the third switch S3. The first contact of the third switch S3 is connected to the INTL signal output terminal of the main control module. The second contact of the third switch S3 is connected to the first contact of the sixth switch S6. The third contact of the sixth switch S6 is connected to the second contact of the fourth switch S4. The first contact of the fourth switch S4 is connected to the MODSELT signal output terminal of the main control module. The third contact of the fourth switch S4 is connected to the first input port VCCOUT. The second contact of the sixth switch S6 is connected to the second output port among the two output ports;
[0077] The second contact is the common terminal;
[0078] The first input port VCCOUT is used to receive the VCCOUT signal;
[0079] The first output port is connected to the third interface of the oscilloscope;
[0080] The second output port is connected to the fourth interface of the oscilloscope.
[0081] Further, the channel selection circuit further includes an eighth switch S8, and the eighth switch S8 is disposed between the second contact of the fifth switch S5 and the first output port. The channel selection circuit further includes a ninth switch S9, and the ninth switch S9 is disposed between the second contact of the sixth switch S6 and the second output port. At this time, the second contact of the first switch S1 is connected to the LPMODE signal output terminal of the main control module, the third contact of the first switch S1 is connected to the third contact of the second switch S2, the first contact of the second switch S2 is connected to the RESELT signal output terminal of the main control module, the second contact of the second switch S2 is connected to the third contact of the fifth switch S5, the first contact of the fifth switch S5 is connected to the MCU TRIG signal output terminal of the main control module, the second contact of the fifth switch S5 is connected to the first contact of the eighth switch S8, and the second contact of the eighth switch S8 is connected to the first output port among the two output ports;
[0082] The first contact of the first switch S1 is connected to the third contact of the third switch S3, the first contact of the third switch S3 is connected to the INTL signal output terminal of the main control module, the second contact of the third switch S3 is connected to the first contact of the sixth switch S6, the third contact of the sixth switch S6 is connected to the second contact of the fourth switch S4, the first contact of the fourth switch S4 is connected to the MODSELT signal output terminal of the main control module, the third contact of the fourth switch S4 is connected to the first input port VCCOUT, the second contact of the sixth switch S6 is connected to the first contact of the ninth switch S9, and the second contact of the ninth switch S9 is connected to the second output port among the two output ports.
[0083] Further, the channel selection circuit further includes a seventh switch S7. The first contact of the seventh switch S7 is connected to the second input port TX, the third contact of the seventh switch S7 is connected to the third input port RX, and the second contact of the seventh switch S7 is connected to the second output port among the two output ports. The second input port TX (here the electrical signal module has TX+ and TX-) is connected to the module test board; the third input port RX (here the electrical signal module has RX+ and RX-) is connected to the module test board. The second input port TX and the third input port RX are external interface switches for reserved design.
[0084] In some embodiments, the switch can be but is not limited to a relay.
[0085] Further, the optical module timing signal test system of the present invention further includes an optoelectronic probe, and the optoelectronic probe is used to convert the optical signal at the receiving end of the module to be tested into an electrical signal and transmit it to the sixth interface of the oscilloscope.
[0086] The optical module timing signal test system of the present invention further includes a current probe, which is used to collect the current signal provided by the control test board to the module under test on the module test board and transmit it to the fifth interface of the oscilloscope.
[0087] The current probe is a device designed based on the Faraday principle and is used to measure the current signal in the connection wire. The power output port of the control test board is connected to the VCC IN of the module test board through a wire, and the current probe is clamped on the wire to detect the signal of the current magnitude provided to the module.
[0088] In the test item, measure the time from 0A when the module is powered on to a certain current (such as 2.5A) when the module is fully working, which indicates how long it takes for the module to be fully powered on. For the hardware function of the LPMODE to control the high and low power consumption of the module, it is necessary to detect the time from when LPMODE is pulled high to when the current drops below 432 mA. The current magnitude of 432 mA here needs to be indicated by the current probe.
[0089] Further, the control test board is also provided with a power supply module, a first power input port for supplying a first voltage input, a second power input port for supplying a second voltage input, and a power output port for supplying power to the module test board. The power supply module includes a switch soft start module. The input end of the switch soft start module is connected to the second power input port, and the output end of the switch soft start module is connected to the power output port. The power output port of the control test board is connected to the first input port VCCOUT.
[0090] The power output port of the control test board is used to connect to the module test board. The first power input port and the second power input port are connected to a power supply (such as a bench power supply).
[0091] The first voltage input from the first power input port is respectively supplied to the main control module and the channel selection circuit after passing through each power module. The first voltage in one embodiment is 5V. The second voltage in one embodiment is 3.3V. The switch soft start module has a slow start function and is enabled according to the VCC_EN signal switch.
[0092] The control test board has three power supply input ports, which respectively supply power to the channel selection circuit, the main control module circuit, and the module channel power supply input port, and perform ground isolation processing among them. It has one power supply output port, which provides the module channel output voltage to supply power to the module. It has a switch soft start module and overcurrent protection ability, and enables the module test board.
[0093] Further, the optical module timing signal test system of the present invention further includes a light source board. The light source board is provided with a third connector for connecting the light source module, and the light source board is connected to the control test board.
[0094] Furthermore, the optical module timing signal test system of the present invention further includes an error code detector, which is used to provide modulation signals for the light source module and the module under test, so that the light source module and the module under test operate in a fully operational state; the error code detector is connected to the control host.
[0095] Furthermore, the control host is used to control the oscilloscope to display the trigger timing waveform, make data determination, capture and record data, and read the test timing waveform data recorded by the oscilloscope, perform data analysis to obtain the test values of each test item, and compare the test values of each test item with the preset reference values;
[0096] The control host also has the functions of reading and writing the register status of modules of different package types, controlling the power soft switch, and controlling and detecting the status of low-speed pins; the control host also has the function of making data determination according to the timing limit ranges specified by protocols SFF-8419, SFF-8636, and QSFP-DD MSA, and saving the oscilloscope screenshots and outputting test data reports.
[0097] The power supply is connected to the control host. The power supply uses a high-current bench power supply.
[0098] In some embodiments, the control host PC controls the error code detector to provide modulation signals for the light source module and the device under test (DUT) through the GPIB communication interface, so that the light source module and the DUT operate in a fully operational state.
[0099] The control host PC controls the high-current bench power supply through the GPIB communication interface. The high-current bench power supply has three power output ports. Among them, the high-current power supply channel outputs to the module test board after controlling the power switch circuit on the test board, and the other two power supply channels supply power to the control test board and the light source test board respectively.
[0100] The control host PC controls the multi-channel oscilloscope through the USB communication interface to display the trigger timing waveform, make data determination, capture and record data. The control software of the control host PC reads the test timing waveform data recorded by the oscilloscope, performs raw data analysis and function data analysis, and calculates the waveform timing time to obtain the test results.
[0101] The control host PC is connected to the control test board through serial communication. The control test board has three power supply input ports, which supply power to the channel selection circuit, the main control chip circuit, and the module channel power supply input port respectively, and perform ground isolation processing among them. It has one power supply output port, which provides the module channel output voltage to supply power to the module. It has a switch soft start module and overcurrent protection ability, and enables the module test board.
[0102] The control test board is equipped with a main control module (such as an MCU), which provides a trigger source signal, a low-speed control signal for module pins, and an IIC signal, and generates and captures specific timing waveforms; at the same time, it performs channel selection on the channel selection circuit; at the same time, it processes and responds to the host computer signal of the control host PC.
[0103] The control test board has the function of a channel selection circuit, which selects channels for signals such as the trigger source signal, TX_DIS, RX_LOS, LPMODE, RESET, MODSELT, INTL, VCCOUT POWER, etc., and outputs them to two output ports. The output ports are connected to an oscilloscope through voltage probes for waveform detection.
[0104] The control test board has multiple interface parts, including a DB9 communication interface for communicating with the host computer of the control host PC, a programming interface for the control bottom logic code of the main control chip, a voltage probe inspection interface for connecting the SDA and SCL signals of IIC to an oscilloscope, a connection port for connecting the low-speed control signal pins encapsulated by SFP modules, QSFP modules, and QSFPDD modules respectively, and at the same time has the expansion ability for other package type modules such as DSFP modules and OSFP modules.
[0105] The control host PC is equipped with host computer software to integrate and send control instructions, and has the functions of controlling a bench power supply, a bit error tester, an oscilloscope, and a control test board.
[0106] The host computer software also has the functions of reading and writing the register status of different package type modules, controlling the power soft switch, and controlling and detecting the status of low-speed pins.
[0107] The host computer software also has the function of data determination according to the timing limit ranges specified by protocols SFF-8419, SFF-8636, and QSFP-DD MSA, and saves the oscilloscope screenshots and outputs test data reports. Among them, those with large differences in data units will be automatically converted in units, and those test results that do not meet the protocol requirements will be automatically highlighted.
[0108] For SFP type modules, it has Tx Disable and Rx Los pins. It can complete the Tx Dis ON and OFF timings of software and hardware for the Tx Dis function, and can complete the Rx Los ON and OFF timings of hardware and software for the Rx Los function. At the same time, it has the functions of completing the test of power-on time and power-on surge, and also has password permission test and slow power-on test.
[0109] For QSFP and QSFPDD type modules, the pin functions are basically the same, but the register positions are different. They have Lpmode, Intl, Mask, Modeselt, and Reset pins. It can complete the switching timing of software and hardware low-power on and off for the Lpmode function, the Intl ON and OFF timing for the Intl function, the MaskON and OFF timing for the Mask function, the setup time, hold time, and bus release time timing for the Modeselt function, and the Reset set time, pull-down minimum pulse time, and current response time after setting for the Reset function. Correspondingly, it also has the functions of completing the power-on test time and power-on surge, the TX DIS ON and OFF timing tests for software, the power consumption mode function check, password permission test, and slow power-on test.
[0110] At the same time, it can perform IIC timing tests on SFP, QSFP, and QSFPDD type modules.
[0111] For the IIC slave, it can complete the IIC clock rate tests at 1Hz, 100kHz, and 400kHz, complete the 400K clock delay verification, complete the IIC bus hardware preparation time test, complete the power-on single-byte read test, complete the write-back read time interval tests for four bytes and eight bytes (only available for SFP), complete the IIC diagnostic data preparation time test, complete the power-off test for writing data to the user area Flash, and complete the 100k IIC read data hold time test.
[0112] For the 100k and 400k IIC masters, it can complete the low-level cycle test of the SCL clock, complete the high-level cycle test of the SCL clock, complete the clock bus idle time test before a new transmission starts, complete the Start hold time test, complete the Start setup time test, complete the data setup time test, complete the data hold time test, complete the SCL input rise and fall time test, complete the stop condition setup time test, complete the SDA master input rise and fall time test, and complete the SDA slave rise and fall time test.
[0113] It is capable of testing whether data can be read normally after continuously sending 2 to 10 Start signals for IIC abnormal timing, testing whether data can be read normally after continuously sending 2 to 10 Stop signals, testing whether data can be read normally after continuously sending 2 to 10 Start+Stop signals, testing whether data can be read normally after sending Start+1 to 10 Bit data, testing whether data can be read normally after sending 1 to 10 Bit data, testing whether data can be read normally after sending 1 to 10 Bit data+Stop, testing whether data can be read normally after sending Start+1 to 10 Bit data+Stop, testing whether data can be read normally after sending Start+AO+ACK, testing whether data can be read normally after sending Start+A1+ACK, testing whether data can be read normally after sending Start+A2+ACK, testing whether data can be read normally after sending Start+A3+ACK, testing whether data can be read normally after sending Start+AO+ACK+9bit1, testing whether data can be read normally after sending Start+A2+ACK+9bit1. It is capable of testing whether data can be read normally after writing data after continuously sending 2 to 10 Start signals, testing whether data can be read normally after writing data after continuously sending 2 to 10 Stop signals, testing whether data can be read normally after writing data after continuously sending 2 to 10 Start+Stop signals, testing whether data can be read normally after writing data after sending Start+1 to 10 Bit data, testing whether data can be read normally after writing data after sending 1 to 10 Bit data, testing whether data can be read normally after writing data after sending 1 to 10 Bit data+Stop, testing whether data can be read normally after writing data after sending Start+1 to 10 Bit data+Stop, testing whether data can be read normally after writing data after sending Start+AO+ACK, testing whether data can be read normally after writing data after sending Start+A1+ACK, testing whether data can be read normally after writing data after sending Start+A2+ACK, testing whether data can be read normally after writing data after sending Start+A3+ACK, testing whether data can be read normally after writing data after sending Start+AO+ACK+9bit1, testing whether data can be read normally after writing data after sending Start+A2+ACK+9bit1.
[0114] Embodiment 2
[0115] See Figures 1 to 6, an embodiment of the present invention discloses a method for testing the timing signal of an optical module, which adopts the test system described in Embodiment 1 and includes the following steps:
[0116] Select the product test type;
[0117] Initialize the test system;
[0118] Control the error code detector to provide modulation signals to the light source module and the module under test, so that the light source module and the DUT (Device Under Test) work in a fully operating state;
[0119] Control the test board to make its main control module provide a trigger source signal and a low-speed control signal, output the low-speed control signal to the module under test, and receive the signal output by the module under test;
[0120] Control the test board to make its main control module control the channel selection circuit to at least select the trigger source signal and the low-speed control signal and output them to the output port, and the output port is connected to the oscilloscope;
[0121] Control the oscilloscope to display, capture and record the trigger timing waveform;
[0122] Read the test timing waveform data recorded by the oscilloscope, perform data analysis to obtain the test values of each test item, and compare the test values of each test item with the preset reference values to obtain the test results.
[0123] The interrupt set time (ton IntL) refers to: the time from the occurrence of the condition trigger IntL to the output voltage: IntL = Vol. Any operation that sets IntL low can be called a condition.
[0124] The interrupt inversion time (toff IntL) refers to: the time from the clear read operation of the associated flag to Vout: IntL = Voh. This includes the inversion time of Rx LOS, Tx Fault and other flag bits.
[0125] There are many reasons for causing an interruption of the module under test. Enabling the optical Los through software is one of the ways. Only one case regarding the detailed flag bits is shown in this test case. See Figure 7 .
[0126] Test steps:
[0127] 1. According to Figure 1 Build a test platform according to the test architecture. Connect the voltage probe 1 of the CH1 channel of the oscilloscope to SCL, and connect the voltage probe 2 of the CH channel of the oscilloscope to SDA. Connect the voltage probe 3 of the CH3 channel of the oscilloscope to the control signal RESET, and connect the voltage probe 4 of the CH4 channel of the oscilloscope to INTL. Connect the optoelectronic conversion probe to one of the channels at the transmitting end.
[0128] 2. Disable the TX transmission of the tested channel through software.
[0129] 3. Through the trigger in the previous step, the oscilloscope will capture the changes in light and IntL. This time interval is the interrupt set time (ton_IntL).
[0130] 4. Mask the redundant intl caused by the disable operation, such as txpower low, txbias low, etc. Only leave one int1 interrupt bit (the toff_intl protocol requires a very short time, so reading too many flag bits may also cause the time to exceed the standard). Cancel the software Disable operation.
[0131] 5. Read the only intl interrupt flag bit, such as Figure 7 The toff_intl time in is the time from the SCL falling edge to the IntL rising edge.
[0132] INTL is the pin shared by the module test board and the control test board (INTL: provides for the module output, and the MCU detects the level status. It is used to indicate the abnormal problem status of the module). SDA and SCL are IIC communication signals and are the pins shared by the module test board and the control test board. SDA: is the data line of the IIC signal. SCL: is the clock line of the IIC signal.
[0133] For an example of the Reset set time. The optical module timing signal test method of the present invention includes: first, completing the initialization of the control test board, second, completing the initialization of the oscilloscope, third, measuring the trigger threshold, fourth, implementing the measurement logic, and fifth, processing the measurement results.
[0134] The steps included in the initialization of the control test board include:
[0135] Perform a reset on the control test board;
[0136] Configure test channel 1 of the control test board to the Reset function;
[0137] Configure test channel 2 of the control test board to the Intl function;
[0138] Configure the power switch of the control test board to supply power output to the test board.
[0139] The steps included in the initialization of the oscilloscope include:
[0140] Restore the oscilloscope to the factory settings;
[0141] Turn off the UI display of oscilloscope channel 1;
[0142] Set the oscilloscope return value format. The return value contains the test result value; Turn on oscilloscope channel 3;
[0143] Set the name display of channel 3 to Reset;
[0144] Set the font size of the name of channel 3;
[0145] Set the vertical precision of channel 3 to 1V;
[0146] Turn on oscilloscope channel 4;
[0147] Set the name display of channel 4 to Intl;
[0148] Set the font size of the name of channel 4;
[0149] Set the vertical precision of channel 4 to 0.5V;
[0150] Set the horizontal precision to 10ms;
[0151] Set the trigger source of the trigger to channel 3;
[0152] Set the trigger mode of the trigger to falling edge trigger;
[0153] Set the trigger mode event trigger mode;
[0154] Set the measurement mode to Delay;
[0155] Set the measurement data source 1 to channel 3;
[0156] Set the measurement data source 2 to channel 4;
[0157] Set the measurement level setting to independent and irrelevant;
[0158] Set the metric unit format to percentage;
[0159] Set to use a custom percentage setting;
[0160] Set the read mode of source 1 to rising edge;
[0161] Set the mid-value of the rising edge of the reference level to 90%;
[0162] Set the maximum value of the rising edge of the reference level to 99%;
[0163] Set the minimum value of the rising edge of the reference level to 1%;
[0164] Set the read mode of source 2 to falling edge;
[0165] Set the mid-value of the falling edge of the reference level to 10%;
[0166] Set the maximum value of the falling edge of the reference level to 99%;
[0167] Set the minimum value of the reference level falling edge to 1%;
[0168] Turn on the cursor;
[0169] Set cursor source 1 to be bound to channel 3;
[0170] Set cursor source 2 to be bound to channel 3.
[0171] The steps included in measuring the trigger threshold are as follows:
[0172] Configure the call to the measurement 2 test method as RMS;
[0173] Configure the call to the measurement 2 data source as channel 3;
[0174] Start running;
[0175] Read the test result max of the call to measurement 2;
[0176] Set the trigger value of the trigger to 0.1max;
[0177] Clear all statuses.
[0178] The steps included in implementing the measurement logic are as follows:
[0179] Control the test board to read the status of the INTL pin of the test board, which must be HVCC; control the test board to pull down INTL;
[0180] Control the test board to read via IIC to clear the Mask flag bit;
[0181] Trigger the test signal;
[0182] The oscilloscope pauses;
[0183] Read the Intl level.
[0184] The steps included in processing the measurement results are as follows:
[0185] Read the measurement results;
[0186] Move the cursor A-axis to the position where the time axis is 0;
[0187] Move the cursor B-axis to the position where the time is the test result;
[0188] Save the waveform to the USB flash drive;
[0189] Take out the picture of the USB flash drive;
[0190] Configure the control of the test board power switch to turn off the power supply output, and the test presentation effect is as Figure 8 shown.
[0191] The present invention relates to the field of optical module timing signal testing, and specifically relates to an automatic and precise testing method for the control, status signals, and two-wire interface timing of modules packaged in SFP, QSFP, and QSFPDD types. The present invention proposes an automatic and precise testing method for the control, status signals, and two-wire interface timing of modules packaged in SFP, QSFP, and QSFPDD types, which greatly improves the degree of automation of testing, reduces manual intervention, and thus improves the testing efficiency. The testing of the present invention is comprehensive. The present invention can not only test the timing characteristics such as TX_DIS, RX_LOS, LPMODE, RESET, MODSELT, INTL, etc. of the optical module, but also accurately test important timing characteristics such as power-on and power-off testing and IIC timing testing, making the test results more comprehensive and accurate. The present invention has strong data processing capabilities. The bottom layer of the control test board and the upper computer software of the present invention can complete the processing and screening of the test result data, avoiding the problem of cumbersome data sorting that occurs when manually testing and processing a large amount of test data in the prior art, and thus improving the speed and accuracy of the test result output. The present invention has a wide range of applications. The method of the present invention can not only be used for the timing signal testing of optical modules, but also for other electronic devices that require precise timing control, and has a wide range of applications.
[0192] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure. However, the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.
Claims
1. An optical module timing signal test system, characterized in that: The test system comprises a control host, a power supply, a control test board, an oscilloscope, a module test board and a light source module. The power supply is used to supply power to the entire test system. The control host is connected with the oscilloscope and the control test board. The module test board is provided with a first connector for connecting the module to be tested and a second connector for connecting the control test board. The first connector is electrically connected to the second connector. The light receiving end of the module to be tested connected to the module test board is connected to the control test board through an optical fiber line. The module test board is electrically connected to the control test board. The output port of the control test board is connected to the oscilloscope. The oscilloscope is used to record test timing waveform data.
2. The optical module timing signal testing system according to claim 1, characterized in that: The control test board includes a main control module, a channel selection circuit and an output port, wherein the main control module is used to provide a trigger source signal, a low-speed control signal and an IIC signal; the input end of the channel selection circuit is used to at least receive the trigger source signal and the low-speed control signal output by the main control module, and the output end of the channel selection circuit is connected to the output port, and the main control module is used to control the switch state of the switch of the channel selection circuit to at least select the trigger source signal and the low-speed control signal through a channel and output them to the output port; The control test board is provided with a communication interface for communicating with a control host, and a first IIC signal interface, a second IIC signal interface, and various connection ports for connecting the IIC signal to an oscilloscope, and low-speed control signal pins of various optical modules. The connection port, the first IIC signal interface, and the second IIC signal interface are connected to the main control module.
3. The optical module timing signal testing system according to claim 2, characterized in that: The main control module is used to provide at least one of TRIG, LPMODE, RESELT, MODSELT, TX_DIS, and VCCOUT_EN signals to the module test board, and the main control module is used to detect at least one of INTL, RX_LOS, MOD_ABS, and ModPrsL output by the module to be tested. The main control module is used to control the switch state of the channel selection circuit to select the channel of TRIG, TX_DIS, RX_LOS, LPMODE, RESELT, MODSELT, INTL, and VCCOUT signals and output them to two output ports.
4. The optical module timing signal testing system according to claim 3, characterized in that: The channel selection circuit includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, an eighth switch S8 and a ninth switch S9, a second contact of the first switch S1 is connected to an LPMODE signal output terminal of the main control module, a third contact of the first switch S1 is connected to a third contact of the second switch S2, a first contact of the second switch S2 is connected to a RESELT signal output terminal of the main control module, a second contact of the second switch S2 is connected to a third contact of the fifth switch S5, a first contact of the fifth switch S5 is connected to a TRIG signal output terminal of the main control module, and a second contact of the fifth switch S5 is connected to a first output port of the two output ports; The first contact of the first switch S1 is connected to the third contact of the third switch S3, the first contact of the third switch S3 is connected to the INTL signal output terminal of the main control module, the second contact of the third switch S3 is connected to the first contact of the sixth switch S6, the third contact of the sixth switch S6 is connected to the second contact of the fourth switch S4, the first contact of the fourth switch S4 is connected to the MODSELT signal output terminal of the main control module, the third contact of the fourth switch S4 is connected to the first input port VCCOUT, and the second contact of the sixth switch S6 is connected to the second output port of the two output ports; The second contact is the common terminal; The first input port VCCOUT is used to receive a VCCOUT signal; The first output port is connected to a third interface of the oscilloscope; The second output port is connected to the fourth interface of the oscilloscope.
5. The optical module timing signal testing system according to claim 4, characterized in that: The channel selection circuit further includes an eighth switch S8, which is arranged between the second contact point of the fifth switch S5 and the first output port; and / or, The channel selection circuit further includes a ninth switch S9, which is arranged between the second contact point of the sixth switch S6 and the second output port; and / or, The channel selection circuit further includes a seventh switch S7, a first contact of the seventh switch S7 is connected to the second input port TX, a third contact of the seventh switch S7 is connected to the third input port RX, and a second contact of the seventh switch S7 is connected to the second output port of the two output ports.
6. The optical module timing signal testing system according to any one of claims 1 to 5, characterized in that: It also includes a photoelectric probe, which is used to convert the optical signal of the receiving end of the module to be tested into an electrical signal and transmit it to the sixth interface of the oscilloscope; or / and, It also includes a current probe, which is used to collect the current signal of the module to be tested on the module test board provided by the control test board, and transmit it to the fifth interface of the oscilloscope.
7. The optical module timing signal testing system according to claim 1, characterized in that: It also includes a bit error meter, which is used to provide a modulation signal for the light source module and the module to be tested, so that the light source module and the module to be tested work in a fully working state; The bit error meter is connected to a control host.
8. The optical module timing signal testing system according to claim 1, characterized in that: The control host is used to control the oscilloscope, display the trigger timing waveform, determine the data, capture and record the data, and read the test timing waveform data recorded by the oscilloscope, perform data analysis and obtain the test value of each test item, and compare the test value of each test item with a preset reference value; The control host also has the functions of reading and writing the register status of modules of different package types, controlling the soft switch of the power supply, and controlling and detecting the status of low-speed pins; the control host also has the function of making data judgments according to the prescribed timing limit range, and saving oscilloscope screenshots and outputting test data reports.
9. The optical module timing signal testing system according to claim 1, characterized in that: It also includes a light source board, on which a third connector for connecting the light source module is provided, and the light source board is connected to the control test board.
10. A method for testing timing signals of an optical module, characterized in that: The steps include: Control the bit error meter to provide modulation signals to the light source module and the module to be tested, so that the light source module and the module to be tested work in a fully working state; Control the control test board so that its main control module provides a trigger source signal and a low-speed control signal, outputs the low-speed control signal to the module to be tested, and receives the signal output by the module to be tested; Control the control test board so that its main control module controls the channel selection circuit to at least select the channel of the trigger source signal and the low-speed control signal and output them to the output port, wherein the output port is connected to the oscilloscope; Control the oscilloscope to display the trigger timing waveform, capture and record data; The test timing waveform data recorded by the oscilloscope is read, the data is analyzed and the test value of each test item is obtained, and the test value of each test item is compared with the preset reference value to obtain the test result.