Semiconductor structure and manufacturing method thereof

Abstract

An embodiment of the present disclosure provides a semiconductor structure and a method for manufacturing the same, wherein the semiconductor structure includes: a substrate, the substrate including a substrate and an insulating structure located within the substrate; a plurality of groove structures discretely arranged within the substrate; wherein the insulating structure includes at least one first sub-portion, the first sub-portion being located between two adjacent groove structures, and in the arrangement direction of the two adjacent groove structures, an extension length of the first sub-portion is equal to a distance between the two adjacent groove structures; a capacitor structure including a plurality of electrode layers stacked and a first dielectric layer at least located between two adjacent electrode layers, wherein the capacitor structure covers at least the inner walls of the plurality of groove structures.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the growing market demand for high-performance, miniaturized, and low-power chips, high-density silicon capacitors have broad application prospects in advanced packaging, particularly in high-performance computing, 5G communications, the Internet of Things (IoT), artificial intelligence (AI), and automotive electronics. The current mainstream high-density silicon capacitor technology is TSMC's Deep Trench Capacitor (DTC) technology. In the package, silicon capacitors can be placed in the middle of the package substrate or below the chip. This placement helps achieve lower equivalent series inductance (ESL) characteristics, thereby improving filtering performance.

[0003] However, current deep trench capacitors suffer from high loss in high-frequency applications. Summary of the Invention

[0004] An embodiment of the present disclosure provides a semiconductor structure, comprising:

[0005] A substrate, comprising a substrate and an insulating structure located within the substrate;

[0006] A plurality of trench structures are discretely disposed in the substrate; wherein the insulating structure includes at least one first sub-portion, the first sub-portion being located between two adjacent trench structures, and an extension length of the first sub-portion being equal to a distance between the two adjacent trench structures in an arrangement direction of the two adjacent trench structures;

[0007] The capacitor structure comprises a plurality of stacked electrode layers and a first dielectric layer at least between two adjacent electrode layers. The capacitor structure at least covers inner walls of the plurality of groove structures.

[0008] In some embodiments, a plurality of the groove structures and a first sub-portion located between two adjacent groove structures are defined as a target structure; the insulating structure further includes a second sub-portion connected to the first sub-portion, the second sub-portion surrounds the side wall of the target structure and is partially located below the target structure, and the plurality of the groove structures are located within the space defined by the insulating structure.

[0009] In some embodiments, the insulating structure is made of silicon oxide.

[0010] In some embodiments, the capacitor structure further covers a portion of the upper surface of the substrate, and an edge of the portion of the capacitor structure covering the upper surface of the substrate includes a step structure;

[0011] The semiconductor structure further includes: a second dielectric layer covering at least the step structure; and a plurality of contact plugs extending from the top surface of the second dielectric layer to surfaces of the plurality of electrode layers of the step structure and electrically connected to the plurality of electrode layers in a one-to-one correspondence.

[0012] The present disclosure also provides a method for manufacturing a semiconductor structure, including:

[0013] Providing a substrate, and forming a plurality of discrete trench structures and an insulating structure in the substrate, wherein the insulating structure includes at least one first sub-portion, the first sub-portion being located between two adjacent trench structures, and an extension length of the first sub-portion being equal to a distance between the two adjacent trench structures in an arrangement direction of the two adjacent trench structures;

[0014] A capacitor structure is formed that at least covers the inner walls of the plurality of groove structures. The capacitor structure includes a plurality of stacked electrode layers and a first dielectric layer located at least between two adjacent electrode layers.

[0015] In some embodiments, a plurality of discrete trench structures and insulating structures are formed in the substrate, including:

[0016] Etching the substrate to form a plurality of discrete trench structures and a spacer structure between two adjacent trench structures in the substrate;

[0017] An oxidation process is performed on a portion of the substrate from sidewalls and bottoms of the plurality of trench structures, so that a spacer structure located between two adjacent trench structures is completely oxidized to form the first sub-portion.

[0018] In some embodiments, a plurality of the trench structures and a spacer junction between two adjacent trench structures are defined as an initial target structure; and an oxidation process is performed on a portion of the substrate from the sidewalls and bottoms of the plurality of the trench structures, further comprising:

[0019] A portion of the substrate surrounding the sidewall of the initial target structure and a portion of the substrate located below the target structure are oxidized to form a second sub-portion. The first sub-portion and the second sub-portion are connected to each other to form the insulating structure. The plurality of trench structures are located in the space defined by the insulating structure.

[0020] In some embodiments, the oxidation process includes a dry oxidation process and / or a wet oxidation process.

[0021] In some embodiments, the reaction temperature of the oxidation process ranges from 550°C to 1300°C.

[0022] In some embodiments, the capacitor structure further covers the upper surface of the substrate and the insulating structure; and the method further comprises:

[0023] Etching a portion of the capacitor structure located on the substrate and the insulating structure to form a step structure at an edge of the capacitor structure;

[0024] forming a second dielectric layer, wherein the second dielectric layer at least covers the step structure;

[0025] Etching the second dielectric layer to form a plurality of contact holes, wherein the plurality of contact holes correspond to each other and expose the plurality of electrode layers of the stepped structure;

[0026] A contact plug is formed in the contact hole, and the contact plug is electrically connected to the electrode layer.

[0027] The embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure includes: a substrate, the substrate including a substrate and an insulating structure located within the substrate; a plurality of groove structures, discretely arranged within the substrate; wherein the insulating structure includes at least one first sub-portion, the first sub-portion being located between two adjacent groove structures, and in the arrangement direction of the two adjacent groove structures, the extension length of the first sub-portion is equal to the distance between the two adjacent groove structures; a capacitor structure, including a plurality of electrode layers stacked and a first dielectric layer at least located between two adjacent electrode layers, the capacitor structure at least covering the inner walls of the plurality of groove structures. The insulating structure provided by the embodiment of the present disclosure includes at least a first sub-portion arranged between two adjacent groove structures, the material of the insulating structure having a high resistivity, and when the capacitor structure performs signal transmission within the substrate, especially high-frequency signal transmission, the presence of the first sub-portion having a high resistivity reduces the energy loss caused by electron movement between the capacitor structures, thereby reducing the delay and attenuation of the signal in the substrate.

[0028] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0030] Figure 1 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0031] Figure 2 for Figure 1 A schematic top view of the substrate and insulating structure;

[0032] Figure 3 A flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0033] Figure 4 The process flow of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 1 ;

[0034] Figure 5 The process flow of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 2 ;

[0035] Figure 6 The process flow of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 3 ;

[0036] Figure 7 The process flow of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 4 ;

[0037] Figure 8 The process flow of the semiconductor structure provided in the embodiment of the present disclosure during the manufacturing process Figure 5 . DETAILED DESCRIPTION

[0038] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0039] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0040] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0041] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both the above and below orientations. The device can be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] With the growing market demand for high-performance, miniaturized, and low-power chips, high-density silicon capacitors have broad application prospects in advanced packaging, particularly in high-performance computing, 5G communications, the Internet of Things (IoT), artificial intelligence (AI), and automotive electronics. The current mainstream high-density silicon capacitor technology is TSMC's Deep Trench Capacitor (DTC) technology. In the package, silicon capacitors can be placed in the middle of the package substrate or below the chip. This placement helps achieve lower equivalent series inductance (ESL) characteristics, thereby improving filtering performance.

[0045] In related technologies, high-resistance silicon can be used as the substrate material, and deep trench capacitors are typically formed in high-resistance silicon substrates. Compared to ordinary silicon substrates, high-resistance silicon has a lower carrier concentration and higher resistivity, typically exceeding 1000Ω·cm. It also has excellent insulation properties and chemical stability, thus reducing parasitic capacitance and signal loss in silicon capacitors. However, silicon is a semiconductor material, and deep trench capacitors formed in high-resistance silicon substrates suffer from high losses in high-frequency applications.

[0046] Based on this, the technical solution of the embodiment of the present disclosure is proposed.

[0047] In the embodiment of the present disclosure, an insulating structure is provided in the substrate, and the insulating structure includes at least a first sub-portion provided between two adjacent groove structures. The material of the insulating structure has a high resistivity. When the capacitor structure transmits signals in the substrate, especially high-frequency signals, the presence of the first sub-portion with a high resistivity reduces the energy loss caused by the movement of electrons between the capacitor structures, thereby reducing the delay and attenuation of the signal in the substrate.

[0048] The following is a detailed description of the specific embodiments of the present disclosure in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present disclosure.

[0049] like Figure 1 and Figure 2As shown, the present disclosure provides a semiconductor structure, including: a substrate 10, including 11 and an insulating structure 13; a plurality of groove structures 12, separately arranged in the substrate 10; wherein the insulating structure 13 includes at least one first sub-portion 131, the first sub-portion 131 is located between two adjacent groove structures 12, and in the arrangement direction of the two adjacent groove structures 12, the extension length of the first sub-portion 131 is equal to the distance between the two adjacent groove structures 12; a capacitor structure 14, including a plurality of electrode layers 141 stacked and a first dielectric layer 142 located at least between two adjacent electrode layers 141, and the capacitor structure 14 covers at least the inner walls of the plurality of groove structures 12.

[0050] In some embodiments, substrate 11 may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate or a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, substrate 11 may be a high-resistance silicon substrate.

[0051] In some embodiments, the trench structure 12 may be a trench with a high aspect ratio. Figure 2 As shown, in some embodiments, the plurality of trench structures 12 can be arranged along a first direction parallel to the plane of the substrate 10 and extend along a second direction parallel to the plane of the substrate 10, with the first direction and the second direction intersecting. The trench structures 12 and the first sub-portions 131 of the insulating structure 13 are alternately arranged along the first direction. However, this is not limiting, and the plurality of trench structures 12 can also have other arrangements, such as an array arrangement, with the first sub-portion 131 located between two adjacent trench structures 12 in any direction.

[0052] In the embodiment of the present disclosure, the capacitor structure 14 formed in the two adjacent trench structures 12 is separated by the first sub-section 131. In the embodiment of the present disclosure, the first sub-section 131 is provided between the two adjacent trench structures 12, and the material of the insulating structure 13 is an insulating material. Compared with high-resistance silicon, the insulating material has a higher resistivity (for example, at 10 8 Ω•m to 10 22 Ω•m), lower dielectric constant (e.g., between 3.9 and 4.1), and lower dielectric loss (e.g., less than 10 -3), with almost no free carriers inside, when capacitor structure 14 transmits signals within substrate 10, especially high-frequency signals, insulating structure 13 can reduce energy loss and parasitic capacitance caused by electron motion between capacitor structures 14. This allows the electric field to more easily penetrate insulating structure 13, thereby reducing energy loss during signal propagation and, in turn, signal delay and attenuation within substrate 10. Dielectric loss, also known as loss tangent, is a measure of a material's ability to dissipate energy in an AC field.

[0053] In the present application, in the arrangement direction of two adjacent groove structures 12, the extension length of the first sub-portion 131 located between the two adjacent groove structures 12 is equal to the distance between the two adjacent groove structures 12, that is, there is no conductor or semiconductor capable of carrier transmission between the two adjacent groove structures 12, thereby avoiding insertion loss between the two adjacent capacitor structures 14.

[0054] like Figure 1 and Figure 2 As shown, in some embodiments, a plurality of groove structures 12 and a first sub-portion 131 located between two adjacent groove structures 12 are defined as a target structure 20; the insulating structure 13 also includes a second sub-portion 132 connected to the first sub-portion 131, the second sub-portion 132 surrounds the side wall of the target structure 20 and is partially located below the target structure 20, and the plurality of groove structures 12 are located in the space enclosed by the insulating structure 13, the second sub-portion 132 separates the plurality of groove structures 12 from the substrate 11, and the material of the second sub-portion 132 is an insulating material. In this way, the existence of the second sub-portion 132 further reduces the signal delay and attenuation during signal transmission.

[0055] In some embodiments, the material of the insulating structure 13 includes silicon oxide, which has a high resistivity, a low dielectric constant and a low dielectric loss, thus achieving the above-mentioned effect.

[0056] In actual operation, the substrate 11 may first be etched to form a plurality of trench structures 12 and a spacer structure between two adjacent trench structures 12 within the substrate 11. Subsequently, a dry oxidation process and / or a wet oxidation process may be performed on the substrate 11 from the sidewalls and bottoms of the plurality of trench structures 12 to completely oxidize the spacer structure between the two adjacent trench structures 12 to form a first sub-portion 131, and a portion of the substrate 11 located below and on the peripheral sidewalls of the trench structures 12 and the spacer structure may be oxidized to form a second sub-portion 132. In the embodiment of the present disclosure, the insulating structure 13 is formed by performing an oxidation process on a portion of the substrate 11. Thus, the insulating structure 13 is more tightly bonded to the substrate 11 and has high mechanical stability, thereby improving the mechanical stability of the capacitor structure 14.

[0057] like Figure 1 As shown, in some embodiments, the capacitor structure 14 also covers a portion of the upper surface of the substrate 10. Specifically, the capacitor structure 14 covers at least the upper surface of the first sub-portion 131. The portions of the capacitor structure 14 located within the plurality of trench structures 12 are sequentially connected via the portions of the capacitor structure 14 located on the first sub-portion 131. The capacitor structure 14 may also cover the upper surface of the second sub-portion 132 and a portion of the upper surface of the substrate 11.

[0058] like Figure 1 As shown, the electrode layer 141 and the first dielectric layer 142 of the capacitor structure 14 are alternately stacked and conformally cover the inner wall of the groove structure 12 and part of the upper surface of the substrate 10. The material of the electrode layer 141 and the material of the first dielectric layer 142 can be a material with good step coverage.

[0059] In some embodiments, the materials of any two electrode layers 141 in the multiple electrode layers 141 may be the same or different, and the material of each electrode layer 141 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, etc. For example, the electrode layer 141 may be a titanium nitride film formed by an atomic layer deposition (ALD) process.

[0060] In some embodiments, the first dielectric layer 142 may also cover the topmost electrode layer 141 among the multiple stacked electrode layers 141; for example, when there are two electrode layers 141, the number of first dielectric layers 142 may also be two layers, one of which is located between two adjacent electrode layers 141, and the other covers the topmost electrode layer 141.

[0061] In actual operation, the material of the first dielectric layer 142 can be one or more of silicon nitride, zirconium oxide, aluminum oxide, hafnium oxide, etc. formed by atomic layer deposition process or furnace tube method, and when the material of the first dielectric layer 142 is multilayer, the materials of any two first dielectric layers 142 in the multiple first dielectric layers 142 can be the same or different.

[0062] like Figure 1As shown, in some embodiments, the semiconductor structure further includes a third dielectric layer 15. The third dielectric layer 15 covers at least the upper surface of the substrate 11, and a portion of the third dielectric layer 15 is located between the substrate 11 and the capacitor structure 14, thereby protecting the substrate 11 and electrically isolating the substrate 11 from the capacitor structure 14. In some embodiments, the third dielectric layer 15 may also cover the upper surface of the insulating structure 13. The third dielectric layer 15 may be formed by a thin film deposition process or by performing an oxidation process on the surface of the substrate 11. The material of the third dielectric layer 15 includes, but is not limited to, one or more of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), and an oxynitride (e.g., silicon oxynitride).

[0063] like Figure 1 As shown, in some embodiments, the edge of a portion of the capacitor structure 14 located on the upper surface of the substrate 10 includes a stepped structure 16. The semiconductor structure further includes: a second dielectric layer 17 covering at least the stepped structure 16; and a plurality of contact plugs 19 extending from the upper surface of the second dielectric layer 17 to the surfaces of the plurality of electrode layers 141 of the stepped structure 16 and electrically connected to the plurality of electrode layers 141 in a one-to-one correspondence.

[0064] In some embodiments, the second dielectric layer 17 further fills the remaining space of the trench structure 12 and covers the entire capacitor structure 14. Figure 1 As shown, in some embodiments, the second dielectric layer 17 includes a first sublayer 171 and a second sublayer 172 , the first sublayer 171 fills the remaining space of the groove structure 12 and covers the electrode layer 141 located at the top layer; the second sublayer 172 covers the first sublayer 171 and the step structure 16 .

[0065] In actual operation, the first sublayer 171 and the second sublayer 172 can be formed in different process steps, and the material of the first sublayer 171 and the material of the second sublayer 172 can be the same or different. For example, the material of the first sublayer 171 and the material of the second sublayer 172 include but are not limited to one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride), and nitrogen oxides (such as silicon oxynitride).

[0066] like Figure 1 As shown, the step structure 16 includes a plurality of upward step surfaces 161. The step surface 161 can be the electrode layer 141 or the first dielectric layer 142. When the step surface 161 is the electrode layer 141, the contact plug 19 penetrates the second dielectric layer 17 to reach the surface of the electrode layer 141 and is electrically connected thereto. When the step surface 161 is the first dielectric layer 142, the contact plug 19 penetrates the second dielectric layer 17 and the first dielectric layer 142 serving as the step surface 161 to reach the electrode layer 141 located below the first dielectric layer 142 and is electrically connected thereto.

[0067] In some embodiments, the number of electrode layers 141 is n, where n is a positive integer greater than or equal to 2. The n electrode layers 141 can be sequentially designated as layer 1, layer 2, ..., layer n from bottom to top. In some embodiments, the plurality of contact plugs 19 include one or more first contact plugs 191 and one or more second contact plugs 192. The one or more first contact plugs 191 are electrically connected to one or more odd-numbered electrode layers 141 in a one-to-one correspondence, and the one or more second contact plugs 192 are electrically connected to one or more even-numbered electrode layers 141 in a one-to-one correspondence.

[0068] In some embodiments, the semiconductor structure further includes a first interconnect layer 211 and a second interconnect layer 212 located on the second dielectric layer 17, the first interconnect layer 211 is electrically connected to the first contact plug 191, and the odd-numbered electrode layers 141 are electrically connected to each other through the first interconnect layer 211 and the first contact plug 191 to serve as one electrode of the capacitor structure 14; the second interconnect layer 212 is electrically connected to the second contact plug 192, and the even-numbered electrode layers 141 are electrically connected to each other through the second interconnect layer 212 and the second contact plug 192 to serve as another electrode of the capacitor structure 14.

[0069] In actual operation, the materials of the contact plug 19 , the first interconnection layer 211 and the second interconnection layer 212 may be copper, aluminum, or other metal materials (such as tungsten) or metal compound materials (such as titanium nitride) with better high temperature stability.

[0070] It should be noted that Figure 1 The number of electrode layers 141 shown in FIG is 3, and the number of first dielectric layers 142 is 2. However, the present invention is not limited thereto, and the number of electrode layers 141 can be more or less, for example, 2, 5, 7, 10, etc.

[0071] The present disclosure also provides a method for manufacturing a semiconductor structure. Figure 3 As shown, the method includes the following steps:

[0072] Step S101: providing a substrate, and forming a plurality of discrete trench structures and an insulating structure in the substrate, wherein the insulating structure includes at least one first sub-portion, the first sub-portion being located between two adjacent trench structures, and an extension length of the first sub-portion being equal to a distance between the two adjacent trench structures in an arrangement direction of the two adjacent trench structures;

[0073] Step S102 : forming a capacitor structure covering at least the inner walls of the plurality of trench structures, wherein the capacitor structure includes a plurality of stacked electrode layers and a first dielectric layer located at least between two adjacent electrode layers.

[0074] The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is further described in detail below with reference to the accompanying drawings.

[0075] First, execute step S101, as Figures 4 to 6 As shown, a substrate 11 is provided, and a plurality of discretely arranged groove structures 12 and an insulating structure 13 are formed in the substrate 11. The insulating structure 13 includes at least one first sub-portion 131. The first sub-portion 131 is located between two adjacent groove structures 12, and in the arrangement direction of the two adjacent groove structures 12, the extension length of the first sub-portion 131 is equal to the distance between the two adjacent groove structures 12.

[0076] In some embodiments, substrate 11 may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate or a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, substrate 11 may be a high-resistance silicon substrate.

[0077] Specifically, a plurality of discrete trench structures 12 and an insulating structure 13 are formed in the substrate 11, including:

[0078] The substrate 11 is etched to form a plurality of discrete trench structures 12 in the substrate 11, and a spacer structure 111 (eg, a spacer structure 111 located between two adjacent trench structures 12) Figures 4 and 5 );

[0079] An oxidation process is performed on a portion of the substrate 11 from the sidewalls and bottom of the plurality of trench structures 12, so that the spacer structure 111 located between two adjacent trench structures 12 is completely oxidized to form a first sub-portion 131 (eg, Figure 6 ).

[0080] See again Figure 4 In some embodiments, before forming the trench structure 12 in the substrate 11, a third dielectric layer 15 may be formed on the surface of the substrate 11. The third dielectric layer 15 is used to protect the substrate 11 during the subsequent formation of the trench structure 12. The third dielectric layer 15 may be formed by one or more thin film deposition processes or by performing an oxidation process on the surface of the substrate 11. The material of the third dielectric layer 15 includes, but is not limited to, one or more of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), and an oxynitride (e.g., silicon oxynitride).

[0081] See again Figure 4 and Figure 5In actual operation, the trench structure 12 can be formed in the substrate 11 by the following method: first, a mask pattern M is formed on the third dielectric layer 15, and then the third dielectric layer 15 is etched using the mask pattern M as a mask to form an opening (not marked) exposing the substrate 11, and then the substrate 11 exposed by the opening is etched to form a plurality of trench structures 12.

[0082] In some embodiments, the trench structure 12 may be a trench with a high aspect ratio. Figure 2 As shown, in some embodiments, the plurality of groove structures 12 can be arranged along a first direction parallel to the plane of the substrate 10 and extend along a second direction parallel to the plane of the substrate 10. The spacing structure 111 located between two adjacent groove structures 12 can be a wall-like structure, with the first direction and the second direction intersecting. However, this is not limiting. The plurality of groove structures 12 can also have other arrangements, such as an array arrangement, with the first sub-section 131 located between two adjacent groove structures 12 in any direction.

[0083] like Figure 6 As shown, before the oxidation process is performed on the substrate 11, the third dielectric layer 15 located on the surface of the substrate 11 may not be removed; but not limited to this, the third dielectric layer 15 may also be removed, and when the oxidation process is subsequently performed, an oxide layer may be re-formed on the upper surface of the substrate 11.

[0084] like Figure 6 As shown, in actual operation, when performing an oxidation process on the substrate 11 from the sidewalls of the plurality of trench structures 12, the width of the portion of the substrate 11 oxidized during the oxidation process can be made greater than or equal to half the extension length of the spacer structure 111 in the arrangement direction of two adjacent trench structures 12. In this way, after performing the oxidation process on the portion of the substrate 11, the spacer structure 111 can be completely oxidized, and in the arrangement direction of the two adjacent trench structures 12, the extension length of the formed first sub-portion 131 is equal to the distance between the two adjacent trench structures 12. Here, the width of the portion of the substrate 11 oxidized refers to the dimension of the portion of the substrate 11 oxidized extending from the sidewalls of the trench structure 12 toward the interior of the substrate 11 in a direction parallel to the substrate 11.

[0085] See again Figure 6In some embodiments, the plurality of trench structures 12 and the isolation structure 111 are defined as an initial target structure 20'; an oxidation process is performed on a portion of the substrate 11 from the sidewalls and bottoms of the plurality of trench structures 12, further comprising: oxidizing a portion of the substrate 11 surrounding the sidewalls of the initial target structure 20' and a portion of the substrate 11 located below the initial target structure 20' to form a second sub-portion 132. The first sub-portion 131 and the second sub-portion 132 are connected to form an insulating structure 13, and the plurality of trench structures 12 are located within a space defined by the insulating structure 13. In some embodiments, the plurality of trench structures 12 and the first sub-portion 131 formed after oxidation are defined as a target structure 20, and the second sub-portion 132 surrounds the sidewalls of the target structure 20 and is located partially below the target structure 20.

[0086] In actual operation, the first sub-portion 131 and the second sub-portion 132 can be formed simultaneously in a single oxidation process. In some examples, an oxidation process can be performed on a portion of the substrate 11 using a wet oxidation process, a dry oxidation process, or a combination of a wet oxidation process and a dry oxidation process to form the insulating structure 13. In the embodiment of the present disclosure, the insulating structure 13 is formed by performing an oxidation process on a portion of the substrate 11. In this way, the insulating structure 13 is more tightly bonded to the substrate 11 and has high mechanical stability, thereby improving the mechanical stability of the capacitor structure 14.

[0087] In some embodiments, the substrate 11 is made of silicon, and an insulating structure 13 made of silicon oxide is formed by performing an oxidation process on a portion of the substrate 11. The chemical reaction formula for the wet oxidation process is: Si (solid) + H2O (gas) → SiO2 (solid) + 2H2 (gas); the chemical reaction formula for the dry oxidation process is: Si (solid) + O2 (gas) → SiO2 (solid).

[0088] In some embodiments, the reaction temperature of the oxidation process ranges from 550°C to 1300°C (including endpoint values), such as 550°C, 850°C, 1000°C, 1100°C, 1250°C, etc. By controlling the reaction temperature within the above range, the spacer structure 111 can be fully oxidized so that the spacer structure 111 is completely oxidized.

[0089] Next, execute step S102, as shown in FIG. Figure 7 As shown, a capacitor structure 14 is formed that at least covers the inner walls of the plurality of trench structures 12 . The capacitor structure 14 includes a plurality of stacked electrode layers 141 and a first dielectric layer 142 located at least between two adjacent electrode layers 141 .

[0090] In the embodiment of the present disclosure, a first sub-portion 131 is provided between two adjacent trench structures 12, that is, the capacitor structures 14 located in adjacent trench structures 12 are separated by the first sub-portion 131, and the material of the insulating structure 13 is an insulating material. Compared with high-resistance silicon, the insulating material has a higher resistivity (for example, between 108Ω·m and 1022Ω·m), a lower dielectric constant (for example, between 3.9 and 4.1), and a lower dielectric loss (for example, less than 10 -3 ), with almost no free carriers inside, when capacitor structure 14 transmits signals within substrate 10, especially high-frequency signals, insulating structure 13 can reduce energy loss and parasitic capacitance caused by electron motion between capacitor structures 14. This allows the electric field to more easily penetrate insulating structure 13, thereby reducing energy loss during signal propagation and, in turn, signal delay and attenuation within substrate 10. Dielectric loss, also known as loss tangent, is a measure of a material's ability to dissipate energy in an AC field.

[0091] In the present application, the extension length of the first sub-section 131 is equal to the distance between two adjacent groove structures 12, that is, the portion of the substrate 11 located between the two adjacent groove structures 12 is completely oxidized, and there is no conductor or semiconductor capable of carrier transmission between the two adjacent groove structures 12, thereby avoiding insertion loss between the two adjacent capacitor structures 14.

[0092] In some embodiments, the insulating structure 13 also includes a second sub-portion 132 connected to the first sub-portion 131. The second sub-portion 132 surrounds the side wall of the target structure 20 and is partially located below the target structure 20. The multiple groove structures 12 are located in the space surrounded by the insulating structure 13. The second sub-portion 132 separates the multiple groove structures 12 from the substrate 11. The material of the second sub-portion 132 is an insulating material. In this way, the existence of the second sub-portion 132 further reduces the signal delay and attenuation during signal transmission.

[0093] In some embodiments, the material of the insulating structure 13 includes silicon oxide, which has a high resistivity, a low dielectric constant and a low dielectric loss, thus achieving the above-mentioned effect.

[0094] like Figure 7 As shown, in some embodiments, the capacitor structure 14 further covers the upper surfaces of the substrate 11 and the insulating structure 13. In actual operation, electrode layers 141 and first dielectric layers 142 can be alternately deposited on the inner wall of the trench structure 12 and on the substrate 11 and the insulating structure 13 using one or more thin film deposition processes. In some embodiments, the capacitor structure 14 further covers a third dielectric layer 15, which is located between the upper surfaces of the substrate 11 and the insulating structure 13 and the capacitor structure 14.

[0095] Here, the thin film deposition process includes chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, chemical plating, sputtering, evaporation, etc.

[0096] In some embodiments, the material of the electrode layer 141 and the material of the first dielectric layer 142 may be materials with good step coverage.

[0097] In some embodiments, the materials of any two electrode layers 141 in the multiple electrode layers 141 may be the same or different, and the material of each electrode layer 141 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, etc. For example, the electrode layer 141 may be a titanium nitride film formed by an atomic layer deposition (ALD) process.

[0098] In some embodiments, the first dielectric layer 142 may also cover the topmost electrode layer 141 among the multiple stacked electrode layers 141; for example, when there are two electrode layers 141, the number of first dielectric layers 142 may also be two layers, one of which is located between two adjacent electrode layers 141, and the other covers the topmost electrode layer 141.

[0099] In actual operation, the material of the first dielectric layer 142 can be one or more of silicon nitride, zirconium oxide, aluminum oxide, hafnium oxide, etc. formed by atomic layer deposition process or furnace tube method, and when the material of the first dielectric layer 142 is multilayer, the materials of any two first dielectric layers 142 in the multiple first dielectric layers 142 can be the same or different.

[0100] like Figure 8 As shown, in some embodiments, the method further includes: etching a portion of the capacitor structure 14 located on the substrate 11 and the insulating structure 13 to form a stepped structure 16 at the edge of the capacitor structure 14; the stepped structure 16 includes a plurality of upward step surfaces 161, and the step surfaces 161 can be the electrode layer 141 or the first dielectric layer 142. In actual operation, multiple photolithography and etching processes can be used to form the stepped structure 16.

[0101] In some embodiments, the method further includes: forming a second dielectric layer 17, wherein the second dielectric layer 17 at least covers the step structure 16. Specifically, forming the second dielectric layer 17 includes: first, as shown in FIG. Figure 7 As shown, after forming the capacitor structure 14, a first sub-layer 171 is formed, and the first sub-layer 171 fills the remaining space of the trench structure 12 and covers the capacitor structure 14; then, as shown in FIG. Figure 8As shown, in the process of forming the step structure 16, part of the first sub-layer 171 is removed, and the remaining first sub-layer 171 fills the remaining space of the trench structure 12 and covers the electrode layer 141 located at the top layer; then, as shown in FIG. Figure 1 As shown, a second sub-layer 172 is formed, and the second sub-layer 172 covers the first sub-layer 171 and the stepped structure 16 .

[0102] The material of the first sublayer 171 and the material of the second sublayer 172 can be the same or different. For example, the material of the first sublayer 171 and the material of the second sublayer 172 include but are not limited to one or more of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), and oxynitrides (e.g., silicon oxynitride).

[0103] Continue to see Figure 1 In some embodiments, after forming the second dielectric layer 17 , the method further includes: etching the second dielectric layer 17 to form a plurality of contact holes V, wherein the plurality of contact holes V correspond to and expose the plurality of electrode layers 141 of the step structure 16 ; forming contact plugs 19 in the contact holes V, wherein the contact plugs 19 are electrically connected to the electrode layers 141 .

[0104] Specifically, when the step surface 161 of the step structure 16 is the electrode layer 141, the contact plug 19 penetrates the second dielectric layer 17 to reach the surface of the electrode layer 141 and is electrically connected thereto; when the step surface 161 is the first dielectric layer 142, the contact plug 19 penetrates the second dielectric layer 17 and the first dielectric layer 142 serving as the step surface 161 to reach the electrode layer 141 located below the first dielectric layer 142 and is electrically connected thereto.

[0105] In some embodiments, the number of electrode layers 141 is n, where n is a positive integer greater than or equal to 2. The n electrode layers 141 can be sequentially designated as layer 1, layer 2, ..., layer n from bottom to top. In some embodiments, the plurality of contact plugs 19 include one or more first contact plugs 191 and one or more second contact plugs 192. The one or more first contact plugs 191 are electrically connected to one or more odd-numbered electrode layers 141 in a one-to-one correspondence, and the one or more second contact plugs 192 are electrically connected to one or more even-numbered electrode layers 141 in a one-to-one correspondence.

[0106] like Figure 1As shown, in some embodiments, the method further includes: forming a first interconnection layer 211 and a second interconnection layer 212 on the second dielectric layer 17, the first interconnection layer 211 is electrically connected to the first contact plug 191, the odd-numbered electrode layers 141 are electrically connected to each other through the first interconnection layer 211 and the first contact plug 191 to serve as one electrode of the capacitor structure 14, the second interconnection layer 212 is electrically connected to the second contact plug 192, and the even-numbered electrode layers 141 are electrically connected to each other through the second interconnection layer 212 and the second contact plug 192 to serve as another electrode of the capacitor structure 14.

[0107] In actual operation, the materials of the contact plug 19 , the first interconnection layer 211 and the second interconnection layer 212 may be copper, aluminum, or other metal materials (such as tungsten) or metal compound materials (such as titanium nitride) with better high temperature stability.

[0108] It should be noted that Figures 7 and 8 as well as Figure 1 The number of electrode layers 141 shown in FIG is 3, and the number of first dielectric layers 142 is 2. However, the present invention is not limited thereto, and the number of electrode layers 141 can be more or less, for example, 2, 5, 7, 10, etc.

[0109] It should be noted that the above is only a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the scope of protection of this application.

Claims

1. A semiconductor structure, characterized in that include: A substrate, comprising a substrate and an insulating structure located within the substrate; A plurality of trench structures are discretely disposed in the substrate; wherein the insulating structure includes at least one first sub-portion, the first sub-portion being located between two adjacent trench structures, and an extension length of the first sub-portion being equal to a distance between the two adjacent trench structures in an arrangement direction of the two adjacent trench structures; The plurality of trench structures and a first sub-portion located between two adjacent trench structures are defined as a target structure; the insulating structure further includes a second sub-portion connected to the first sub-portion, the second sub-portion surrounding the sidewall of the target structure and partially located below the target structure, and the plurality of trench structures are located within a space defined by the insulating structure; The capacitor structure comprises a plurality of stacked electrode layers and a first dielectric layer at least between two adjacent electrode layers. The capacitor structure at least covers inner walls of the plurality of groove structures.

2. The semiconductor structure according to claim 1, wherein: The insulating structure is made of silicon oxide.

3. The semiconductor structure according to claim 1, wherein: The capacitor structure further covers a portion of the upper surface of the substrate, and an edge of the portion of the capacitor structure covering the upper surface of the substrate includes a step structure; The semiconductor structure further includes: a second dielectric layer covering at least the step structure; and a plurality of contact plugs extending from the top surface of the second dielectric layer to surfaces of the plurality of electrode layers of the step structure and electrically connected to the plurality of electrode layers in a one-to-one correspondence.

4. A method for manufacturing a semiconductor structure, characterized in that: include: A substrate is provided, and a plurality of discrete trench structures and an insulating structure are formed in the substrate, wherein the insulating structure includes at least one first sub-portion, the first sub-portion being located between two adjacent trench structures, and an extension length of the first sub-portion being equal to a distance between the two adjacent trench structures in an arrangement direction of the two adjacent trench structures; wherein: A plurality of discrete trench structures and insulating structures are formed in the substrate, including: Etching the substrate to form a plurality of discrete trench structures and a spacer structure between two adjacent trench structures in the substrate; defining the plurality of trench structures and the spacer structure between two adjacent trench structures as an initial target structure; performing an oxidation process on a portion of the substrate from the sidewalls and bottoms of the plurality of trench structures, so that a spacer structure located between two adjacent trench structures is completely oxidized to form a first sub-portion, and a portion of the substrate surrounding the sidewalls of the initial target structure and a portion of the substrate located below the initial target structure are oxidized to form a second sub-portion, wherein the first sub-portion and the second sub-portion are connected to each other to form the insulating structure, and the plurality of trench structures are located within a space defined by the insulating structure; A capacitor structure is formed that at least covers the inner walls of the plurality of groove structures. The capacitor structure includes a plurality of stacked electrode layers and a first dielectric layer located at least between two adjacent electrode layers.

5. The manufacturing method according to claim 4, characterized in that The oxidation process includes a dry oxidation process and / or a wet oxidation process.

6. The manufacturing method according to claim 4, characterized in that The reaction temperature of the oxidation process ranges from 550°C to 1300°C.

7. The manufacturing method according to claim 4, characterized in that The capacitor structure also covers the upper surface of the substrate and the insulating structure; and the method further includes: Etching a portion of the capacitor structure located on the substrate and the insulating structure to form a step structure at an edge of the capacitor structure; forming a second dielectric layer, wherein the second dielectric layer at least covers the step structure; Etching the second dielectric layer to form a plurality of contact holes, wherein the plurality of contact holes correspond to each other and expose the plurality of electrode layers of the stepped structure; A contact plug is formed in the contact hole, and the contact plug is electrically connected to the electrode layer.

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