Integrated circuit (IC) with corrugated channel structure with vertically separated source and body contact regions

Abstract

The application relates to an integrated circuit (IC) having a corrugated channel structure with vertically separated source and body contact regions. An IC device (200) includes one or more corrugated channel structures (204A, 204B) formed in or over a semiconductor substrate (202), where the corrugated channel structure (204A) includes a first sidewall surface (216A), a second sidewall surface (216B), and a top surface (208). In an example, the IC device (200) includes a first contact region (229A, 229B) having a first conductivity type extending into a sidewall surface (216A, 216B) of the corrugated channel structure (204A), and a second contact region (231) having an opposite second conductivity type extending into a horizontal surface (203, 214) adjacent to the sidewall surface (216A, 216B).

Description

Technical Field

[0001] The disclosed embodiments generally relate to the field of integrated circuits (ICs) and IC manufacturing. More specifically, but not exclusively, the disclosed embodiments relate to IC devices that include one or more corrugated channel structures. Background Art

[0002] A FinFET is a three-dimensional (3D) MOSFET transistor type in which the channel includes a non-planar structure similar to a "fin" and includes semiconductor material protruding from a semiconductor substrate. FinFETs are considered candidates for future advanced CMOS technology nodes due to the excellent gate control of the FinFET over the channel, which in turn results in faster switching times, improved short-channel effect immunity, higher current density, and improved I on / I off ratio. As the integration of FinFET technology continues to become more popular, there is an increasing need for improvements in various aspects of FinFET design. Summary of the Invention

[0003] A simplified overview is presented below to provide a basic understanding of some examples of the present disclosure. This summary of the invention is not an extensive overview of the examples and is neither intended to identify key or important elements of the examples nor to depict their scope. Indeed, the main purpose of the summary of the invention is to present some concepts of the present disclosure in a simplified form as a prelude to the more detailed description presented in the subsequent sections below.

[0004] In one example, a method of manufacturing an IC device is disclosed. The method may particularly include: forming a corrugated channel structure over a semiconductor substrate including a substrate material, the corrugated channel structure having a vertical height along a surface normal relative to a top surface of the semiconductor substrate; and forming a first contact region of a first conductivity type extending into sidewall surfaces of the corrugated channel structure and a second contact region of a second opposite conductivity type extending into horizontal surfaces adjacent to the sidewall surfaces. In one example, the first contact region may be a body contact region and the second contact region may be a source contact region. In another example, the first contact region may be a source contact region and the second contact region may be a body contact region.

[0005] In one example, an IC device is disclosed, which may particularly include: a corrugated channel structure over a semiconductor substrate; and a first contact region of a first conductivity type extending into sidewall surfaces of the corrugated channel structure and a second contact region of a second opposite conductivity type extending into horizontal surfaces adjacent to the sidewall surfaces. Brief Description of the Drawings

[0006] In the figures of the drawings, embodiments of the present disclosure are illustrated by way of example and not limitation. Different references to "an" or "one" embodiment in the present disclosure do not necessarily refer to the same embodiment, and such references may mean at least one. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, such feature, structure, or characteristic is feasible in combination with other embodiments whether or not explicitly described. For the purpose of facilitating drafting and / or presentation and supporting the concept, the shapes depicted in the accompanying drawings are simplified. It does not limit the scope of the examples of the present disclosure in terms of size, count, aspect ratio, contour, or specific angles and radii of transitions and / or other related features that may be present in the exemplary embodiments.

[0007] Terms describing fabrication methods such as "implantation" and its derivatives are examples and do not reflect all methods of doping semiconductor materials in the exemplary embodiments, which may include vapor or gas phase, solid source, liquid source, and plasma and beam line implants. Alternative methods are likely and may be used in additional and / or alternative arrangements as needed, depending on factors such as performance, cost, and availability.

[0008] To illustrate one or more exemplary embodiments of the present disclosure, the drawings are incorporated into the specification and form a part of the specification. The various advantages and features of the present disclosure will be understood from the following detailed description taken in conjunction with the appended claims and with reference to the accompanying drawings, in which:

[0009] Figure 1A A top plan view depicting an IC device including one or more corrugated channel structures according to some examples of the present disclosure, wherein a vertically separated body and source contact regions may be provided;

[0010] Figure 1B-1 to 1B-3 Depicting a cross-sectional view of the IC device shown in Figure 1A along three cross-sectional planes respectively passing through the drain region, channel region, and source / body region of the corrugated channel structure;

[0011] Figure 2A-1 to 2A-3 to Figure 2K-1 to 2K-3 Depicting cross-sectional views of the IC device at various formation stages in a process flow for fabricating body contact regions and source contact regions in different surfaces of the corrugated channel structure according to examples of the present disclosure; and

[0012] Figure 3 is a flow chart of an IC manufacturing method according to some examples of the present disclosure. Detailed Description

[0013] The examples of the present disclosure are described with reference to the accompanying drawings, in which like reference numerals generally refer to like elements throughout. The figures are not drawn to scale and are provided only to illustrate the examples. Many specific details, relationships, and methods are set forth below to provide an understanding of one or more examples. However, it should be understood that some examples may be practiced without these specific details. In other instances, well-known subsystems, components, structures, and techniques have not been shown in detail so as not to obscure an understanding of the examples. Thus, the examples of the present disclosure may be practiced without such specific components.

[0014] Additionally, terms such as "coupled" and "connected" and their derivatives may be used in the following detailed description, claims, or both. It should be understood that these terms are not necessarily intended as synonyms for each other. "Coupled" may be used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, cooperate or interact with each other. "Connected" may be used to indicate the establishment of communication between two or more elements that are coupled to each other, i.e., a communication relationship. Additionally, in one or more examples set forth herein, generally speaking, if an element can be programmed to perform or is otherwise structurally arranged to perform a certain function, then the element, component, or module may be configured to perform that function.

[0015] In the context of improving the performance of FinFET devices, examples of IC devices including one or more raised channel structures and their fabrication will be set forth below. Similar to planar MOSFET devices, FinFETs can also exhibit sensitivity to performance trade - offs, such as on - resistance (R sp ) versus safe operating area (SOA), where the SOA can be defined as the voltage and current conditions under which the device can be expected to operate without damage, which in turn can involve the breakdown voltage BVDSS of the device. Additionally, FinFETs also suffer from parasitic bipolar effects that can affect device operation. In both of these conditions, internal resistances, such as gate - to - body resistance and / or gate - to - source resistance, typically play an important role.

[0016] Examples of the present disclosure recognize these and other related performance constraints and provide a contact region architecture for FinFET devices, where by leveraging the 3 - dimensional configuration of the fins, low - ohmic contact regions for both the body and source terminals can be provided on different surfaces of the raised fins in a region close to the gate of the FinFET. In some arrangements, the examples herein may be configured to reduce the source path resistance as well as the body path resistance in a FinFET by placing the body and source contact regions closer to the gate and thus placing the active channel on surfaces that can be separated in the vertical dimension. A lower source path resistance is expected to reduce the overall device resistance, thereby improving R spPerformance. Additionally, it is expected that the resistance in the body of the device is reduced to reduce the bias of parasitic bipolar junction transistors that snap back during high current / voltage conditions. Accordingly, it is also expected that the breakdown performance of the device is improved. In additional and / or alternative arrangements, only a subset of the fins of the FinFET may be selected for fabricating the source and / or body contact regions, thereby further reducing the overall contact path resistance. While such examples provide structures and processes that may advantageously assist in modulating the performance trade-offs of the FinFET in a more optimal manner, no specific results are claimed unless explicitly recited in a particular claim.

[0017] Referring now to the drawings, Figure 1A A top plan view of an IC device 100A including one or more corrugated channel structures or "fins" is depicted in accordance with some examples of the present disclosure, where vertically separated body and source contact regions may be provided. Figure 1B-1 to 1B-3 Collectively depict cross-sectional views of the IC device 100A shown in Figure 1A through different regions of the corrugated channel structure formed in accordance with some examples of the present disclosure. Depending on the implementation and application, the exemplary IC device 100A may represent any type of stand-alone FinFET device or a portion of an integrated microelectronic device that includes one or more FinFETs integrated with various other types of circuitry. In some arrangements, the IC device 100A or at least a portion thereof may illustrate a device, such as, but not limited to, a metal oxide semiconductor (DEMOS) field effect transistor (FET) device including a folded drain extension, a laterally diffused MOS (LDMOS) FinFET device, and a device configured for high voltage power applications (e.g., having an appropriate breakdown voltage (V bd )) and a specific on-resistance (R sp)Features), low-voltage logic applications, high-voltage radio frequency (RF) applications, etc. of FinFETs. Additionally, according to embodiments and / or applications, the IC device 100A can be fabricated in silicon or other semiconductor materials as mentioned below, such as a bulk FinFET, an epitaxial FinFET, a silicon-on-insulator (SOI) FinFET, etc. In an exemplary arrangement, the IC device 100A can include one or more FinFETs, each FinFET comprising a plurality of fins or corrugated channel structures 104A, 104B formed in a semiconductor substrate 108 or a region of the substrate 108, which semiconductor substrate or region of the substrate can include any suitable semiconductor material having an appropriate conductivity type (e.g., in a bulk material or in a well region, etc.) and having a first conductivity type, such as p-type, as used in various disclosed examples. In some arrangements, adjacent regions or FinFETs can be arranged in parallel connection or, alternatively, isolated from each other, such that in the first case a channel is formed across multiple fins / grooves and in the second case one or more fin channels defined by the grooves are formed. Additionally, adjacent corrugated channel structures of the FinFET can be separated by corresponding trenches formed in the substrate 108 between the corrugated channel structures, e.g., as illustrated by trench 106 formed between corrugated channel structures 104A, 104B.

[0018] For example, a first FinFET 102A and a second FinFET 102B are shown as part of the IC device 100A, wherein the corrugated channel structures 104A and 104B of each FinFET 102A, 102B can be appropriately doped to form a plurality of regions, such as source regions, body regions, channel regions, and drain regions, for facilitating the operation of the FinFET 102A / 102B. As will be further elaborated below, one or more source and body contact regions of the FinFET device can be formed in the same part of the corrugated channel structure by utilizing the vertical configuration of the corrugated channel structure, e.g., relative to the Figure 1A and Figure 1B-1 to 1B-3 IC device 100A shown in along the Z-axis of the reference 3D X-Y-Z Cartesian coordinate system. In some optional arrangements in which a drift region is included in the exemplary FinFET, the drift region can be disposed between the channel region and the drain contact region and can be placed under a field plate, wherein the drift region has the same conductivity type as the drain contact region.

[0019] In some instances, suitable dopant materials can be used to dope different surfaces of the corrugated channel structures 104A, 104B of FinFETs 102A, 102B in their different regions. For example, depending on the type of contact region to be formed (e.g., source contact region or body contact region), one or more surfaces associated with a portion of the corrugated channel structure (e.g., the top surface of the corrugated channel structure, the sidewall surface of the corrugated channel structure, and / or the bottom surface adjacent to the trench) can be doped with different materials of appropriate conductivity. As will be further elaborated below, according to some examples herein, different combinations of one or more hard masks can be used in combination with beamline implantation techniques to implement a suitable doping process for selectively masking different surfaces of the corrugated channel structure depending on the desired combination of contact regions.

[0020] As Figure 1A shown, the corrugated channel structures 104A, 104B of FinFETs 102A and 102B extend along a first axis (e.g., the Y-axis of a reference X-Y-Z Cartesian coordinate system), where each corrugated channel structure associated with a particular FinFET can include a drain region, a channel region, and a region having both a source and a body contact region shared between the two FinFETs 102A and 102B. In some instances, the sequence of source / gate / drain regions with an appropriate body region can be reflected in an array such that a pattern of s / g / d / g / s / g / d / s... regions exists depending on the layout in the Y direction. Thus, a FinFET (e.g., FinFETs 102A, 102B) can appear to include three corresponding regions or portions that can be appropriately doped in a selective manner. By way of illustration, drain regions 110A and 110B, channel regions 112A and 112B are shown relative to FinFETs 102A and 102B, respectively, where the source / body region 114 is shared by both FinFETs 102A and 102B. Gate structures 120A and 120B (e.g., including doped polysilicon structures) that can be fabricated in some additional and / or alternative arrangements in other suitable electrodes or materials can be provided relative to FinFETs 102A and 102B, respectively, where the gate structures 120A and 120B can overlap the respective channel regions 112A, 112B and extend along a second axis (e.g., the X-axis) orthogonal to the first axis. In Figure 1AIn the exemplary arrangement shown, the two FinFETs 102A and 102B can each be provided as a mirror image of the other, where like components in one FinFET are denoted with the same reference numeral or acronym as the corresponding component in the other FinFET, but with "b" or "B" appended as appropriate instead of "a" or "A". Thus, unless otherwise indicated, at least for the purposes of some of the examples herein, the description of one FinFET in the following discussion applies equally to the other FinFET.

[0021] Each corrugated channel structure 104A / 104B can be formed to have a three-dimensional configuration, such as extending vertically along a third axis, the Z-axis, for example, as previously mentioned, where the corrugated channel structure can include horizontal surfaces such as a top surface 116 and non-horizontal surfaces such as a first sidewall surface 118A and a second sidewall surface 118B, as Figure 1B-1 to 1B-3 shown in a cluster of views. Focusing on FinFET 102A, three cross-sectional views of different regions of the IC device 100A along cross-sectional planes A-A, B-B, and C-C passing through FinFET 102A are shown in Figure 1B-1 to 1B-3 . The cross-sectional view 100B-1 along A-A illustrates a cross-section in the drain region 110A of FinFET 102A that includes the corrugated channel structures 104A and 104B, where all surfaces of the corrugated channel structure and the horizontal surfaces adjacent to the sidewall surfaces can be doped with a dopant material having a suitable conductivity type and sufficient concentration to facilitate an ohmic drain contact region for FinFET 102A. In an example, the dopant material can include a second conductivity type opposite to the first conductivity type of the substrate 108 on which FinFET 102A is formed. As illustrated in the cross-sectional view 100B-1 of Figure 1B-1 , a heavily doped layer 130 can be conformally formed over the top surface 116, the sidewall surfaces 118A / 118B, the bottom 136 of the trench 106 formed between the adjacent corrugated channel structures 104A and 104B, and the horizontal top surface 199 of the semiconductor substrate 108 adjacent to the corrugated channel structures 104A and 104B, which in some examples can be provided as the respective "end fins" of the plurality of corrugated channel structures of a representative FinFET of the IC device 100A.

[0022] Continuing to refer to Figure 1A and 1B-2, a cross-sectional view 100B-2 along B-B illustrates a cross-section of a channel region 112A in a FinFET 102A, the FinFET including corrugated channel structures 104A and 104B, wherein all surfaces of the corrugated channel structures and the horizontal surfaces adjacent to the sidewall surfaces 116A, 116B may be overlaid with a gate dielectric layer 132 of a suitable thickness and composition. In an exemplary arrangement, a planarized gate structure 120A (e.g., polysilicon) may be formed over the gate dielectric layer 132. As will be further elaborated below, since diffusion region formation for contacts in this portion of the FinFET 102A may not be required, corresponding regions of the corrugated channel structures 104A / 104B of the IC device 100A may be appropriately masked while injecting a suitable dopant species for forming drain, source, and / or body contact regions of the FinFET 102A.

[0023] Cross-sectional view 100B-3 illustrates a cross-section in a source / body region 114 of a FinFET 102A including corrugated channel structures 104A and 104B, wherein different surfaces of the corrugated channel structures and the horizontal surfaces adjacent to the sidewall surfaces may be selectively doped with a dopant species having a suitable conductivity type and sufficient concentration to facilitate ohmic body contact regions and ohmic source contact regions for the FinFET 102A. In one example, the dopant species for forming the contact regions may include a dopant having a first conductivity type but having a higher concentration than that used for doping the substrate 108, and the dopant may be selectively injected only into one or more of the top surface 116, the bottom 136 of the trench 106, and / or the horizontal top surface 199 of the semiconductor substrate 108 adjacent to the corrugated channel structures 104A and 104B to form a so-called body contact region relative to the body region of the FinFET 102A. Thus, Figure 1B-3 one or more body contact regions 134 are illustrated in cross-sectional view 100B-3. In one example, the dopant species for forming a contact region (also referred to as a source contact region) relative to the source of the FinFET 102A may include a dopant species having a suitable conductivity type and sufficient concentration to facilitate an ohmic source contact region for the FinFET 102A, and it may be selectively doped only in one or more sidewall surfaces 118A, 118B of the respective corrugated channel structures 104A, 104B. For example, the dopant species for forming the source contact region may include a second conductivity type opposite to the first conductivity type of the semiconductor substrate 108, wherein the second conductivity type may be similar to the conductivity type of the dopant species used for forming the drain contact region 130. As Figure 1B-3As described, by appropriately masking the remaining surface of the IC device 100A that includes the horizontal surface configured to form the body contact region as set forth above, one or more source contact regions 138 can be selectively formed in the sidewall surfaces 118A / 118B.

[0024] Although Figure 1B-3 the foregoing examples illustrate an arrangement in which the body contact region is formed in a horizontal surface and the source contact region is formed in the sidewall surfaces of the corrugated channel structures 104A / 104B in the source / body region 114, a large number of arrangements and combinations of body and source contact region configurations can be implemented in additional and / or alternative arrangements. For example, the positions of the body and source contact regions can be interchanged or switched in some arrangements such that the body contact region can be formed in the sidewall surface while the source contact region can be formed in the horizontal surface of the FinFET 102A. Additionally, in some instances, only a portion or subset of the plurality of corrugated channel structures can be used to form the body and source contact regions. In additional and / or alternative variations, the subset of corrugated channel structures selected to form the body and source contact regions can be evenly spaced in some arrangements, e.g., the corrugated channel structures selected to form the body and source contact regions can be separated by the same number of non-selected corrugated channel structures.

[0025] Figure 2A-1 to 2A-3 to Figure 2K-1 to 2K-3 FIGS. illustrate cross-sectional views of an IC device 200 including a FinFET at various formation stages in a process flow for fabricating body contact regions and source contact regions in different surfaces of a corrugated channel structure according to examples of the present disclosure. For the purposes of some examples, the IC device 200 may also be referred to as a FinFET device. As set forth herein, Figure 2A-1 to 2A-3 to Figure 2K-1 to 2K-3 the views depicted in FIGS. each illustrate a cluster of three cross-sectional views that respectively represent the progression of three different portions or regions of the FinFET device (e.g., a drain region, a channel region, and a source / body region) when processing the IC device 200 in a manufacturing process. In other words, Figure 2A-1 to 2K-1 the view shown in FIG. refers to a cross-sectional view of the drain region, Figure 2A-2 to 2K-2 the view shown in FIG. refers to a cross-sectional view of the channel region, and Figure 2A-3 to 2K-3 the view shown in FIG. refers to a cross-sectional view of the source / body region of the IC device 200 at various stages of the manufacturing process. By way of illustration, the reference numerals 200A, 200B, and 200C shown in these clusters Figure 2A-1 to 2K-1 , Figure 2A-2 to 2K-2 and Figure 2A-3 to 2K-3 correspond generally to the IC device 200 along the lines as shown in Figure 1A and 1B-1Cross-sectional views of the IC device 100A taken along planes A-A, B-B, and C-C through the drain region, channel region, and source / bulk region shown in FIGS. 1B-3. Accordingly, Figure 2A-1 to 2K-1 , Figure 2A-2 to 2K-2 and Figure 2A-3 to 2K-3 the reference numerals 200A, 200B, and 200C in FIGS. refer to the drain region, channel region, and source / bulk region, respectively, of a plurality of corrugated channel structures formed over or in a suitable substrate as part of the FinFET device 200. It should be noted that after this reference, a variety of process flows can be used to fabricate various types of FinFETs, and the examples of the present disclosure are not limited to any particular FinFET implementation. Accordingly, all of the manufacturing stages involved in the FinFET process flow are not depicted herein so as not to obscure the understanding of the examples of the present disclosure.

[0026] Specifically, referring to Figure 2A-1 to 2A-3, depicts an IC device 200 including a semiconductor substrate 202 at a representative early front-end-of-line (FEOL) manufacturing stage, where one or more corrugated channel structures or fins of a FinFET may be formed in a subsequent stage as part of a process depending on the technology, process node, and / or product application of the IC device 200. In some arrangements, the semiconductor substrate 202 may be part of a larger semiconductor substrate (which may include other electronic circuitry and components not shown in the figures), which is doped appropriately depending on the type of FinFET to be fabricated in the semiconductor substrate 202. Depending on the application, exemplary FinFET implementations may be based on metal-oxide-semiconductor (MOS) technology, complementary metal-oxide-semiconductor (CMOS) technology, double-diffused metal-oxide-semiconductor (DMOS) technology, etc., including analog, digital, and / or mixed-signal device designs. In some instances, a combination of semiconductor technologies may be implemented, where different technologies suitable for corresponding types of product designs may be integrated within the same chip or IC device, such as linear BiCMOS or LBC (where MOS and bipolar technologies may be used for analog functions and CMOS may be used for digital logic design in a bipolar-CMOS combination technology), BCD (where DMOS may be integrated within the IC device for a bipolar-CMOS-DMOS combination technology for power and high-voltage portions that also have analog and digital parts). Thus, without being limited to a particular implementation, the semiconductor substrate 202 may include a portion of a semiconductor processing wafer (e.g., an IC die), which may be processed to include any combination of an epitaxial layer, a buried layer, a laterally diffused extension, an N-well, a P-well, a deep well, a shallow well, a reduced surface field (RESURF) layer formed above a dielectric layer of a SOI substrate, etc. Additionally, the exemplary semiconductor substrate 202 may include various isolation structures for dielectric isolation of constituent layers, regions, well structures, etc. using a variety of isolation techniques (e.g., shallow trench isolation (STI), local oxidation of silicon (LOCOS), etc.), which may be formed at or during any suitable FEOL stage integrated within the process as described herein.

[0027] In some instances, in Figure 2A-1 to 2A-3 the semiconductor substrate 202 depicted in the early manufacturing stage may have received various types of doping steps, such as one or more depositions, including threshold voltage adjustment implants (V TEpitaxial steps of implants), implantations, deep isolation implants (e.g., NWELL / PWELL implants), ground plane (GP) implants (which may also be used in some instances to isolate devices from each other), and / or anti-punchthrough (APT) implants, etc. Although in some instances the semiconductor substrate 202 may mainly include appropriately doped silicon as the substrate material, other semiconductor materials such as Ge, SiGe, GaAs, SiC, GaN, other Group III-V materials, etc. may be used in some embodiments, where one or more epitaxial layers or single crystal layers may be formed or provided as part of the semiconductor substrate 202 in some arrangements.

[0028] Without limitation, the semiconductor substrate 202 may include semiconductor material of a first conductivity type (e.g., p-type), which may be provided as part of the FinFET manufacturing process described in U.S. Patent No. 10,978,559; U.S. Patent No. 11,152,506; U.S. Patent No. 11,437,49; U.S. Patent No. 11,508,842 and U.S. Patent Application Publication No. 2022 / 0123130, each of the U.S. patents being incorporated herein by reference in its entirety for all purposes, which may be referred to individually and / or collectively as the "incorporated disclosures". Figure 2B-1 to 2B-3Describe the manufacturing stage in which multiple corrugated channel structures (e.g., fins 204A, 204B) have been formed in the semiconductor substrate 202. In an exemplary embodiment, adjacent corrugated channel structures 204A, 204B can be connected in parallel or separated by corresponding grooves or trenches 212 formed therebetween. For example, each groove or trench has a bottom 214 formed close to the horizontal surfaces of the adjacent corrugated channel structures 204A, 204B. In some instances, the trenches 212 can be formed by appropriate anisotropic etching (e.g., reactive ion etching (RIE) process using fluorine groups) in combination with appropriate patterned masking, as set forth in one or more incorporated disclosures. For example, the trenches 212 can have an average depth of 300 nanometers (nm) to 1200 nm or greater, which corresponds to the average vertical height 210 of the corrugated channel structures 204A, 204B along the surface normal relative to the top main surface (e.g., surface 203) of the semiconductor substrate 202 after the corrugated channel structures 204A, 204B are formed. As illustrated, the corrugated channel structures 204A, 204B can each appear to have a top surface 208 and sidewall surfaces 216A, 216B, and in some cases adjacent to the trench bottom 214, where the sidewall surfaces 216A, 216B can be provided as corresponding lateral portions of the respective corrugated channel structures 204A / B. In some arrangements, the sidewall surfaces 216A, 216B can be inclined or angled such that the respective corrugated channel structures 204A / 204B can be formed as tapered structures, where the upper portion including the top surface 208 can have a width that is about 40% to 50% of the height 210 of the corrugated channel structures 204A / B. In some arrangements, the lower portion of the corrugated channel structures 204A / B can have a width that is about 50% to 60% of the height 210 of the corrugated channel structures 204A / B close to the bottom 214 of the adjacent trench 212. Thus, in some instances, the sidewall surfaces 216A, 216B can be inclined about 80° to 89° relative to the horizontal surface (e.g., bottom 214 and / or top main surface 203). In some arrangements, the representative width (W) and pitch (P) of the "fin and trench" section can vary generally or individually. Although the depth of the trenches is typically consistent, it can vary with the trench width. The sidewall angles and shapes can be different from the examples shown in the figures and can be optimized for different process / device attributes.

[0029] Depending on the embodiment, the semiconductor substrate 202 including the corrugated channel structures 204A, 204B can be doped with a suitable dopant to form or adjust one or more charge balance regions and drain drift regions in appropriate regions of the corrugated channel structures 204A, 204B Figure 2B-1 to 2B-3(not shown in the figure), such as drain region 200A, channel region 202B, and source / bulk region 200C, as described in the incorporated disclosure. Gate dielectric layer 217 and gate layer 218 (e.g., including polysilicon) are formed over different regions of the corrugated channel structures 204A, 204B, respectively, as illustrated in Figure 2C-1 to 2C-3 and Figure 2D-1 to 2D-3 . Subsequently, gate layer 218 is removed from drain region 200A and source / bulk region 200C of the corrugated channel structures 204A, 204B, as Figure 2E-1 to 2E-3 shown therein. In some arrangements, gate dielectric layer 217 can be formed by thermal oxidation or other processes and can mainly include silicon dioxide or other layers with a thickness of about 3 nm to 10 nm. In some arrangements, nitrogen can be introduced into gate dielectric layer 217 by exposing gate dielectric layer 217 to a nitrogen-containing plasma. In some arrangements, gate dielectric layer 217 can include a high dielectric constant (high-k) material, such as hafnium oxide, zirconium oxide, or tantalum oxide. In some arrangements, after appropriate etchback and polishing (e.g., chemical mechanical polishing / planarization (CMP)), gate layer 218 can have an initial thickness that can depend on the desired final thickness of the remaining gate layer 218 in channel region 200B, such as 100 nm to 200 nm. Depending on the embodiment, gate layer 218 can include boiler-deposited polysilicon, in-situ doped polysilicon, amorphous polysilicon, etc. Additionally, appropriate dopants can be implanted or otherwise introduced into drain region 200A and source / bulk region 200C to provide an appropriate amount of dopants in the drain region and the source and bulk regions relative to the FinFET device 200. In an NMOS example, the source and drain regions can be formed by implanting n-type dopants (e.g., phosphorus, arsenic, and antimony, etc.), while the bulk region can include a portion of the substrate material with a p-type dopant (e.g., boron, gallium, and indium, etc.). Without any limitation, Figure 2E-1 and 2E-3 the junction profiles 275 and 277 shown therein illustrate the doped drains and sources of the corrugated channel structures 204A, 204B in their corresponding regions, respectively.

[0030] In some embodiments, a drain contact region can be formed in drain region 200A, such as a heavily doped conformal layer 224 that can be formed over one or more surfaces including the sidewalls 216A / 216B and the top surface 208 of the corrugated channel structures 204A / 204B, the bottom 214 of the trench 212, and the top surface 203 of the semiconductor substrate 202 in the drain region 200A, as Figure 2F-1 depicted therein. In some embodiments, channel region 200B and source / bulk region 200C can be covered by an appropriate patterned mask 222 (e.g., photoresist and anti-reflective materials, such as bottom anti-reflective coating (BARC)), and the mask can be formed by a lithography process, such as Figure 2F-2 and2F-3 As described in 2F-3 . A line-of-sight implantation technique (e.g., angled beam line implantation 220) can be used to implant the exposed drain region 200A, which technique can involve one or more beam line tilt angles for implanting dopant species into each of the sidewall surfaces 216A, 216B in multiple implantation steps (e.g., implants 220A, 220B, involving appropriate dopant species, implantation energy, concentration, etc.). In some instances, the dopant species can include a second conductivity type opposite to the first conductivity type of the semiconductor substrate 202, where the second conductivity type dopant can be implanted and activated to achieve an average net concentration greater than or equal to about 5×10 18 cm -3 to 5×10 20 cm -3 (e.g., having a degenerate doping concentration) profile in order to achieve a low resistance ohmic contact to the drain region 200A of the FinFET device 200.

[0031] Figure 2G-1 to 2G-3 to Figure 2I-1 to 2I-3Depict a series of manufacturing stages in which different surfaces associated with the corrugated channel structures 204A / 204B of the FinFET device 200 can be selectively implanted or otherwise doped with dopant species of different conductive types to form body contacts and source contact regions, such as source / body region 200C, in a portion of the corrugated channel structures 204A / 204B, while using one or more mask layers to mask the remaining regions 200A and 200B. Depending on which portions of the exposed surfaces in the source / body region 200C (e.g., the top surface 208 of the corrugated channel structures 204A / 204B, the bottom 214 of the trench 212, and the horizontal surface of the top main surface 203 of the semiconductor substrate 202, as well as the non-horizontal surfaces of the sidewall surfaces 216A, 216B of the corrugated channel structures 204A / 204B) are used for which type of contact region (e.g., body contact region or source contact region), different configurations of the body and source contact regions can be formed according to the examples herein by implementing appropriate patterned masks to selectively mask the horizontal or non-horizontal surfaces. Additionally, in some examples, only the surfaces associated with a subset of the multiple corrugated channel structures can be utilized to form the body and / or source contact regions, which can be implemented using various combinations of layout and masking schemes. Thus, in some arrangements, the body and / or source contact regions can be formed in one or more surfaces selected from every Nth corrugated channel structure (e.g., every other, every third, every fourth, etc.) of the multiple corrugated channel structures. In some arrangements, the selected corrugated channel structures can include one corrugated channel structure in a proper subset of the multiple corrugated channel structures, where the selected corrugated channel structure in the proper subset is separated by the same number of corrugated channel structures not in the proper subset. In some arrangements, the body contact and / or source contact regions can be implanted as continuous strips or in segments, which can be oriented in various ways with respect to the corrugated channel structures. Various arrangements and / or combinations of the body and source contact regions can thus be configured according to the examples herein, depending on the implementation, product type, and design considerations in the optimization or modulation performance trade-off (e.g., SOA vs. R sp trade-off). Without limitation, examples can include forming one or more body contact regions in the horizontal surface associated with at least a portion of the corrugated channel structure, while one or more source contact regions can be formed in the sidewall surface of the corresponding corrugated channel structure. Another non-limiting example can include forming one or more source contact regions in the horizontal surface associated with at least a portion of the corrugated channel structure, and forming one or more body contact regions in the sidewall surface of the corresponding corrugated channel structure.

[0032] To facilitate forming contact regions only in the source / body region 200C of the corrugated channel structures 204A and 204B, in some examples, the drain region 200A and the channel region 200B can be covered by a properly patterned mask layer 225, asFigure 2G-1 / 2G-2 to Figure 2I-1 / 2I-2 as depicted. Additionally, in order to form contacts only in the sidewall surfaces of the (selected) corrugated channel structures (e.g., corrugated channel structures 204A and 204B), the horizontal surfaces of the corrugated channel structures 204A and 204B in the source / bulk region 200C can be masked by a suitable hard mask, such as a hard mask 228 covering the top surface 208 of the corrugated channel structures 204A and 204B, the bottom 214 of the trench 212, and the top surface 203 of the semiconductor substrate 202, as Figure 2G-3 and 2H-3 shown. In some instances, the hard mask 228 can include an oxide hard mask formed in a dual-mask process that involves an initial conformal nitride hard mask (not shown in the figures), the oxide hard mask being formed over the initial conformal nitride hard mask and subsequently anisotropically etched (e.g., by an RIE process) to expose the sidewall surfaces 216A, 216B of the corrugated channel structures 204A / 204B while the horizontal surfaces remain covered. Details regarding an exemplary dual-mask process are described in U.S. Patent Application No. 18 / 496,697, filed on October 27, 2023 (referred to as the '697 patent application), which is incorporated herein by reference for all purposes. A line-of-sight implantation process 227 (e.g., a beam-line implantation process) can be used to implant a suitable dopant at one or more tilt angles in the sidewall surfaces 216A, 216B, as exemplified by implants 227A, 227B in Figure 2G-1 to 2G-3 and Figure 2H-1 to 2H-3 . The implanted dopant species can be annealed or otherwise activated to form contact regions 229A, 229B (e.g., first contact regions) in the respective sidewall surfaces 216A, 216B (shown in Figure 2H-3 ). In one arrangement, the implanted dopant species can include a p-type dopant (e.g., for forming a bulk contact region). In another arrangement, the implanted dopant species can include an n-type (e.g., for forming a source contact region). Similar to the drain contact region 224, the dopant profile in the sidewall contact regions 229A, 229B can have an average net concentration greater than or equal to about 5×10 18 cm -3 to 5×10 20 cm -3 e.g., a degenerate doping concentration, in order to achieve a low-resistance ohmic contact to the source or bulk of the FinFET device 200 depending on the conduction type involved.

[0033] The oxide hard mask 228 can then be removed from the horizontal surfaces of the corrugated channel structures 204A and 204B in the source / body region 200C (e.g., using a dilute hydrofluoric acid (HF) etch process), while the drain region 200A and the channel region 200B remain covered by the mask layer 225. A substantially vertical implant 230 (e.g., having a zero tilt angle within a certain range (e.g., 0° ± 2°)) can be implemented to implant the exposed horizontal surfaces in the source / body region 200C, as Figure 2I-1 to 2I-3 shown therein, thereby forming contact regions (e.g., second contact regions) therein. The sidewall surfaces 216A, 216B receive little or no secondary doping from the vertical implant process because they are substantially parallel to the incident angle of the implant 230, thereby maintaining approximately the same net concentration of the dopant species previously introduced in the angled beam line implant 220. Thereafter, the dopant species in the corrugated channel structures 204A, 204B and the remaining portions and regions of the semiconductor substrate 202 can be activated using one or more annealing steps (not specifically shown in the figures). In some instances, the annealing process can include a rapid thermal annealing (RTA) process at about 1000 °C to 1200 °C for about 10 to 15 seconds (but not limited thereto), similar to the examples set forth in the '697 patent application incorporated herein by reference.

[0034] As Figure 2J-1 to 2J-3 shown therein, suitable metal silicide layers can be formed over the drain region 200A, the channel region 200B, and the source / body region 200C of the FinFET device 200, respectively, to facilitate contact formation with metal interconnects in subsequent manufacturing stages. By way of illustration, metal silicide 234A is formed over the doped conformal layer 224 in the drain region 200A of the FinFET device 200. Similarly, metal silicide 234B is formed over the gate layer 218 in the channel region 200B, and metal silicide 234C is formed over the contact regions formed in the horizontal and sidewall surfaces of the FinFET device in the source / body region 200C. In an exemplary embodiment, metal silicides 234A to 234C can be formed by forming a metal layer (not specifically shown) over the respective contact regions or gate structures, where the metal layer can include one or more metals suitable for forming metal silicides, such as titanium, cobalt, nickel, or platinum, but not limited thereto. In some instances, the metal layer can be formed by a sputtering process, an ion plating process, or a metal organic chemical vapor deposition (MOCVD) process to provide a more uniform coverage of the corrugated surfaces in the drain and source / body regions of the FinFET device 200.

[0035] After silicidation, a pre-metal dielectric (PMD) layer 250 extending over the semiconductor substrate 202 is formed over different regions of the FinFET device 200, as Figure 2K-1 to 2K-3As shown. In some instances, the PMD layer 250 may include one or more (sub)layers of different compositions and thicknesses. In some arrangements, the PMD layer 250 may be formed as a dielectric stack, including, for example, a PMD liner formed on the FinFET device 200, a PMD main layer formed on the PMD liner, and a capping layer formed on the PMD main layer. The PMD liner may include one or more layers of silicon dioxide, silicon nitride, or silicon oxynitride, and may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process or a low-pressure chemical vapor deposition (LPCVD) process. The PMD main layer may mainly include silicon dioxide, silicon dioxide with hydrogen, phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG), for example, and may be formed by a PECVD process, an atmospheric pressure CVD (APCVD) process, a high-density plasma (HDP) process, or a high aspect ratio process using ozone (HARP). The capping layer may include silicon nitride, silicon carbide, silicon carbonitride, or other materials suitable for a termination layer of a CMP process. For example, the capping layer may be formed by a PECVD process. Thereafter, one or more contacts may be formed on the metal silicides 234A to 234C in the corresponding regions of the FinFET device 200. For illustrative purposes, a contact 256 is formed for contacting a drain contact region 224 in the drain region 200A, a contact 254 is formed for contacting the gate layer 218 in the channel region 200B, and a contact 252 is formed for contacting the contact regions 231 and 229A / 229B, which may be a combination of a body contact region and a source contact region that may be shunted together in some instances herein. Additional details regarding metal silicidation, PMD layer, and contact formation can be found in one or more of the incorporated disclosures mentioned above.

[0036] It should be noted that the metal silicides 234A to 234C and / or the associated contacts 256, 254, 252 are shown only in the foregoing examples. Some additional and / or alternative examples may include a source silicide 234C, a drain silicide 234A, and / or a gate silicide 234B, where the above-mentioned silicides are disposed to terminals outside the views of, for example, Figure 2J-1 to 2J-3 and Figure 2K-1 to 2K-3 such diagrams, to provide device terminals that comply with various contact design rules depending on the application.

[0037] Figure 3FIG. 300 is a flow chart of an IC manufacturing method 300 in accordance with some examples of the present disclosure. At block 302, a corrugated channel structure may be formed over a semiconductor substrate including a substrate material, where the corrugated channel structure may have a vertical height along a surface normal with respect to a top major surface of the semiconductor substrate. As elaborated above, the corrugated channel structure may be composed of a shared source / bulk region and a drain region. At block 304, a first contact region of a first conductivity type may be formed, where the first contact region extends into a sidewall surface of the corrugated channel structure. In some arrangements, the first contact region may be formed by doping the sidewall surface with a dopant material of the first conductivity type, e.g., by injecting the dopant material at a beam line angle with respect to the surface normal. A second contact region may be formed as elaborated in block 306, where the second contact region may have an opposite second conductivity type and extends into a horizontal surface adjacent to the sidewall surface. In some arrangements, the second contact region may be formed by doping the horizontal surface with a dopant material of the second conductivity type, e.g., by injecting the dopant material at a zero tilt beam line angle with respect to the surface normal. As previously elaborated, in some examples, the first contact region may be a bulk contact region, and the second contact region may be a source contact region. In some additional and / or alternative examples, the first contact region may be a source contact region, and the second contact region may be a bulk contact region. Additionally, a drain contact region may also be formed by suitable doping, e.g., with a dopant material of the same conductivity type as the dopant material for forming the source contact region in the same beam injection step or in a separate injection step (e.g., in an injection step prior to forming the source contact region). Thereafter, the contact regions may be silicided and disposed as needed to appropriate locations configured to form contacts compliant with applicable design rules (block 308). At block 310, various contacts may be formed in apertures defined in a PMD layer disposed over the corrugated channel structure, where the contacts may be used to provide electrical connectivity with respect to the source / bulk region and the drain region of the corrugated channel structure.

[0038] Although various examples of the present disclosure have been described above, the examples have been presented by way of example only and not limitation. Numerous changes may be made to the disclosed examples in accordance with the disclosure herein without departing from the spirit or scope of the present disclosure. Accordingly, the breadth and scope of the present disclosure should not be limited by any of the examples described above. Indeed, the scope of the present disclosure should be defined in accordance with the appended claims and their equivalents.

[0039] For example, in the present disclosure and the following claims, unless otherwise stated and / or specified to the contrary, any one or more of the layers described herein can be formed in any number of suitable ways, such as by spin coating techniques, sputtering techniques (e.g., magnetron and / or ion beam sputtering), (thermal) growth techniques, or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), PECVD, LPCVD, or atomic layer deposition (ALD), etc. As another example, silicon nitride can be silicon-rich silicon nitride or oxygen-rich silicon nitride. The silicon nitride can contain some oxygen, but not so much that the dielectric constant of the material is significantly different from that of high-purity silicon nitride. Furthermore, although the exemplary FinFETs are depicted as having sub-surface fins, e.g., where the fins are formed by etching into the substrate to create trenches for separating the resulting fins, aspects of the present disclosure can also be implemented in other FinFET architectures, such as those that include fins formed or grown above the substrate as a set of protruding fins extending from the surface of the substrate.

[0040] In at least some additional or alternative embodiments, the functions / actions described in the blocks may not occur in the order shown in the flowchart. For example, depending on the functionality / action involved, two consecutive blocks shown may actually be performed substantially simultaneously or the blocks may sometimes be performed in the reverse order. Additionally, the functionality of a given block of a flowchart and / or block diagram can be divided into multiple blocks, and / or the functionality of two or more blocks of a flowchart and / or block diagram can be at least partially integrated. Also, some blocks in the flowchart may optionally be omitted. Further, although some of the figures include arrows on communication paths to show the primary direction of communication, it should be understood that communication can occur in a direction opposite to the depicted arrows. Finally, other blocks can be added / inserted between the illustrated blocks.

[0041] The order or sequence of actions, steps, functions, components, or blocks illustrated in any of the flowcharts and / or block diagrams depicted in the drawings of the present disclosure can be modified, changed, replaced, customized, or otherwise rearranged within a particular flowchart or block diagram, including the deletion or omission of a particular action, step, function, component, or block. Additionally, the actions, steps, functions, components, or blocks illustrated in a particular flowchart can be intermixed with or otherwise arranged or rearranged with the actions, steps, functions, components, or blocks illustrated in another flowchart so as to effect additional changes, modifications, and configurations relative to one or more processes for the purpose of practicing the teachings of the present disclosure. Similarly, although various examples have been set forth herein, not all features of a particular example are necessarily limited thereto and / or required therefor.

[0042] At least some portions of the foregoing description may include certain directional terms, such as "upper", "lower", "top", "bottom", "left", "right", "front", "back", "vertical", "horizontal", etc., which may be used with reference to the orientation of some of the described figures or their illustrative elements. Since the components of some examples may be positioned in several different orientations, the directional terms are used for illustrative purposes and are in no way limiting. Similarly, references to features referred to as "first", "second", etc. do not indicate any particular order, importance, etc., and such references may be interchanged, depending on the context, embodiment, etc. Additionally, unless specifically stated otherwise, the features of the examples described herein may be combined with each other.

[0043] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. The foregoing detailed description should not be considered to imply that any particular component, element, step, action, or function is essential such that it must be included within the scope of the claims. In the case of reciting or describing a phrase such as "at least one of A and B" or a phrase of similar import, such a phrase should be understood to mean "only A, only B, or both A and B". References to elements in the singular form are not intended to mean "one and only one" but rather "one or more" unless expressly so stated. In a similar manner, depending on the context, phrases such as "a plurality" or "multiple" etc. may mean "one or more" or "at least one". All structural and functional equivalents of the elements of the embodiments described above are expressly incorporated herein by reference and are intended to be covered by the appended claims.

Claims

1. A method for manufacturing an integrated circuit IC, comprising: forming a corrugated channel structure over a semiconductor substrate including a substrate material, the corrugated channel structure having a vertical height along a surface normal relative to a top major surface of the semiconductor substrate; as well as A first contact region having a first conductivity type extending into a sidewall surface of the corrugated channel structure and a second contact region having an opposite second conductivity type extending into a horizontal surface adjacent to the sidewall surface are formed. 2 . The method of claim 1 , wherein the first contact region is a body contact region and the second contact region is a source contact region. 3 . The method of claim 1 , wherein the first contact region is a source contact region and the second contact region is a body contact region. The method of claim 1 , wherein the horizontal surface is a bottom of a groove between the corrugation channel structure and an adjacent corrugation channel structure. The method of claim 1 , wherein the horizontal surface is a top surface of the corrugated channel structure. 6 . The method of claim 1 , wherein the first contact region is formed by implanting a dopant species of the first conductivity type at a beamline tilt angle relative to the surface normal.

7. The method of claim 1, wherein the second contact region is formed by implanting a dopant species of the second conductivity type at a substantially 0° tilt angle relative to the surface normal.

8. The method of claim 1, wherein the corrugated channel structure extends above a top surface of the semiconductor substrate. 9 . The method of claim 1 , wherein a top surface of the corrugated channel structure is at or below a top surface of the semiconductor substrate.

10. The method of claim 1, wherein the corrugated channel structure has a p-type body region, and the second contact region is p-type.

11. An integrated circuit IC, comprising: a corrugated channel structure over a semiconductor substrate having a top major surface, the top major surface having a surface normal; as well as A first contact region having a first conductivity type extends into a sidewall surface of the corrugated channel structure and a second contact region having an opposite second conductivity type extends into a horizontal surface adjacent to the sidewall surface.

12. The IC of claim 11, wherein the corrugation channel structure is one of a plurality of corrugation channel structures separated by respective trenches formed between adjacent corrugation channel structures, the horizontal surface being a bottom of the respective trenches.

13. An IC according to claim 11, wherein the first contact region is a source contact region formed in the sidewall surface of the corrugated channel structure, and the second contact region is a body contact region formed in the top surface of the corrugated channel structure or in the bottom of a groove between the corrugated channel structure and an adjacent corrugated channel structure.

14. The IC of claim 13, wherein the body contact region contains a dopant species implanted at a substantially 0° tilt angle relative to the surface normal.

15. The IC of claim 13, wherein the source contact region contains a dopant species implanted at one or more beamline tilt angles relative to the surface normal.

16. An IC according to claim 11, wherein the first contact region is a body contact region formed in the sidewall surface of the corrugated channel structure, and the second contact region is a source contact region formed in the top surface of the corrugated channel structure or in the bottom of a trench between the corrugated channel structure and an adjacent corrugated channel structure.

17. The IC of claim 16, wherein the source contact region contains a dopant species implanted at a substantially 0° tilt angle relative to the surface normal.

18. The IC of claim 16, wherein the body contact region contains a dopant species implanted at one or more beamline tilt angles relative to the surface normal.

19. An IC according to claim 11, wherein the corrugated channel structure is one of a plurality of corrugated channel structures separated by corresponding grooves formed between adjacent corrugated channel structures, the first contact area is one of a plurality of first contact areas each formed in the sidewall surface of a corresponding one of the corrugated channel structures, and the second contact area is one of a plurality of second contact areas each formed in the top surface of a corresponding one of the corrugated channel structures and formed in the bottom of a groove adjacent to a corresponding one of the corrugated channel structures.

20. The IC of claim 17, wherein the corrugated channel structure is a corrugated channel structure of a true subset of a plurality of corrugated channel structures, and the first contact region is one of a plurality of first contact regions each formed in the sidewall surface of a corresponding corrugated channel structure of the true subset of corrugated channel structures.

21. The IC of claim 20, wherein the corrugation channel structures in the proper subset are separated by a same number of corrugation channel structures not in the proper subset.

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