Vertical semiconductor device with body contact, method of manufacturing the same, and electronic device

Abstract

Disclosed is a vertical semiconductor device having a body contact, a method of manufacturing the same, and an electronic device including the semiconductor device. According to embodiments, the semiconductor device can include an active region vertically disposed on a substrate with respect to the substrate, including a lower source / drain region, an upper source / drain region, and a middle portion between the lower source / drain region and the upper source / drain region to define a channel region; a gate stack disposed on a first side of the active region in a lateral direction with respect to the substrate to at least overlap the middle portion of the active region; and a body contact layer disposed on a second side of the active region opposite the first side in the lateral direction to overlap the middle portion of the active region to apply a body bias to the active region, wherein, in a vertical direction with respect to the substrate, a portion of the middle portion of the active region overlapping the body contact layer is a first spaced distance from the lower source / drain region and a second spaced distance from the upper source / drain region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and in particular, to a vertical semiconductor device with body contact and a method of manufacturing the same, and an electronic device including the same. BACKGROUND

[0002] To meet the demand for metal-oxide-semiconductor field-effect transistors (MOSFETs) to be increasingly miniaturized, various types of devices have been proposed, such as fin field-effect transistors (FinFETs), multi-bridge-channel field-effect transistors (MBCFETs), etc. However, they still have certain limitations.

[0003] Vertical FETs are a promising type of MOSFETs in terms of miniaturization. However, fully-depleted vertical FETs have a floating body effect, which can cause threshold voltage (Vt) shift and increase off-state current. Body contact can be used to suppress the floating body effect. However, body contact can increase channel thickness and degrade device performance, such as short-channel control. It is currently difficult to fabricate high-quality body contact on vertical devices. SUMMARY

[0004] In view of the above, it is at least in part an object of the present disclosure to provide a vertical semiconductor device with body contact and a method of manufacturing the same, and an electronic device including the same.

[0005] According to an aspect of the present disclosure, there is provided a semiconductor device, comprising: an active region vertically disposed on a substrate with respect to the substrate, including a lower source / drain region, an upper source / drain region, and a middle portion between the lower source / drain region and the upper source / drain region to define a channel region; a gate stack disposed on a first side of the active region in a lateral direction with respect to the substrate to at least overlap the middle portion of the active region; and a body contact layer disposed on a second side of the active region opposite to the first side in the lateral direction to overlap the middle portion of the active region to apply a body bias to the active region, wherein a portion of the middle portion of the active region overlapping the body contact layer is at a first spaced distance from the lower source / drain region and at a second spaced distance from the upper source / drain region in a vertical direction with respect to the substrate.

[0006] According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: providing a stack of a first source / drain definition layer, a first channel definition layer, a body contact definition layer, a second channel definition layer, and a second source / drain definition layer on a substrate; forming an active layer on vertical sidewalls of the stack extending in a first direction; driving dopants in the first source / drain definition layer, dopants in the body contact definition layer, and dopants in the second source / drain definition layer into respective portions of the active layer to form a lower source / drain region, a body contact region, and an upper source / drain region, respectively; forming a gate stack on a side of the active layer opposite to the stack in a second direction intersecting the first direction; and forming a body contact to the body contact definition layer.

[0007] According to another aspect of the present disclosure, there is provided an electronic device including the above semiconductor device.

[0008] According to an embodiment of the present disclosure, a body contact is provided for a vertical semiconductor device, so that a floating body effect can be suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments thereof taken in conjunction with the accompanying drawings, in which:

[0010] Figures 1 to 12 Fig. 1 shows a schematic diagram of part of a flow of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0011] Figures 13 to 17 Fig. 2 shows a schematic diagram of part of a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0012] Throughout the drawings, same or similar reference numerals can represent same or similar functionality throughout the several views. DETAILED DESCRIPTION

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary of the present disclosure, but is not intended to limit the scope of the present disclosure. Also, in the following description, description of well-known functions and constructions can be omitted to provide a more clear and concise description of the embodiments of the present disclosure.

[0014] In the drawings, schematic diagrams of various structures according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and certain details can be omitted. The shapes of various regions, layers, and their relative sizes and positional relationships shown in the diagrams are merely exemplary, and in actuality can be deviated due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, relative positions can be additionally designed by those skilled in the art as needed.

[0015] In the context of the present disclosure, when a layer / element is said to be located "on" another layer / element, it can be directly on the other layer / element, or there can be intervening layers / elements therebetween. Additionally, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0016] According to embodiments of the present disclosure, a vertical-type semiconductor device with body contact is provided. The vertical-type device can include an active region disposed vertically (e.g., along a direction substantially perpendicular to a surface of the substrate) with respect to a substrate, including a lower source / drain region disposed at a lower end and an upper source / drain region disposed at an upper end. A middle portion of the active region between the lower source / drain region and the upper source / drain region can define a channel region. The lower source / drain region and the upper source / drain region can be electrically communicated with each other through the channel region. The lower source / drain region and the upper source / drain region can be defined by doped regions. The channel region can also be doped as desired.

[0017] A gate stack can be disposed on a first side of the active region in a lateral direction (a direction substantially parallel to the surface of the substrate) to overlap at least the middle portion (or the channel region) of the active region so as to control on / off of a conduction channel in the channel region. A body contact layer can be disposed on a second side of the active region opposite the first side. The body contact layer can overlap the middle portion (or the body portion) of the active region so as to apply a body bias to the active region. Thus, the gate stack can control on / off of the channel from the first side, while the body contact layer can control floating body effect from the second side.

[0018] The active region, particularly the middle portion thereof, can be provided with a doped region as a body contact region through which the body contact layer applies the body bias to the active region. Such a body contact region can occupy only a portion of the middle portion of the active region in the vertical direction, and thus can have different doping characteristics from the rest of the middle portion of the active region. For example, the rest of the middle portion of the active region can be intentionally un-doped, or have a different doping concentration. As described below, the body contact region can be self-aligned to the body contact layer. For example, the body contact region can be formed by implanting dopants into the active region (substantially laterally) from the body contact layer.

[0019] The separation distance of the body contact layer (and thus, the body contact region) from the lower source / drain region and the upper source / drain region in the vertical direction can be adjusted as desired, e.g., substantially the same, or biased towards the lower source / drain region or the upper source / drain region. As described below, such distance adjustment can be achieved by the film thickness of the epitaxial semiconductor layer, and thus the film thickness precision of the epitaxial growth process can be reached.

[0020] The body contact layer can be laterally extended so that the body contact portion to apply the body bias can be able to be contacted thereon.

[0021] Similarly, an upper source / drain region contact layer can be provided in contact with the upper source / drain region at the second side of the active region. The upper source / drain region contact layer can laterally extend so that an upper source / drain region contact for applying / outputting an electrical signal to / from the upper source / drain region can be attached thereto. As described below, the upper source / drain region can be self-aligned to the upper source / drain region contact layer. For example, the upper source / drain region can be formed by implanting dopants into the active region (essentially laterally) from the upper source / drain region contact layer.

[0022] The spacing between the upper source / drain region contact layer and the body contact layer in the vertical direction can be substantially uniform. As described below, this spacing can be achieved by the film thickness of the epitaxial semiconductor layer and thus the film thickness accuracy of the epitaxial growth process can be reached.

[0023] The active region can be provided by an active layer of semiconductor. The active layer can be in the form of a nanosheet or nanowire and can include a vertically extending portion extending in the vertical direction to provide the vertically active region described above. In addition, the active layer can also include a laterally extending portion extending away from the vertically extending portion at the first side from a lower end of the vertically extending portion (more specifically, the lower source / drain region). Such a laterally extending portion facilitates the formation of a lower source / drain region contact to the lower source / drain region. For example, the laterally extending portion of the active layer can extend beyond the overlying gate stack to which the lower source / drain region contact can be attached.

[0024] The active layer can be formed on a lower source / drain region defining layer. The lower source / drain region defining layer can extend from below the laterally extending portion of the active layer to the surface of the vertically extending portion of the active layer at the second side. As described below, the lower source / drain region can be self-aligned to the portion of the lower source / drain region defining layer at the second side. For example, the lower source / drain region can be formed by implanting dopants into the active layer from the lower source / drain region defining layer.

[0025] The spacing between the lower source / drain region defining layer and the body contact layer in the vertical direction can be substantially uniform. As described below, this spacing can be achieved by the film thickness of the epitaxial semiconductor layer and thus the film thickness accuracy of the epitaxial growth process can be reached.

[0026] The active layer can be an epitaxial layer on the lower source / drain region defining layer, the body contact layer and the upper source / drain region contact layer and thus can have a crystal interface with the lower source / drain region defining layer, the body contact layer and the upper source / drain region contact layer. These layers can all be single-crystal semiconductors.

[0027] According to embodiments, such a vertical-type semiconductor device can be manufactured as follows.

[0028] A stack of a first source / drain-defining layer, a first channel-defining layer, a body-contact-defining layer, a second channel-defining layer and a second source / drain-defining layer can be provided on a substrate. The stack can be formed by epitaxial growth. Thus, the thickness of each layer therein can be well controlled. The layers in the stack can be doped in situ while being grown, so as to achieve the desired doping characteristics. For example, the first source / drain-defining layer and the second source / drain-defining layer can be heavily doped, so as to achieve source / drain regions; the body-contact layer can be lightly doped, so as to achieve a body-contact region; and the first channel-defining layer and the second channel-defining layer can be lightly doped or not intentionally doped. There can be a crystal plane / doping interface between the layers grown / doped separately.

[0029] The stack can have vertical sidewalls extending in a first direction. On the vertical sidewalls, an active layer for defining an active region can be formed. The active layer can be formed by epitaxial growth, and thus its thickness and the thickness of the channel region defined thereby can be well controlled. In addition, the material of the active layer can be appropriately selected depending on the application. Since the following processes, in particular etching processes, are mainly directed to the stack as described above, the selection of the active layer material can be less restricted.

[0030] The dopants in the first source / drain-defining layer, the dopants in the body-contact-defining layer and the dopants in the second source / drain-defining layer can be driven into the respective portions of the active layer, for example by a heat treatment, to form a lower source / drain region, a body-contact region and an upper source / drain region, respectively. The lower source / drain region, the body-contact region and the upper source / drain region thus formed can be self-aligned to the first source / drain-defining layer, the body-contact-defining layer and the second source / drain-defining layer, respectively.

[0031] On a side of the active layer facing away from the stack in a second direction intersecting (e.g. perpendicular to) the first direction, a gate stack comprising a gate dielectric layer and a gate conductor layer can be formed. The gate stack can at least overlap the channel region, so as to effectively control the channel region.

[0032] In addition, the gate stack can be formed by a self-alignment process. For example, the first channel-defining layer and the second channel-defining layer can be recessed with respect to each other at the vertical sidewalls, so as to define a space accommodating at least a portion of the gate stack, by selective etching, before the active layer is formed. A dummy gate can be formed to maintain the space thus defined.

[0033] On a side of the active layer facing away from the gate stack, i.e. on the side of the stack, contact portions can be made, for example an upper source / drain region contact portion to the upper source / drain region, a body-contact portion to the body-contact region (and optionally a contact portion to a well region in the substrate).

[0034] This disclosure may be presented in various forms, some of which will be described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation, conductive materials for forming electrodes, interconnect structures, etc.) but also etching selectivity. In the following description, the desired etching selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etching selectivity relative to other layers exposed to the same etching formulation.

[0035] Figures 1 to 12 A schematic diagram of a portion of the process for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0036] like Figure 1 As shown, a substrate 1001 is provided. This substrate 1001 can be of various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, and compound semiconductor substrates such as SiGe substrates. In the following description, for ease of explanation, a bulk Si substrate, such as a Si wafer, will be used as an example.

[0037] In substrate 1001, a well region 1001w can be formed, for example, by ion implantation. The well region 1001w may contain a specific conductivity type (e.g., p-type conductivity for n-type devices; n-type conductivity for p-type devices) and a concentration such as approximately 1E17-1E19 cm⁻¹. -3 The dopant. There are various ways in the art to set up such a well region, which will not be described in detail here.

[0038] On substrate 1001, a first source / drain defining layer 1003, a first channel layer defining layer 1005, a bulk contact defining layer 1007, a second channel defining layer 1009, and a second source / drain defining layer 1011 can be sequentially formed, for example, by epitaxial growth. Each layer grown on substrate 1001 can be a single-crystal semiconductor layer and can have crystal interfaces between them.

[0039] The first source / drain defining layer 1003 and the second source / drain defining layer 1011 can then define the locations of the source / drain regions, each having a thickness of, for example, about 20 nm to 200 nm. The first source / drain defining layer 1003 and the second source / drain defining layer 1011 can be doped with a specific conductivity type (e.g., n-type conductivity for n-type devices; p-type conductivity for p-type devices) and a concentration such as about 1E18-1E21 cm⁻¹, for example, by in-situ doping during growth. -3 Dopant.

[0040] The bulk contact defining layer 1007 can then define the location of the bulk contact, and its thickness can be, for example, about 2 nm to 100 nm. To optimize device performance, such as adjusting the threshold voltage (Vt), the bulk contact defining layer 1007 can be doped with a certain conductivity type (e.g., p-type conductivity for n-type devices; n-type conductivity for p-type devices) and a certain concentration, such as about 1E17-1E20 cm⁻¹, for example, by in-situ doping during growth. -3 Dopant.

[0041] The first channel layer defining 1005 and the second channel layer defining 1009 may then define the location of the channel region together with the bulk contact defining layer 1007, and their respective thicknesses may be, for example, about 5 nm to 50 nm. To optimize device performance such as adjusting Vt, at least one of the first channel layer defining 1005 and the second channel layer defining 1009 may be doped, for example, by in-situ doping during growth.

[0042] Because each layer is doped separately, there can be doping concentration interfaces between them.

[0043] The first source / drain defining layer 1003, the first channel layer defining layer 1005, the bulk contact defining layer 1007, the second channel layer defining layer 1009, and the second source / drain defining layer 1011 may comprise various suitable semiconductor materials, such as elemental semiconductor materials like Si or Ge, compound semiconductor materials like SiGe, etc. To provide appropriate etching selectivity in subsequent processes, there may be etching selectivity between adjacent layers. For example, in the case where the substrate 1001 is a Si wafer, the first source / drain defining layer 1003, the bulk contact defining layer 1007, and the second source / drain defining layer 1011 may comprise Si, while the first channel layer defining layer 1005 and the second channel layer defining layer 1009 may comprise SiGe (e.g., the atomic percentage of Ge is about 10%-30%).

[0044] For ease of composition, such as Figure 2 As shown, an etch stop layer 1013, a mandrel layer 1015, and a hard mask layer 1017 can be sequentially formed on the aforementioned semiconductor layer stack, for example, by deposition. For example, the etch stop layer 1013 may include an oxide (e.g., silicon oxide) with a thickness of about 2 nm to 15 nm; the mandrel layer 1015 may include amorphous silicon or polycrystalline silicon with a thickness of about 50 nm to 200 nm; and the hard mask layer 1017 may include a nitride (e.g., silicon nitride) with a thickness of about 20 nm to 100 nm.

[0045] Photoresist (not shown) can be formed on the hard mask layer 1017 and patterned by photolithography to have a shape along a first direction ( Figure 2The semiconductor layer stack can have vertical sidewalls extending in the first direction. A photoresist can be patterned as an etch mask, and the hard mask layer 1017 and the core module layer 1015 can be selectively etched in sequence by, for example, reactive ion etching (RIE) to transfer the pattern of the photoresist to the hard mask layer 1017 and the core module layer 1015. The RIE can be performed in the vertical direction. The etching can stop at the etch stop layer 1011. The photoresist can then be removed. The core module layer 1015 (and the hard mask layer 1017) can then have vertical sidewalls extending in the first direction.

[0046] On the sidewalls, spacers 1019 can be formed. For example, a layer of nitride having a thickness of about 5 nm to 50 nm can be deposited in a substantially conformal manner, and then anisotropically etched, such as by RIE (which can stop at the etch stop layer 1013), in the vertical direction to remove the laterally extending portions and leave the vertically extending portions to form the spacers 1019. The spacers 1019 can then be used to at least partially define the dimensions of the upper source / drain contact layer.

[0047] In Figure 2 For convenience, the curved shape of the top ends of the spacers 1019 due to the RIE is not shown. Such curved shape, if present, does not affect the subsequent processes. The same applies to the spacers shown in the following figures.

[0048] As shown in FIG. 3(a), the spacers 1019 and the hard mask layer 1017 can be used as etch masks, and the second source / drain defining layer 1011, the second channel defining layer 1009, the body contact defining layer 1007, the first channel layer defining 1005, and the first source / drain defining layer 1003 can be selectively etched in sequence by, for example, RIE, to make the semiconductor layer stack have vertical sidewalls extending in the first direction as the active layer growth surface. The RIE can be performed in the vertical direction and can stop within the first source / drain defining layer 1003 without reaching the bottom surface of the first source / drain defining layer 1003.

[0049] On the vertical sidewalls of the semiconductor layer stack, an active layer 1021 can be formed by, for example, selective epitaxial growth. The active layer 1021 can include various suitable semiconductor materials, such as elemental semiconductor materials, such as Si, compound semiconductor materials, such as III-V compound semiconductors, SiC, etc. The active layer 1021 can then define a channel region having a thickness of, for example, about 3 nm to 20 nm. According to embodiments of the present disclosure, the thickness of the active layer 1021 (and thus, the channel region) can be determined by the epitaxial growth process, and thus the thickness of the channel region can be better controlled and the fluctuation of the thickness can be reduced.

[0050] The dopants can be driven from the first source / drain confinement layer 1003 and the second source / drain confinement layer 1011 into the active layer 1021 by annealing to form doped regions in the active layer 1021 corresponding to the first source / drain confinement layer 1003 and the second source / drain confinement layer 1011, respectively, as lower source / drain regions S / D L and upper source / drain regions S / D U and the dopants, if any, from the body contact confinement layer 1017 into the active layer 1021 to form a doped region in the active layer 1021 corresponding to the body contact confinement layer 1017 as a body contact region BD. In addition, if dopants are also present in the first channel confinement layer 1005 and / or the second channel confinement layer 1009, these dopants can also be driven into the corresponding regions in the active layer 1021 in the annealing process.

[0051] Here, the conditions of the annealing process (e.g., annealing time) can be controlled such that the degree of diffusion of the dopants from the first source / drain confinement layer 1003, the second source / drain confinement layer 1011, and the body contact confinement layer 1017 into the active layer 1021 can be comparable to the thickness of the active layer 1021. In this way, the positions of the lower source / drain regions S / D L , the body contact region BD, and the upper source / drain regions S / D U in the vertical direction can be defined by the first source / drain confinement layer 1003, the body contact confinement layer 1007, and the second source / drain confinement layer 1011, respectively. Accordingly, the positions of the channel regions between the lower source / drain regions S / D L and the upper source / drain regions S / D U may be defined by the first channel confinement layer 1005, the body contact confinement layer 1007, and the second channel confinement layer 1009. That is, the length of the channel regions can be determined by the thicknesses of the first channel confinement layer 1005, the body layer 1007, and the second channel confinement layer 1009, which can be determined by an epitaxial growth process and thus can be better controlled.

[0052] In this example, the upper source / drain regions S / D U and the lower source / drain regions S / D L may have the same conductivity type, and the body contact region BD can have a different conductivity type. However, the present disclosure is not limited thereto. For example, the upper source / drain regions S / D U and the lower source / drain regions S / D L may have different conductivity types (and thus can form, for example, a tunneling type device), and the body contact region BD can have a different conductivity type from one of them.

[0053] In Fig. 3(a), for ease of understanding, the lower source / drain region S / D L , the body contact region BD and the upper source / drain region S / D U In the following figures, for ease and clarity, these doped regions are not shown separately.

[0054] According to embodiments of the present disclosure, the size and the relative position in the vertical direction of the body contact region BD can be adjusted by controlling the thickness of at least one of the first channel-defining layer 1005, the body contact-defining layer 1007 and the second channel-defining layer 1009. For example, in the case where the thickness of the first channel-defining layer 1005 and the second channel-defining layer 1009 are substantially the same, the body contact region BD can be located substantially in the middle of the channel region in the vertical direction. Alternatively, in the case where the thickness of the first channel-defining layer 1005 and the second channel-defining layer 1009 are different from each other, the body contact region BD can be located close to the lower source / drain region S / D L (e.g. in the case where the first channel-defining layer 1005 is thinner than the second channel-defining layer 1009) or the upper source / drain region S / D U (e.g. in the case where the first channel-defining layer 1005 is thicker than the second channel-defining layer 1009).

[0055] In this example, the first source / drain-defining layer 1003 has a portion extending beyond the area defined by the sidewall 1019 and the hard mask layer 1017, and thus the active layer 1021 is also grown on this portion so as to have a laterally extending portion. This laterally extending portion of the active layer 1021 is doped due to the diffusion of the dopant in the first source / drain-defining layer 1003 underneath in the annealing process, and thus can serve as part of the lower source / drain region S / D L . This laterally extending portion of the lower source / drain region S / D L facilitates the landing of the subsequently formed contact to the lower source / drain region S / D L thereon.

[0056] According to another embodiment of the present disclosure, for realizing a self-aligned gate, as shown in Fig. 3(b), after the vertical sidewalls are patterned in the semiconductor layer stack using the sidewall 1019 and the hard mask layer 1017 as described above in connection with Fig. 3(a), the first channel-defining layer 1005 and the second channel-defining layer 1009 can be made laterally relatively recessed by selective etching. For controlling the etching depth, atomic layer etching (ALE) can be employed.

[0057] Here, the body contact confinement layer 1007 protrudes relative to the first channel confinement layer 1005 and the second channel confinement layer 1009 due to etch selectivity. However, the present disclosure is not limited thereto. For example, by selecting appropriate materials, an etch recipe can be employed that enables selective etching of the first channel confinement layer 1005 and the second channel confinement layer 1009 (relative to the first source / drain confinement layer 1003 and the second source / drain confinement layer 1011) and the body contact confinement layer 1007 such that the first channel confinement layer 1005 and the second channel confinement layer 1009 as well as the body contact confinement layer 1007 can all be recessed relative, thereby defining space for the gate stack.

[0058] Thereafter, an active layer 1021'can be similarly grown and doped with dopants therein. With regard to the active layer 1021'and the dopant implantation, reference can be made to the above description with regard to the active layer 1021 and the dopant implantation, except that the active layer 1021'can be in a curved shape due to the relative recessing of the first channel confinement layer 1005 and the second channel confinement layer 1009.

[0059] In the recessing of the ends of the first channel confinement layer 1005 and the second channel confinement layer 1009 (and, optionally, the body contact confinement layer 1007), a dummy gate 1023 can be formed by, for example, deposition and vertical RIE, as shown in Figure 4 Taking into account etch selectivity, the dummy gate 1023 can comprise, for example, SiC.

[0060] In the following, the embodiments of Fig. 3(a) will mainly be described. The descriptions are generally also applicable to the embodiments of Fig. 3(b), and separate descriptions with regard to the embodiments of Fig. 3(b) are provided where necessary.

[0061] So far, the semiconductor layer stack and the active layer 1021, 1021'formed thereon can extend continuously in a first direction. As shown in Figure 5 A photoresist 1025 can be formed and patterned to have strip-shaped openings extending in a second direction (in a horizontal direction in a top view of Figure 5 , intersecting (e.g., perpendicular) the first direction (in a vertical direction in a top view of Figure 5 ). Based on the photoresist 1025, the semiconductor layer stack and the active layer 1021, 1021'can be cut into different segments arranged in the first direction by, for example, vertical RIE, so as to define active regions of different devices. Thereafter, the photoresist 1025 can be removed. The RIE can proceed into the substrate 1001. In the thus formed trenches (areas cut between the segments), a dielectric material such as oxide can be filled to form isolation between the devices, such as shallow trench isolation (STI). In Figure 5The top view also schematically shows the section point AA′ in the cross-sectional view of the other accompanying figures.

[0062] To ensure that the subsequent gate stack primarily overlaps with the channel region and minimizes overlap with the source / drain regions, such as Figure 6 As shown, an isolation layer 1027 can be formed first. For example, an oxide layer completely covering the structure formed on the substrate 1001 can be formed by deposition, and the deposited oxide layer can be planarized by chemical mechanical polishing (CMP) (CMP can stop at the nitride hard mask layer 1017 and / or sidewall 1019), and then the planarized oxide layer can be etched back by, for example, RIE to form the isolation layer 1027. The thickness of the isolation layer 1027 is such that the region of the channel region in the active layer 1021 can be exposed (i.e., the region corresponding to the first channel defining layer 1005, the body contact defining layer 1007 and the second channel defining layer 1009). For example, the top surface of the isolation layer 1027 can be no higher than, preferably (slightly) lower than, the bottom surface of the first channel defining layer 1005.

[0063] A gate stack can be formed on the isolation layer 1027. The gate stack may include a gate dielectric layer 1029 and a gate conductor layer 1031. For example, the gate dielectric layer 1029 may include a high-k dielectric (such as HfO2) layer with a thickness of about 1 nm to 10 nm formed by, for example, deposition. The gate dielectric layer 1029 may be formed in a generally conformal manner. Before forming the gate dielectric layer 1029, a thin interface layer, such as an oxide of about 0.3 nm to 2 nm, may also be formed by, for example, oxidation or deposition. The gate conductor layer 1031 may include a work function adjustment layer such as TiN, TiAlN, Ta- or La-containing materials, and may also include a conductive material layer such as W, as needed. The gate conductor layer 1031 may be etched back so that its top surface can be higher than the top surface of the second channel defining layer 1009 to ensure overlap with the channel region (but should not be too high to reduce the upper source / drain region S / D corresponding to the second source / drain defining layer 1011). U (overlapping).

[0064] The resulting gate stack (1029 / 1031) is not self-aligned and therefore may be inconsistent with the lower source / drain S / D ratio. L and / or source / drain S / D U There is some overlap.

[0065] In combination with the above Figure 3(b) and 4 In another embodiment described, the gate stack may be self-contained for the channel region in the active layer 1021′.

[0066] For example, such as Figure 7As shown, the isolation layer 1027' can be formed as the isolation layer 1027 is formed above. The isolation layer 1027' differs from the isolation layer 1027 mainly in that the top surface of the isolation layer 1027' can be higher than the bottom surface of the first channel-defining layer 1005. This is due to the presence of the dummy gate 1023, such that the lower end of the channel region is not blocked by the isolation layer 1027' (despite its higher top surface).

[0067] Then, as shown, the dummy gate 1023 can be removed by selective etching. On the isolation layer 1027', the gate stack (1029 / 1031) can be formed as described above. The gate stack formed will enter into the space previously occupied by the dummy gate 1023, and thus overlap the channel region in the active layer 1021'. Figure 8

[0068] In this example, the gate conductor layer 1031 can be etched back so that its top surface is lower than the top surface of the second channel-defining layer 1009, and additionally due to the placement of the top surface of the isolation layer 1027' as described above, the end of the gate stack proximate to the active layer 1021' is defined by the dummy gate 1023, and the location of the dummy gate 1023 is defined by the first and second channel-defining layers 1005 and 1009 themselves, so the gate stack can be self-aligned to the channel region in the active layer 1021'.

[0069] Next, various contacts can be made. According to embodiments of the present disclosure, in addition to making contacts to the source / drain regions and the gate stack of the device, contacts can also be made to the body contact region.

[0070] For example, as shown, a masking layer 1033 can be formed to mask the gate stack. For example, the masking layer 1033 can be formed by depositing an oxide layer that completely covers the structures already formed on the substrate 1001, and planarizing the deposited oxide layer, such as by CMP (which can stop on the nitride hard mask layer 1017 and / or the sidewall 1019). Prior to forming the masking layer 1033, a portion of the gate conductor layer 1031 can be removed by selective etching, so as not to affect the contacts to the first source / drain-defining layer 1003 formed thereunder subsequently. Figure 9 The hard mask layer 1017 can be removed by selective etching, such as vertical RIE, to expose the core layer 1015. Here, the sidewall 1019, which is also nitride as the hard mask layer 1017, can be preserved due to its thickness. The core layer 1015 and the etch stop layer 1013 can be removed in sequence by selective etching, such as vertical RIE, to expose the second source / drain-defining layer 1011.

[0071]

[0072] ​​In this way, the semiconductor stack is exposed on the side of the active layer 1021 that is opposite to the gate stack. Landing pads for the contacts can be formed in the exposed semiconductor stack.

[0073] Here, the sidewall 1019 covers a portion of the second source / drain defining layer 1011, and this portion of the second source / drain defining layer 1011 covered by the sidewall 1019 can define the upper source / drain region S / D. U The contact pad of the contact part.

[0074] Next, the contact pad can be defined to the contact portion of the body contact area BD.

[0075] For example, such as Figure 10 As shown, the sidewall 1019 can be used as an etching mask to etch the second source / drain defining layer 1011 through, for example, a vertical RIE, to expose the second channel defining layer 1009. The second channel defining layer 1009 can be removed by selective etching. Due to the etching selectivity of the second channel defining layer 1009 (in this example, SiGe) relative to the second source / drain defining layer 1011 and the body contact defining layer 1007 (in this example, Si), the second source / drain defining layer 1011 and the body contact defining layer 1007 can be substantially unaffected.

[0076] Therefore, the body contact limiting layer 1007 can extend relative to the upper second source / drain limiting layer 1011, and this extended portion can limit the contact pad of the contact portion of the body contact area BD.

[0077] According to some embodiments, a contact portion can also be formed into the well region 1001w in the substrate 1001. In this case, to expose the underlying well region 1001w, the upper source / drain region S / D can be defined similarly using the sidewall 1019. U The contact pads of the contact portion are defined by sidewalls 1035 formed on the body contact defining layer 1007, thereby defining the contact pads of the contact portion of the body contact region BD. The sidewalls 1035 can be formed by the process described above for sidewall 1019. Considering etching selectivity, the sidewalls 1035 can include SiC. The portion of the body contact defining layer 1007 covered by the sidewalls 1035 can define the contact pads of the contact portion of the body contact region BD. Here, the sidewalls 1035 can also extend into the space between the second source / drain defining layer 1011 and the body contact defining layer 1007 that was originally occupied by the second channel defining layer 1009.

[0078] Then, as Figure 11As shown, sidewall 1035 (and sidewall 1019 and masking layer 1033) can be used as an etching mask to sequentially etch the body contact defining layer 1007, the first channel defining layer 1005, and the first source / drain defining layer 1003 via, for example, a vertically oriented RIE, to expose the well region 1001w. In this example, since both the first source / drain defining layer 1003 and the substrate 1001 comprise Si, the etching of the first source / drain defining layer 1003 may extend into the well region 1001w.

[0079] In addition, the first channel defining layer 1005 can be removed by selective etching.

[0080] like Figure 12 As shown, an interlayer dielectric layer 1037 can be formed on a substrate. For example, an oxide layer completely covering the structure formed on substrate 1001 can be deposited, and the deposited oxide layer can be planarized, such as by CMP (CMP can stop at the nitride sidewalls 1019), to form the interlayer dielectric layer 1037. Here, the oxide masking layer 1033 can be part of the interlayer dielectric layer 1037 and is not shown separately. Even if the masking layer 1033 includes different dielectric materials, it can be part of the interlayer dielectric layer; or it can be removed and replaced by the interlayer dielectric layer 1037. In addition, the sidewalls 1035 can be retained as part of the interlayer dielectric layer, or they can be removed and replaced by the interlayer dielectric layer 1037. Figure 12 The image shows the situation where sidewall 1035 has been removed.

[0081] In the interlayer dielectric layer 1037, S / D to the lower source / drain region can be formed. L Contact part 1039 L , to the source / leakage area S / D U Contact part 1039 U , Contact portion 1039 of the body contact area BD BD Contact 1039 to the gate stack (specifically, gate conductor layer 1031) G and the contact portion 1039 to the trap area 1001w w . Contact Department 1039 L It is attached to the portion of the first source / drain defining layer 1003 that extends relative to the upper conductive layer (e.g., gate conductor layer 1031). Contact portion 1039 U It is attached to the second source / drain limiting layer 1011 (the portion defined by the sidewall 1019) (the second source / drain limiting layer 1011 realizes the contact portion 1039) U To the source / leakage zone S / D U The electrical contact, and therefore can be called the upper source / drain contact layer). Contact portion 1039BD It is attached to the body contact limiting layer 1007 (the portion defined by the side wall 1035) (the body contact limiting layer 1007 realizes the contact portion 1039) BD These contacts are formed by etching holes in the interlayer dielectric layer 1037 and filling the holes with a conductive material such as a metal.

[0082] Furthermore, considering that the bulk contact limiting layer 1007 and the well region 1001w are relatively lightly doped, in order to reduce the contact resistance, ion implantation can be performed through the holes before filling the holes with conductive material to form relatively heavily doped contact regions 1041 (with the same conductivity type as the bulk contact limiting layer 1007 and the well region 1001w) in the bulk contact limiting layer 1007 and the well region 1001w, respectively. BD and 1041 W . Contact Department 1039 BD and 1039 W Contact area 1041 can be used separately BD and 1041 W The electrical connections are to the body contact area BD and the well area 1001w.

[0083] like Figure 12 As shown, the semiconductor device according to this embodiment may include a vertical active region defined by the active layer 1021. The vertical active region may include a lower source / drain region S / D. L Source / Drain S / D U And the channel regions between them. The thickness and length of the channel regions, as described above, can be controlled by epitaxial growth, which can achieve control precision even at the single-atom-layer level.

[0084] A volume contact area BD may be present in the channel region. The volume contact area BD may occupy only a portion of the channel region in the vertical direction. As mentioned above, the volume contact area BD may be located substantially in the middle of the channel region in the vertical direction, or it may be biased towards the lower source / drain region S / DL or the upper source / drain region S / D. U It can be achieved through contact part 1039 BD A volume bias is applied to the active region (via the volume contact region BD) to reduce the buoyancy effect. The position and size of the volume contact region BD in the vertical direction can be controlled by epitaxial growth, which can achieve control precision even at the single-atom-layer level.

[0085] The portion of the channel region other than the body contact region BD can also be doped (e.g., by diffusion from the first channel defining layer 1005 and / or the second channel defining layer 1009), and the doping characteristics can differ from those in the body contact region BD. For example, the doping concentration in the body contact region BD can be higher than that between the body contact region BD and the lower source / drain region S / D.L The doping concentration in the region between (defined by diffusion from the first channel defining layer 1005) and / or the bulk contact region BD and the upper source / drain region S / D U The doping concentration in the region between (defined by diffusion from the second channel defining layer 1009).

[0086] The gate stack (1029 / 1031) can be set on one side of the vertical active region in the second direction. Figure 12 The gate stack (left side) faces the vertical active region and overlaps with the channel region therein. The gate stack can be self-aligned with the channel region. In this case, the end of the gate stack near the vertical active region can have an upper protrusion, a lower protrusion, and a recess between the upper and lower protrusions. The body contact defining layer 1007 can be self-aligned with the recess at the end of the gate stack.

[0087] On the side of the vertical active region opposite to the gate stack ( Figure 12 The right side of the image may have a body contact limiting layer 1007 (or, body contact layer) and a contact portion 1039. BD It can be attached to it. The body contact area BD can be self-aligned with the body contact layer.

[0088] In the above embodiments, the contact portion 1039 can be used respectively. BD and 1039 W Apply volume bias and well bias. However, this disclosure is not limited thereto.

[0089] Figures 13 to 17 A schematic diagram of a portion of the process for manufacturing a semiconductor device according to another embodiment of the present disclosure is shown.

[0090] In combination as described above Figure 10 After the sidewall 1035 is formed, as Figure 13 As shown, the sidewall 1035 (as well as the sidewall 1019 and the shielding layer 1033) can be used as an etching mask to selectively etch the body contact defining layer 1007 through, for example, a vertical RIE. Figure 13 The diagram shows that a portion of the first channel defining layer 1005 is also etched to ensure that the subsequently formed protective layer can completely cover the sidewalls of the body contact defining layer 1007.

[0091] like Figure 14 As shown, a protective layer 1043 in the form of a sidewall can be formed through a sidewall forming process to shield the sidewall of the body contact defining layer 1007. Considering etching selectivity and subsequent removal of the sidewall 1035 and the protective layer 1043, the protective layer 1043 may include SiC, just like the sidewall 1035.

[0092] like Figure 15As shown, the protective layer 1043 and sidewall 1035 (as well as sidewall 1019 and shielding layer 1033) can be used as etching masks to selectively etch the first channel defining layer 1005 through, for example, a vertical RIE, to expose the first source / drain defining layer 1003. The first source / drain defining layer 1003 can be selectively etched to expose the well region 1001w. Unlike the above embodiment, in this embodiment, the selective etching of the first source / drain defining layer 1003 can cause the first source / drain defining layer 1003 to be recessed relative to the body contact defining layer 1007. For example, ALE or wet etching using a TMAH solution can be used. Similarly, the Si substrate 1001 can also be etched here. However, due to the presence of the protective layer 1043 and the first channel defining layer 1005, the body contact defining layer 1007 can remain unaffected.

[0093] After that, as Figure 16 As shown, the first channel defining layer 1005 of SiGe and the protective layer 1043 and sidewall 1035 of SiC can be removed separately by selective etching. And it can be combined as described above. Figure 12 The interlayer dielectric layer 1037 is formed.

[0094] like Figure 17 As shown, various contact portions can be formed in the interlayer dielectric layer 1037. The difference from the above embodiment lies in the body contact portion 1039. BD It can extend downwards into the well region 1001w. Body bias can be achieved via contact portion 1039. W Trap area 1001w and body contact part 1039 BD ′ and is applied.

[0095] The semiconductor devices according to embodiments of this disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such semiconductor devices, and electronic devices can be constructed therefrom. Therefore, this disclosure also provides an electronic device including the aforementioned semiconductor devices. The electronic device may further include components such as a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit. Examples of such electronic devices include smartphones, personal computers, tablet computers (PCs), artificial intelligence devices, wearable devices, power banks, automotive electronic devices, communication devices, or Internet of Things (IoT) devices.

[0096] According to embodiments of this disclosure, a method for manufacturing a system-on-a-chip (SoC) is also provided. This method may include the methods described above. Specifically, multiple devices may be integrated on the chip, at least some of which are manufactured according to the methods of this disclosure.

[0097] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, it should be understood by those skilled in the art that the layers, regions, etc. of the desired shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0098] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: an active region disposed vertically with respect to a substrate on the substrate, including a lower source / drain region, an upper source / drain region, and a middle portion between the lower source / drain region and the upper source / drain region to define a channel region; a gate stack disposed on a first side of the active region in a lateral direction with respect to the substrate to at least overlap the middle portion of the active region; a body contact layer disposed on a second side of the active region in the lateral direction opposite the first side to overlap the middle portion of the active region to apply a body bias to the active region; a body contact to the body contact layer to receive the body bias, wherein the body contact layer extends away from the active region in the lateral direction, the body contact being in contact with the body contact layer; an upper source / drain region contact layer disposed on the second side of the active region in the lateral direction to contact the upper source / drain region; and an upper source / drain region contact on the upper source / drain region contact layer, wherein in a vertical direction with respect to the substrate, a portion of the middle portion of the active region overlapping the body contact layer is a first spaced distance from the lower source / drain region and a second spaced distance from the upper source / drain region, wherein the active region is defined by a single-crystalline semiconductor layer including a vertically-extending portion to provide the active region and a laterally-extending portion extending from a lower end of the vertically-extending portion on the first side in the vertical direction, the semiconductor device further comprising: a lower source / drain region contact to the lower source / drain region on the laterally-extending portion of the semiconductor layer; a lower source / drain region-defining layer extending from below the laterally-extending portion of the semiconductor layer to a surface of the semiconductor layer on the second side.

2. The semiconductor device of claim 1, wherein, the first spaced distance is substantially equal to the second spaced distance.

3. The semiconductor device of claim 1, wherein, the middle portion of the active region includes a body contact region as a body contact region, the body contact layer being in contact with the body contact region.

4. The semiconductor device of claim 3, wherein, a conductivity type of the body contact region is opposite to a conductivity type of at least one of the lower source / drain region and the upper source / drain region.

5. The semiconductor device of claim 3, wherein, the body contact region is self-aligned to the body contact layer.

6. The semiconductor device of claim 3, wherein, the body contact layer includes a dopant of a same conductivity type as a dopant in the body contact region.

7. The semiconductor device of claim 3, wherein, the body contact region occupies only a portion of a range of the middle portion of the active region in the vertical direction.

8. The semiconductor device of claim 7, wherein, the body contact region has different doping characteristics from a remaining portion of the middle portion of the active region.

9. The semiconductor device of claim 8, wherein, a doping concentration in the body contact region is higher than a doping concentration in at least one of a region between the body contact region and the lower source / drain region and a region between the body contact region and the upper source / drain region in the middle portion of the active region.

10. The semiconductor device of claim 1, wherein, the body contact layer includes a single-crystalline semiconductor.

11. The semiconductor device of claim 1, further comprising: a contact region in the body contact layer, the contact region being highly doped with respect to a remaining region in the body contact layer, the body contact being in contact with the contact region.

12. The semiconductor device of claim 1, wherein, the upper source / drain region contact layer includes a single-crystalline semiconductor.

13. The semiconductor device of claim 1, wherein, the upper source / drain region is self-aligned to the upper source / drain region contact layer.

14. The semiconductor of claim 1, wherein, The upper source / drain contact layer includes dopants of the same conductivity type as the upper source / drain region.

15. The semiconductor device of claim 1, wherein, The upper source / drain contact layer and the body contact layer are substantially uniformly spaced apart from each other in the vertical direction.

16. The semiconductor device of claim 1, wherein, The body contact layer extends beyond the upper source / drain contact layer in the lateral direction, wherein the body contact portion is in contact with the portion of the body contact layer that extends beyond the upper source / drain contact layer.

17. The semiconductor device of claim 1, further comprising: a well region in the substrate; and a well region contact portion to the well region, wherein the body contact portion extends to the well region.

18. The semiconductor device of claim 1, wherein, The semiconductor layer is in the form of nanosheets or nanowires.

19. The semiconductor device of claim 1, wherein, The lower source / drain region is self-aligned to the portion of the lower source / drain definition layer on the second side.

20. The semiconductor device of claim 1, wherein, The lower source / drain definition layer includes dopants of the same conductivity type as the lower source / drain region.

21. The semiconductor device of claim 1, wherein, The lower source / drain definition layer comprises a single-crystalline semiconductor.

22. The semiconductor device of claim 1, wherein, The lower source / drain definition layer and the body contact layer are substantially uniformly spaced apart from each other in the vertical direction.

23. The semiconductor device of claim 1, wherein, The gate stack is self-aligned to a middle portion of the active region.

24. The semiconductor device of claim 23, wherein, An end portion of the gate stack proximate to the active region has a recess, and the body contact layer is self-aligned to the recess.

25. A method of manufacturing the semiconductor device of claim 1, comprising: providing a stack of a first source / drain definition layer, a first channel definition layer, a body contact definition layer, a second channel definition layer, and a second source / drain definition layer on a substrate; forming an active layer on vertical sidewalls of the stack that extend in a first direction; implanting dopants in the first source / drain definition layer, dopants in the body contact definition layer, and dopants in the second source / drain definition layer into respective portions of the active layer to form a lower source / drain region, a body contact region, and an upper source / drain region, respectively; forming a gate stack on a side of the active layer opposite to the stack in a second direction that intersects the first direction; and forming a body contact portion to the body contact definition layer. The stack and the active layer are formed by an epitaxial growth process.

26. The method of claim 25, wherein, 27. The method of claim 25, wherein, prior to forming the active layer, the method further comprises selectively etching the first channel definition layer and the second channel definition layer from the vertical sidewalls to be relatively recessed, after forming the active layer, the method further comprises forming a dummy gate in the recess in a space formed after forming the active layer, and forming the gate stack further comprises removing the dummy gate.

28. The method of claim 25, further comprising: patterning the stack such that the body contact definition layer is overhanging relative to the second source / drain definition layer and the first channel definition layer and the second channel definition layer are removed, wherein the body contact portion is in contact with the portion of the body contact definition layer that is overhanging relative to the second source / drain definition layer. A well region is formed in the substrate, and the method further comprises:

29. The method of claim 25, wherein, ​ patterning the stack to have the body contact defining layer overhang relative to the first source / drain defining layer and to remove the first channel defining layer and the second channel defining layer, wherein the body contact extends from the body contact defining layer to the well region.

30. The method of claim 25, wherein, forming the body contact includes: forming an interlayer insulating layer on the substrate; forming a body contact hole in the interlayer insulating layer to expose a portion of the body contact defining layer; implanting dopants into the exposed portion of the body contact defining layer via the body contact hole; and filling the body contact hole with a conductive material to form the body contact.

31. An electronic device comprising the semiconductor device of any one of claims 1 to 24.

32. The electronic device of claim 31, wherein, The electronic device comprises a smartphone.

33. The electronic device of claim 31, wherein, The electronic device comprises a personal computer.

34. The electronic device of claim 31, wherein, The electronic device comprises a tablet computer.

35. The electronic device of claim 31, wherein, The electronic device comprises an artificial intelligence device.

36. The electronic device of claim 31, wherein, The electronic device comprises a wearable device.

37. The electronic device of claim 31, wherein, The electronic device comprises a mobile power supply.

38. The electronic device of claim 31, wherein, The electronic device comprises a car electronic device.

39. The electronic device of claim 31, wherein, The electronic device comprises a communication device.

40. The electronic device of claim 31, wherein, The electronic device comprises an Internet of Things device.

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