Display panel, display device and preparation method of display panel

Abstract

The invention provides a display panel, a display device and a preparation method of the display panel. The display panel comprises a substrate and a driving circuit layer. The driving circuit layer is located on one side of the substrate and comprises a driving circuit, and the driving circuit comprises at least one first type transistor. The first type transistor comprises a grid electrode, an active layer, a first electrode and a second electrode, the second electrode is located on the side, away from the substrate, of the first electrode, the active layer comprises a first end face and a second end face which are opposite in the direction perpendicular to the substrate, the first end face makes contact with the first electrode, and the second end face makes contact with the second electrode. The second end face is in contact with the second electrode. The active layer further comprises a side face located between the first end face and the second end face, the grid electrode is located on one side of the side face of the active layer, and the orthographic projection of the grid electrode on the plane where the side face is located is overlapped with the side face.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a display panel, a display device, and a method for manufacturing a display panel. Background Art

[0002] An electronic paper display panel has advantages such as being easy to read, portable, resource-saving, low in energy consumption, and fast in transmission speed, and thus has broad development prospects.

[0003] The characteristics of the transistors in the existing electronic paper display panel are affected by the black glue layer located above it, resulting in a decline in the display performance of the electronic paper display panel. Summary of the Invention

[0004] The present application provides a display panel, a display device, and a method for manufacturing a display panel.

[0005] In a first aspect of the present application, a display panel is provided, and the display panel includes:

[0006] A substrate;

[0007] A driving circuit layer, located on one side of the substrate, includes a driving circuit; the driving circuit includes at least one first type of transistor; the first type of transistor includes a gate, an active layer, a first electrode, and a second electrode; the second electrode is located on a side of the first electrode away from the substrate, in a direction perpendicular to the substrate, the active layer includes opposite first and second end faces, the first end face is in contact with the first electrode, the second end face is in contact with the second electrode; the active layer further includes a side surface located between the first end face and the second end face, the gate is located on one side of the side surface of the active layer, and a positive projection of the gate on the plane where the side surface is located overlaps with the side surface.

[0008] In one embodiment, the first electrode includes a first main body portion and a first protruding portion extending from the first main body portion toward the second electrode, and a positive projection of the first protruding portion on the plane where the side surface is located overlaps with the side surface; and / or,

[0009] The second electrode includes a second main body portion and a second protruding portion extending from the second main body portion toward the active layer, and a positive projection of the second protruding portion on the plane where the side surface is located overlaps with the side surface.

[0010] In one embodiment, the first main body portion is in contact with the first end face; and / or, the second main body portion is in contact with the second end face.

[0011] In one embodiment, the orthographic projections of the first protrusions on the plane where the side surface is located are all within the side surface; and / or, the orthographic projections of the second protrusions on the plane where the side surface is located are all within the side surface.

[0012] In one embodiment, the first protrusions are located on a side of the active layer away from the gate; and / or, the second protrusions are located on a side of the active layer away from the gate.

[0013] In one embodiment, the side surface between the first end surface and the second end surface where the active layer is located is perpendicular to the surface of the substrate facing the first electrode.

[0014] In one embodiment, the driving circuit layer further includes a first trace, the first trace is located between the first electrode and the substrate, and the first trace is overlapped with the first electrode.

[0015] In one embodiment, the display panel includes a display area and a non-display area: the driving circuit layer includes transistors located in the non-display area and transistors located in the display area;

[0016] The driving circuit layer further includes a first trace and a second trace, the first trace is located between the first electrode and the substrate and is electrically connected to the transistors located in the non-display area; the second trace is provided on the same layer as the second electrode and is electrically connected to the transistors located in the display area;

[0017] The driving circuit layer further includes an insulating layer between the first trace and the second trace, the insulating layer is provided with a contact hole exposing the first trace, and the second trace contacts the first trace through the contact hole.

[0018] A second aspect of the present application provides another display panel, the display panel including a display area and a non-display area:

[0019] A substrate;

[0020] A driving circuit layer located on the substrate, the driving circuit layer including transistors located in the non-display area, and the transistors including an active layer;

[0021] A protective layer located on a side of the driving circuit layer away from the substrate, and the orthographic projection of the protective layer on the substrate covers the orthographic projection of the active layer located in the non-display area on the substrate;

[0022] An electrophoretic layer located on a side of the driving circuit layer away from the substrate;

[0023] A light-shielding layer is located on the side of the protective layer away from the substrate, and the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the active layer located in the non-display area on the substrate.

[0024] In one embodiment, the protective layer is only located in the non-display area.

[0025] The third aspect of the present application provides a display device, which includes a power supply circuit and the above-mentioned display panel, and the power supply circuit is used to supply power to the display panel.

[0026] The fourth aspect of the present application provides a method for manufacturing a display panel, and the manufacturing method includes:

[0027] Providing a substrate, and forming a gate and a first electrode on one side of the substrate;

[0028] Forming an active layer, in a direction perpendicular to the substrate, the active layer includes opposite first end faces and second end faces, and a side surface located between the first end face and the second end face; the first electrode is in contact with the first end face, and at least part of the first electrode is located on the side of the first end face facing the substrate; the gate is located on one side of the side surface of the active layer, and the orthographic projection of the gate on the plane where the side surface is located overlaps with the side surface;

[0029] Forming a second electrode, the second electrode is in contact with the second end face, and at least part of the second electrode is located on the side of the second end face away from the substrate.

[0030] The display panel, display device and manufacturing method of the display panel provided by the embodiments of the present application can reduce the influence of conductive particles or external electric fields on the active layer, ensure the working stability of the transistor, and improve the display quality and reliability of the display panel.

[0031] It should be understood that the above general description and subsequent detailed description are only exemplary and explanatory, and cannot limit the present application. Description of the Drawings

[0032] The drawings here are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0033] Figure 1 Partial structural schematic diagram of a display panel provided in the related art;

[0034] Figure 2 Partial structural schematic diagram of a display panel provided in an embodiment of the present application;

[0035] Figure 3 ForFigure 2 Top view of a display panel provided by the illustrated embodiment;

[0036] Figure 4 is Figure 2 Schematic cross-sectional view of the display panel provided by the illustrated embodiment taken along the AA direction;

[0037] Figure 5 Schematic cross-sectional view of the display panel provided by another embodiment of the present application taken along the AA direction;

[0038] Figures 6 to 11 Flow chart for preparing the display panel provided by an embodiment of the present application;

[0039] Figure 12 Partial schematic view of the display panel provided by another embodiment of the present application. Detailed implementation manners

[0040] Here, the technical solutions in the embodiments (or "implementation manners") of the present application will be clearly and completely described in conjunction with the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numerals in different drawings represent the same or similar elements.

[0041] If there are terms related to directional indications or positional relationships in the embodiments of the present application (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, lateral, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement conditions between components in a specific posture (as shown in the accompanying drawings); if this specific posture changes, then the directional indication or positional relationship also changes accordingly. In addition, terms such as "first" and "second" in the embodiments of the present application are only used for the purpose of convenient description and cannot be construed as indicating or implying relative importance.

[0042] The display panel, display device, and preparation method of the display panel in the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. Without conflict, the features in the following embodiments and implementation manners can be supplemented or combined with each other.

[0043] The electronic paper display panel includes a display area and a non-display area. When the electronic paper display panel adopts GOA (Gate Driver On Array) technology, the non-display area of the electronic paper display panel includes a gate driving circuit. Figure 1The partial structure of the non-display area of a display panel is shown when the electronic display panel adopts the GOA technology. Among them, the display panel includes a substrate 10', a driving circuit layer 20', and a light-shielding layer 30'. The driving circuit layer 20' includes a transistor 21', and the transistor 21' includes a gate 211', and an active layer 212', a first electrode 213', and a second electrode 214' located on the side of the gate 211' away from the substrate 10'. The active layer 212', the first electrode 213', and the second electrode 214' are arranged in a direction parallel to the substrate 10'. The light-shielding layer 30' is located on the side of the driving circuit layer 20' away from the substrate 10'.

[0044] The light-shielding layer 30' generally contains toner to increase its light-shielding performance. Since the toner is a conductive particle, the light-shielding layer 30' cannot prevent the influence of an external electric field and static electricity on the active layer 212'. Moreover, when the orthographic projection of the light-shielding layer 30' above the transistor 21' on the substrate 10' overlaps with the orthographic projection of the active layer 212' on the substrate 10', the conductive particles are equivalent to forming a top-gate structure above the active layer 212', which will affect the characteristics of the active layer 212', making its turn-on and turn-off affected, and further affecting the display effect of the display panel.

[0045] An embodiment of the present application provides a display panel, as Figure 2 and Figure 3 shown. The display panel includes a substrate 10 and a driving circuit layer 20 located on one side of the substrate 10. Among them,

[0046] The driving circuit layer 20 includes a driving circuit, and the driving circuit includes at least one first-type transistor 21. The first-type transistor 21 includes a gate 211, an active layer 212, a first electrode 213, and a second electrode 214. In at least one of the first-type transistors 21, the second electrode 214 is located on the side of the first electrode 213 away from the substrate 10. In a direction perpendicular to the substrate 10, the active layer 212 includes opposite first end faces 2121 and second end faces 2122. The first end face 2121 is in contact with the first electrode 213, and the second end face 2122 is in contact with the second electrode 214. The active layer 212 further includes a side face 2123 located between the first end face 2121 and the second end face 2122. The gate 211 is located on one side of the side face 2123 of the active layer 212, and the orthographic projection of the gate 211 on the plane where the side face 2123 is located overlaps with the side face 2123.

[0047] Compared with the arrangement of the active layer, the first electrode, and the second electrode in a direction parallel to the substrate, in the display panel of the present application, the active layer 212, the first electrode 213, and the second electrode 214 of the first type of transistor 21 are arranged in a direction perpendicular to the substrate 10, that is, in the vertical direction, and the gate 211 is located on one side of the side surface 2123 of the active layer 212. When the gate-source voltage of the first type of transistor 21 is greater than the threshold voltage (turn-on voltage), a conductive channel is formed in the vertical direction in the active layer 212, enabling current to flow between the first electrode 213 and the second electrode 214. Even if there are conductive particles in the light-shielding layer above the driving circuit layer 20 or an external electric field exists, the vertical channel design can reduce the influence of the conductive particles or the external electric field on the active layer 212, ensuring the reliability of carrier generation and transmission in the conductive channel. Moreover, the second electrode 214 is located above the active layer 212 and is connected to the active voltage signal. The second electrode 214 will not be interfered with by the conductive particles or the external electric field, and can also improve the influence of the conductive particles or static electricity on the contact of the active layer 212, thereby being beneficial to improving the switching characteristics and operating stability of the first type of transistor 21.

[0048] In one embodiment, one of the first electrode 213 and the second electrode 214 is the source electrode, and the other is the drain electrode.

[0049] In one embodiment, the gate 211 and the active layer 212 of the first type of transistor 21 are arranged horizontally in the driving circuit layer 20, and the distance between the gate 211 and the active layer 212 can be adjusted, thereby realizing the adjustment of the switching performance, threshold voltage, etc. of the first type of transistor 21. The active layer 212, the first electrode 213, and the second electrode 214 of the first type of transistor 21 are arranged vertically, and the first electrode 213 and the second electrode 214 can be laid out according to signal transmission and circuit function requirements, which is beneficial to simplifying the signal transmission path of the driving circuit.

[0050] In one embodiment, the size range of the distance between the gate 211 and the active layer 212 is If the distance between the gate and the active layer is too small, leakage current may occur. If it is too large, the electric field intensity generated by the voltage applied to the gate may not effectively control the carrier concentration in the active layer, and it will also cause the first type of transistor to occupy more space. When the distance between the gate 211 and the active layer 212 is within the above size range, it can not only ensure the switching performance of the first type of transistor but also be beneficial to reducing the space occupied by the first type of transistor. In some embodiments, the distance between the gate 211 and the active layer 212 can be, for example, etc.

[0051] In one embodiment, such as Figure 2As shown, the active layer 212 is perpendicular to the surface of the substrate 10 facing the first electrode 213 on the side between the first end face 2121 and the second end face 2122. When there are conductive particles in other film layers above the driving circuit layer 20, through the above arrangement, the influence of the conductive particles on the active layer 212 can be avoided to the greatest extent, which is beneficial to further improving the switching performance and stability of the first type of transistor 21.

[0052] In one embodiment, the positive projection of the first electrode on the plane where the side surface of the active layer is located does not overlap with the positive projection of the gate on the plane where this side surface is located. With such an arrangement, the parasitic capacitance of the first type of transistor can be reduced, the switching speed of the first type of transistor can be increased, and the power consumption of the first type of transistor can be reduced.

[0053] In one embodiment, as Figure 2 shown, the positive projection of the second electrode 214 on the plane where the side surface 2123 of the active layer 212 is located does not overlap with the positive projection of the gate 211 on the plane where this side surface is located. With such an arrangement, the parasitic capacitance of the first type of transistor can be reduced, the switching speed of the first type of transistor can be increased, and the power consumption of the first type of transistor can be reduced.

[0054] In one embodiment, as Figure 4 shown, the second electrode 214 includes a second main body portion 2141 and a second protrusion portion 2142 extending from the second main body portion 2141 towards the active layer 212, and the positive projection of the second protrusion portion 2142 on the plane where the side surface 2123 is located overlaps with the side surface 2123.

[0055] In the direction perpendicular to the substrate, the shortest distance between the first electrode 213 and the second electrode 214 is the first dimension L of the channel of the first type of transistor 21; the total length of the contour line of the overlapping part of the positive projection of the second electrode 214 on the plane where the side surface 2123 is located and the side surface 2123 is the second dimension W of the channel of the first type of transistor. In the Figure 4 shown embodiment, the second electrode 214 includes the second protrusion portion 2142. Compared with the Figure 5 embodiment without the second protrusion portion, when the second electrode 214 includes the second protrusion portion 2142, the ratio of its second dimension W to the first dimension L is larger, that is, the ratio of the channel width to the channel length of the first type of transistor is larger. With such an arrangement, the first type of transistor 21 can allow more carriers to pass through in the on state, enabling the first type of transistor 21 to have a larger on-current, which is beneficial to reducing display delay and improving the smoothness of the display screen.

[0056] In Figure 4In the illustrated embodiment, the second electrode 214 includes a plurality of second protrusions 2142, and all the second protrusions 2142 have overlapping portions with the side surface 2123. The cross-sectional shape of the second protrusion 2142 is rectangular. In other embodiments, the cross-sectional shape of the second protrusion may also be other shapes, which are not limited herein.

[0057] In one embodiment, as Figure 2 and Figure 4 shown, the second main body portion 2141 contacts the second end surface 2122. Specifically, a portion of the second main body portion 2141 facing the substrate contacts the second end surface 2122, and a partial region is connected to the second protrusion 2142. With such an arrangement, the structure of the second electrode 214 is simple and convenient to fabricate.

[0058] In one embodiment, as Figure 2 and Figure 4 shown, the orthographic projections of the second protrusions 2142 on the plane where the side surface 2123 is located are all within the side surface 2123. Thus, when the size of the second protrusion 2132 is fixed, the value of the second dimension W can be maximized, which is more conducive to increasing the on-current of the first type of transistor.

[0059] In another embodiment, the first electrode includes a first main body portion and a first protrusion extending from the first main body portion toward the second electrode, and the orthographic projection of the first protrusion on the plane overlaps with the side surface. With such an arrangement, the ratio of the channel width to the channel length of the first type of transistor is larger, and more carriers can pass through the first type of transistor in the on-state, enabling the first type of transistor to have a larger on-current, which is beneficial to reducing display delay and improving the smoothness of the display screen.

[0060] In one embodiment, the first main body portion contacts the first end surface. Specifically, a portion of the first main body portion facing the substrate contacts the first end surface, and a partial region is connected to the first protrusion. With such an arrangement, the structure of the first electrode is simple and convenient to fabricate.

[0061] In one embodiment, the orthographic projections of the first protrusions on the plane where the side surface is located are all within the side surface. Thus, when the size of the first protrusion is fixed, the value of the second dimension W can be maximized, which is more conducive to increasing the on-current of the first type of transistor.

[0062] In one embodiment, the ratio of the second dimension W to the first dimension L ranges from 6:4 to 3000:4. When the ratio of the second dimension W to the first dimension L is too small, the on-current of the first type of transistor 21 is small, and the driving ability of the first type of transistor is weak; when the ratio of the second dimension W to the first dimension L is too large, the current density in the conductive channel of the first type of transistor is large, resulting in an increase in the power consumption of the first type of transistor. In some embodiments, the ratio of the second dimension W to the first dimension L can be, for example, 6:4, 50:4, 500:4, 2000:4, or 3000:4, etc.

[0063] In one embodiment, as Figure 2 and Figure 4 shown, the first protrusion or the second protrusion 2142 is located on the side of the active layer 212 away from the gate 211. In the first type of transistor 21, an electric field is generated between the gate 211 and the first electrode 213 or the second electrode 214, and the electric field exerts a force on the carriers in the active layer 212. When the first protrusion or the second protrusion 2142 is located on the side of the active layer 212 away from the gate 211, it is possible to avoid an additional influence of the first protrusion or the second protrusion on the carrier transport in the active layer, which is beneficial to improving the stability of the first type of transistor 21.

[0064] In one embodiment, the display panel includes a display area and a non-display area. As Figure 2 shown, the driving circuit layer 20 includes the first type of transistor 21 located in the non-display area. The display panel may further include transistors located in the display area. The first type of transistor 21 has the advantages of being free from external environmental interference and the distance between the gate 211 and the active layer 212 being adjustable. The transistors located in the display area can be the first type of transistor 21. Alternatively, the transistors in the display area can be the second type of transistor, and the structure of the second type of transistor can be as Figure 1 shown. Among them, the transistors in the non-display area can be the transistors of the gate driving circuit, and the transistors in the display area can be the transistors of the pixel circuit.

[0065] In one embodiment, as Figure 2 and Figure 3 shown, the driving circuit layer 20 further includes a first trace 22, the first trace 22 is located between the first electrode 213 and the substrate 10, and the first trace 22 is overlapped with the first electrode 213. With this arrangement, the flat surface of the substrate 10 can be fully utilized for wiring, reducing the detour or crossing of the traces, and reducing the interference and loss during signal transmission.

[0066] In one embodiment, as Figure 2 and Figure 3As shown, the first trace 22 of the driving circuit layer 20 is electrically connected to the first type of transistor 21 located in the non-display area. The driving circuit layer 20 further includes a second trace 23, which is provided on the same layer as the second electrode 214 and is electrically connected to the transistor located in the display area. The driving circuit layer 20 further includes an insulating layer 24 located between the first trace 22 and the second trace 23. The insulating layer 24 is provided with a contact hole 241 exposing the first trace 22, and the second trace 23 contacts the first trace 22 through the contact hole 241. In some embodiments, the gate driving circuit and the pixel circuit are electrically connected through the first trace 22 and the second trace 23.

[0067] In Figure 1 it is, the first trace 22' and the second trace 23' are electrically connected through the transparent electrode layer 30'. The transparent electrode layer 30' is located above the driving circuit layer 20 and is easily damaged during the manufacturing process, thus having an adverse effect on the signal transmission of the display panel. Moreover, the transparent electrode layer 30' is connected to the trace through the via 251' in the passivation layer 25'. When a light-shielding layer 30' is provided above the driving circuit layer 20, part of the material of the light-shielding layer 30' will enter the via, causing the resistance of the transparent electrode layer 30' in the via to change, resulting in the problem of weak line defects in the display panel under a heavy-load picture. In Figure 2 the embodiment shown, the first trace 22 directly contacts the second trace 23 through the contact hole 241, which can avoid the above problems, prevent the traces from being interfered by external factors, and improve the reliability of the signal transmission of the display panel.

[0068] In one embodiment, as Figure 2 shown, the display panel further includes a light-shielding layer 30 located on the side of the driving circuit layer 20 away from the substrate. The active layer 212 in the driving circuit layer 20 may generate carriers under the excitation of external light, affecting the normal switching characteristics of the first type of transistor and the accuracy of signal transmission. The light-shielding layer 30 can block the light, avoid the direct irradiation of the light on the driving circuit layer, and ensure the normal operation of the first type of transistor and the like.

[0069] In one embodiment, the material of the light-shielding layer 30 is a conductive adhesive, and the conductive adhesive contains particles such as carbon powder.

[0070] The embodiment of the present application further provides a manufacturing method of a display panel. This manufacturing method can be used to manufacture the above-mentioned display panel, and this manufacturing method includes the following steps S100 to S300:

[0071] S100: As Figure 6 and Figure 7 shown, provide a substrate 10, and form a gate 211 and a first electrode 213 on one side of the substrate 10;

[0072] S200: As shown in Figure 8 , an active layer 212 is formed. In a direction perpendicular to the substrate 10, the active layer includes opposite first end faces 2121 and second end faces 2122, and side faces 2123 located between the first end faces 2121 and the second end faces 2122; the first electrode 213 is in contact with the first end face 2121, and at least part of the first electrode 213 is located on a side of the first end face 2121 facing the substrate 10; the gate 211 is located on one side of the side face 2123 of the active layer 212, and a positive projection of the gate 211 on the plane where the side face 2123 is located overlaps with the side face 2123.

[0073] S300: As shown in Figure 10 , a second electrode 214 is formed. The second electrode 214 is in contact with the second end face 2122, and at least part of the second electrode 214 is located on a side of the second end face 2122 away from the substrate 10.

[0074] In one embodiment, in step S100, the gate 211 is formed first, and then the first electrode 213 is formed. As shown in Figure 6 , the first trace 22 is formed while the gate 211 is formed. The specific steps include depositing an electrode material layer on the substrate 10 and coating a photoresist above the electrode material layer. Then, a halftone mask is used for exposure and the photoresist is patterned to form photoresist patterns with different thicknesses. Through an etching process, the electrode material layer is etched. The electrode material in the area where the electrode material layer is not covered by the photoresist or is covered by a thinner photoresist is completely etched or etched more, and the electrode material in the area where the electrode material layer is covered by a thicker photoresist is not etched or etched less, so that the gate 211 and the first trace 22 can be formed simultaneously.

[0075] In one embodiment, in step S100, the active layers located in the display area and the non-display area can be formed simultaneously. When the thicknesses of the active layers in different regions are inconsistent, the specific steps of forming the active layer include depositing a semiconductor material layer on the substrate 10 and coating a photoresist above the semiconductor material layer. Then, a halftone mask is used for exposure and the photoresist is patterned to form photoresist patterns with different thicknesses. The semiconductor material layer is etched through an etching process. In the areas where the semiconductor material layer is not covered by the photoresist or the covered photoresist is thinner, the semiconductor material is completely etched or etched more, and in the areas where the semiconductor material layer is covered by the thicker photoresist, the semiconductor material is not etched or etched less, so that semiconductor materials with different thicknesses can be formed simultaneously. Then, N-type impurities are introduced into specific regions of the etched semiconductor material layer by ion implantation or diffusion to form an N+ layer. Among them, the etching solution used for etching the N+ layer cannot corrode the materials of the gate, the first electrode, and the second electrode.

[0076] In one embodiment, before step S300, as Figure 9 shown, the method for manufacturing a display panel further includes forming an insulating layer 24 above the substrate 10.

[0077] In one embodiment, in the step of forming the insulating layer 24, a groove can be formed on the surface of the insulating layer 24 away from the substrate 10.

[0078] In one embodiment, in step S300, during the process of forming the second electrode 214, the deposited electrode material is partially located in the second protrusion part that fills the groove to form the second electrode 214, and partially located on the side of the second protrusion part away from the substrate 10 to form the second main body part of the second electrode 214.

[0079] In one embodiment, after step S300, as Figure 10 shown, the method for manufacturing a display panel further includes etching the insulating layer 24 to form a contact hole 241. The contact hole 241 exposes the first trace 22, and a second trace 23 is formed above the insulating layer 24. The second trace 23 is connected to the first trace 22 through the contact hole 241.

[0080] In one embodiment, after step S300, as Figure 11 shown, the method for manufacturing a display panel further includes forming a passivation layer 25 above the insulating layer 24 and forming a light-shielding layer 30 above the passivation layer 25.

[0081] The method for manufacturing a display panel provided by the embodiments of the present application belongs to the same inventive concept as the embodiments of the above display panel, and the descriptions of relevant details and beneficial effects can be referred to each other.

[0082] Another display panel is also provided in an embodiment of the present application. The display panel includes a display area and a non-display area. The display panel includes a substrate, a driving circuit layer, a protective layer, and an electrophoretic layer.

[0083] As Figure 12 shown, the driving circuit layer 20 is located on the substrate 10. The driving circuit layer 20 includes a transistor 21 located in the non-display area. The transistor 21 includes a gate 211, an active layer 212, a first electrode 213, and a second electrode 214. The protective layer 40 is located on the side of the driving circuit layer 20 away from the substrate 10. The orthographic projection of the protective layer 40 on the substrate 10 covers the orthographic projection of the active layer 212 located in the non-display area on the substrate 10. The electrophoretic layer is located on the side of the driving circuit layer 20 away from the substrate 10. The light-shielding layer 30 is located on the side of the protective layer 40 away from the substrate 10. The orthographic projection of the light-shielding layer 30 on the substrate 10 covers the orthographic projection of the active layer 212 located in the non-display area on the substrate 10. In this embodiment, the transistor 21 can be a second type of transistor.

[0084] During the preparation process of the electronic paper display panel, as Figure 1 shown, the uppermost insulating layer of the driving circuit layer 20' cannot effectively protect the driving circuit. Mechanical operations during the preparation process may cause bruising or scratching to the driving circuit layer 20', resulting in damage to the transistor 21' or other traces. Moreover, some chemical substances in the preparation environment may also corrode the transistor 21' and other traces, thereby affecting the signal transmission of the display panel and causing display defects such as horizontal stripes on half of the screen in the display panel. By providing the protective layer 40, the driving circuit layer can be protected from the influence of the external environment, which is beneficial to improving the reliability and stability of the display panel.

[0085] In one embodiment, the protective layer 40 is only located in the non-display area of the display panel. Structures such as an electrophoretic layer are provided in the display area of the display panel, which can provide protection for the driving circuit layer located in the display area to a certain extent. Therefore, the protective layer 40 can be only provided in the non-display area of the display panel. This is beneficial to reducing the process flow and cost. At the same time, since the protective layer is not provided in the display area of the display panel, it is beneficial to reduce the film layer thickness in the display area and realize the thinning of the display panel.

[0086] In one embodiment, as Figure 12As shown, the driving circuit layer 20 includes a first trace 22 and a second trace 23. The first trace 22 is disposed on the same layer as the gate 211, and the second trace 23 is disposed on the same layer as the second electrode 214. The driving circuit layer 20 further includes an insulating layer 24 located between the first trace 22 and the second trace 23. The insulating layer 24 is provided with a contact hole 241 exposing the first trace 22, and the second trace 23 is in contact with the first trace 22 through the contact hole 241. With such a setting, the traces can be prevented from being damaged or interfered by external factors, improving the reliability of signal transmission of the display panel.

[0087] In one embodiment, the material of the light-shielding layer 30 can be a conductive adhesive, and the conductive adhesive contains particles such as carbon powder.

[0088] In one embodiment, the protective layer 40 does not chemically react with materials such as silicon nitride and the electrophoretic layer of the electronic paper, and the thermal expansion coefficient of the protective layer 40 is the same as or approximate to that of silicon nitride. In some embodiments, the material of the protective layer 40 is an insulating material with high compressive strength, high hardness, good toughness, and no corrosion, for example, the material of the protective layer 40 is a ceramic material such as calcium carbonate, zirconia, alumina, or a cement material, or a polymer material such as graphene.

[0089] The embodiment of the present application further provides a display device, and the display device includes the above-mentioned display panel.

[0090] In one embodiment, the display device includes a housing, and the display panel is disposed in the housing.

[0091] In one embodiment, the display device further includes a power supply circuit for supplying power to the display panel.

[0092] The present application does not make specific limitations on the applicability of the display device, and it can be any product or component with a display function such as a television, a notebook computer, a tablet computer, a wearable display device, a mobile phone, an e-book, an electronic price tag, a digital photo frame, an advertising light box, etc.

[0093] It should be noted that the technical solutions or technical features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of the present application is not limited to the precise structures described in the above embodiments and shown in the drawings; any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: substrate; A driving circuit layer is located on one side of the substrate and includes a driving circuit; the driving circuit includes at least one first-type transistor; the first-type transistor includes a gate, an active layer, a first electrode, and a second electrode; the second electrode is located on a side of the first electrode away from the substrate, and in a direction perpendicular to the substrate, the active layer includes a first end face and a second end face opposite to each other, the first end face is in contact with the first electrode, and the second end face is in contact with the second electrode; the active layer also includes a side face between the first end face and the second end face, the gate is located on one side of the side face of the active layer, and the orthographic projection of the gate on the plane where the side face is located overlaps with the side face.

2. The display panel according to claim 1, characterized in that: The first electrode comprises a first main body and a first protrusion extending from the first main body toward the second electrode, and an orthographic projection of the first protrusion on the plane where the side surface is located overlaps with the side surface; and / or, The second electrode includes a second main body portion and a second protruding portion extending from the second main body portion toward the active layer, and an orthographic projection of the second protruding portion on the plane where the side surface is located overlaps with the side surface.

3. The display panel according to claim 2, characterized in that: The first main body portion contacts the first end surface; and / or the second main body portion contacts the second end surface.

4. The display panel according to claim 2, characterized in that: The orthographic projections of the first protrusions on the plane where the side surface is located are all located inside the side surface; and / or the orthographic projections of the second protrusions on the plane where the side surface is located are all located inside the side surface.

5. The display panel according to claim 2, characterized in that: The first protrusion is located on a side of the active layer away from the gate; and / or the second protrusion is located on a side of the active layer away from the gate.

6. The display panel according to claim 1, characterized in that: A side surface of the active layer located between the first end surface and the second end surface is perpendicular to a surface of the substrate facing the first electrode.

7. The display panel according to claim 1, characterized in that: The driving circuit layer further includes a first wiring, wherein the first wiring is located between the first electrode and the substrate, and the first wiring is overlapped with the first electrode.

8. The display panel according to claim 1, characterized in that: The display panel includes a display area and a non-display area; the driving circuit layer includes a transistor located in the non-display area and a transistor located in the display area; The driving circuit layer further includes a first wiring and a second wiring, wherein the first wiring is located between the first electrode and the substrate and is electrically connected to the transistor located in the non-display area; the second wiring is arranged in the same layer as the second electrode and is electrically connected to the transistor located in the display area; The driving circuit layer further includes an insulating layer located between the first wiring and the second wiring, the insulating layer is provided with a contact hole exposing the first wiring, and the second wiring contacts the first wiring through the contact hole.

9. A display panel, characterized in that: The display panel includes a display area and a non-display area: substrate; a driving circuit layer located on the substrate, the driving circuit layer comprising a transistor located in the non-display area, the transistor comprising an active layer; A protective layer, located on a side of the driving circuit layer away from the substrate, wherein the orthographic projection of the protective layer on the substrate covers the orthographic projection of the active layer located in the non-display area on the substrate; an electrophoretic layer, located on a side of the driving circuit layer away from the substrate; The light shielding layer is located on a side of the protective layer away from the substrate, and the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the active layer located in the non-display area on the substrate.

10. The display panel according to claim 9, characterized in that: The protection layer is only located in the non-display area.

11. A display device, characterized in that: The display device comprises a power supply circuit and the display panel according to any one of claims 1 to 10; the power supply circuit is used to supply power to the display panel.

12. A method for preparing a display panel, characterized in that: The preparation method comprises: Providing a substrate, and forming a gate and a first electrode on one side of the substrate; An active layer is formed, wherein in a direction perpendicular to the substrate, the active layer comprises a first end face and a second end face opposite to each other, and a side face located between the first end face and the second end face; the first electrode is in contact with the first end face, and at least a portion of the first electrode is located on a side of the first end face facing the substrate; the gate is located on one side of the side face of the active layer, and an orthographic projection of the gate on a plane where the side face is located overlaps with the side face; A second electrode is formed, wherein the second electrode is in contact with the second end surface, and the second electrode is at least partially located on a side of the second end surface away from the substrate.

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