Solar cell and preparation method thereof

Abstract

The present invention provides a solar cell and a method for preparing the same. The solar cell includes a silicon substrate, the front side of the silicon substrate having a velvet structure, the front side of the silicon substrate being divided into a working area and an edge isolation area, the working area including a p-type emitter, a first passivation layer, and a first electrode arranged on the front side in sequence from the inside out, the edge isolation area including the first passivation layer arranged on the front side, and the back side of the silicon substrate being provided with a tunneling oxide layer, an n-type doped polysilicon layer, a second passivation layer, and a second electrode in sequence from the inside out, wherein the reflectivity of the velvet structure in the working area is R1, the reflectivity of the velvet structure in the edge isolation area is R2, R1 / R2 is in the range of 0.3-3, and the distance between the velvet structure substrate of the working area and the velvet structure substrate of the edge isolation area is in the range of 3μm-10μm.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof. Background Art

[0002] TOPCon (Tunnel Oxide Passivated Contact) solar cells significantly reduce carrier recombination losses, achieving high open-circuit voltage and conversion efficiency, thanks to the synergistic passivation effect of their ultra-thin tunnel oxide layer and doped polysilicon layer on the backside. However, to meet the requirements of half-cut module technology, the cells must be separated by laser cutting. Laser thermal damage to the exposed silicon substrate surface in the cut section creates dangling bonds and defect states, which become strong recombination centers for carriers. This results in a 0.1%-0.2% loss in cell efficiency after slicing, limiting module power output.

[0003] In response to the above problems, the existing technology has attempted to optimize through various paths. The edge passivation technology currently used by the industry mainstream covers the cut surface with an aluminum oxide passivation layer through atomic layer deposition (ALD). Although it can increase the power of the component, it requires the introduction of high-temperature annealing and special equipment. The process cost is high, and the passivation layer plating problem is prominent, affecting the consistency of the battery appearance. The patent application with publication number CN118507594A discloses a solution of "setting polished surface isolation areas on both sides of the cutting area". It reduces recombination by physically blocking the lateral migration path of carriers, but its polished surface reflectivity is as high as 30%-40%, which loses some light and reduces the short-circuit current of the battery. At the same time, since laser damage is difficult to remove, the isolation area passivation is poor and the PL image is black, which affects the open circuit voltage of the battery. Although the patent application with publication number CN119029092A discloses a nanosecond laser etching and step-by-step cleaning process, which improves passivation by forming a planar or velvet structure, and adjusts the surface morphology of the isolation area by adjusting the spot overlap rate, the operation of this technology is complicated, and the inventors of this application found that when using alkaline solution to remove the residual boron emitter in the isolation area, the boron emitter in the working area is also damaged, thereby affecting the light absorption rate and short-circuit current of the solar cell.

[0004] Therefore, the industry urgently needs to develop a new TOPCon solar cell structure and preparation method that can block carrier recombination channels while taking into account high light absorption rate and short-circuit current. Summary of the Invention

[0005] In view of the problems in the prior art of low light utilization and low short-circuit current of sliced cells with isolation regions, the present invention provides a solar cell and a method for preparing the same.

[0006] The first aspect of the present application provides a solar cell, including a silicon substrate, the front side of the silicon substrate having a velvet structure, the front side of the silicon substrate being divided into a working area and an edge isolation area, the working area including a p-type emitter, a first passivation layer and a first electrode arranged on the front side in sequence from the inside to the outside, the edge isolation area including a first passivation layer arranged on the front side, and a tunneling oxide layer, an n-type doped polysilicon layer, a second passivation layer and a second electrode arranged on the back side of the silicon substrate in sequence from the inside to the outside, wherein the reflectivity of the velvet structure in the working area is R1, the reflectivity of the velvet structure in the edge isolation area is R2, R1 / R2 is in the range of 0.3-3, and the distance between the velvet structure substrate of the working area and the velvet structure substrate of the edge isolation area is in the range of 3μm-10μm.

[0007] The solar cell of the above structure achieves multiple reflections and scattering by providing a velvet structure on the front side to reduce light reflection loss and enhance light absorption efficiency, thereby improving the photoelectric conversion performance of the cell; by providing an edge isolation region to separate the p-type emitter space, the recombination loss of the entire p-type emitter surface can be reduced; a passivation layer is provided outside the p-type emitter and the edge isolation region to inhibit surface carrier recombination, optimize light absorption and carrier selective transmission, thereby improving the open circuit voltage, short circuit current and overall conversion efficiency of the cell; at the same time, the reflectivity ratio of the velvet structure of the working area and the edge isolation region is controlled within the range of 0.3-3, which not only achieves the optical property regulation of the specific film layer, but also reduces the local light intensity difference, making the generation and collection of carriers more uniform and maintaining a stable carrier transport path; the distance between the velvet structure base of the working area and the velvet structure base of the edge isolation region is controlled within the range of 3μm-10μm, which achieves the severance of the pn junction for insulation isolation while avoiding excessive etching to damage the silicon substrate.

[0008] In any embodiment of the first aspect, the reflectivity R1 is 7%-15%. The low reflectivity design of the working area can reduce the surface reflection loss of incident light, especially enhance the absorption of long-wavelength light, thereby increasing the short-circuit current.

[0009] In any embodiment of the first aspect, the reflectivity R2 is 7%-30%. Controlling the reflectivity of the edge isolation region within the above range not only achieves passivated contact performance, but also optimizes light utilization, while avoiding process instability caused by extreme reflectivity.

[0010] In any embodiment of the first aspect, a minimum dimension of the edge isolation region in a direction away from the working region is in a range of 10 μm to 1000 μm.

[0011] In any embodiment of the first aspect, the edge isolation area is a rectangular area.

[0012] In any embodiment of the first aspect, the silicon substrate is an N-type silicon substrate. Optionally, the silicon substrate is a phosphorus-doped single crystal silicon wafer. Optionally, the resistivity of the silicon substrate is 0.1 Ω·cm-100 Ω·cm. Optionally, the thickness of the silicon substrate is 100 μm-500 μm.

[0013] In any embodiment of the first aspect, the doping concentration of the p-type emitter is 2×10 18 atoms / cm 3 - 1×10 19 atoms / cm 3 Optionally, the junction depth of the p-type emitter is 0.5 μm-2 μm.

[0014] In any embodiment of the first aspect, the tunnel oxide layer includes one or more of silicon oxide, silicon nitride, and aluminum oxide.

[0015] In any embodiment of the first aspect, the thickness of the tunnel oxide layer is 0.5 nm to 2.5 nm.

[0016] In any embodiment of the first aspect, the thickness of the n-type doped polysilicon layer is 100 nm-300 nm.

[0017] In any embodiment of the first aspect, the doping concentration of the n-type doped polysilicon layer is 3×10 20 atoms / cm 3 - 1×10 21 atoms / cm 3 .

[0018] In any embodiment of the first aspect, the first passivation layer and the second passivation layer each independently include at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride or silicon oxynitride.

[0019] In any embodiment of the first aspect, the first electrode and the second electrode each independently include at least one of silver, silver alloy, copper, copper alloy, and nickel / copper / silver multilayer electrode.

[0020] The second aspect of the present application provides a method for preparing a solar cell, which comprises the following steps: S1, texturing the front surface of a silicon substrate to obtain a first textured surface; S2, preparing a p-type emitter on the front surface of the textured silicon substrate, and sequentially preparing a tunneling oxide layer and an n-type doped polysilicon layer on the back surface of the silicon substrate; S3, using a green picosecond laser to remove the p-type emitter at a preset position to form a pre-isolation region; S4, acid-washing to remove the winding phosphosilicate glass and winding phosphosilicate borosilicate glass on the front surface; S5, using an alkali containing a texturing additive to remove the winding phosphosilicate glass and the winding phosphosilicate borosilicate glass on the front surface; The front side is re-textured with liquid to form a second velvet surface in the pre-isolation area; S6, acid pickling to remove the borosilicate glass on the front side and the phosphosilicate glass on the back side; S7, passivation of the front and back sides; S8, setting electrodes on the front and back sides respectively; S9, performing laser non-destructive cutting, and the cutting position is in the pre-isolation area or on one side of the pre-isolation area, wherein the reflectivity of the first velvet surface is R1, the reflectivity of the second velvet surface is R2, R1 / R2 is in the range of 0.3-3, and the distance between the base of the first velvet surface and the base of the second velvet surface is in the range of 3μm-10μm.

[0021] In the above preparation method, in step S3, the pn junction is cut off by using the pre-isolation area formed by using a green picosecond laser, so that the emitters on both sides of the isolation area are isolated, providing space for subsequent electrode isolation and cutting. Moreover, the green picosecond laser can remove the P-type emitter in the pre-isolation area more thoroughly than the nanosecond laser, and there is no residual P-type emitter, which can increase the processing window of the isolation area. Therefore, during the alkaline solution treatment in step S5, there is no need to remove the remaining P-type emitter in the pre-isolation area. It is only necessary to use the alkaline solution to remove the n-type doped polysilicon plated around the positive surface. At the same time, since there is no P-type emitter blocking the pre-isolation area, the alkaline solution can also remove the borosilicate melt and laser damage generated in the pre-isolation area, and the pre-isolation area is textured to increase the etching depth of the pre-isolation area and obtain a second texture surface, thereby reducing the reflectivity of the isolation area to light, that is, increasing the absorption rate of light in the isolation area, and effectively improving the short-circuit current. The above steps work together to achieve zonal control of the reflectivity of the isolation and working areas, increasing the light absorption rate in the isolation area and avoiding damage to the p-type emitter in the working area, thereby effectively increasing the short-circuit current. The first and second velvet surfaces also effectively increase the open-circuit voltage of the battery. The overall preparation method is efficient and convenient, facilitating mass production. Furthermore, because the isolation area forms a controllable pyramid structure after velvet treatment, the light utilization rate for non-destructive laser scribing is higher. Compared with other structures, the power of non-destructive laser cutting can be further reduced, making cutting damage more controllable.

[0022] In any embodiment of the second aspect, the wavelength of the green picosecond laser is 532 nm or 1064 nm. Optionally, the radiation power of the green picosecond laser is 1 W to 50 W. Optionally, the spot overlap rate of the green picosecond laser is 40% to 80%. Optionally, the energy density of the green picosecond laser is 100 mJ / cm2 -400mJ / cm 2 Picosecond lasers have short pulse duration and high peak power, and can focus and release a large amount of energy in a very short time, resulting in a very efficient etching effect on the p-type emitter in the pre-isolation area with less thermal and mechanical damage.

[0023] In any embodiment of the second aspect, the reflectivity R1 of the first suede surface is 7%-15%.

[0024] In any embodiment of the second aspect, the reflectivity R2 of the second suede surface is 7%-30%.

[0025] In any embodiment of the second aspect, after the pre-isolation region is formed, the distance between two adjacent emitters is in the range of 10 μm to 1000 μm.

[0026] In any embodiment of the second aspect, in step S4, the acid solution used for pickling is an HF solution with a concentration of 5%-30%, and the pickling time is 10s-70s.

[0027] In any embodiment of the second aspect, in step S5, the mass ratio of the alkali in the alkali solution to the texturing additive is 1:2-5:1. Optionally, the texturing temperature is 65° C.-85° C. Optionally, the texturing time is 600s-900s. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0029] Figure 1 This is a schematic diagram of the cross-sectional structure of the solar cell provided in Example 1 of the present invention.

[0030] Figure 2 A flow chart of a method for preparing a solar cell provided by one embodiment of the present invention is shown.

[0031] Figure 3 This is a schematic diagram of the cross-sectional structure of a solar cell provided in Comparative Example 1 of the present invention.

[0032] Figure 4 This is a schematic diagram of the cross-sectional structure of the solar cell provided in Example 8 of the present invention.

[0033] Figure 5 These are the topographic planar SEM images and cross-sectional SEM images of the first velvet surface and the second velvet surface of the solar cell provided in Example 1 of the present invention.

[0034] Figure 6These are the topographic planar SEM images and cross-sectional SEM images of the first and second velvet surfaces of the solar cell provided in Comparative Example 1 of the present invention.

[0035] Figure 7 These are the topographic planar SEM images and cross-sectional SEM images of the first velvet surface and the second velvet surface of the solar cell provided in Example 8 of the present invention.

[0036] Reference numerals:

[0037] 1-silicon substrate, 2-p-type emitter, 3-tunneling oxide layer, 4-n-type doped polysilicon layer, 5-first passivation layer, 6-second passivation layer, 7-first electrode, 8-second electrode. DETAILED DESCRIPTION

[0038] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples. However, it will be understood by those skilled in the art that the following examples are merely illustrative of the present invention and should not be construed as limiting the scope of the invention. Where specific conditions are not specified in the examples, the methods are carried out according to conventional conditions or the conditions recommended by the manufacturer. Where the manufacturer of the reagents or instruments is not specified, they are all conventional products that can be obtained commercially. Unless otherwise specified, the concentrations mentioned in this application are all by mass content. Taking a 20% HF solution as an example, this means that the mass content of HF in the solution is 20%.

[0039] Unless otherwise specified, the technical or scientific terms used in this application should have the ordinary meaning understood by people with ordinary skills in the field to which this disclosure belongs. Unless otherwise specified, the "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are simply used to distinguish different components. All steps of this application can be performed sequentially or randomly, and preferably sequentially. Unless otherwise specified, the "including" and "comprising" mentioned in this application are open-ended. For example, the "including" and "comprising" can mean that other components not listed can also be included or comprised.

[0040] In order to solve the problem of low light absorption rate and short-circuit current of TOPCon solar cells after setting up the isolation area, the present application conducted in-depth research and found that the direct reason is that when the residual boron emitter in the isolation area is removed by alkaline solution, the boron emitter in the working area is also damaged, affecting the light absorption rate and short-circuit current. However, since the boron emitter in the isolation area and the boron emitter in the working area have the same composition, it is difficult to avoid damaging the boron emitter in the working area when removing the boron emitter in the isolation area. In order to avoid this damage, the present application solves the problem from the root, that is, the boron emitter in the pre-formed isolation area is completely removed during laser processing, and the reflectivity of the isolation area is adjusted to match the reflectivity of the working area to improve the light absorption rate. Based on the technical ideas, the present application provides a solar cell and a preparation method thereof.

[0041] The first embodiment of the present application provides a solar cell, such as Figure 1 As shown, the solar cell includes a silicon substrate 1, the front side of the silicon substrate 1 has a velvet structure, the front side of the silicon substrate is divided into a working area and an edge isolation area, the working area includes a p-type emitter 2, a first passivation layer 5 and a first electrode 7 arranged on the front side from the inside to the outside, the edge isolation area includes a first passivation layer arranged on the front side, and the back side of the silicon substrate is provided with a tunneling oxide layer 3, an n-type doped polysilicon layer 4, a second passivation layer 6 and a second electrode 8 from the inside to the outside, wherein the reflectivity of the velvet structure in the working area is R1, the reflectivity of the velvet structure in the edge isolation area is R2, R1 / R2 is in the range of 0.3-3, and the distance h between the velvet structure substrate of the working area and the velvet structure substrate of the edge isolation area is in the range of 3μm-10μm.

[0042] The applicant has discovered that, in the above-mentioned solar cell structure, providing a velvet structure on the front surface can reduce light reflection loss through multiple reflections and scattering, enhance light absorption efficiency, and thus improve the photoelectric conversion performance of the cell; by providing an edge isolation region to separate the p-type emitter, the recombination loss of the entire p-type emitter surface can be reduced; providing a passivation layer outside the p-type emitter and the edge isolation region can inhibit surface carrier recombination, optimize light absorption and selective carrier transmission, thereby improving the open circuit voltage, short-circuit current, and overall conversion efficiency of the cell; at the same time, controlling the reflectivity ratio of the velvet structure in the working area and the edge isolation region within the range of 0.3-3 not only achieves the regulation of the optical properties of a specific film layer, but also reduces local light intensity differences, making the generation and collection of carriers more uniform and maintaining a stable carrier transport path; controlling the distance h between the velvet structure base in the working area and the velvet structure base in the edge isolation region within the range of 3μm-10μm, achieves the severance of the pn junction for insulation isolation while avoiding excessive etching to damage the silicon substrate.

[0043] In some embodiments, the R1 / R2 is 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3 or within the range of any two of the above values. In a preferred embodiment, R1 / R2 is 0.3-1.9, for example, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.875, 1.9 or within the range of any two of the above values.

[0044] In some embodiments, the reflectivity R1 is 7%-15%, for example, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, or any two of the above values. The low reflectivity design of the passivated p-type emitter can reduce surface reflection losses of incident light, particularly enhancing absorption of long-wavelength light, thereby increasing short-circuit current.

[0045] In some embodiments, the reflectivity R2 is 7%-30%, for example, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, or any range between any two of the above values. By controlling the reflectivity of the passivated isolation region within the above range, both passivated contact performance and optimized light utilization are achieved, while avoiding process instability caused by extreme reflectivity.

[0046] In some embodiments, as Figure 1 As shown, the minimum dimension b of the edge isolation region in the direction away from the working area is in the range of 10μm-1000μm, such as 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 200μm, 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, 1000μm, or in the range of any two of the above values. This width range design balances the isolation effect, passivation effect, and light utilization of the edge isolation region, while reserving a larger working window for laser slicing, which is beneficial for improving the alignment problem of subsequent slicing and achieving higher component efficiency. At the same time, it meets the requirements of different application scenarios for voltage resistance, appearance, and quality reliability.

[0047] In some embodiments, the edge isolation region is a rectangular region, and the regular rectangular boundary can be precisely controlled by a laser direct writing process, which can not only ensure the isolation of the pn junction, but also facilitate matching with the vertical arrangement of the gate line electrode.

[0048] In some embodiments, the silicon substrate is an N-type silicon substrate. In some implementations, the N-type silicon substrate includes a phosphorus-doped single crystal silicon wafer, a phosphorus-doped polycrystalline silicon wafer, an arsenic-doped single crystal silicon wafer, or an antimony-doped single crystal silicon wafer.

[0049] In some embodiments, the resistivity of the silicon substrate is 0.1 Ω·cm-100 Ω·cm, for example, 0.1 Ω·cm, 0.2 Ω·cm, 0.3 Ω·cm, 0.4 Ω·cm, 0.5 Ω·cm, 0.6 Ω·cm, 0.7 Ω·cm, 0.8 Ω·cm, 0.9 Ω·cm, 1 Ω·cm, 5 Ω·cm, 10 Ω·cm, 20 Ω·cm, 30 Ω·cm, 40 Ω·cm, 50 Ω·cm, 60 Ω·cm, 70 Ω·cm, 80 Ω·cm, 90 Ω·cm, 100 Ω·cm, or within a range of any two of the foregoing values. A silicon substrate within the foregoing resistivity range helps increase carrier migration speed, thereby improving battery performance.

[0050] In some embodiments, the thickness of the silicon substrate is 100 μm to 500 μm, for example, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, or a range between any two of the foregoing values. A silicon substrate that is too thin may result in insufficient light absorption, while a silicon substrate that is too thick may increase resistive losses. By selecting the appropriate silicon substrate thickness, a balance is achieved between light absorption and current collection efficiency.

[0051] In some embodiments, the doping concentration of the p-type emitter is 2×10 18 atoms / cm 3 - 1×10 19 atoms / cm 3 , for example 2×10 18 atoms / cm 3 , 3×10 18 atoms / cm 3 , 4×10 18 atoms / cm 3 , 5×10 18 atoms / cm 3 , 6×10 18 atoms / cm 3 , 7×10 18 atoms / cm 3 , 8×10 18atoms / cm 3 , 9×10 18 atoms / cm 3 , 1×10 19 atoms / cm 3 Or within the range of any two of the above values. A moderate doping concentration of the p-type emitter can improve the electrical properties of the p-type emitter, forming a good junction structure while avoiding carrier recombination caused by excessive doping.

[0052] In some embodiments, the junction depth of the p-type emitter is 0.5 μm to 2 μm, such as 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 0.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, 2 μm, or a range between any two of the foregoing values. Such a junction depth can optimize carrier collection efficiency and reduce junction recombination losses, thereby improving the open circuit voltage and overall performance of the battery.

[0053] In some embodiments, the tunnel oxide layer comprises one or more of silicon oxide, silicon nitride, and aluminum oxide, and / or has a thickness of 0.5 nm to 2.5 nm. Selecting tunnel oxide layers of varying materials or thicknesses can adjust their conductivity and dielectric properties, adaptively improving the photovoltaic conversion efficiency and stability of the battery.

[0054] In some embodiments, the thickness of the n-type doped polysilicon layer is 100 nm to 300 nm, for example, 100 nm, 1100 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm, or a range between any two of the foregoing values. The n-type doped polysilicon layer having this thickness range helps improve passivation and dielectric effects and minimizes contact resistance of the metal electrode, thereby improving battery efficiency and reliability.

[0055] In some embodiments, the doping concentration of the n-type doped polysilicon layer is 3×10 20 atoms / cm 3 - 1×10 21 atoms / cm 3 , for example 3×10 20 atoms / cm 3 , 4×10 20 atoms / cm 3 , 5×10 20atoms / cm 3 , 6×10 20 atoms / cm 3 , 7×10 20 atoms / cm 3 , 8×10 20 atoms / cm 3 , 9×10 20 atoms / cm 3 , 1×10 21 atoms / cm 3 Or within the range of any two of the above values.

[0056] In some embodiments, the first passivation layer and the second passivation layer each independently include at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, or silicon oxynitride. The use of these materials helps reduce surface defects and recombination, improves battery stability and efficiency, and particularly enhances surface passivation and prevents recombination losses of current.

[0057] In some embodiments, the first electrode and the second electrode each independently comprise at least one of silver, a silver alloy, copper, a copper alloy, or a nickel / copper / silver multilayer electrode. These metal materials can ensure good electrical conductivity, stability, and corrosion resistance of the electrodes during long-term use, thereby optimizing the current conduction performance and efficiency of the battery.

[0058] The second embodiment of the present application provides a method for preparing a solar cell, such as Figure 2 As shown, the preparation method includes the following steps: S1, texturing the front surface of the silicon substrate to obtain a first texturing surface; S2, preparing a p-type emitter on the front surface of the silicon substrate after texturing, and sequentially preparing a tunneling oxide layer and an n-type doped polysilicon layer on the back surface of the silicon substrate; S3, using a green picosecond laser to remove the p-type emitter at a preset position to form a pre-isolation area; S4, acid washing to remove the winding phosphosilicate glass and winding phosphosilicate borosilicate glass on the front surface; S5, using an alkaline solution including a texturing additive to re-texture the front surface, Form a second velvet surface in the pre-isolation area; S6, remove the borosilicate glass on the front and the phosphosilicate glass on the back by pickling; S7, passivate the front and back; S8, set electrodes on the front and back respectively; S9, perform laser non-destructive cutting, and the cutting position is in the pre-isolation area or on one side of the pre-isolation area, wherein the reflectivity of the first velvet surface is R1, the reflectivity of the second velvet surface is R2, R1 / R2 is in the range of 0.3-3, and the distance h between the first velvet surface base and the second velvet surface base is in the range of 3μm-10μm.

[0059] In the above preparation method, in step S3, the pn junction is cut off by using the pre-isolation area formed by using a green picosecond laser, so that the emitters on both sides of the isolation area are isolated, providing space for subsequent electrode isolation and cutting. Moreover, the green picosecond laser can remove the P-type emitter in the pre-isolation area more thoroughly than the nanosecond laser, and there is no residual P-type emitter, which can increase the processing window of the isolation area. Therefore, during the alkaline solution treatment in step S5, there is no need to remove the remaining P-type emitter in the pre-isolation area. It is only necessary to use the alkaline solution to remove the n-type doped polysilicon plated around the positive surface. At the same time, since there is no P-type emitter blocking the pre-isolation area, the alkaline solution can also remove the borosilicate melt and laser damage generated in the pre-isolation area, and the pre-isolation area is textured to increase the etching depth of the pre-isolation area and obtain a second texture surface, thereby reducing the reflectivity of the isolation area to light, that is, increasing the absorption rate of light in the isolation area, and effectively improving the short-circuit current. The above steps work together to achieve zonal control of the reflectivity of the isolation and working areas, increasing the light absorption rate in the isolation area and avoiding damage to the p-type emitter in the working area, thereby effectively increasing the short-circuit current. The first and second velvet surfaces also effectively increase the open-circuit voltage of the battery. The overall preparation method is efficient and convenient, facilitating mass production. Furthermore, because the isolation area forms a controllable pyramid structure after velvet treatment, the light utilization rate for non-destructive laser scribing is higher. Compared with other structures, the power of non-destructive laser cutting can be further reduced, making cutting damage more controllable.

[0060] The above preparation method is described below in the order of step execution.

[0061] First, step S1 is performed to texture the front surface of the silicon substrate to obtain a first textured surface. The first textured surface formed in step S1 can enhance light capture capability and reduce reflection loss.

[0062] Step S2 is performed to form a p-type emitter on the front surface of the textured silicon substrate, and a tunneling oxide layer and an n-type doped polysilicon layer are sequentially formed on the back surface of the silicon substrate. The above methods for forming the p-type emitter, tunneling oxide layer, and n-type doped polysilicon layer can be used as a reference for conventional techniques and will not be repeated here.

[0063] In step S2, the p-type emitter prepared on the front side realizes a pn junction, and the tunneling oxide layer and the n-type doped polysilicon layer prepared on the back side form a passivation contact structure to improve carrier selectivity.

[0064] Step S3 is performed to remove the p-type emitter at a preset position using a green picosecond laser to form a pre-isolation region.

[0065] In some embodiments, the wavelength of the green picosecond laser is 532 nm or 1064 nm. Picosecond laser refers to a laser with a pulse duration of picoseconds (10 -12Picosecond lasers have very short pulse durations, resulting in higher peak power. Picosecond lasers can focus and release a large amount of energy in a very short time, resulting in highly efficient etching of the p-type emitter in the pre-isolation region with minimal thermal and mechanical damage.

[0066] In some embodiments, the radiation power of the green picosecond laser is 1 W-50 W, for example, 1 W, 2 W, 3 W, 4 W, 5 W, 6 W, 7 W, 8 W, 9 W, 10 W, 15 W, 20 W, 25 W, 30 W, 35 W, 40 W, 45 W, 50 W, or within the range of any two of the above values.

[0067] In some embodiments, the spot overlap rate of the green picosecond laser is 40%-80%, for example, 40%, 50%, 60%, 70%, 80%, or within the range of any two of the above values. It should be noted that the above embodiment controls the spot overlap rate of the green picosecond laser primarily to improve the efficiency of laser processing, and does not intend to use it to form a textured surface in isolated areas.

[0068] In some embodiments, the energy density of the green picosecond laser is 100 mJ / cm 2 -400mj / cm 2 , for example 100mj / cm 2 、150mj / cm 2 , 200mj / cm 2 , 250mj / cm 2 、300mj / cm 2 、350mj / cm 2 , 400mj / cm 2 Or within the range of any two of the above values. The radiation power, spot overlap rate and energy density within the above range can achieve higher precision and low thermal damage processing effects while taking into account both efficiency and quality.

[0069] Execute step S4 to remove the curved phosphosilicate glass and curved phosphosilicate glass on the front side by pickling.

[0070] In some embodiments, the acid solution used for pickling in step S4 is an HF solution having a concentration of 5%-30%, for example, 5%, 7%, 8%, 9%, 10%, 15%, 20%, 25%, 30%, or any range between two of the foregoing values. This concentration range can effectively dissolve the phosphosilicate glass and phosphosilicate glass on the surface of the silicon wafer while avoiding excessive corrosion of the silicon substrate, thereby maintaining the flatness and electrical properties of the silicon wafer surface.

[0071] In some embodiments, the pickling time in step S4 is 10 seconds to 70 seconds, for example, 10 seconds, 20 seconds, 30 seconds, 40 seconds, 50 seconds, 60 seconds, or 70 seconds, or within a range of any two of the foregoing values. Proper pickling time control ensures that the phosphosilicate glass or phosphosilicate glass is sufficiently removed while avoiding excessive corrosion of the silicon wafer surface, thereby maintaining good surface morphology and electrical properties.

[0072] Step S5 is executed to re-texture the front surface using an alkaline solution containing a texturing additive, so that the pre-isolation area forms a second texturing surface.

[0073] In some embodiments, the alkali solution used for texturing in step S5 is not particularly limited, as long as its alkaline corrosion properties are sufficient to form a textured structure on the silicon wafer surface. In a preferred embodiment, the alkali solution used for texturing in step S5 is a NaOH or KOH solution. Compared to other alkali solutions, NaOH or KOH has a stable reaction rate and strong crystal orientation selective corrosion, which can effectively avoid texture collapse or metal contamination caused by excessive corrosion.

[0074] In some embodiments, the texturing additive used in step S5 is not particularly limited, as long as it can form a textured surface structure on the silicon wafer surface with the alkaline solution. Commonly used texturing additives include surfactants (such as isopropyl alcohol and ethanol), corrosion inhibitors (such as sodium silicate and sodium gluconate), complexing agents (such as EDTA), and pH adjusters (such as acetic acid).

[0075] In some embodiments, the mass ratio of alkali to texturing additive in the alkali solution is 1:2-5:1, for example, 1:2, 1:1, 2:1, 3:1, 4:1, 5:1, or within a range of any two of the above ratios. The mass ratio of alkali to texturing additive affects the chemical activity and reaction selectivity of the texturing solution. The above appropriate ratio can balance the corrosion rate and the uniformity of the texturing surface, resulting in a more uniform texturing surface.

[0076] In some embodiments, the temperature of the texturing is 65°C-85°C, for example, 65°C, 66°C, 67°C, 68°C, 69°C, 70°C, 71°C, 72°C, 73°C, 74°C, 75°C, 76°C, 77°C, 78°C, 79°C, 80°C, 81°C, 82°C, 83°C, 84°C, 85°C, or within the range of any two of the above values. Temperature is a key parameter for controlling reaction kinetics and texture morphology. Within the above temperature range, the corrosion rate of the alkali on silicon and the directional control effect of the additive are balanced, which is conducive to achieving uniform formation of the texture.

[0077] In some embodiments, the velvet preparation time is 600s-900s, for example, 600s, 700s, 800s, 900s, or within the range of any two of the above values. The time parameter determines the integrity and size distribution of the velvet structure. The above time range can ensure a relatively complete reaction and the resulting velvet size is within an appropriate range.

[0078] Step S6 is executed to remove the borosilicate glass on the front side and the phosphosilicate glass on the back side by pickling.

[0079] Execute step S7 to passivate the front and back surfaces. The passivation treatment in step S7 can reduce the surface recombination rate and increase the open circuit voltage.

[0080] In some embodiments, the reflectivity of the first suede surface after passivation is 7%-15%, for example, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, or any two of the above values. The low reflectivity design of the first suede surface after passivation can reduce surface reflection loss of incident light, especially enhance absorption of long-wavelength light, thereby increasing short-circuit current.

[0081] In some embodiments, the reflectivity of the second suede surface after passivation is 7%-30%, for example, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, or within the range of any two of the above values. By controlling the reflectivity of the first suede surface after passivation to the above range, both passivation contact performance and light utilization efficiency are achieved, while avoiding process instability problems caused by extreme reflectivity.

[0082] In some embodiments, after the pre-isolation region is formed, the distance between two adjacent emitters is in the range of 10μm-1000μm, for example, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 200μm, 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, 1000μm, or within the range of any two of the foregoing values. This width range design balances the isolation effect of the pre-isolation region, the passivation effect, the light utilization rate, and the subsequent slicing alignment issues, thereby improving the efficiency of the component while meeting the requirements of different application scenarios for voltage resistance, appearance, and quality reliability.

[0083] Step S8 is executed to respectively provide electrodes on the front and back surfaces. The electrodes can be provided by screen printing or other methods to provide silver paste, which is then cured and sintered to form the electrodes.

[0084] Execute step S9 to perform laser non-destructive cutting, with the cutting area within or to one side of the pre-isolation area. This laser non-destructive cutting can be based on conventional laser non-destructive cutting. Because the isolation area of this application has a better isolation effect, and because the isolation area can form a controllable pyramid structure after texturing, the light utilization rate for non-destructive laser scribing is higher. Compared with other structures, the power of laser non-destructive cutting can be further reduced, making the cutting damage more controllable.

[0085] [Example]

[0086] Below, the embodiment of the present application is described. The embodiment described below is exemplary and is only used to explain the present application, and is not to be construed as limiting the present application. Where specific techniques or conditions are not specified in the embodiments, the techniques or conditions described in the literature in this area or the product specifications are used. Reagents or instruments used that do not specify the manufacturer are conventional products that can be obtained commercially.

[0087] Test Method: Under standard test conditions (STC: AM1.5G spectrum, 1000W / m² light intensity, 25°C), the measurement methods and corresponding standards for each parameter are as follows: A steady-state IV tester is used to directly measure the open-circuit voltage (Voc) and short-circuit current (Isc). The IV curve is scanned and the maximum power point is calculated. The photoelectric conversion efficiency (pEFF) is calculated according to ASTM E948. A WCT120-SunsVoc tester is used to generate and fit the Suns-Voc curve. The pseudo fill factor (pFF) is calculated according to ASTM E1036. The base diffusion current (J01) and junction recombination current (J02) are analyzed using the Suns-Voc technique.

[0088] Example 1

[0089] Prepare the solar cell by following these steps:

[0090] Step S1, the resistivity of 1Ω · cm, a thickness of 130μm N-type silicon wafer is subjected to a texturing process to obtain a first velvet surface a, the reflectivity of the first velvet surface a is 9%;

[0091] In step S2, the silicon wafer is then loaded into a high-temperature tubular diffusion furnace and introduced with boron trichloride (BCl3) to complete the boron diffusion process. At this time, a P+ emitter and borosilicate glass (BSG) are formed on the surface of the silicon wafer. Subsequently, single-sided etching is performed with 40% HF acid to remove the BSG on the back of the cell. Subsequently, the back of the cell is polished with a 10% KOH solution and a polishing additive (Shichuang NI10V01). Because the front of the cell is protected by BSG, its morphology and structure do not change. Next, 20,000 sccm of oxygen is introduced at 600°C to thermally grow a 1nm tunneling oxide layer, and low-pressure chemical vapor deposition (LPCVD) is used at 620°C to introduce silane to grow a 200nm layer of intrinsic polysilicon (i-Poly Si). Subsequently, phosphorus trichloride is used as a phosphorus source for phosphorus diffusion at 900°C. After phosphorus diffusion, an n-type doped polysilicon layer and phosphosilicate glass (PSG) are formed on the surface, and winding PSG and PBSG (phosphorus borosilicate glass) are formed on the front.

[0092] In step S3, a green picosecond laser is then used to perform laser etching at the preset laser slicing area on the front surface to remove the P emitter. The laser wavelength is 532 nm, and the power, frequency, and energy density are set to 20 W, 1000 kHz, 60% spot overlap, and 200 mJ / cm 2 , set the isolation region width to 400μm;

[0093] Step S4, followed by pickling with 20% HF acid for 40 seconds to remove the PSG / PBSG plated on the front side;

[0094] Step S5, then use a 10% NaOH solution (the concentration of the texturing additive (Shichuang ST10V18) in the NaOH solution is 2%) to texturize the front of the battery again, at a temperature of 68°C and a reaction time of 900s to obtain a second texturing surface b, as shown in FIG. Figure 1 As shown, the reflectivity of the second velvet surface b is 15%, the reflectivity ratio of the first velvet surface a to the second velvet surface b is 3:5, and the substrate distance between the first velvet surface and the second velvet surface is 7μm. At this time, the back of the silicon wafer is protected by PSG and the P+ area on the front is protected by BSG and is not damaged.

[0095] Step S6, finally using 10% HF solution to remove the front BSG and back PSG;

[0096] Step S7: Al2O3 coating is then performed on the front side of the silicon wafer. Trimethylaluminum and water are introduced at 250°C to grow a 6 nm thick Al2O3 layer on both sides. Next, silane and ammonia are introduced at 540°C in a plasma enhanced chemical vapor deposition device to complete the SiN coating on both sides. x The thickness of the deposited thin films was 75 nm.

[0097] Step S8, then, silver paste is printed on the P emitter and n-type doped polysilicon layer of the battery by screen printing, and then sintered at high temperature to complete the metallization. Finally, after light injection treatment, the TOPCon battery is obtained. The cross-sectional structure diagram of the TOPCon battery is shown in FIG. Figure 1 As shown, the morphology plan view and cross-sectional view of the first velvet surface a and the second velvet surface b of the TOPCon battery were taken using a scanning electron microscope, as shown in FIG. Figure 5 As shown in .

[0098] Example 2

[0099] The difference from Example 1 is that in step S5, the reaction time for re-texturing the front side of the battery is 550s to obtain a second velvet surface. The reflectivity of the first velvet surface is measured to be 9%, the reflectivity of the second velvet surface is 30%, the reflectivity ratio of the first velvet surface to the second velvet surface is 0.3, the base distance between the first velvet surface and the second velvet surface is 7.5μm, and the width of the isolation area is 400μm.

[0100] Example 3

[0101] The difference from Example 1 is that in step S1, the N-type silicon wafer is textured to obtain a first texture surface with a reflectivity of 15%. In step S5, the concentration of the texture additive in the 10% NaOH solution is 3.33%. The reaction time for re-texturing the front of the battery is 900s to obtain a second texture surface. The reflectivity of the second texture surface is measured to be 8%. The reflectivity ratio of the first texture surface to the second texture surface is 1.875. The substrate distance between the first texture surface and the second texture surface is 7.4μm, and the width of the isolation area is 400μm.

[0102] Comparative Example 1

[0103] The difference from Example 1 is that in step S5, the reaction time for re-texturing the front surface of the battery is 400s, and the second velvet surface b is obtained. The reflectivity of the first velvet surface a is measured to be 8.8%, the reflectivity of the second velvet surface b is 50%, the reflectivity ratio of the first velvet surface a to the second velvet surface b is 0.176, the base distance between the first velvet surface and the second velvet surface is 4.3μm, and the width of the isolation region is 400μm. The cross-sectional structure diagram of the obtained TOPCon battery is shown as follows: Figure 3 As shown, the morphology plan view and cross-sectional view of the first velvet surface a and the second velvet surface b of the TOPCon battery were taken using a scanning electron microscope, as shown in FIG. Figure 6 As shown in .

[0104] Comparative Example 2

[0105] The difference from Example 1 is that there is no re-texturing step S5. The reflectivity of the first velvet surface a is measured to be 9%, the reflectivity of the isolation area surface is 60%, the reflectivity ratio of the first velvet surface a to the isolation area surface is 0.15, the substrate distance between the first velvet surface and the isolation area surface is 3μm, and the isolation area width is 380μm.

[0106] Comparative Example 3

[0107] The difference from Example 1 is that in step S3, nanosecond laser etching with a wavelength of 520 nm is used to remove the P emitter, and the spot overlap rate is set to 50% and the energy density is set to 10 J / cm 2 , the pulse width is 10ns, the reflectivity of the first velvet surface is measured to be 10%, the reflectivity of the second velvet surface is 20%, the reflectivity ratio of the first velvet surface to the second velvet surface is 0.5, the substrate distance between the first velvet surface and the second velvet surface is 11.5μm, and the isolation area width is 600μm.

[0108] Comparative Example 4

[0109] The difference from Example 1 is that in step S5, the reaction time for re-texturing the front side of the battery is 1200s to obtain a second velvet surface. The reflectivity of the first velvet surface is measured to be 9%, the reflectivity of the second velvet surface is 2.8%, the reflectivity ratio of the first velvet surface to the second velvet surface b is 3.21, the base distance between the first velvet surface and the second velvet surface is 11μm, and the width of the isolation area is 700μm.

[0110] The pEFF, Voc, Isc, pFF, J01 and J02 parameters of the TOPCon batteries obtained in Example 1 and Comparative Examples 1-4 were measured and recorded in Table 1 below.

[0111] Table 1

[0112]

[0113] The data in Table 1 show that Examples 1-3 all achieved higher pEFF, Voc, Isc and pFF and lower J01 and J02, achieving a photoelectric conversion efficiency greater than 26.2%, with excellent performance. Figure 6It can also be seen from the photos that almost no texturing was done, resulting in a high reflectivity, which in turn caused the defect recombination of J02 to increase, resulting in a decrease in the overall photoelectric conversion efficiency; when comparative example 2 was not texturized, Isc was significantly low, indicating that the carrier collection efficiency decreased, resulting in limited current output, which reduced the photoelectric conversion efficiency; in comparative example 3, a nanosecond laser with lower peak power was used. Under this condition, J02 surged and J01 also increased significantly, indicating that the possible residual P-type emitter simultaneously worsened the recombination mechanism of the diffusion layer and the space charge region, thereby significantly reducing the photoelectric conversion efficiency; when the texturing time was too long in comparative example 4, both J01 and J02 increased, indicating that it may have caused excessive corrosion on the surface of the isolation area, thereby aggravating carrier recombination, while weakening light absorption and carrier separation efficiency, resulting in a decrease in photoelectric conversion efficiency.

[0114] The following examines the effects of laser power and energy density on the performance of solar cells.

[0115] Example 4

[0116] The difference from Example 1 is that in step S3, the laser power is set to 30 W. The reflectivity of the first suede surface is measured to be 8.9%, the reflectivity of the second suede surface is 16%, the reflectivity ratio of the first suede surface to the second suede surface is 0.5563, the substrate distance between the first suede surface and the second suede surface is 6.8 μm, and the isolation region width is 395 μm.

[0117] Example 5

[0118] The difference from Example 1 is that in step S3, the laser energy density is set to 280 mJ / cm 2 The reflectivity of the first velvet surface was measured to be 9.1%, the reflectivity of the second velvet surface was 15.3%, the reflectivity ratio of the first velvet surface to the second velvet surface was 0.5948, the substrate distance between the first velvet surface and the second velvet surface was 7.5 μm, and the width of the isolation area was 420 μm.

[0119] The pEFF, Voc, Isc, pFF, J01 and J02 parameters of the TOPCon cells obtained in Examples 4 and 5 above were measured and recorded in Table 2 below.

[0120] Table 2

[0121]

[0122] The data in Table 2 show that the TOPCon cells produced under the above conditions all have a high level of photoelectric conversion efficiency (pEFF>26%), and the performance results of each group are close, indicating that its process stability is good.

[0123] The influence of the pickling conditions in step S4 on the performance of the solar cell is examined below.

[0124] Example 6

[0125] The difference from Example 1 is that in step S4, pickling is performed with 5% HF acid for 70 seconds, and the reflectivity of the first velvet surface is measured to be 8.7%, the reflectivity of the second velvet surface is 14.9%, the reflectivity ratio of the first velvet surface to the second velvet surface is 0.5839, the substrate distance between the first velvet surface and the second velvet surface is 6.8μm, and the isolation area width is 405μm.

[0126] Example 7

[0127] The difference from Example 1 is that in step S4, pickling is performed with 30% HF acid for 10 seconds, and the reflectivity of the first velvet surface is measured to be 9.4%, the reflectivity of the second velvet surface is 15.1%, the reflectivity ratio of the first velvet surface to the second velvet surface is 0.6225, the substrate distance between the first velvet surface and the second velvet surface is 6.9μm, and the isolation area width is 408μm.

[0128] The pEFF, Voc, Isc, pFF, J01 and J02 parameters of the TOPCon cells obtained in Examples 6 and 7 above were measured and recorded in Table 3 below.

[0129] The data in Table 3 show that the performance data of each group of TOPCon cells prepared under the above HF acid conditions are similar, and all can achieve high photoelectric conversion efficiency.

[0130] Table 3

[0131]

[0132] The following examines the influence of the re-texturing conditions in step S5 on the performance of the solar cell.

[0133] Example 8

[0134] The difference from Example 1 is that in step S5, the reaction time for re-texturing the front surface of the battery is 600s to obtain a second velvet surface. The reflectivity of the first velvet surface is 9%, the reflectivity of the second velvet surface is 21%, the reflectivity ratio of the first velvet surface to the second velvet surface is 3:7, and the base distance between the first velvet surface and the second velvet surface is 5.8μm. The cross-sectional structure diagram of the obtained TOPCon battery is shown in the figure below. Figure 4 As shown, the morphology plan view and cross-sectional view of the first velvet surface a and the second velvet surface b of the TOPCon battery were taken using a scanning electron microscope, as shown in FIG. Figure 7 As shown in .

[0135] Example 9

[0136] The difference from Example 1 is that in step S5, the concentration of the texturing additive in the 10% NaOH solution is 20%. The measured reflectivity of the first velvet surface is 9.2%, the reflectivity of the second velvet surface is 17%, the reflectivity ratio of the first velvet surface to the second velvet surface is 0.5412, the base distance between the first velvet surface and the second velvet surface is 7.6 μm, and the width of the isolation region is 410 μm.

[0137] Example 10

[0138] The difference from Example 1 is that in step S5, the re-texturing temperature is 65°C. The reflectivity of the first velvet surface is measured to be 9.5%, the reflectivity of the second velvet surface is 16.5%, the reflectivity ratio of the first velvet surface to the second velvet surface is 0.5758, the base distance between the first velvet surface and the second velvet surface is 6.3 μm, and the width of the isolation region is 395 μm.

[0139] Example 11

[0140] The difference from Example 1 is that in step S5, the re-texturing temperature is 85°C. The reflectivity of the first velvet surface is measured to be 8.7%, the reflectivity of the second velvet surface is 14.8%, the reflectivity ratio of the first velvet surface to the second velvet surface is 0.5878, the base distance between the first velvet surface and the second velvet surface is 7.1 μm, and the width of the isolation region is 410 μm.

[0141] The pEFF, Voc, Isc, pFF, J01 and J02 parameters of the TOPCon cells obtained in Examples 8-11 above were measured and recorded in Table 4 below.

[0142] Table 4

[0143]

[0144] The data in Table 4 show that the TOPCon cells produced under the above conditions all have high levels of photoelectric conversion efficiency. In Example 8, when the texturing time is shorter than in Example 1, the second surface texture is reduced, resulting in an increase in the second surface reflectivity and a decrease in the number of effective photogenerated carriers, which in turn slightly decreases the photoelectric conversion efficiency. The performance data of Examples 9-11 are similar to that of Example 1, and all achieve high photoelectric conversion efficiency.

[0145] Although the specific embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that various modifications and substitutions may be made to those details based on all the teachings disclosed, and these changes are all within the scope of protection of the present invention. The full scope of the present invention is given by the appended claims and any equivalents thereof.

Claims

1. A solar cell, comprising a silicon substrate, wherein the front surface of the silicon substrate has a velvet structure, the front surface of the silicon substrate being divided into an operating area and an edge isolation area, the operating area comprising, from the inside out, a p-type emitter, a first passivation layer, and a first electrode disposed on the front surface in sequence, the edge isolation area comprising the first passivation layer disposed on the front surface, and the back surface of the silicon substrate comprising, from the inside out, a tunneling oxide layer, an n-type doped polysilicon layer, a second passivation layer, and a second electrode disposed in sequence, wherein: The reflectivity of the suede structure in the working area is R1, the reflectivity of the suede structure in the edge isolation area is R2, R1 / R2 is in the range of 0.3-3, and The distance between the velvet structure base in the working area and the velvet structure base in the edge isolation area is in the range of 3 μm-10 μm, and the edge of the edge isolation area is formed by laser cutting.

2. The solar cell according to claim 1, wherein The reflectivity R1 is 7%-15%; and / or the reflectivity R2 is 7%-30%.

3. The solar cell according to claim 1 or 2, wherein A minimum dimension of the edge isolation region in a direction away from the working region is in a range of 10 μm to 1000 μm.

4. The solar cell according to claim 1 or 2, wherein The edge isolation area is a rectangular area.

5. The solar cell according to claim 1 or 2, wherein The silicon substrate is an N-type silicon substrate.

6. The solar cell according to claim 1 or 2, wherein: The silicon substrate is a single crystal silicon wafer doped with phosphorus atoms.

7. The solar cell according to claim 1 or 2, wherein: The resistivity of the silicon substrate is 0.1 Ω·cm-100 Ω·cm; and / or the thickness of the silicon substrate is 100 μm-500 μm.

8. The solar cell according to claim 1 or 2, wherein: The doping concentration of the p-type emitter is 2×10 18 atoms / cm 3 - 1×10 19 atoms / cm 3 ; and / or the junction depth of the p-type emitter is 0.5μm-2μm.

9. The solar cell according to claim 1 or 2, wherein: The tunnel oxide layer includes one or more of silicon oxide, silicon nitride, and aluminum oxide, and / or the thickness of the tunnel oxide layer is 0.5 nm-2.5 nm.

10. The solar cell according to claim 1 or 2, wherein The thickness of the n-type doped polysilicon layer is 100 nm to 300 nm; and / or The doping concentration of the n-type doped polysilicon layer is 3×10 20 atoms / cm 3 - 1×10 21 atoms / cm 3 .

11. The solar cell according to claim 1 or 2, wherein: The first passivation layer and the second passivation layer each independently include at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride or silicon oxynitride.

12. The solar cell according to claim 1 or 2, wherein: The first electrode and the second electrode each independently include at least one of silver, silver alloy, copper, copper alloy, and nickel / copper / silver multilayer electrodes.

13. A method for preparing a solar cell, comprising the following steps: S1, texturing the front surface of the silicon substrate to obtain a first textured surface; S2, preparing a p-type emitter on the front surface of the textured silicon substrate, and sequentially preparing a tunneling oxide layer and an n-type doped polysilicon layer on the back surface of the silicon substrate; S3, using a green picosecond laser to remove the p-type emitter at a preset position to form a pre-isolation region; S4, pickling to remove the winding phosphosilicate glass and winding phosphosilicate borosilicate glass on the front surface; S5, re-texturing the front surface using an alkaline solution containing a texturing additive, so that the pre-isolated area forms a second texturing surface; S6, removing the borosilicate glass on the front surface and the phosphosilicate glass on the back surface by pickling; S7, passivating the front surface and the back surface; S8. Electrodes are provided on the front and back sides respectively; S9, performing laser non-destructive cutting, wherein the cutting portion is within the pre-isolation area or on one side of the pre-isolation area, The reflectivity of the first velvet surface is R1, the reflectivity of the second velvet surface is R2, and R1 / R2 is in the range of 0.3-3. The distance between the base of the first textured surface and the base of the second textured surface is in the range of 3 μm to 10 μm.

14. The preparation method according to claim 13, wherein The green picosecond laser meets one or more of the following conditions: 1) The wavelength of the green picosecond laser is 532nm or 1064nm; 2) The radiation power of the green picosecond laser is 1W-50W; 3) The spot overlap rate of the green picosecond laser is 40%-80%; or 4) The energy density of the green picosecond laser is 100 mJ / cm 2 -400mJ / cm 2 .

15. The preparation method according to claim 13 or 14, wherein The reflectivity of the first suede surface is 7%-15%, and / or the reflectivity of the second suede surface is 7%-30%.

16. The preparation method according to claim 13 or 14, wherein After the pre-isolation region is formed, the distance between two adjacent emitters is in the range of 10 μm to 1000 μm.

17. The preparation method according to claim 13 or 14, wherein In step S4, the acid solution used for pickling is an HF solution with a concentration of 5%-30%, and the pickling time is 10s-70s.

18. The preparation method according to claim 13 or 14, wherein The conditions of step S5 meet one or more of the following conditions: 1) The mass ratio of the alkali in the alkali solution to the texturing additive is 1:2-5:1; 2) The temperature of the texturing is 65°C-85°C; 3) The texturing time is 600s-900s.

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