Heterojunction battery and preparation method thereof

Abstract

The invention discloses a heterojunction cell and a preparation method thereof. The heterojunction cell comprises: a silicon wafer; the first intrinsic layer and the first doping layer are sequentially stacked on the light receiving surface of the silicon wafer; the second intrinsic layer and the second doping layer are sequentially stacked on the backlight surface of the silicon wafer; wherein the first intrinsic layer and / or the second intrinsic layer comprises an intrinsic oxygen-doped amorphous silicon layer and an intrinsic hydrogenated amorphous silicon layer which are stacked in sequence. A double-layer amorphous silicon structure of the intrinsic oxygen-doped amorphous silicon layer and the intrinsic hydrogenated amorphous silicon layer is adopted by the front surface and the back surface of the heterojunction cell, so that excellent passivation performance and contact performance can be realized under the thin intrinsic amorphous silicon layer, the cell efficiency is remarkably improved, meanwhile, attenuation of the cell and components can be slowed down, and the reliability of the cell and the components can be ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar energy, and particularly relates to a heterojunction cell and a preparation method thereof. Background Art

[0002] Heterojunction (HJT) cells have high conversion efficiency due to excellent surface passivation. However, maintaining their performance during the guaranteed life of photovoltaic modules requires excellent passivation performance and stability.

[0003] As is well known, HJT cells exhibit an increase or decrease in performance under light illumination. This instability is related to changes in the passivated regions on the cell surface. A thinner amorphous silicon (a-Si) thin film provides a lower interface defect density and higher passivation performance, but this passivation is vulnerable to instability. For example, the passivation performance of the a-Si thin film decreases under light illumination or in a humid and hot environment, resulting in a significant power attenuation of the cell module. In addition, a certain thickness of the a-Si thin film is required to achieve good passivation effect, but an increase in thickness will also lead to poor contact performance and affect the efficiency of the cell.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a heterojunction cell and a preparation method thereof. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a heterojunction cell and a preparation method thereof to improve the passivation performance and contact performance of the heterojunction cell.

[0006] To achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0007] A heterojunction cell, the heterojunction cell comprising:

[0008] A silicon wafer;

[0009] A first intrinsic layer and a first doped layer sequentially stacked on the light-receiving surface of the silicon wafer;

[0010] A second intrinsic layer and a second doped layer sequentially stacked on the backlight surface of the silicon wafer;

[0011] Wherein, the first intrinsic layer and / or the second intrinsic layer includes an intrinsic oxygen-doped amorphous silicon layer and an intrinsic hydrogenated amorphous silicon layer sequentially stacked.

[0012] In one embodiment, the first intrinsic layer includes a first intrinsic oxygen-doped amorphous silicon layer and a first intrinsic hydrogenated amorphous silicon layer sequentially stacked on the light-receiving surface of the silicon wafer.

[0013] In one embodiment, the second intrinsic layer includes a second intrinsic oxygen-doped amorphous silicon layer and a second intrinsic hydrogenated amorphous silicon layer sequentially stacked on the light-receiving surface of the silicon wafer.

[0014] In one embodiment, the first intrinsic layer includes a first intrinsic oxygen-doped amorphous silicon layer and a first intrinsic hydrogenated amorphous silicon layer that are sequentially stacked on the light-receiving surface of the silicon wafer; the second intrinsic layer includes a second intrinsic oxygen-doped amorphous silicon layer and a second intrinsic hydrogenated amorphous silicon layer that are sequentially stacked on the light-receiving surface of the silicon wafer.

[0015] In one embodiment, the total thickness of the first intrinsic oxygen-doped amorphous silicon layer and the first intrinsic hydrogenated amorphous silicon layer is 4 nm to 5 nm; and / or,

[0016] the thickness of the first intrinsic oxygen-doped amorphous silicon layer is 1 nm to 2 nm; and / or,

[0017] the thickness of the first intrinsic hydrogenated amorphous silicon layer is 2 nm to 4 nm.

[0018] In one embodiment, the total thickness of the second intrinsic oxygen-doped amorphous silicon layer and the second intrinsic hydrogenated amorphous silicon layer is 4 nm to 5 nm; and / or,

[0019] the thickness of the second intrinsic oxygen-doped amorphous silicon layer is 1 nm to 2 nm; and / or,

[0020] the thickness of the second intrinsic hydrogenated amorphous silicon layer is 2 nm to 4 nm.

[0021] In one embodiment, the oxygen doping amount in the first intrinsic oxygen-doped amorphous silicon layer is greater than the oxygen doping amount in the second intrinsic oxygen-doped amorphous silicon layer.

[0022] In one embodiment, the silicon wafer is an N-type silicon wafer, the doping type of the first doping layer is the same as that of the silicon wafer, and the doping type of the second doping layer is the same as that of the silicon wafer; and / or,

[0023] the first doping layer is a doped amorphous silicon layer or a doped microcrystalline silicon layer; and / or,

[0024] the second doping layer is a doped amorphous silicon layer or a doped microcrystalline silicon layer; and / or,

[0025] the thickness of the first doping layer is 20 nm to 40 nm; and / or,

[0026] the thickness of the second doping layer is 20 nm to 40 nm.

[0027] The technical solution provided by an embodiment of the present invention is as follows:

[0028] A method for manufacturing a heterojunction battery, the manufacturing method including the following steps:

[0029] Provide a silicon wafer;

[0030] Deposit a first intrinsic layer and a first doping layer on the light-receiving surface of the silicon wafer in sequence;

[0031] Deposit a second intrinsic layer and a second doped layer on the backlight surface of the silicon wafer in sequence;

[0032] Wherein, the first intrinsic layer and / or the second intrinsic layer include an oxygen-doped intrinsic amorphous silicon layer and a hydrogenated intrinsic amorphous silicon layer stacked in sequence.

[0033] In one embodiment, the first intrinsic layer includes a first oxygen-doped intrinsic amorphous silicon layer and a first hydrogenated intrinsic amorphous silicon layer stacked in sequence on the light-receiving surface of the silicon wafer. The deposition of the first intrinsic layer is specifically as follows:

[0034] Adopt the PECVD process, introduce carbon dioxide and silane, and the flow ratio of carbon dioxide to silane is (2-12):100, and deposit a first oxygen-doped intrinsic amorphous silicon layer with a thickness of 1nm-2nm on the light-receiving surface of the silicon wafer;

[0035] Adopt the PECVD process, introduce hydrogen and silane, and the flow ratio of hydrogen to silane is (2-2.5):1, and deposit a first hydrogenated intrinsic amorphous silicon layer with a thickness of 2nm-4nm on the first oxygen-doped intrinsic amorphous silicon layer.

[0036] In one embodiment, in the deposition process of the first intrinsic layer:

[0037] The deposition power of the first oxygen-doped intrinsic amorphous silicon layer is 500W-600W, and the chamber pressure is 0.4 Torr-0.6 Torr;

[0038] The deposition power of the first hydrogenated intrinsic amorphous silicon layer is 200W-300W, and the chamber pressure is 0.4 Torr-0.6 Torr.

[0039] In one embodiment, the second intrinsic layer includes a second oxygen-doped intrinsic amorphous silicon layer and a second hydrogenated intrinsic amorphous silicon layer stacked in sequence on the light-receiving surface of the silicon wafer. The deposition of the second intrinsic layer is specifically as follows:

[0040] Adopt the PECVD process, introduce carbon dioxide and silane, and the flow ratio of carbon dioxide to silane is (1-5):100, and deposit a second oxygen-doped intrinsic amorphous silicon layer with a thickness of 1nm-2nm on the backlight surface of the silicon wafer;

[0041] Adopt the PECVD process, introduce hydrogen and silane, and the flow ratio of hydrogen to silane is (2-2.5):1, and deposit a second hydrogenated intrinsic amorphous silicon layer with a thickness of 2nm-4nm on the second oxygen-doped intrinsic amorphous silicon layer.

[0042] In one embodiment, in the deposition process of the second intrinsic layer:

[0043] The deposition power of the second oxygen-doped intrinsic amorphous silicon layer is 600W-800W, and the chamber pressure is 0.4 Torr-0.6 Torr;

[0044] The deposition power of the second intrinsic hydrogenated amorphous silicon layer is 100W - 200W, and the chamber pressure is 0.4 Torr - 0.6 Torr.

[0045] In one embodiment, the first intrinsic layer includes a first intrinsic oxygen-doped amorphous silicon layer and a first intrinsic hydrogenated amorphous silicon layer that are sequentially stacked on the light-receiving surface of the silicon wafer; the second intrinsic layer includes a second intrinsic oxygen-doped amorphous silicon layer and a second intrinsic hydrogenated amorphous silicon layer that are sequentially stacked on the light-receiving surface of the silicon wafer;

[0046] The first intrinsic oxygen-doped amorphous silicon layer and the second intrinsic oxygen-doped amorphous silicon layer are deposited by PECVD process. Carbon dioxide and silane are introduced in the PECVD process, and the flow ratio of carbon dioxide to silane during the deposition of the first intrinsic oxygen-doped amorphous silicon layer is greater than that during the deposition of the second intrinsic oxygen-doped amorphous silicon layer.

[0047] The present invention has the following beneficial effects:

[0048] In the heterojunction battery of the present invention, the front / back surface adopts a double-layer amorphous silicon structure of an intrinsic oxygen-doped amorphous silicon layer and an intrinsic hydrogenated amorphous silicon layer, which can achieve excellent passivation performance and contact performance under a relatively thin intrinsic amorphous silicon layer, significantly improve the battery efficiency, and at the same time can slow down the attenuation of the battery and components, ensuring its reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0050] Figure 1 It is a schematic structural diagram of the heterojunction battery in Embodiment 1 of the present invention;

[0051] Figure 2 It is a schematic structural diagram of the heterojunction battery in Embodiment 2 of the present invention;

[0052] Figure 3 It is a schematic structural diagram of the heterojunction battery in Embodiment 3 of the present invention;

[0053] Figure 4a It is a wave number (Wavelength)-light intensity (Intensity) spectrogram of the battery when the intrinsic amorphous silicon layer is not oxygen-doped in the prior art;

[0054] Figure 4bThis is the wavelength - intensity spectrogram of the battery when the intrinsic amorphous silicon layer in the present invention is doped with oxygen. Detailed implementation manners

[0055] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0056] In the present invention, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "below" and "beneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0057] The present invention discloses a heterojunction battery, including:

[0058] A silicon wafer;

[0059] A first intrinsic layer and a first doped layer sequentially stacked on the light - receiving surface of the silicon wafer;

[0060] A second intrinsic layer and a second doped layer sequentially stacked on the back - light surface of the silicon wafer;

[0061] Wherein, the first intrinsic layer and / or the second intrinsic layer includes an intrinsic oxygen - doped amorphous silicon layer and an intrinsic hydrogenated amorphous silicon layer stacked in sequence.

[0062] The present invention also discloses a method for manufacturing a heterojunction battery, including the following steps:

[0063] Providing a silicon wafer;

[0064] Sequentially depositing a first intrinsic layer and a first doped layer on the light - receiving surface of the silicon wafer;

[0065] Sequentially depositing a second intrinsic layer and a second doped layer on the back - light surface of the silicon wafer;

[0066] Wherein, the first intrinsic layer and / or the second intrinsic layer includes an intrinsic oxygen - doped amorphous silicon layer and an intrinsic hydrogenated amorphous silicon layer stacked in sequence.

[0067] In the present invention, by optimizing the intrinsic layer in the heterojunction cell, excellent passivation performance and contact performance can be achieved under a relatively thin intrinsic amorphous silicon layer, thereby improving the photoelectric conversion efficiency of the cell.

[0068] It should be understood that the heterojunction cell also includes a front electrode and a back electrode. The electrodes in the present invention are exactly the same as those in the prior art, so they will not be elaborated here.

[0069] The present invention will be further described below in conjunction with specific embodiments.

[0070] Example 1:

[0071] Refer Figure 1 As shown, the heterojunction cell in this embodiment includes:

[0072] A silicon wafer 10, including a light-receiving surface (i.e., the front or upper surface) and a light-backing surface (i.e., the back or lower surface) arranged oppositely;

[0073] A first intrinsic layer 11 and a first doped layer 12 stacked in sequence on the light-receiving surface of the silicon wafer;

[0074] A second intrinsic layer 21 and a second doped layer 22 stacked in sequence on the light-backing surface of the silicon wafer;

[0075] Among them, the first intrinsic layer 11 includes a first intrinsic oxygen-doped amorphous silicon layer 111 and a first intrinsic hydrogenated amorphous silicon layer 112 stacked in sequence on the light-receiving surface of the silicon wafer.

[0076] In this embodiment, the total thickness of the first intrinsic oxygen-doped amorphous silicon layer 111 and the first intrinsic hydrogenated amorphous silicon layer 112 is 4 nm to 5 nm, wherein the thickness of the first intrinsic oxygen-doped amorphous silicon layer 111 is 1 nm to 2 nm, and the thickness of the first intrinsic hydrogenated amorphous silicon layer 112 is 2 nm to 4 nm.

[0077] The second intrinsic layer 21 is an intrinsic amorphous silicon layer in the prior art, with a thickness of 6 nm to 8 nm, and will not be elaborated here.

[0078] In addition, the silicon wafer 10 in this embodiment is an N-type silicon wafer; the first doped layer 12 is an N-type doped amorphous silicon layer or a doped microcrystalline silicon layer, with a thickness of 20 nm to 40 nm; the second doped layer 22 is a P-type doped amorphous silicon layer or a doped microcrystalline silicon layer, with a thickness of 20 nm to 40 nm. The silicon wafer 10, the first doped layer 12, and the second doped layer 22 are the same as those in the prior art and will not be elaborated here.

[0079] The preparation method of the heterojunction cell in this embodiment includes the following steps:

[0080] A silicon wafer 10;

[0081] Deposit a first intrinsic layer 11 and a first doped layer 12 on the light-receiving surface of the silicon wafer in sequence;

[0082] Deposit a second intrinsic layer 21 and a second doped layer 22 on the backlight surface of the silicon wafer in sequence.

[0083] Among them, the deposition of the first intrinsic layer 11 is specifically as follows:

[0084] Adopt the PECVD process, introduce carbon dioxide and silane, the flow ratio of carbon dioxide to silane (CO2:SiH4) is (2 - 12):100, and deposit a first intrinsic oxygen-doped amorphous silicon layer 111 with a thickness of 1 nm - 2 nm on the light-receiving surface of the silicon wafer;

[0085] Adopt the PECVD process, introduce hydrogen and silane, the flow ratio of hydrogen to silane (H2:SiH4) is (2 - 2.5):1, and deposit a first intrinsic hydrogenated amorphous silicon layer 112 with a thickness of 2 nm - 4 nm on the first intrinsic oxygen-doped amorphous silicon layer.

[0086] Preferably, the deposition power of the first intrinsic oxygen-doped amorphous silicon layer 111 is 500 W - 600 W, and the chamber pressure is 0.4 Torr - 0.6 Torr; the deposition power of the first intrinsic hydrogenated amorphous silicon layer 112 is 200 W - 300 W, and the chamber pressure is 0.4 Torr - 0.6 Torr.

[0087] In this embodiment, the deposition processes of the first doped layer 12, the second intrinsic layer 21, and the second doped layer 22 are exactly the same as those in the prior art, and will not be elaborated here.

[0088] Example 2:

[0089] Refer Figure 2 As shown, the heterojunction battery in this embodiment includes:

[0090] A silicon wafer 10, including a light-receiving surface (i.e., the front or upper surface) and a backlight surface (i.e., the back or lower surface) arranged oppositely;

[0091] A first intrinsic layer 11 and a first doped layer 12 stacked in sequence on the light-receiving surface of the silicon wafer;

[0092] A second intrinsic layer 21 and a second doped layer 22 stacked in sequence on the backlight surface of the silicon wafer;

[0093] Among them, the second intrinsic layer 21 includes a second intrinsic oxygen-doped amorphous silicon layer 211 and a second intrinsic hydrogenated amorphous silicon layer 212 stacked in sequence on the light-receiving surface of the silicon wafer.

[0094] In this embodiment, the total thickness of the second intrinsic oxygen-doped amorphous silicon layer 211 and the second intrinsic hydrogenated amorphous silicon layer 212 is 4 nm to 5 nm, where the thickness of the second intrinsic oxygen-doped amorphous silicon layer 211 is 1 nm to 2 nm, and the thickness of the second intrinsic hydrogenated amorphous silicon layer 212 is 2 nm to 4 nm.

[0095] The first intrinsic layer 11 is an intrinsic amorphous silicon layer in the prior art with a thickness of 6 nm to 8 nm, which will not be elaborated here.

[0096] In addition, the silicon wafer 10 in this embodiment is an N-type silicon wafer; the first doping layer 12 is an N-type doped amorphous silicon layer or a doped microcrystalline silicon layer with a thickness of 20 nm to 40 nm; the second doping layer 22 is a P-type doped amorphous silicon layer or a doped microcrystalline silicon layer with a thickness of 20 nm to 40 nm. The silicon wafer 10, the first doping layer 12, and the second doping layer 22 are the same as those in the prior art, which will not be elaborated here.

[0097] The preparation method of the heterojunction battery in this embodiment includes the following steps:

[0098] Provide the silicon wafer 10;

[0099] Deposit the first intrinsic layer 11 and the first doping layer 12 successively on the light-receiving surface of the silicon wafer;

[0100] Deposit the second intrinsic layer 21 and the second doping layer 22 successively on the backlight surface of the silicon wafer.

[0101] Among them, the deposition of the second intrinsic layer 21 is specifically as follows:

[0102] Adopt the PECVD process, introduce carbon dioxide and silane, and the flow ratio of carbon dioxide to silane (CO2:SiH4) is (1 - 5):100, and deposit the second intrinsic oxygen-doped amorphous silicon layer 211 with a thickness of 1 nm to 2 nm on the backlight surface of the silicon wafer;

[0103] Adopt the PECVD process, introduce hydrogen and silane, and the flow ratio of hydrogen to silane (H2:SiH4) is (2 - 2.5):1, and deposit the second intrinsic hydrogenated amorphous silicon layer 212 with a thickness of 2 nm to 4 nm on the second intrinsic oxygen-doped amorphous silicon layer.

[0104] Preferably, the deposition power of the second intrinsic oxygen-doped amorphous silicon layer 211 is 600 W to 800 W, and the chamber pressure is 0.4 Torr to 0.6 Torr; the deposition power of the second intrinsic hydrogenated amorphous silicon layer 212 is 100 W to 200 W, and the chamber pressure is 0.4 Torr to 0.6 Torr.

[0105] In this embodiment, the deposition processes of the first intrinsic layer 11, the first doping layer 12, and the second doping layer 22 are exactly the same as those in the prior art, which will not be elaborated here.

[0106] Example 3:

[0107] Refer Figure 3 As shown, the heterojunction cell in this embodiment includes:

[0108] A silicon wafer 10, including a light-receiving surface (i.e., the front or upper surface) and a backlight surface (i.e., the back or lower surface) arranged oppositely;

[0109] A first intrinsic layer 11 and a first doped layer 12 stacked in sequence on the light-receiving surface of the silicon wafer;

[0110] A second intrinsic layer 21 and a second doped layer 22 stacked in sequence on the backlight surface of the silicon wafer;

[0111] Among them, the first intrinsic layer 11 includes a first intrinsic oxygen-doped amorphous silicon layer 111 and a first intrinsic hydrogenated amorphous silicon layer 112 stacked in sequence on the light-receiving surface of the silicon wafer; the second intrinsic layer 21 includes a second intrinsic oxygen-doped amorphous silicon layer 211 and a second intrinsic hydrogenated amorphous silicon layer 212 stacked in sequence on the light-receiving surface of the silicon wafer.

[0112] In this embodiment, the total thickness of the first intrinsic oxygen-doped amorphous silicon layer 111 and the first intrinsic hydrogenated amorphous silicon layer 112 is 4 nm to 5 nm, wherein the thickness of the first intrinsic oxygen-doped amorphous silicon layer 111 is 1 nm to 2 nm, and the thickness of the first intrinsic hydrogenated amorphous silicon layer 112 is 2 nm to 4 nm; the total thickness of the second intrinsic oxygen-doped amorphous silicon layer 211 and the second intrinsic hydrogenated amorphous silicon layer 212 is 4 nm to 5 nm, wherein the thickness of the second intrinsic oxygen-doped amorphous silicon layer 211 is 1 nm to 2 nm, and the thickness of the second intrinsic hydrogenated amorphous silicon layer 212 is 2 nm to 4 nm.

[0113] In addition, the silicon wafer 10 in this embodiment is an N-type silicon wafer; the first doped layer 12 is an N-type doped amorphous silicon layer or a doped microcrystalline silicon layer with a thickness of 20 nm to 40 nm; the second doped layer 22 is a P-type doped amorphous silicon layer or a doped microcrystalline silicon layer with a thickness of 20 nm to 40 nm. The silicon wafer 10, the first doped layer 12, and the second doped layer 22 are the same as those in the prior art and will not be elaborated here.

[0114] The preparation method of the heterojunction cell in this embodiment includes the following steps:

[0115] Provide a silicon wafer 10;

[0116] Deposit the first intrinsic layer 11 and the first doped layer 12 in sequence on the light-receiving surface of the silicon wafer;

[0117] Deposit the second intrinsic layer 21 and the second doped layer 22 in sequence on the backlight surface of the silicon wafer.

[0118] The deposition of the first intrinsic layer 11 in this embodiment is specifically:

[0119] Using the PECVD process, carbon dioxide and silane are introduced, and the flow rate ratio of carbon dioxide to silane (CO2:SiH4) is (2 - 12):100. A first intrinsic oxygen-doped amorphous silicon layer 111 with a thickness of 1 nm to 2 nm is deposited on the light-receiving surface of the silicon wafer.

[0120] Using the PECVD process, hydrogen and silane are introduced, and the flow rate ratio of hydrogen to silane (H2:SiH4) is (2 - 2.5):1. A first intrinsic hydrogenated amorphous silicon layer 112 with a thickness of 2 nm to 4 nm is deposited on the first intrinsic oxygen-doped amorphous silicon layer.

[0121] Preferably, the deposition power of the first intrinsic oxygen-doped amorphous silicon layer 111 is 500 W to 600 W, and the chamber pressure is 0.4 Torr to 0.6 Torr; the deposition power of the first intrinsic hydrogenated amorphous silicon layer 112 is 200 W to 300 W, and the chamber pressure is 0.4 Torr to 0.6 Torr.

[0122] In this embodiment, the deposition of the second intrinsic layer 21 is specifically as follows:

[0123] Using the PECVD process, carbon dioxide and silane are introduced, and the flow rate ratio of carbon dioxide to silane (CO2:SiH4) is (1 - 5):100. A second intrinsic oxygen-doped amorphous silicon layer 211 with a thickness of 1 nm to 2 nm is deposited on the backlight surface of the silicon wafer.

[0124] Using the PECVD process, hydrogen and silane are introduced, and the flow rate ratio of hydrogen to silane (H2:SiH4) is (2 - 2.5):1. A second intrinsic hydrogenated amorphous silicon layer 212 with a thickness of 2 nm to 4 nm is deposited on the second intrinsic oxygen-doped amorphous silicon layer.

[0125] Preferably, the deposition power of the second intrinsic oxygen-doped amorphous silicon layer 211 is 600 W to 800 W, and the chamber pressure is 0.4 Torr to 0.6 Torr; the deposition power of the second intrinsic hydrogenated amorphous silicon layer 212 is 100 W to 200 W, and the chamber pressure is 0.4 Torr to 0.6 Torr.

[0126] In this embodiment, the deposition processes of the first doping layer 12 and the second doping layer 22 are exactly the same as those in the prior art, and will not be elaborated here.

[0127] It should be noted that after doping oxygen into the intrinsic amorphous silicon layer, the bandgap width of amorphous silicon can be broadened, the parasitic absorption effect of the amorphous silicon layer can be reduced, and the photoelectric conversion efficiency of the battery can be improved. In this embodiment, the oxygen doping amount of the first intrinsic oxygen-doped amorphous silicon layer on the light-receiving surface of the silicon wafer is slightly higher than that of the second intrinsic oxygen-doped amorphous silicon layer on the backlight surface of the silicon wafer; that is, the flow rate ratio of carbon dioxide to silane (CO2:SiH4) during the deposition of the first intrinsic oxygen-doped amorphous silicon layer is greater than the flow rate ratio of carbon dioxide to silane (CO2:SiH4) during the deposition of the second intrinsic oxygen-doped amorphous silicon layer.

[0128] In the present invention, by setting the intrinsic oxygen-doped amorphous silicon layer, the passivation performance of the intrinsic amorphous silicon layer can be improved. As shown in the spectrogram Figure 4a in, when the intrinsic amorphous silicon layer is not doped with oxygen, there are fewer Si-H2 bonds, and the content of Si-H bonds is 75% +. Generally, the higher the content of Si-H2 bonds, the higher the passivation performance of the film layer. As shown in the spectrogram Figure 4b in, when the intrinsic amorphous silicon layer is doped with oxygen, when the O atom combines with the Si atom, due to higher electronegativity, it will strongly attract hydrogen atoms, resulting in the inhibition of the Si hydrogen absorption reaction, thereby generating more Si-H2 bonds, which can significantly improve the passivation performance of the film layer.

[0129] In addition, the oxygen doping content of the intrinsic amorphous silicon layer has a certain influence on the minority carrier lifetime. Doping a small amount of oxygen can appropriately increase the minority carrier lifetime, but when the oxygen doping amount is too high, the minority carrier lifetime will decrease.

[0130] In Example 1, the flow rate ratio of hydrogen to silane (H2:SiH4) in the deposition process of the first intrinsic hydrogenated amorphous silicon layer 112 is controlled to be 2.2:1, the deposition thickness is 3 nm, and the deposition thickness of the first intrinsic oxygen-doped amorphous silicon layer 111 is 1.5 nm. By changing the flow rate ratio of carbon dioxide to silane (CO2:SiH4) during the deposition of the first intrinsic oxygen-doped amorphous silicon layer 111, the following table of different CO2:SiH4 flow rate ratios and minority carrier lifetimes can be obtained:

[0131]

[0132] It can be seen that the minority carrier lifetime is the highest when the flow rate ratio CO2:SiH4 is about 6:100, and the minority carrier lifetime shows a downward trend after continuing to increase the CO2 flow rate. Therefore, in the present invention, in order to balance the passivation performance and the minority carrier lifetime, finally, the flow rate ratio of carbon dioxide to silane (CO2:SiH4) during the deposition of the first intrinsic oxygen-doped amorphous silicon layer needs to be controlled to be (2-12):100, preferably (5-8):100, and the optimal ratio is about 6:100.

[0133] In Example 2, the flow rate ratio of hydrogen to silane (H2:SiH4) in the deposition process of the second intrinsic hydrogenated amorphous silicon layer 212 was controlled to be 2.2:1, the deposition thickness was 3 nm, and the deposition thickness of the second intrinsic oxygen-doped amorphous silicon layer 211 was 1.5 nm. By changing the flow rate ratio of carbon dioxide to silane (CO2:SiH4) during the deposition of the second intrinsic oxygen-doped amorphous silicon layer 211, the following table shows the different CO2:SiH4 flow rate ratios and the minority carrier lifetime:

[0134]

[0135] It can be seen that the minority carrier lifetime is the highest when the flow rate ratio CO2:SiH4 is around 2.5:100. When the CO2 flow rate is further increased, the minority carrier lifetime shows a downward trend. Therefore, in the present invention, in order to balance the passivation performance and the minority carrier lifetime, finally, the flow rate ratio of carbon dioxide to silane (CO2:SiH4) during the deposition of the second intrinsic oxygen-doped amorphous silicon layer needs to be controlled to be (1-5):100, preferably (2-3):100, and the optimal ratio is about 2.5:100.

[0136] In Example 3, the flow rate ratio of carbon dioxide to silane during the deposition of the first intrinsic oxygen-doped amorphous silicon layer was controlled to be 6:100, and the flow rate ratio of carbon dioxide to silane during the deposition of the second intrinsic oxygen-doped amorphous silicon layer was 2.5:100. By changing the total thickness of the first intrinsic layer 11 and the second intrinsic layer 21, it can be found that different thicknesses will affect the electrical performance of the heterojunction battery, as shown in the following table:

[0137]

[0138] Among them, the thickness in the brackets of the first intrinsic layer is the sum of the thicknesses of the first intrinsic oxygen-doped amorphous silicon layer and the first intrinsic hydrogenated amorphous silicon layer, and the thickness in the brackets of the second intrinsic layer is the sum of the thicknesses of the second intrinsic oxygen-doped amorphous silicon layer and the second intrinsic hydrogenated amorphous silicon layer.

[0139] It can be found that when the thicknesses of the first intrinsic layer and the second intrinsic layer are less than 4 nm, although there is still an advantage in tunneling contact, the overall thickness of the amorphous silicon layer is relatively thin, the passivation effect is insufficient, the minority carrier lifetime is low, resulting in a still low final battery efficiency. Therefore, in the present invention, in order to balance the passivation performance, the minority carrier lifetime, and the tunneling contact, etc., the overall thickness of the intrinsic layer needs to be controlled to be 4 nm - 5 nm, and the optimal is about 4.5 nm.

[0140] In addition, the flow rate ratio of carbon dioxide to silane (CO2:SiH4) in the deposition process of the intrinsic oxygen-doped amorphous silicon layer in the present invention will also affect the reliability of the battery module. Taking the different flow rate ratios (CO2:SiH4) in the first intrinsic oxygen-doped amorphous silicon layer on the light-receiving surface as an example, the reliability test of the corresponding battery module is as follows in the table:

[0141]

[0142] It can be seen that when the different flow ratios (CO2:SiH4) of the light-receiving surface are (5-8):100, the attenuation of the battery module is small, and the reliability is significantly improved. Further increasing the flow ratio does not result in a significant improvement in attenuation. Considering both the battery efficiency and the reliability of the battery module, the final optimal flow ratio (CO2:SiH4) is approximately 6:100.

[0143] Similarly, different flow ratios (CO2:SiH4) in the second intrinsic oxygen-doped amorphous silicon layer on the backlight surface also affect the reliability of the battery module. By testing with the same reliability test method, the optimal flow ratio (CO2:SiH4) can be obtained as approximately 2.5:100.

[0144] From the above technical solutions, it can be seen that the present invention has the following beneficial effects:

[0145] In the heterojunction battery of the present invention, the double-layer amorphous silicon structure of the intrinsic oxygen-doped amorphous silicon layer and the intrinsic hydrogenated amorphous silicon layer is adopted on the front / back surface, which can achieve excellent passivation performance and contact performance under a relatively thin intrinsic amorphous silicon layer, significantly improving the battery efficiency, and at the same time being able to slow down the attenuation of the battery and the module, ensuring its reliability.

[0146] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, in any aspect, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed rights.

[0147] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A heterojunction battery, characterized in that, The heterojunction battery includes: a silicon wafer; a first intrinsic layer and a first doped layer sequentially stacked on the light-receiving surface of the silicon wafer; a second intrinsic layer and a second doped layer sequentially stacked on the backlight surface of the silicon wafer; wherein, the first intrinsic layer and / or the second intrinsic layer includes an intrinsic oxygen-doped amorphous silicon layer and an intrinsic hydrogenated amorphous silicon layer stacked in sequence.

2. The heterojunction battery according to claim 1, characterized in that, The first intrinsic layer includes a first intrinsic oxygen-doped amorphous silicon layer and a first intrinsic hydrogenated amorphous silicon layer sequentially stacked on the light-receiving surface of the silicon wafer.

3. The heterojunction battery according to claim 1, characterized in that, The second intrinsic layer includes a second intrinsic oxygen-doped amorphous silicon layer and a second intrinsic hydrogenated amorphous silicon layer sequentially stacked on the light-receiving surface of the silicon wafer.

4. The heterojunction battery according to claim 1, characterized in that, The first intrinsic layer includes a first intrinsic oxygen-doped amorphous silicon layer and a first intrinsic hydrogenated amorphous silicon layer sequentially stacked on the light-receiving surface of the silicon wafer; the second intrinsic layer includes a second intrinsic oxygen-doped amorphous silicon layer and a second intrinsic hydrogenated amorphous silicon layer sequentially stacked on the light-receiving surface of the silicon wafer.

5. The heterojunction battery according to claim 2 or 4, characterized in that, The total thickness of the first intrinsic oxygen-doped amorphous silicon layer and the first intrinsic hydrogenated amorphous silicon layer is 4 nm to 5 nm; and / or, the thickness of the first intrinsic oxygen-doped amorphous silicon layer is 1 nm to 2 nm; and / or, the thickness of the first intrinsic hydrogenated amorphous silicon layer is 2 nm to 4 nm.

6. The heterojunction battery according to claim 3 or 4, characterized in that, The total thickness of the second intrinsic oxygen-doped amorphous silicon layer and the second intrinsic hydrogenated amorphous silicon layer is 4 nm to 5 nm; and / or, the thickness of the second intrinsic oxygen-doped amorphous silicon layer is 1 nm to 2 nm; and / or, the thickness of the second intrinsic hydrogenated amorphous silicon layer is 2 nm to 4 nm.

7. The heterojunction battery according to claim 4, characterized in that, The oxygen doping amount in the first intrinsic oxygen-doped amorphous silicon layer is greater than the oxygen doping amount in the second intrinsic oxygen-doped amorphous silicon layer.

8. The heterojunction battery according to claim 1, characterized in that, The silicon wafer is an N-type silicon wafer, the doping type of the first doped layer is the same as that of the silicon wafer, and the doping type of the second doped layer is the same as that of the silicon wafer; and / or, the first doped layer is a doped amorphous silicon layer or a doped microcrystalline silicon layer; and / or, the second doped layer is a doped amorphous silicon layer or a doped microcrystalline silicon layer; and / or, the thickness of the first doped layer is 20 nm to 40 nm; and / or, the thickness of the second doped layer is 20 nm to 40 nm.

9. A method for preparing a heterojunction battery, characterized in that, The preparation method includes the following steps: providing a silicon wafer; depositing a first intrinsic layer and a first doped layer on the light-receiving surface of the silicon wafer in sequence; depositing a second intrinsic layer and a second doped layer on the backlight surface of the silicon wafer in sequence; wherein, the first intrinsic layer and / or the second intrinsic layer includes an intrinsic oxygen-doped amorphous silicon layer and an intrinsic hydrogenated amorphous silicon layer stacked in sequence.

10. The preparation method according to claim 9, characterized in that, The first intrinsic layer includes a first intrinsic oxygen-doped amorphous silicon layer and a first intrinsic hydrogenated amorphous silicon layer sequentially stacked on the light-receiving surface of the silicon wafer. The deposition of the first intrinsic layer is specifically: using the PECVD process, introducing carbon dioxide and silane, the flow ratio of carbon dioxide to silane is (2 to 12):100, and depositing a first intrinsic oxygen-doped amorphous silicon layer with a thickness of 1 nm to 2 nm on the light-receiving surface of the silicon wafer; using the PECVD process, introducing hydrogen and silane, the flow ratio of hydrogen to silane is (2 to 2.5):1, and depositing a first intrinsic hydrogenated amorphous silicon layer with a thickness of 2 nm to 4 nm on the first intrinsic oxygen-doped amorphous silicon layer.

11. The preparation method according to claim 10, characterized in that, In the deposition process of the first intrinsic layer: The deposition power of the first intrinsic oxygen-doped amorphous silicon layer is 500W - 600W, and the chamber pressure is 0.4 Torr - 0.6 Torr; The deposition power of the first intrinsic hydrogenated amorphous silicon layer is 200W - 300W, and the chamber pressure is 0.4 Torr - 0.6 Torr.

12. The preparation method according to claim 9, wherein The second intrinsic layer includes a second intrinsic oxygen-doped amorphous silicon layer and a second intrinsic hydrogenated amorphous silicon layer that are sequentially stacked on the light-receiving surface of the silicon wafer. The deposition of the second intrinsic layer is specifically as follows: Using the PECVD process, carbon dioxide and silane are introduced, and the flow ratio of carbon dioxide to silane is (1 - 5):

100. A second intrinsic oxygen-doped amorphous silicon layer with a thickness of 1nm - 2nm is deposited on the backlight surface of the silicon wafer; Using the PECVD process, hydrogen and silane are introduced, and the flow ratio of hydrogen to silane is (2 - 2.5):

1. A second intrinsic hydrogenated amorphous silicon layer with a thickness of 2nm - 4nm is deposited on the second intrinsic oxygen-doped amorphous silicon layer.

13. The preparation method according to claim 12, wherein In the deposition process of the second intrinsic layer: The deposition power of the second intrinsic oxygen-doped amorphous silicon layer is 600W - 800W, and the chamber pressure is 0.4 Torr - 0.6 Torr; The deposition power of the second intrinsic hydrogenated amorphous silicon layer is 100W - 200W, and the chamber pressure is 0.4 Torr - 0.6 Torr.

14. The preparation method according to claim 9, wherein The first intrinsic layer includes a first intrinsic oxygen-doped amorphous silicon layer and a first intrinsic hydrogenated amorphous silicon layer that are sequentially stacked on the light-receiving surface of the silicon wafer; the second intrinsic layer includes a second intrinsic oxygen-doped amorphous silicon layer and a second intrinsic hydrogenated amorphous silicon layer that are sequentially stacked on the light-receiving surface of the silicon wafer; The first intrinsic oxygen-doped amorphous silicon layer and the second intrinsic oxygen-doped amorphous silicon layer are deposited using the PECVD process. Carbon dioxide and silane are introduced in the PECVD process, and the flow ratio of carbon dioxide to silane during the deposition of the first intrinsic oxygen-doped amorphous silicon layer is greater than that during the deposition of the second intrinsic oxygen-doped amorphous silicon layer.

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