Hybrid passivation back contact battery and preparation method thereof

Abstract

The invention discloses a hybrid passivation back contact battery and a preparation method thereof, the battery comprises a silicon wafer, the silicon wafer comprises a first surface and a second surface which are oppositely arranged, the second surface comprises a first area and a second area, and the area of the first area is larger than that of the second area; the heterostructure comprises a first passivation layer and a first doping layer which are at least stacked on the first region; the first electrode structure is located on the first doping layer in the heterostructure; the first passivation structure comprises a tunneling oxide layer and a second doping layer which are stacked on the second region; the second electrode structure is located on the second doping layer in the first passivation structure, and the first electrode structure and the second electrode structure are electrically isolated through an isolation groove; and the second passivation structure is located on the first surface of the silicon wafer. The passivation effect of the HTBC battery is good, and the photoelectric conversion efficiency can be remarkably improved; and the preparation process of the battery is simple, few in process steps and low in equipment cost.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar energy, and particularly relates to a hybrid passivated back contact (HTBC) cell and a preparation method thereof. Background Art

[0002] Heterojunction cells (HJT) have the advantages of high open-circuit voltage (Voc) and high fill factor (FF), but the low current is an obstacle to further improving the efficiency. The main reasons are as follows: 1. The absorption of light by the front transparent conductive film (TCO); 2. The absorption of light by the front amorphous silicon film; 3. The shading loss of the front grid lines. The future development of heterojunction cells must be in the direction of low current.

[0003] Back contact cells (IBC) are a kind of cell technology that integrates the positive and negative electrodes entirely on the back of the cell. Specifically, it has the characteristic of no light shading on the front, and the high current is its significant advantage. The current mainstream IBC cells include TBC cells that stack TOPCon technology on IBC technology, and HBC cells that stack HJT technology on IBC technology. The back emitter region and field passivation region of TBC cells both adopt an oxide layer stacked with doped polysilicon structure, and the back emitter region and field passivation region of HBC cells both adopt an intrinsic amorphous silicon layer stacked with doped amorphous silicon (or microcrystalline silicon) structure. The process equipment of TBC cells is cheap, but the passivation effect is poor. The passivation effect of HBC is good, but the process equipment is expensive.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a hybrid passivated back contact cell and a preparation method thereof. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a hybrid passivated back contact cell and a preparation method thereof to improve the photoelectric conversion efficiency, optimize the preparation process, and reduce the process cost.

[0006] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0007] A hybrid passivated back contact cell, the cell comprising:

[0008] A silicon wafer, including a first surface and a second surface arranged opposite to each other, the second surface including a first region and a second region, and the area of the first region is larger than that of the second region;

[0009] A heterostructure, including at least a first passivation layer and a first doping layer stacked on the first region;

[0010] A first electrode structure, located on the first doping layer in the heterostructure;

[0011] A first passivation structure, including a tunneling oxide layer and a second doping layer stacked on the second region;

[0012] A second electrode structure, located on a second doped layer in a first passivation structure, wherein the first electrode structure and the second electrode structure are electrically isolated by an isolation groove;

[0013] A second passivation structure, located on a first surface of a silicon wafer.

[0014] In one embodiment, the area of the first region is 70% - 95% of the area of the second surface; or,

[0015] the area of the first region is 80% - 85% of the area of the second surface.

[0016] In one embodiment, the silicon wafer is a doped silicon wafer, the doping type of the first doped layer is opposite to that of the silicon wafer, and the doping type of the second doped layer is the same as that of the silicon wafer.

[0017] In one embodiment, the first passivation layer is an intrinsic amorphous silicon layer; and / or,

[0018] the tunneling oxide layer is any one or a combination of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0019] the first doped layer is an amorphous silicon layer or a microcrystalline silicon layer; and / or,

[0020] the second doped layer is a polysilicon layer; and / or,

[0021] the thickness of the first passivation layer is 5 nm - 10 nm; and / or,

[0022] the thickness of the tunneling oxide layer is 1 nm - 2 nm; and / or,

[0023] the thickness of the first doped layer is 20 nm - 40 nm; and / or,

[0024] the thickness of the second doped layer is 60 nm - 300 nm; and / or,

[0025] The doping concentration of the first doped layer is 1E17 cm -3 ~1E20 cm -3 ; and / or,

[0026] The doping concentration of the second doped layer is 1E20 cm -3 ~1E22 cm -3 .

[0027] In one embodiment, the second passivation structure includes a second passivation layer and an antireflection layer stacked on the first surface, wherein the second passivation layer is an intrinsic amorphous silicon layer, and the antireflection layer includes one or a combination of a SiNx layer, a SiNxOy layer, and a TCO layer.

[0028] In one embodiment, the second passivation structure further includes a third doped layer located between the second passivation layer and the antireflection layer, and the doping type of the third doped layer is the same as that of the silicon wafer.

[0029] In one embodiment, the third doped layer is an amorphous silicon layer or a microcrystalline silicon layer; and / or,

[0030] The thickness of the third doped layer is 15 nm to 30 nm; and / or,

[0031] The doping concentration of the third doped layer is 1E17 cm -3 ~1E22 cm -3 .

[0032] In one embodiment, the first passivation layer and the first doped layer are stacked on all of the first regions and on the first passivation structure of a part of the second regions, and an electrode window that is not covered by the first passivation layer and the first doped layer is formed on the second doped layer.

[0033] In one embodiment, the first electrode structure includes a first TCO layer and a first electrode. The first TCO layer is at least located on the first doped layer of the first region, and the first electrode is in electrical contact with the first TCO layer;

[0034] The second electrode structure includes a second TCO layer and a second electrode. The second TCO layer is at least located in the electrode window of the second region, and the second electrode is in electrical contact with the second TCO layer;

[0035] Wherein, the first TCO layer and the second TCO layer are electrically isolated by an isolation groove.

[0036] In one embodiment, the isolation groove is located on the first region and / or the second region, and the isolation groove extends at least to the surface of the first doped layer.

[0037] In one embodiment, the first surface is a pyramidal texture surface or a polished surface; and / or,

[0038] The first region is a pyramidal texture surface or a polished surface; and / or,

[0039] The second region is a pyramidal texture surface.

[0040] The technical solution provided by an embodiment of the present invention is as follows:

[0041] A method for manufacturing a hybrid passivated back contact battery, the manufacturing method including the following steps:

[0042] A silicon wafer is provided, including a first surface and a second surface which are oppositely arranged. The second surface includes a first region and a second region, and the area of the first region is larger than that of the second region;

[0043] A tunneling oxide layer, a second doped layer and a first mask are sequentially deposited on the second surface;

[0044] The first mask on the first region is pattern-opened by a laser process, and the tunneling oxide layer and the second doped layer on the first region are removed;

[0045] The first mask on the second surface of the silicon wafer is removed;

[0046] A first passivation layer and a first doped layer are sequentially deposited on the second surface of the silicon wafer;

[0047] A second passivation structure is formed on the first surface of the silicon wafer;

[0048] Part of the first passivation layer and the first doped layer on the second region are removed by a laser process to form an electrode window;

[0049] A first electrode structure is prepared on the first doped layer, and a second electrode structure is prepared in the electrode window on the second doped layer.

[0050] In one embodiment, in the laser process of pattern-opening the first mask, the laser wavelength is 495 nm to 570 nm, the pulse width is 10 ns to 50 ns, the power is 5 W to 30 W, the duty cycle is 30% to 80%, and the scribing speed is 15 m / s to 25 m / s; and / or,

[0051] In the laser process of removing the first passivation layer and the first doped layer, the laser wavelength is 380 nm to 450 nm, the pulse width is 10 ns to 50 ns, the power is 5 W to 20 W, the duty cycle is 30% to 80%, and the scribing speed is 15 m / s to 25 m / s.

[0052] In one embodiment, the preparation of the first electrode structure and the second electrode structure includes:

[0053] A TCO layer is prepared in the first doped layer and the electrode window;

[0054] Part of the TCO layer on the first region and / or the second region is removed by a laser process to form an electrically isolated first TCO layer and second TCO layer in the first doped layer and the electrode window;

[0055] A first electrode in electrical contact with the first TCO layer is prepared on the first TCO layer, and a second electrode in electrical contact with the second TCO layer is prepared on the second TCO layer.

[0056] In one embodiment, in the laser process of removing a part of the TCO layer, the laser wavelength is 380 nm to 570 nm, the pulse width is 10 ns to 50 ns, the power is 5 W to 20 W, the duty ratio is 30% to 80%, and the scribing speed is 15 m / s to 25 m / s.

[0057] In one embodiment, after removing the tunneling oxide layer and the second doped layer on the first region, it further includes:

[0058] Treating the first region on the first surface and / or the second surface by an alkaline texturing process to form a pyramid texture structure.

[0059] In one embodiment, forming the second passivation structure on the first surface of the silicon wafer includes:

[0060] Depositing a second passivation layer on the first surface of the silicon wafer, and the second passivation layer is an intrinsic amorphous silicon layer;

[0061] Depositing a third doped layer on the second passivation layer, and the third doped layer is an amorphous silicon layer or a microcrystalline silicon layer;

[0062] Depositing an antireflection layer on the third doped layer, and the antireflection layer includes a combination of one or more of SiNx layer, SiNxOy layer, and TCO layer.

[0063] The present invention has the following beneficial effects:

[0064] For the first region and the second region on the back surface of the HTBC battery of the present invention, the passivation structures in the HJT battery and the TOPCon battery are respectively adopted, and the passivation effect is good, which can significantly improve the photoelectric conversion efficiency; and the preparation process of the battery is simple, the process steps are few, and the equipment cost is low. Description of the Drawings

[0065] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0066] Figure 1 It is a schematic structural diagram of an HTBC battery in a specific embodiment of the present invention;

[0067] Figures 2a to 2j It is a process flow chart for preparing an HTBC battery in a specific embodiment of the present invention. Detailed Embodiments

[0068] To enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0069] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "under" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0070] The present invention discloses a hybrid passivated back contact cell (i.e., HTBC cell), comprising:

[0071] A silicon wafer, including a first surface and a second surface arranged opposite to each other, the second surface including a first region and a second region, and the area of the first region is larger than the area of the second region;

[0072] A heterostructure, including at least a first passivation layer and a first doping layer stacked on the first region;

[0073] A first electrode structure, located on the first doping layer in the heterostructure;

[0074] A first passivation structure, including a tunneling oxide layer and a second doping layer stacked on the second region;

[0075] A second electrode structure, located on the second doping layer in the first passivation structure, and the first electrode structure and the second electrode structure are electrically isolated by an isolation groove;

[0076] A second passivation structure, located on the first surface of the silicon wafer.

[0077] The present invention also discloses a method for manufacturing a hybrid passivated back contact cell, comprising the following steps:

[0078] Provide a silicon wafer, including a first surface and a second surface arranged opposite to each other, the second surface including a first region and a second region, and the area of the first region is larger than the area of the second region;

[0079] Deposit a tunneling oxide layer, a second doping layer and a first mask layer on the second surface in sequence;

[0080] The first mask on the first region is pattern-opened by a laser process, and the tunneling oxide layer and the second doped layer on the first region are removed;

[0081] The first mask on the second surface of the silicon wafer is removed;

[0082] A first passivation layer and a first doped layer are sequentially deposited on the second surface of the silicon wafer;

[0083] A second passivation structure is formed on the first surface of the silicon wafer;

[0084] Part of the first passivation layer and the first doped layer on the second region are removed by a laser process to form an electrode window;

[0085] A first electrode structure is fabricated on the first doped layer, and a second electrode structure is fabricated in the electrode window on the second doped layer.

[0086] The present invention will be further described below in conjunction with specific embodiments.

[0087] See Figure 1 As shown, the HTBC battery in a specific embodiment of the present invention includes:

[0088] A silicon wafer 10, the silicon wafer is a doped silicon wafer, including a first surface S1 and a second surface which are oppositely arranged, the second surface includes a first region S21 and a second region S22, and the area of the first region S21 is larger than the area of the second region S22;

[0089] A heterostructure, including at least a first passivation layer 21 and a first doped layer 22 stacked on the first region S21, and the doping type of the first doped layer 22 is opposite to the doping type of the silicon wafer 10;

[0090] A first electrode structure, located on the first doped layer 22 in the heterostructure;

[0091] A first passivation structure, including a tunneling oxide layer 31 and a second doped layer 32 stacked on the second region S22, and the doping type of the second doped layer 32 is the same as the doping type of the silicon wafer 10;

[0092] A second electrode structure, located on the second doped layer 32 in the first passivation structure, and the first electrode structure and the second electrode structure are electrically isolated by an isolation groove 70;

[0093] A second passivation structure, located on the first surface S1 of the silicon wafer.

[0094] Exemplarily, the silicon wafer 10 in this embodiment is described by taking an N-type silicon wafer (i.e., N-type doping) as an example. The doping type of the first doping layer 22 is opposite to that of the silicon wafer 10, which is P-type doping (such as boron doping, etc.), and the doping type of the second doping layer 32 is the same as that of the silicon wafer 10, which is N-type doping (such as phosphorus doping, etc.).

[0095] The first region S21 in this embodiment is a back emitter (P-Emitter). The area of the first region S21 is 70% - 95% of the second surface area. Preferably, the area of the first region S21 is 80% - 85% of the second surface area.

[0096] Furthermore, in the heterostructure of this embodiment, the first passivation layer 21 is an intrinsic amorphous silicon layer with a thickness of 5 nm - 10 nm. The first doping layer 22 is a P-type doped amorphous silicon layer or microcrystalline silicon layer with a thickness of 20 nm - 40 nm and a doping concentration of 1E17 cm -3 ~1E20 cm -3 .

[0097] The second region S22 in this embodiment is a back surface field passivation region (n-BSF). In the first passivation structure, the tunneling oxide layer 31 is any one or a combination of silicon oxide layer (SiOx) and silicon oxynitride layer (SiNxOy) with a thickness of 1 nm - 2 nm. The second doping layer 32 is an N-type doped polysilicon layer with a thickness of 60 nm - 300 nm and a doping concentration of 1E20 cm -3 ~1E22 cm -3 .

[0098] Preferably, the first passivation layer 21 and the first doping layer 22 in this embodiment are stacked on the entire first region S21 and on the first passivation structure of a part of the second region S22. An electrode window that is not covered by the first passivation layer 21 and the first doping layer 22 is formed on the second doping layer 32.

[0099] In addition, the first electrode structure in this embodiment includes a first TCO layer 51 and a first electrode 61. The first TCO layer is at least located on the first doping layer 22 of the first region S21, and the first electrode is in electrical contact with the first TCO layer. The second electrode structure includes a second TCO layer 52 and a second electrode 62. The second TCO layer 52 is at least located in the electrode window on the second region S22, and the second electrode 62 is in electrical contact with the second TCO layer 52. Among them, the first TCO layer 51 and the second TCO layer 52 are electrically isolated by an isolation groove 70.

[0100] Specifically, the TCO (transparent conductive oxide) layer can be one or more of ITO, AZO, IWO, etc. The first electrode 61 and the second electrode 62 are metal grid electrodes, and their materials can be Ag or Ag / Cu alloy.

[0101] The isolation groove 70 in this embodiment is formed on the second region S22. The first TCO layer 51 and the second TCO layer 52 can be isolated by setting the isolation groove to avoid short circuit between the two electrodes. The depth of the isolation groove is greater than or equal to the thickness of the TCO layer, and the width is 20μm to 100μm. In other embodiments, the isolation groove 70 can also be formed on the first region S21, or partially formed on the first region S21 and partially formed on the second region S22. The isolation effect is the same and will not be repeated here.

[0102] Furthermore, an insulating layer (not shown) is formed in all or part of the isolation trench 70, and the isolation effect can be further improved by the provision of the insulating layer. In this embodiment, the isolation trench 70 extends to the surface of the first doping layer 22, and an extremely thin (about 1 nm thick) natural oxide layer (i.e., silicon oxide layer) is formed on the bottom wall and sidewall of the isolation trench.

[0103] The first surface S1 in this embodiment is a front surface field (FSF), and the second passivation structure thereon includes a second passivation layer 41 and an anti-reflection layer 43 stacked on the first surface S1, wherein the second passivation layer 41 is an intrinsic amorphous silicon layer with a thickness of 5nm to 10nm, and the anti-reflection layer 43 includes a combination of one or more of a TCO layer, a SiNx layer, a SiNxOy layer, etc., preferably a SiNx layer.

[0104] Furthermore, in other embodiments, the second passivation structure further includes a third doping layer 42 located between the second passivation layer 41 and the anti-reflection layer 43. The third doping layer 42 is an amorphous silicon layer or a microcrystalline silicon layer, with a thickness of 15 nm to 30 nm, and the doping type is the same as that of the silicon wafer 10, which is N-type doping, and the doping concentration is 1E17 cm -3 ~1E22cm -3 .

[0105] For example, in this embodiment, the first surface S1 and the first area S21 are pyramid-structured velvet surfaces, and the light trapping effect is improved by the pyramid velvet structure, and the second area S22 is a polished surface. In other embodiments, the first surface S1 and the first area S21 may also be polished surfaces, and the second area S22 may also be a pyramid velvet structure, which will not be described one by one here.

[0106] The front and back sides of the HTBC cell of the present invention both adopt passivation structures to reduce the surface recombination rate. The first area and the second area on the back side respectively adopt the passivation structures in the HJT cell and the TOPCon cell, which have good passivation effects and can significantly improve the photoelectric conversion efficiency.

[0107] Ginseng Figures 2a to 2j As shown, a method for preparing a HTBC battery in a specific embodiment of the present invention comprises the following steps:

[0108] 1. Refer to Figure 2a As shown, a silicon wafer 10 is provided. The silicon wafer is an N-type silicon wafer, including a first surface S1 and a second surface which are oppositely arranged. The second surface includes a first region S21 and a second region S22, and the area of the first region S21 is larger than that of the second region S22.

[0109] In this embodiment, the first surface S1 of the silicon wafer is a front surface field (FSF), the first region S21 in the second surface is a back emitter (P-Emitter), the second region S22 is a back surface field passivation region (n-BSF), and the area of the first region S21 is 70% - 95% of the area of the second surface, preferably 80% - 85%.

[0110] Exemplarily, in this embodiment, first in a tank cleaning machine, the front and back surfaces of the silicon wafer are polished by a polishing solution (such as NaOH solution) to form a smooth surface.

[0111] 2. Refer to Figure 2b As shown, through a dual-sided PECVD (Plasma Enhanced Chemical Vapor Deposition) process, a tunneling oxide layer 31, a second doping layer 32 and a first mask 80 are sequentially deposited on the second surface.

[0112] Exemplarily, the tunneling oxide layer 31 is a silicon dioxide layer with a thickness of 1nm - 2nm, the second doping layer 32 is a phosphorus-doped amorphous silicon layer with a thickness of 60nm - 300nm, and the doping concentration is 1E20cm -3 ~1E22cm -3 .

[0113] Then, the amorphous silicon layer is annealed in an annealing furnace to form a polycrystalline silicon layer. Oxygen is introduced during the annealing process, and the annealing temperature is ~850°C. Annealing can activate the phosphorus doping from interstitial phosphorus to substitutional phosphorus to form effective doping.

[0114] Among them, the first mask 80 can be any one of a SINx mask, a SiNxOy mask, a SiOx mask, etc., as a mask for subsequent processes. Exemplarily, in this embodiment, the SINx mask is taken as an example for illustration, and its thickness is 40nm - 120nm, preferably 70nm - 80nm.

[0115] 3. Refer to Figure 2c As shown, the first mask 80 on the first region S21 is patterned and opened by a laser process, and the tunneling oxide layer 31 and the second doping layer 32 on the first region S21 are removed.

[0116] In this step, the laser wavelength in the laser process is 495 nm to 570 nm, the pulse width is 10 ns to 50 ns, the power is 5 W to 30 W, the duty cycle is 30% to 80%, and the scribing speed is 15 m / s to 25 m / s. The laser film opening depth is controlled by the above process parameters to completely remove the tunneling oxide layer 31 and the second doping layer 32 on the first region S21. Exemplarily, in this embodiment, green laser with a wavelength of ~532 nm is used for film opening.

[0117] 4. Refer Figure 2d As shown, remove the first mask 80 on the second surface of the silicon wafer.

[0118] In this embodiment, in a chain cleaner, the back surface of the silicon wafer after the laser process is placed in a hydrofluoric acid solution to remove the SINx mask on the back surface of the silicon wafer.

[0119] Preferably, in this embodiment, in a texturing cleaner, the first region S21 on the second surface and the first surface S1 of the silicon wafer are processed by an alkali (such as NaOH solution) texturing process to form a pyramid texture structure, and the pyramid size is 0.5 μm to 5 μm.

[0120] 5. Refer Figure 2e As shown, by PECVD (Plasma Enhanced Chemical Vapor Deposition) process, a first passivation layer 21 and a first doping layer 22 are sequentially deposited on the second surface of the silicon wafer, and a second passivation layer 41 and a third doping layer 42 are sequentially deposited on the first surface of the silicon wafer.

[0121] Exemplarily, the first passivation layer 21 is an intrinsic amorphous silicon layer with a thickness of 5 nm to 10 nm, the first doping layer 22 is a boron-doped amorphous silicon layer or microcrystalline silicon layer with a thickness of 20 nm to 40 nm, and the doping concentration is 1E17 cm -3 ~1E20 cm -3 ; the second passivation layer 41 is an intrinsic amorphous silicon layer with a thickness of 5 nm to 10 nm, the third doping layer 42 is a phosphorus-doped amorphous silicon layer or microcrystalline silicon layer with a thickness of 15 nm to 30 nm, the doping type is the same as that of the silicon wafer 10, and the doping concentration is 1E17 cm -3 ~1E22 cm -3 .

[0122] In other embodiments, only the second passivation layer 41 may be deposited on the first surface S1 of the silicon wafer without depositing the third doping layer 42.

[0123] 6. Refer Figure 2f As shown, continue to deposit an antireflection layer 43 on the first surface S1 of the silicon wafer by a tube PECVD or PVD device at a low temperature.

[0124] Exemplarily, the anti-reflection layer 43 in this embodiment is a SiNx layer, and in other embodiments, it can also be a TCO layer or the like.

[0125] 7. Refer Figure 2g As shown, the first passivation layer 21 and the first doping layer 22 on part of the second region S22 are removed by a laser process to form an electrode window 23.

[0126] In this step of the laser process, the laser wavelength is 380 nm to 450 nm, the pulse width is 10 ns to 50 ns, the power is 5 W to 20 W, the duty cycle is 30% to 80%, and the scribing speed is 15 m / s to 25 m / s. The laser processing depth (i.e., the first passivation layer 21 and the first doping layer 22) is controlled by the above process parameters, and at least processed to the surface of the second doping layer 32 to ensure that the second doping layer 32 below the electrode window 23 is exposed.

[0127] 8. Refer Figure 2h As shown, in a PVD (Physical Vapor Deposition) apparatus, a TCO layer 50 is prepared in the first doping layer 22 and the electrode window 23.

[0128] 9. Refer Figure 2i As shown, part of the TCO layer on the first region S21 and / or the second region S22 is removed by a laser process to form an electrically isolated first TCO layer 51 and a second TCO layer 52 in the first doping layer and the electrode window. The first TCO layer 51 and the second TCO layer 52 are electrically isolated by an isolation groove 70 formed by the laser process.

[0129] In this step of the laser process, the laser wavelength is 380 nm to 570 nm, the pulse width is 10 ns to 50 ns, the power is 5 W to 20 W, the duty cycle is 30% to 80%, and the scribing speed is 15 m / s to 25 m / s. The laser processing depth (i.e., the thickness of the TCO layer) is controlled by the above process parameters to ensure that the depth of the isolation groove is greater than or equal to the thickness of the TCO layer.

[0130] 10. Refer Figure 2j As shown, a first electrode 61 electrically contacting the first TCO layer is prepared on the first TCO layer 51, and a second electrode 62 electrically contacting the second TCO layer is prepared on the second TCO layer 52.

[0131] Preferably, the metal electrode (the first electrode 61 or the second electrode 62) is prepared by screen printing using a conductive paste. The conductive paste uses a low-temperature silver paste or a silver-copper paste, and the curing temperature is 190 °C to 220 °C.

[0132] In addition, the antireflection layer in this embodiment includes one or a combination of a TCO layer, a SiNx layer, and a SiNxOy layer. If the antireflection layer uses a TCO layer, the preparation of this layer can be carried out in the same process as the preparation of the back TCO layer; if the antireflection layer uses a SiNx layer or a SiNxOy layer, an additional process is required, but the antireflection effect of the SiNx layer or the SiNxOy layer is better than that of the TCO layer.

[0133] As can be seen from the above technical solutions, the present invention has the following beneficial effects:

[0134] For the first region and the second region on the back of the HTBC battery of the present invention, the passivation structures in the HJT battery and the TOPCon battery are respectively adopted, and the passivation effect is good, which can significantly improve the photoelectric conversion efficiency; and the preparation process of this battery is simple, the process steps are few, and the equipment cost is low.

[0135] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed rights.

[0136] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A hybrid passivated back contact battery, characterized in that, The battery includes: A silicon wafer, including a first surface and a second surface arranged opposite to each other. The second surface includes a first region and a second region, and the area of the first region is larger than that of the second region; A heterostructure, including at least a first passivation layer and a first doping layer stacked on the first region; A first electrode structure, located on the first doping layer in the heterostructure; A first passivation structure, including a tunneling oxide layer and a second doping layer stacked on the second region; A second electrode structure, located on the second doping layer in the first passivation structure. The first electrode structure and the second electrode structure are electrically isolated by an isolation groove; A second passivation structure, located on the first surface of the silicon wafer.

2. The hybrid passivated back contact battery according to claim 1, characterized in that, The area of the first region is 70% - 95% of the area of the second surface; or, The area of the first region is 80% - 85% of the area of the second surface.

3. The hybrid passivated back contact battery according to claim 1, characterized in that, The silicon wafer is a doped silicon wafer. The doping type of the first doping layer is opposite to that of the silicon wafer, and the doping type of the second doping layer is the same as that of the silicon wafer.

4. The hybrid passivated back contact battery according to claim 1, characterized in that, The first passivation layer is an intrinsic amorphous silicon layer; and / or, The tunneling oxide layer is any one or a combination of a silicon oxide layer and a silicon oxynitride layer; and / or, The first doping layer is an amorphous silicon layer or a microcrystalline silicon layer; and / or, The second doping layer is a polycrystalline silicon layer; and / or, The thickness of the first passivation layer is 5nm - 10nm; and / or, The thickness of the tunneling oxide layer is 1nm - 2nm; and / or, The thickness of the first doping layer is 20nm - 40nm; and / or, The thickness of the second doping layer is 60nm - 300nm; and / or, The doping concentration of the first doping layer is 1E17 cm -3 ~1E20 cm -3 ; and / or, The doping concentration of the second doping layer is 1E20 cm -3 ~1E22 cm -3 .

5. The hybrid passivated back contact battery according to claim 1, characterized in that, The second passivation structure includes a second passivation layer and an antireflection layer stacked on the first surface. Among them, the second passivation layer is an intrinsic amorphous silicon layer, and the antireflection layer includes a combination of one or more of a SiNx layer, a SiNxOy layer, and a TCO layer.

6. The hybrid passivated back contact battery according to claim 5, characterized in that, The second passivation structure further includes a third doping layer located between the second passivation layer and the antireflection layer. The doping type of the third doping layer is the same as that of the silicon wafer.

7. The hybrid passivated back contact battery according to claim 6, characterized in that, The third doping layer is an amorphous silicon layer or a microcrystalline silicon layer; and / or, The thickness of the third doping layer is 15nm - 30nm; and / or, The doping concentration of the third doping layer is 1E17 cm -3 ~1E22 cm -3 .

8. The hybrid passivated back contact battery according to claim 1, characterized in that, The first passivation layer and the first doping layer are stacked on the entire first region and on the first passivation structure of a part of the second region. An electrode window that is not covered by the first passivation layer and the first doping layer is formed on the second doping layer.

9. The hybrid passivated back contact battery according to claim 8, characterized in that, The first electrode structure includes a first TCO layer and a first electrode. The first TCO layer is at least located on the first doping layer of the first region, and the first electrode is in electrical contact with the first TCO layer; The second electrode structure includes a second TCO layer and a second electrode. The second TCO layer is at least located in the electrode window on the second region, and the second electrode is in electrical contact with the second TCO layer; Among them, the first TCO layer and the second TCO layer are electrically isolated by an isolation groove.

10. The hybrid passivated back contact cell according to claim 9, characterized in that, The isolation groove is located on the first region and / or the second region, and the isolation groove extends at least to the surface of the first doping layer.

11. The hybrid passivated back contact cell according to claim 1, characterized in that, The first surface is a pyramidal texture surface or a polished surface; and / or, The first region is a pyramidal-textured or polished surface; and / or, The second region is a pyramidal-textured or polished surface.

12. A method for preparing a hybrid passivated back contact cell, characterized in that, The preparation method includes the following steps: Provide a silicon wafer including a first surface and a second surface disposed opposite to each other. The second surface includes a first region and a second region, and the area of the first region is larger than that of the second region; Deposit a tunneling oxide layer, a second doping layer, and a first mask on the second surface in sequence; Perform patterning and opening of the first mask on the first region through a laser process, and remove the tunneling oxide layer and the second doping layer on the first region; Remove the first mask on the second surface of the silicon wafer; Deposit a first passivation layer and a first doping layer on the second surface of the silicon wafer in sequence; Form a second passivation structure on the first surface of the silicon wafer; Remove part of the first passivation layer and the first doping layer on the second region through a laser process to form an electrode window; Prepare a first electrode structure on the first doping layer and prepare a second electrode structure in the electrode window on the second doping layer.

13. The preparation method according to claim 12, characterized in that, In the laser process of performing patterning and opening on the first mask, the laser wavelength is 495 nm to 570 nm, the pulse width is 10 ns to 50 ns, the power is 5 W to 30 W, the duty cycle is 30% to 80%, and the scribing speed is 15 m / s to 25 m / s; and / or, In the laser process of removing the first passivation layer and the first doping layer, the laser wavelength is 380 nm to 450 nm, the pulse width is 10 ns to 50 ns, the power is 5 W to 20 W, the duty cycle is 30% to 80%, and the scribing speed is 15 m / s to 25 m / s.

14. The preparation method according to claim 12, characterized in that, The preparation of the first electrode structure and the second electrode structure includes: Prepare a TCO layer in the first doping layer and the electrode window; Remove part of the TCO layer on the first region and / or the second region through a laser process to form electrically isolated first and second TCO layers in the first doping layer and the electrode window; Prepare a first electrode in electrical contact with the first TCO layer on the first TCO layer and prepare a second electrode in electrical contact with the second TCO layer on the second TCO layer.

15. The preparation method according to claim 14, characterized in that, In the laser process of removing part of the TCO layer, the laser wavelength is 380 nm to 570 nm, the pulse width is 10 ns to 50 ns, the power is 5 W to 20 W, the duty cycle is 30% to 80%, and the scribing speed is 15 m / s to 25 m / s.

16. The preparation method according to claim 12, characterized in that, After removing the tunneling oxide layer and the second doping layer on the first region, it further includes: Treat the first region in the first surface and / or the second surface through an alkaline texturing process to form a pyramidal-textured structure.

17. The preparation method according to claim 12, characterized in that, Forming the second passivation structure on the first surface of the silicon wafer includes: Deposit a second passivation layer on the first surface of the silicon wafer. The second passivation layer is an intrinsic amorphous silicon layer; Deposit a third doping layer on the second passivation layer. The third doping layer is an amorphous silicon layer or a microcrystalline silicon layer; Deposit an antireflection layer on the third doping layer. The antireflection layer includes one or a combination of SiNx layer, SiNxOy layer, and TCO layer.

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