Display device

Abstract

A display device is disclosed. According to an embodiment of the present disclosure, the display device includes: a lower substrate including a rigid area and a flexible area; a light emitting element disposed in the rigid region above the lower substrate; a connection line disposed in the flexible area on the lower substrate and electrically connected to the light emitting element; and an encapsulation layer including a first encapsulation layer covering the light emitting element in the rigid region and a second encapsulation layer covering the connecting line in the flexible region. Accordingly, a stretchable connecting line of the display device may be protected from moisture and oxygen.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, for example but not limited to, a stretchable display device with stretchable lines having improved reliability. Background Art

[0002] With the true advent of the information age, the display field for visually expressing electrical information signals has rapidly developed. Accordingly, various display devices have been developed, which are thin, light in weight, and have excellent properties such as low power consumption. Examples of display devices may include liquid crystal display (LCD) devices, field emission display (FED) devices, organic light emitting display (OLED) devices, and the like.

[0003] The application range of display devices has diversified from monitors and televisions of computers to personal mobile devices, and research is being conducted on display devices having a wide display area and having a reduced volume and weight.

[0004] In addition, recently, display devices have been manufactured by forming display components, lines, etc. on a substrate made of a flexible plastic material and having flexibility. The display device is manufactured to be stretchable in a specific direction and capable of various shape changes, and thus has attracted attention as a next-generation display device.

[0005] The descriptions provided in the background art section should not be assumed to be prior art merely because they are mentioned in the background art section or are associated with the descriptions in the background art section. The descriptions in the background art section may include information describing one or more aspects of the subject technology, and the descriptions in this section do not limit the present invention. Summary of the Invention

[0006] The inventors have recognized that in the related art, the stretchable connection lines of display devices are vulnerable to damage by moisture and oxygen. Therefore, an object to be achieved by the present disclosure is to provide a display device capable of protecting the stretchable connection lines from moisture and oxygen.

[0007] Another object to be achieved by the present disclosure is to provide a display device capable of reducing or minimizing damage to the connection lines by protecting the stretchable connection lines from moisture and oxygen.

[0008] Still another object to be achieved by the present disclosure is to provide a display device in which a line encapsulation layer for encapsulating the connection lines is formed together with a light-emitting element and an encapsulation layer for sealing the light-emitting element.

[0009] Still another object to be achieved by the present disclosure is to provide a display device in which a lower substrate can be used as an encapsulation layer for the connection lines.

[0010] Another object to be achieved by the present disclosure is to provide a display device in which a fluorine-based residual film is formed on the front surface to minimize the penetration of moisture.

[0011] The object of the present disclosure is not limited to the above object, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

[0012] To achieve the above object, a display device is provided. The display device includes: a lower substrate including a rigid region and a flexible region; a light-emitting element disposed above the lower substrate in the rigid region; a connection line disposed on the lower substrate in the flexible region and electrically connected to the light-emitting element; and a packaging layer including a first packaging layer covering the light-emitting element in the rigid region and a second packaging layer covering the connection line in the flexible region.

[0013] Other details of the exemplary embodiments are included in the detailed description and the drawings.

[0014] According to the present disclosure, the stretchable connection line can be protected from moisture and oxygen.

[0015] According to the present disclosure, the stretchable connection line can be sealed and protected so that the connection line is not damaged by moisture, oxygen, etc.

[0016] According to the present disclosure, the line packaging layer for sealing the connection line can be easily formed by forming the line packaging layer together during the process of manufacturing some components of the pixel.

[0017] According to the present disclosure, the line packaging layer for sealing the connection line can be formed together with the light-emitting element and the packaging layer configured to seal the light-emitting element.

[0018] According to the present disclosure, the lower substrate is used as the packaging layer of the connection line, which can simplify the structure of the display device.

[0019] According to the present disclosure, a fluorine-based residual film is formed on the front surface of the lower substrate, which can delay the penetration of moisture into the light-emitting element, the connection line, etc.

[0020] The effects according to the present disclosure are not limited to the above-exemplified contents, and more various effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the drawings, in which:

[0022] Figure 1 is a top view of a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 2is an enlarged top view of a display area of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 3 is a cross-sectional view taken along line III-III' in Figure 2 ;

[0025] Figure 4 is a cross-sectional view for explaining a process of manufacturing a second encapsulation layer of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 5 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure;

[0027] Figure 6 is a cross-sectional view for explaining a process of manufacturing a second encapsulation layer of a display device according to another exemplary embodiment of the present disclosure;

[0028] Figure 7 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure;

[0029] Figure 8 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure;

[0030] Figure 9 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure;

[0031] Figure 10 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure;

[0032] Figure 11 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure; and

[0033] Figure 12 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure.

[0034] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. DETAILED DESCRIPTION

[0035] Advantages and features of the present disclosure and methods for achieving the advantages and features will become apparent by referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure content of the present disclosure and the scope of the present disclosure.

[0036] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, quantities, etc. of the elements shown in the drawings used to describe the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, like reference numerals generally denote like elements. In addition, in the following description of the present disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising", "having", "including", "containing", "constituting", "made of", "formed by", "composed of" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise expressly stated.

[0037] The dimensions including the size and thickness of each component shown in the drawings are shown for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown. However, it should be noted that the relative dimensions including the relative size, position, and thickness of the components shown in each of the drawings submitted here are part of the present disclosure.

[0038] Even if not explicitly stated, components are interpreted to include a normal error range.

[0039] When using terms such as "on", "above", "over", "under", "below", "beside", "beneath", "near", "close to", "adjacent to", "on the side of", "proximate to" to describe the positional relationship between two parts, one or more parts may be located between these two parts, unless such terms are used together with the terms "immediately" or "directly".

[0040] Spatially relative terms, such as "under", "below", "beneath", "lower", "above", "upper", etc., may be used herein to facilitate the description of the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of the elements during use or operation. For example, if the element in the figure is inverted, the element described as "under" or "below" other elements or features will be oriented "above" other elements or features. Thus, the exemplary term "below" may include both the below and above orientations. Similarly, the exemplary terms "above" or "over" may include both the "above" and "below" orientations.

[0041] When describing temporal relationships, terms such as "after", "subsequently", "next", "then", "before", etc. may include cases where any two events are not consecutive, unless terms such as "immediately", "exactly", or "directly" are explicitly used.

[0042] When an element or layer is disposed "on" another element or layer, another layer or element may be directly interposed on the other element or between the two elements or layers.

[0043] Although terms such as "first", "second", "A", "B", "a", and "b" are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Thus, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0044] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used herein. Each of these terms is not used to define the nature, order, or sequence of the corresponding component, but only to distinguish the corresponding component from other components. In the case where a certain structural element or layer is "connected", "coupled", "adhered", or "joined" to another structural element or layer, it is generally interpreted that the other structural element or layer may be "connected", "coupled", "adhered", or "joined" to the structural element or layer directly or indirectly.

[0045] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of the first element, the second element, and the third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0046] The term "device" used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of the display device may include light-emitting elements, etc. In addition, examples of the device may include a laptop computer, a television, a computer monitor, an automotive device, a wearable device, and an automotive equipment device, and complete product or final product sets of electronic devices (or equipment) or sets of devices (or equipment) respectively including light-emitting elements, etc., such as mobile electronic devices such as smartphones or electronic tablets, but the embodiments of the present disclosure are not limited thereto.

[0047] Throughout the specification, like reference numerals generally denote like elements.

[0048] For ease of description, the size and thickness of each component shown in the figures are illustrated, and the present disclosure is not limited to the size and thickness of the components shown.

[0049] The features of the various exemplary embodiments of the present disclosure may be attached to or combined with each other partially or completely, and may be interlocked and operated in various technical ways, and the exemplary embodiments may be executed independently of or in association with each other.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0051] In aspects of the present disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode may be used interchangeably. The source electrode may be the drain electrode, and the drain electrode may be the source electrode. In addition, the source electrode in any aspect of the present disclosure may be the drain electrode in another aspect of the present disclosure, and the drain electrode in any aspect of the present disclosure may be the source electrode in another aspect of the present disclosure.

[0052] The display device according to the exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0053] Figure 1 is a top view of a display device according to an exemplary embodiment of the present disclosure. Figure 2 is an enlarged top view of a display area of a display device according to an exemplary embodiment of the present disclosure. Figure 3 is along Figure 2 the cross-sectional view taken along line III-III' in Figure 4 is a cross-sectional view for explaining a process of manufacturing a second encapsulation layer of a display device according to an exemplary embodiment of the present disclosure.

[0054] First, the display device 100 according to an exemplary embodiment of the present disclosure is a display device 100 that can display an image even when bent or stretched. The display device 100 may also be referred to as a stretchable display device, a flexible display device, and an expandable display device. Compared with a general display device in the prior art, the display device 100 not only has high flexibility but also has stretchability. Therefore, a user can bend or stretch the display device 100, and the shape of the display device 100 can be freely changed according to the user's manipulation. For example, in a case where a user holds and pulls one end of the display device 100, the display device 100 can be stretched in the direction in which the user pulls the display device. Alternatively, in a case where the user sets the display device 100 on a non-flat outer surface, the display device 100 can be set to bend along the shape of the outer surface. In addition, when the force applied by the user is removed, the display device 100 can return to its original shape.

[0055] Refer together to Figures 1 to 3 , the lower substrate SUB is a lower substrate SUB configured to support and protect several constituent elements of the display device 100. The lower substrate SUB can support a pattern layer PTL on which pixels PX, a gate driver GD, and a power supply PS are formed. The lower substrate SUB can be a flexible substrate. In this case, flexibility can be interpreted in the same way as characteristics such as bendability, non-breakability, rollability, and foldability.

[0056] The lower substrate SUB can be made of a bendable or stretchable insulating material. For example, the lower substrate SUB can be made of a silicone rubber such as polydimethylsiloxane (PDMS) or an elastomer such as polyurethane (PU) and polytetrafluoroethylene (PTFE), and thus has flexibility. However, the material of the lower substrate SUB is presented only for illustrative purposes. The material of the lower substrate SUB is not limited thereto.

[0057] The lower substrate SUB can reversibly expand and contract. Therefore, the lower substrate SUB can also be referred to as a lower stretchable lower substrate SUB, an extendable lower substrate SUB, an expandable lower substrate SUB, a stretchable lower substrate SUB, a flexible lower substrate SUB, etc., but is not limited thereto.

[0058] The lower substrate SUB includes a display area AA that allows image display and a non-display area NA in which no image is displayed and that is configured to be near, partially, or completely around the display area AA. However, the display area AA and the non-display area NA can be mentioned when explaining the entire display device 100, rather than only when explaining the lower substrate SUB.

[0059] The display area AA is an area for displaying an image of the display device 100. A plurality of pixels PX are provided in the display area AA. In addition, each pixel PX may include a display element and various driving elements for operating the display element. For example, the display element may be an organic light-emitting diode including an anode, an organic layer, and a cathode, which is provided in each of the plurality of pixels PX, but is not limited thereto. The various driving elements may include at least one thin-film transistor (TFT) and at least one capacitor. However, the present disclosure is not limited thereto. For example, the number of thin-film transistors TFTs in the pixel circuit of the present disclosure may be two or more, and the number of capacitors may be one or more. For example, the pixel circuit of the present disclosure may be a 3T2C pixel circuit including three TFTs and two capacitors, a 5T1C pixel circuit including five TFTs and one capacitor, a 5T2C pixel circuit including five TFTs and two capacitors, or a 7T2C pixel circuit including seven TFTs and two capacitors, etc.

[0060] The active layer of the thin-film transistor TFT may be formed of a semiconductor material, such as an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor, but is not limited thereto.

[0061] The oxide semiconductor material may have an excellent effect of preventing leakage current and relatively low manufacturing cost. The oxide semiconductor may be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides. Specifically, the oxide semiconductor may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but is not limited thereto.

[0062] The polycrystalline semiconductor material has fast moving speeds of carriers such as electrons and holes, and thus has high mobility, low power consumption, and excellent reliability. The polycrystalline semiconductor may be made of polycrystalline silicon (poly-Si), but is not limited thereto.

[0063] The amorphous semiconductor material may be made of amorphous silicon (a-Si), but is not limited thereto.

[0064] The plurality of pixels PX may each be connected to various lines and operate. For example, the plurality of pixels PX may each be connected to various lines, such as a gate line, a data line, a high-potential voltage line, a low-potential voltage line, a reference voltage line, and an initialization voltage line, but is not limited thereto.

[0065] The non-display area NA is an area where an image is not displayed. The non-display area NA may be an area adjacent to the display area AA. Further, the non-display area NA may be an area that is adjacent to and configured to surround the display area AA. However, the present disclosure is not limited thereto. The non-display area NA may be an area of the lower substrate SUB that does not include the display area AA. The non-display area NA may be modified and divided into various shapes. Components for operating a plurality of pixels PX provided in the display area AA (e.g., the gate driver GD and the power supply PS) may be provided in the non-display area NA. In addition, a plurality of pads connected to the data driver DD and the printed circuit board PCB may be provided in the non-display area NA. The pads may be respectively connected to the plurality of pixels PX in the display area AA.

[0066] The pattern layer PTL is provided on the lower substrate SUB. The pattern layer PTL includes a plurality of first plate patterns PP1 and a plurality of first line patterns LP1 provided in the display area AA and a plurality of second plate patterns PP2 and a plurality of second line patterns LP2 provided in the non-display area NA.

[0067] A plurality of plate patterns PP are provided in the display area AA and the non-display area NA. The plurality of plate patterns PP include a plurality of first plate patterns PP1 and a plurality of second plate patterns PP2. The plurality of first plate patterns PP1 are provided in the display area AA of the lower substrate SUB, and the plurality of second plate patterns PP2 are provided in the non-display area NA of the lower substrate SUB. A plurality of pixels PX may be formed on the plurality of first plate patterns PP1, and the gate driver GD and the power supply PS may be formed on the plurality of second plate patterns PP2.

[0068] The plurality of first plate patterns PP1 and the plurality of second plate patterns PP2 may be provided as island shapes spaced apart from each other. The plurality of first plate patterns PP1 and the plurality of second plate patterns PP2 may be individually separated. Therefore, the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2 may be referred to as the first island patterns and the second island patterns or the first individual patterns and the second individual patterns.

[0069] Reference Figure 1 , the size of each of the plurality of second plate patterns PP2 may be larger than the size of each of the plurality of first plate patterns PP1. One stage of the gate driver GD may be provided on each of the plurality of second plate patterns PP2. Therefore, the area occupied by various circuit components constituting one stage of the gate driver GD is relatively larger than the area occupied by one pixel PX, such that the size of each of the plurality of second plate patterns PP2 may be larger than the size of each of the plurality of first plate patterns PP1.

[0070] In addition, Figure 1It is shown that a plurality of second plate patterns PP2 are disposed in non-display regions NA provided at opposite sides of a display region AA based on a first direction X. For example, some of the plurality of second plate patterns PP2 are disposed in the non-display region NA below the display region AA in the first direction X, while other second plate patterns PP2 of the plurality of second plate patterns PP2 are disposed in the non-display region NA above the display region AA in the first direction X. However, this is provided for illustrative purposes only. The plurality of second plate patterns PP2 may be disposed in any region of the non-display region NA. For example, some of the plurality of second plate patterns PP2 are disposed in the non-display region NA to the left of the display region AA in a second direction Y, while other second plate patterns PP2 of the plurality of second plate patterns PP2 are disposed in the non-display region NA to the right of the display region AA in the second direction Y, but is not limited thereto. In addition, the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2 are shown as each having a quadrilateral shape. However, the present disclosure is not limited thereto. The plurality of first plate patterns PP1 and the plurality of second plate patterns PP2 may be modified into various shapes.

[0071] Referring to Figure 1 and Figure 2 , a plurality of line patterns LP are disposed in the display region AA and the non-display region NA. The plurality of line patterns LP include a plurality of first line patterns LP1 and a plurality of second line patterns LP2. The plurality of first line patterns LP1 are disposed in the display region AA. The plurality of first line patterns LP1 may be patterns configured to connect adjacent first plate patterns PP1 and are also referred to as internal connection patterns. That is, the plurality of first line patterns LP1 may be disposed between the plurality of first plate patterns PP1.

[0072] The plurality of second line patterns LP2 of the pattern layer PTL are disposed in the non-display region NA. The plurality of second line patterns LP2 may be patterns configured to connect adjacent first plate patterns PP1 and second plate patterns PP2 to each other or connect adjacent second plate patterns PP2 to each other and are also referred to as external connection patterns. The plurality of second line patterns LP2 may be disposed between adjacent first plate patterns PP1 and second plate patterns PP2 and between adjacent second plate patterns PP2.

[0073] The plurality of first line patterns LP1 and the plurality of second line patterns LP2 each have a curved shape. For example, the plurality of first line patterns LP1 and the plurality of second line patterns LP2 may each have a sinusoidal shape. However, the shapes of the plurality of first line patterns LP1 and the plurality of second line patterns LP2 are not limited thereto. For example, the plurality of first line patterns LP1 and the plurality of second line patterns LP2 may each extend in a zigzag shape. Alternatively, the plurality of first line patterns LP1 and the plurality of second line patterns LP2 may have various shapes, such as a shape in which a plurality of rhombic substrates are connected at vertices or a shape in which a semicircular substrate and a quarter-circular substrate are connected to each other. In addition, the shapes of the plurality of first line patterns LP1 and the plurality of second line patterns LP2 may be the same as or different from each other. For example, each of the plurality of first line patterns LP1 may have a sinusoidal shape, while each of the plurality of second line patterns LP2 may extend in a zigzag shape, but is not limited thereto. In addition, Figure 1 The number and shapes of the plurality of first line patterns LP1 and the plurality of second line patterns LP2 shown are examples. The plurality of first line patterns LP1 and the plurality of second line patterns LP2 may be variously changed in number and shape according to the design.

[0074] In addition, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 are each rigid patterns. That is, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may be more rigid than the lower substrate SUB.

[0075] The plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2, which serve as the rigid substrate, may each be made of a plastic material having a lower flexibility than the flexibility of the lower substrate SUB. For example, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may each be made of at least one of polyimide (PI), polyacrylate, and polyacetate. In this case, when the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 are made of the same material, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may be integrated. However, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may be made of different materials. However, the present disclosure is not limited thereto. For example, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may all be formed of different materials; alternatively, the plurality of first plate patterns PP1 and the plurality of first line patterns LP1 may be formed of the same material, while the plurality of second plate patterns PP2 and the plurality of second line patterns LP2 may be formed of the same material, but the present disclosure is not limited thereto.

[0076] The plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may each have a modulus of elasticity higher than that of the lower substrate SUB. The modulus of elasticity (modulus of elasticity) is a parameter representing the ratio of the lower substrate SUB deformed due to the stress applied to the lower substrate SUB. As the modulus of elasticity increases relatively, the hardness may increase relatively. Therefore, the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may be referred to as the plurality of first rigid patterns, the plurality of second rigid patterns, the plurality of third rigid patterns, and the plurality of fourth rigid patterns, respectively. The plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may each have a modulus of elasticity that may be 1000 times or more higher than the modulus of elasticity of the lower substrate SUB. For example, the modulus of elasticity of the plurality of first plate patterns PP1, the plurality of first line patterns LP1, the plurality of second plate patterns PP2, and the plurality of second line patterns LP2 may be 1500 times higher than the modulus of elasticity of the lower substrate SUB. However, the present disclosure is not limited thereto.

[0077] In addition, in some exemplary embodiments, the lower substrate SUB may be defined to include a plurality of rigid regions RA and a plurality of flexible regions SA. The plurality of rigid regions RA may be regions of the lower substrate SUB that overlap with the pattern layer PTL. The flexible regions SA may be regions that do not overlap with the pattern layer PTL. The pattern layer PTL is disposed in the plurality of rigid regions RA, and the pattern layer PTL is not disposed in the flexible regions SA, such that the plurality of rigid regions RA may be more rigid than the flexible regions SA. In this case, the flexible regions SA and the plurality of rigid regions RA may be mentioned when explaining the entire display device 100, rather than only when explaining the lower substrate SUB.

[0078] The gate driver GD may be mounted on the plurality of second plate patterns PP2. When manufacturing various components on the plurality of first plate patterns PP1, the gate driver GD may be formed on the plurality of second plate patterns PP2 in a gate-in-panel (GIP) manner. Accordingly, various circuit components (e.g., transistors, capacitors, lines, etc.) constituting the gate driver GD may be disposed on the plurality of second plate patterns PP2. A stage of a circuit constituting the gate driver GD and including transistors, capacitors, etc. may be disposed on the upper portion of each of the plurality of second plate patterns PP2. Alternatively, the gate driver GD may be mounted in a chip-on-film (COF) manner. However, the present disclosure is not limited thereto.

[0079] The power supply PS is disposed on the plurality of second plate patterns PP2. The power supply PS may be formed on a second plate pattern PP2 adjacent to the gate driver GD. The power supply PS formed on the second plate pattern PP2 may be provided as a plurality of power blocks that are patterned when manufacturing various components on the first plate pattern PP1. The power supply PS may be electrically connected to the gate driver GD in the non-display region NA and the plurality of pixels PX in the display region AA, and supply a driving voltage. Specifically, the power supply PS may be electrically connected to the gate driver GD formed on the second plate pattern PP2 and the plurality of pixels PX formed on the first plate pattern PP1 through the second line pattern LP2 and the first line pattern LP1. For example, the power supply PS may supply a gate driving voltage and a clock signal to the gate driver GD. In addition, the power supply PS may supply a power voltage to each of the plurality of pixels PX.

[0080] The printed circuit board PCB is connected to the edge of the lower substrate SUB. The printed circuit board PCB refers to a component that transmits signals and voltages for operating display elements from a controller to the display elements. Therefore, the printed circuit board PCB can be referred to as a driving substrate. Controllers such as IC chips and circuit components can be mounted on the printed circuit board PCB. In addition, a memory, a processor, etc. can be mounted on the printed circuit board PCB. In addition, the printed circuit board PCB provided in the display device 100 can include a stretchable area and a non-stretchable area to ensure stretchability. In addition, IC chips, circuit components, a memory, a processor, etc. can be mounted in the non-stretchable area. Wires electrically connected to the IC chips, circuit components, memory, and processor can be provided in the stretchable area.

[0081] The data driver DD is a component configured to supply data voltages to a plurality of pixels PX provided in the display area AA. The data driver DD can be configured in the form of an IC chip and is thus referred to as a data integrated circuit (D-IC). In addition, the data driver DD can be mounted in the non-stretchable area of the printed circuit board PCB. That is, the data driver DD can be mounted on the printed circuit board PCB in a chip-on-board (COB) manner. Figure 1 It is shown that the data driver DD is mounted in a chip-on-board (COB) manner. However, the present disclosure is not limited thereto. The data driver DD can be mounted in a chip-on-film (COF) manner, a chip-on-glass (COG) manner, a tape carrier package (TCP) manner, etc.

[0082] In addition, Figure 1 It is shown that a single data driver DD is provided corresponding to each of a plurality of columns in which a plurality of first plate patterns PP1 are provided in the display area AA. However, the present disclosure is not limited thereto. For example, a single data driver DD can be provided corresponding to a plurality of columns in which a plurality of first plate patterns PP1 are provided. Alternatively, two or more data drivers DD can be provided corresponding to the plurality of columns formed by the plurality of first plate patterns PP1. In addition, two or more data drivers DD can be provided on one side or both sides of the display area AA, but are not limited thereto.

[0083] Referring to Figure 1 and Figure 2 , the plurality of first plate patterns PP1 are spaced apart from each other and provided in the display area AA of the lower substrate SUB. For example, as Figure 1As shown, a plurality of first plate patterns PP1 may be arranged in a matrix shape on the lower substrate SUB. However, the present disclosure is not limited thereto. In addition, a plurality of first line patterns LP1 may connect the plurality of first plate patterns PP1. Some of the plurality of first line patterns LP1 may connect the plurality of first plate patterns PP1 adjacent to each other in the first direction X, and some of the remaining first line patterns LP1 may connect the plurality of first plate patterns PP1 adjacent to each other in the second direction Y.

[0084] Referring to Figure 2 and Figure 3 , a pixel PX including a plurality of sub-pixels SPX is disposed on each of the plurality of first plate patterns PP1, and the plurality of sub-pixels SPX are individual units configured to emit light. Each of the plurality of sub-pixels SPX may include a light-emitting element LD as a display element and a pixel circuit (e.g., a driving transistor and a switching transistor) configured to operate the light-emitting element LD. The light-emitting element LD may be configured as an inorganic light-emitting diode or an organic light-emitting diode such as a micro LED (light-emitting diode) or a quantum dot light-emitting diode. In addition, the light-emitting element LD may be a light-emitting element LD configured by combining an organic material and an inorganic material. In addition, each of the plurality of pixels PX may include a single light-emitting element LD. In another exemplary embodiment, each of the plurality of pixels PX may include a plurality of light-emitting elements LD, and the plurality of light-emitting elements LD may be connected in series, in parallel, or both in series and in parallel. The display device 100 may display an image by operating the plurality of pixels PX in response to input image data.

[0085] In addition, the plurality of sub-pixels SPX are the smallest units constituting the display area, and n sub-pixels SPX form one pixel. Each of the plurality of sub-pixels SPX may emit light having different wavelengths from each other. The plurality of sub-pixels may include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors from each other. For example, the plurality of sub-pixels SPX may include a red sub-pixel SPX, a green sub-pixel SPX, and a blue sub-pixel SPX. According to this exemplary embodiment, at least some of the plurality of pixels PX may further include a white sub-pixel SPX. The plurality of sub-pixels SPX may be variously modified in color and configuration as needed. However, the present disclosure is not limited thereto.

[0086] For example, the plurality of sub-pixels SPX may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, wherein the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be arranged in a repeating manner. Alternatively, the plurality of sub-pixels SPX may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, wherein the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a repeating manner, or the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a quadrilateral type. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel may be sequentially arranged along the row direction, or the red sub-pixel, the blue sub-pixel, the green sub-pixel, and the white sub-pixel may be sequentially arranged along the row direction. However, in the embodiments of the present disclosure, the color type, the arrangement type, and the arrangement order of the sub-pixels are not limited and may be configured in various forms according to the light-emitting characteristics, the device lifetime, and the device specifications.

[0087] In addition, according to the light-emitting characteristics, the sub-pixels may have different light-emitting areas. For example, a sub-pixel that emits light of a color different from that of the blue sub-pixel may have a light-emitting area different from that of the blue sub-pixel. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel or the red sub-pixel, the blue sub-pixel, the white sub-pixel, and the green sub-pixel may each have a different light-emitting area.

[0088] A plurality of connection lines CL are provided on the plurality of line patterns LP. The plurality of connection lines CL may be lines configured to electrically connect the pads of the plurality of first plate patterns PP1 and the pads of the plurality of second plate patterns PP2. The plurality of connection lines CL are provided between the plurality of first plate patterns PP1, between the plurality of second plate patterns PP2, and between the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2. The plurality of connection lines CL may electrically connect the pads on the plurality of first plate patterns PP1, electrically connect the pads on the plurality of second plate patterns PP2, and electrically connect the pads on the plurality of first plate patterns PP1 and the pads on the plurality of second plate patterns PP2.

[0089] A plurality of connection lines CL include a first connection line CL1 and a second connection line CL2. The first connection line CL1 is a line that extends in a first direction X between a plurality of first plate patterns PP1, between a plurality of second plate patterns PP2, and between the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2. The second connection line CL2 is a line that extends in a second direction Y between a plurality of first plate patterns PP1, between a plurality of second plate patterns PP2, and between the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2. The plurality of connection lines CL may each have a shape corresponding to a line pattern LP. For example, the connection line CL may have a curved shape. For example, the plurality of connection lines CL may each have a sinusoidal shape, but is not limited thereto. For example, the first connection line CL1 and the second connection line CL2 may have the same shape or different shapes. For example, when any one of the plurality of first line patterns LP1 and the plurality of second line patterns LP2 has a sinusoidal shape, extends in a zigzag shape, has a shape in which a plurality of diamond substrates are connected at vertices and extend, or has a shape in which a semicircular substrate and a quarter-circular substrate are connected to each other, each of the first connection line CL1 and the second connection line CL2 has a shape corresponding to the plurality of first line patterns LP1 and / or the plurality of second line patterns LP2. For example, each of the first connection line CL1 and the second connection line CL2 has a sinusoidal shape, extends in a zigzag shape, has a shape in which a plurality of diamond substrates are connected at vertices and extend, or has a shape in which a semicircular substrate and a quarter-circular substrate are connected to each other.

[0090] The plurality of connection lines CL may each be configured as a laminated structure made of a metal material such as copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or a metal material such as copper / molybdenum-titanium (Cu / Mo-Ti) or titanium / aluminum / titanium (Ti / Al / Ti). However, the present disclosure is not limited thereto.

[0091] In addition, in the case of a general display device, various lines such as a plurality of gate lines and a plurality of data lines are provided between a plurality of sub-pixels and extend linearly. The plurality of sub-pixels are connected to a single signal line. Therefore, in the case of a general display device, various lines such as gate lines, data lines, high-potential voltage lines, and reference voltage lines extend in a direction from one side to the other side of the substrate without interruption.

[0092] In contrast, in the case of the display device 100 according to an exemplary embodiment of the present disclosure, various lines such as gate lines, data lines, high-potential voltage lines, reference voltage lines, and initialization voltage lines are provided only on the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2, and these lines can be regarded as straight lines for a general display device. That is, in the display device 100 according to an exemplary embodiment of the present disclosure, straight lines may be provided only on the plurality of first plate patterns PP1 and the plurality of second plate patterns PP2.

[0093] In the display device 100 according to an exemplary embodiment of the present disclosure, pads on two adjacent first plate patterns PP1 may be connected by a connection line CL. Accordingly, the connection line CL electrically connects the pads on two adjacent first plate patterns PP1. Thus, the display device 100 according to the exemplary embodiment of the present disclosure may include a plurality of connection lines CL to electrically connect various lines such as gate lines, data lines, high-potential voltage lines, and reference voltage lines between a plurality of first plate patterns PP1. For example, gate lines may be provided on a plurality of first plate patterns PP1 arranged adjacent to each other in the first direction X, and gate pads may be provided at opposite ends of the gate lines. In this case, a plurality of gate pads on a plurality of first plate patterns PP1 arranged adjacent to each other in the first direction X may be connected to each other by a first connection line CL1 serving as a gate line. Accordingly, the gate lines provided on the plurality of first plate patterns PP1 and the first connection line CL1 provided on the first line pattern LP1 may serve as a single gate line. In addition, among all the various lines that may be included in the display device 100, lines extending in the first direction X, such as light-emitting signal lines, low-potential voltage lines, and high-potential voltage lines, may also be electrically connected by the first connection line CL1 as described above. For example, the light-emitting signal lines provided on the plurality of first plate patterns PP1 and the first connection line CL1 provided on the first line pattern LP1 may serve as a single light-emitting signal line; for example, the low-potential voltage lines provided on the plurality of first plate patterns PP1 and the first connection line CL1 provided on the first line pattern LP1 may serve as a single low-potential voltage line; for example, the high-potential voltage lines provided on the plurality of first plate patterns PP1 and the first connection line CL1 provided on the first line pattern LP1 may serve as a single high-potential voltage line, however, the present disclosure is not limited thereto.

[0094] Among a plurality of second connection lines CL2, some of the second connection lines CL2 may be connected to pads on a plurality of first plate patterns PP1 arranged adjacent to each other in the second direction Y. Internal lines on the plurality of first plate patterns PP1 arranged in the second direction Y may be connected through the plurality of second connection lines CL2 serving as data lines, such that a single data voltage can be transmitted. For example, a data line provided on the plurality of first plate patterns PP1 and the second connection lines CL2 provided on the first line pattern LP1 may serve as one data line. Alternatively, the plurality of second connection lines CL2 may serve as data lines, high potential voltage lines, low potential voltage lines, or reference voltage lines. However, the present disclosure is not limited thereto. For example, a high potential voltage line provided on the plurality of first plate patterns PP1 and the second connection lines CL2 provided on the first line pattern LP1 may serve as one high potential voltage line; for example, a low potential voltage line provided on the plurality of first plate patterns PP1 and the second connection lines CL2 provided on the first line pattern LP1 may serve as one low potential voltage line; for example, a reference voltage line provided on the plurality of first plate patterns PP1 and the second connection lines CL2 provided on the first line pattern LP1 may serve as one reference voltage line, however, the present disclosure is not limited thereto.

[0095] Next, a cross-sectional structure of the display area AA will be described with reference to Figure 3 in detail.

[0096] Referring to Figure 3 , a first shielding pattern BSM is provided on the lower substrate SUB and the first plate pattern PP1. The first shielding pattern BSM may be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and alloys thereof. According to an exemplary embodiment, the first shielding pattern BSM may be defined as a component element of the first transistor TR1. For example, the first shielding pattern BSM may serve as a lower gate electrode of the first transistor TR1.

[0097] The first buffer layer BUF1 is disposed on the first shielding pattern BSM and the first plate pattern PP1. The first buffer layer BUF1 may be formed on a plurality of first plate patterns PP1 to cover the first shielding pattern BSM and protect various constituent elements of the display device 100 from the penetration of moisture and oxygen from the outside of the lower substrate SUB and the first plate pattern PP1. The first buffer layer BUF1 includes a multi-buffer layer BUF1a and an active buffer layer BUF1b. The first buffer layer BUF1 may be made of an insulating material. For example, the first buffer layer BUF1 may be configured as a single layer or multiple layers made of at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). For example, the first buffer layer BUF1 may be formed by a single layer or multiple layers of an inorganic film. For example, the single layer of the inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of the inorganic film may be formed by alternately stacking one or more layers of a silicon oxide (SiOx) film, one or more layers of a silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, depending on the structure or characteristics of the display device 100, the first buffer layer BUF1 may not be included.

[0098] The first transistor TR1 is disposed on the first buffer layer BUF1. The first transistor TR1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. According to an exemplary embodiment, the first transistor TR1 may further include a shielding metal pattern as a gate electrode.

[0099] The first active layer ACT1 is disposed on the first buffer layer BUF1. The first active layer ACT1 may include a source region connected to the first source electrode SE1, a drain region connected to the first drain electrode DE1, and a channel region between the source region and the drain region. The first active layer ACT1 may include a polysilicon semiconductor layer formed by a low-temperature polysilicon (LTPS) process, but the present disclosure is not limited thereto. A polycrystalline semiconductor material such as polysilicon (poly-Si) has a fast moving speed of carriers such as electrons and holes, and thus has a high mobility, and has low power consumption and excellent reliability.

[0100] The first gate insulating layer GI1 is disposed on the first active layer ACT1. The first gate insulating layer GI1 is an insulating layer for insulating the first active layer ACT1 and the first gate electrode GE1. The first gate insulating layer GI1 may be configured as a single layer or multiple layers made of silicon nitride (SiNx) or silicon oxide (SiOx). For example, the first gate insulating layer GI1 may be formed of a single layer or multiple layers of an inorganic film. For example, the single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of inorganic film may be formed by alternately laminating one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, the present disclosure is not limited thereto.

[0101] The first gate electrode GE1 is disposed on the first gate insulating layer GI1. The first gate electrode GE1 is disposed to overlap the first active layer ACT1, wherein the first gate insulating layer GI1 is interposed between the first gate electrode GE1 and the first active layer ACT1. The first gate electrode GE1 may be made of any one of various metal materials such as, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of two or more of these metal materials. Alternatively, the first gate electrode GE1 may be configured as multiple layers made of any one of various metal materials such as, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of two or more of these metal materials. However, the present disclosure is not limited thereto.

[0102] The first interlayer insulating layer ILD1 is disposed on the first gate electrode GE1, and the second interlayer insulating layer ILD2 is disposed on the first interlayer insulating layer ILD1. The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 are disposed to cover the first gate electrode GE1, the first conductive layer GAT1, and the second conductive layer TM1. The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may each be configured as a single layer or multiple layers made of silicon nitride (SiNx) or silicon oxide (SiOx). For example, each of the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may be formed of a single layer or multiple layers of an inorganic film. For example, the single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of inorganic film may be formed by alternately laminating one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, the present disclosure is not limited thereto.

[0103] The first source electrode SE1 and the first drain electrode DE1 are disposed on the second interlayer insulating layer ILD2. The first source electrode SE1 and the first drain electrode DE1 can be electrically connected to the first active layer ACT1 through contact holes formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the first gate insulating layer GI1. The first source electrode SE1 and the first drain electrode DE1 can each be made of any one of various metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of two or more of these metal materials. Alternatively, the first source electrode SE1 and the first drain electrode DE1 can each be configured as a multilayer made of various metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of two or more of these metal materials. However, the present disclosure is not limited thereto.

[0104] The first conductive layer GAT1 is disposed between the first gate insulating layer GI1 and the first interlayer insulating layer ILD1. The first conductive layer GAT1 can constitute at least a part of a light emission control line configured to provide a light emission control signal to the pixel PX, at least a part of a scan line configured to provide a scan signal, and at least a part of a power line configured to provide various types of power supply voltages. In this case, when the first conductive layer GAT1 constitutes at least a part of the power line configured to provide a power supply voltage, the first conductive layer GAT1 can be made of a material having high conductivity such as a metal or a conductive oxide. For example, the first conductive layer GAT1 can be configured to include a single layer or a multilayer of aluminum (Al), copper (Cu), titanium (Ti), etc. In some exemplary embodiments, the first conductive layer GAT1 can be provided as a three-layer structure in which titanium, aluminum, and titanium (Ti / Al / Ti) are sequentially provided. However, the configuration of the first conductive layer GAT1 is not limited thereto. The first conductive layer GAT1 can be configured as a single layer or a multilayer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys. In addition, the first gate electrode GE1 disposed on the same layer as the first conductive layer GAT1 can be configured as the first conductive layer GAT1 that constitutes at least a part of the scan line or the light emission control line of the first conductive layer GAT1.

[0105] The second conductive layer TM1 is disposed between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. The second conductive layer TM1 can be configured to include a single layer or a multilayer of molybdenum (Mo), copper (Cu), titanium (Ti), etc. The second conductive layer TM1 can be disposed to overlap with the first conductive layer GAT1 and serve as a kind of capacitor electrode.

[0106] A second buffer layer BUF2 is disposed on a second interlayer insulating layer ILD2. The second buffer layer BUF2 is arranged to cover a first source electrode SE1 and a first drain electrode DE1 of a first transistor TR1. The second buffer layer BUF2 may be configured as a single layer or multiple layers made of silicon nitride (SiNx) or silicon oxide (SiOx). For example, the second buffer layer BUF2 may be formed by a single layer or multiple layers of inorganic films. For example, the single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of inorganic films may be formed by alternately laminating one or more layers of silicon oxide (SiOx) films, one or more layers of silicon nitride (SiNx) films, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, the present disclosure is not limited thereto.

[0107] A second transistor TR2 is disposed on the second buffer layer BUF2. The second transistor TR2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0108] First, the second active layer ACT2 is disposed on the second buffer layer BUF2. The second active layer ACT2 may include a source region connected to the second source electrode SE2, a drain region connected to the second drain electrode DE2, and a channel region between the source region and the drain region. The second active layer ACT2 may include an oxide semiconductor layer. The oxide semiconductor material may have an excellent effect of preventing leakage current and a relatively low manufacturing cost. The oxide semiconductor may be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides. Specifically, the oxide semiconductor may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but is not limited thereto.

[0109] The second gate insulating layer GI2 is disposed on the second active layer ACT2. The second gate insulating layer GI2 is an insulating layer for insulating the second active layer ACT2 and the second gate electrode GE2. The second gate insulating layer GI2 may be configured as a single layer or multiple layers made of silicon nitride (SiNx) or silicon oxide (SiOx). For example, the second gate insulating layer GI2 may be formed of a single layer or multiple layers of an inorganic film. For example, the single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, the present disclosure is not limited thereto.

[0110] The second gate electrode GE2 is disposed on the second gate insulating layer GI2. The second gate electrode GE2 is disposed to overlap with the second active layer ACT2, where the second gate insulating layer GI2 is interposed between the second gate electrode GE2 and the second active layer ACT2. The second gate electrode GE2 may form at least a part of a scan line. The second gate electrode GE2 may be made of any one of various metal materials such as, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of two or more of these metal materials. Alternatively, the second gate electrode GE2 may be configured as multiple layers made of various metal materials such as, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of two or more of these metal materials. However, the present disclosure is not limited thereto.

[0111] The third interlayer insulating layer ILD3 is disposed on the second gate electrode GE2. The third interlayer insulating layer ILD3 is disposed to cover the second gate electrode GE2. The third interlayer insulating layer ILD3 may be configured as a single layer or multiple layers made of silicon nitride (SiNx) or silicon oxide (SiOx). For example, the third interlayer insulating layer ILD3 may be formed of a single layer or multiple layers of an inorganic film. For example, the single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, the present disclosure is not limited thereto.

[0112] The second source electrode SE2 and the second drain electrode DE2 are disposed on the third interlayer insulating layer ILD3. The second source electrode SE2 and the second drain electrode DE2 may be electrically connected to the second active layer ACT2 through contact holes formed in the third interlayer insulating layer ILD3 and the second gate insulating layer GI2. The second source electrode SE2 and the second drain electrode DE2 may each be made of any one of various metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of two or more of these metal materials. Alternatively, the second source electrode SE2 and the second drain electrode DE2 may each be configured as a multilayer made of various metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of two or more of these metal materials. However, the present disclosure is not limited thereto.

[0113] The third conductive layer SD1 is disposed on the third interlayer insulating layer ILD3. The third conductive layer SD1 may constitute at least a part of a power line configured to provide a power supply voltage. In this case, since the third conductive layer SD1 constitutes at least a part of a power line configured to provide a power supply voltage, the third conductive layer SD1 may be made of a material having high conductivity such as a metal or a conductive oxide. For example, the third conductive layer SD1 may be configured to include a single layer or a multilayer of aluminum (Al), copper (Cu), titanium (Ti), etc. In some exemplary embodiments, the third conductive layer SD1 may be provided as a three-layer of titanium, aluminum, and titanium (Ti / Al / Ti) arranged in sequence. However, the configuration of the third conductive layer SD1 is not limited thereto. The third conductive layer SD1 may be configured as a single layer or a multilayer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys.

[0114] In addition, at least a part of the third conductive layer SD1 can be used as a connection electrode. For example, at least a part of the third conductive layer SD1 can be connected to a conductive layer formed between the second buffer layer BUF2 and the second interlayer insulating layer ILD2 through a contact hole formed via the third interlayer insulating layer ILD3, the second gate insulating layer GI2, and the second buffer layer BUF2. Alternatively, at least a part of the third conductive layer SD1 can be connected to a conductive layer formed between the third interlayer insulating layer ILD3 and the second gate insulating layer GI2 through a contact hole formed via the third interlayer insulating layer ILD3. In addition, at least a part of the third conductive layer SD1 can be connected to another conductive layer provided on the third conductive layer SD1. In addition, at least a part of the third conductive layer SD1 can constitute the second source electrode SE2 and the second drain electrode DE2 of the second transistor TR2. However, the present disclosure is not limited thereto.

[0115] The first planarization layer PNL1 is provided on the third conductive layer SD1 and the second transistor TR2. The first planarization layer PNL1 is an insulating layer configured to planarize the upper portion of the first planarization layer PNL1 and protect other constituent elements provided below the first planarization layer PNL1. For example, the first planarization layer PNL1 can be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. However, the present disclosure is not limited thereto.

[0116] The fourth conductive layer SD2 is provided on the first planarization layer PNL1. The fourth conductive layer SD2 can constitute at least a part of a data line configured to supply a data signal to the pixel PX or at least a part of a power line configured to supply a high-potential power supply voltage. In this case, since the fourth conductive layer SD2 constitutes at least a part of the power line configured to supply the power supply voltage, the fourth conductive layer SD2 can be made of a material having high conductivity such as a metal or a conductive oxide. For example, the fourth conductive layer SD2 can be configured to include a single layer or multiple layers of aluminum (Al), copper (Cu), titanium (Ti), etc. In some exemplary embodiments, the fourth conductive layer SD2 can be provided as a three-layer structure in which titanium, aluminum, and titanium (Ti / Al / Ti) are sequentially provided. However, the fourth conductive layer SD2 is not limited thereto. The fourth conductive layer SD2 can be configured to be a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys. In addition, at least a part of the fourth conductive layer SD2 can be used as a connection electrode. For example, at least a part of the fourth conductive layer SD2 can be connected to at least a part of the third conductive layer SD1 through a contact hole formed via the first planarization layer PNL1.

[0117] The second planarization layer PNL2 is disposed on the fourth conductive layer SD2. The second planarization layer PNL2 is an insulating layer configured to planarize the upper portion of the second planarization layer PNL2 and protect other constituent elements disposed below the second planarization layer PNL2. For example, the second planarization layer PNL2 may be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. However, the present disclosure is not limited thereto.

[0118] The second shielding pattern SM is disposed on the second planarization layer PNL2. Signal interference may occur between the conductive layer below the second shielding pattern SM and the anode electrode AND of the light-emitting element LD disposed on the second shielding pattern SM. In this case, the voltage of the anode electrode AND may fluctuate, and the display quality may deteriorate. Therefore, the second shielding pattern SM may be disposed on the second planarization layer PNL2, overlapping the anode electrode AND, and blocking signals between the conductive layer below the second shielding pattern SM and the anode electrode AND on the second shielding pattern SM, which can stably maintain the voltage of the anode electrode AND and improve the display quality. The second shielding pattern SM may be configured as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys.

[0119] The fifth conductive layer SD3 is disposed on the second planarization layer PNL2. The fifth conductive layer SD3 may be connected to at least a portion of the fourth conductive layer SD2 through a contact hole formed through the second planarization layer PNL2. The fifth conductive layer SD3 may extend to side surfaces of a plurality of insulating layers disposed below the fifth conductive layer SD3 and be connected to a connection line CL disposed in the flexible region SA. For example, the fifth conductive layer SD3 may extend from a top surface of the second planarization layer PNL2 to side surfaces of the second planarization layer PNL2, the first planarization layer PNL1, the third interlayer insulating layer ILD3, the second gate insulating layer GI2, the second buffer layer BUF2, the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, the first gate insulating layer GI1, and the first buffer layer BUF1 and be connected to the connection line CL disposed on the first line pattern LP1. In addition, when the first buffer layer BUF1 includes a multi-buffer layer BUF1a and an active buffer layer BUF1b, the fifth conductive layer SD3 may extend from a top surface of the second planarization layer PNL2 to side surfaces of the second planarization layer PNL2, the first planarization layer PNL1, the third interlayer insulating layer ILD3, the second gate insulating layer GI2, the second buffer layer BUF2, the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, the first gate insulating layer GI1, the side surface of the active buffer layer BUF1b, and the side surface of the multi-buffer layer BUF1a and be connected to the connection line CL disposed on the first line pattern LP1. Accordingly, the fifth conductive layer SD3 may be a conductive layer configured to electrically connect various types of lines disposed on the first plate pattern PP1 and the plurality of connection lines CL. In addition, at least a portion of the fifth conductive layer SD3 may be used as the second shielding pattern SM. The fifth conductive layer SD3 may be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and alloys thereof.

[0120] The third planarization layer PNL3 is disposed on the fifth conductive layer SD3 and the second shielding pattern SM. The third planarization layer is an insulating layer configured to planarize an upper portion of the second planarization layer PNL2 and protect other constituent elements disposed below the second planarization layer PNL2. For example, the third planarization layer PNL3 may be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. However, the present disclosure is not limited thereto.

[0121] The light-emitting element LD is disposed on the third planarization layer PNL3. The light-emitting element LD includes an anode electrode AND, a light-emitting layer EML, and a cathode electrode CAD.

[0122] The anode electrode AND is disposed on the third planarization layer PNL3. For example, the anode electrode AND can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, the present disclosure is not limited thereto.

[0123] In addition, in the case where the display device 100 according to an exemplary embodiment of the present disclosure is a top-emitting type display device, the anode electrode AND may further include a reflective layer made of a metal material having excellent reflection efficiency, such as a material such as aluminum (Al) or silver (Ag), so that the light emitted from the light-emitting layer EML is reflected by the anode electrode AND and propagates in the upward direction, that is, toward the cathode electrode CAD. On the contrary, in the case where the display device 100 is a bottom-emitting type display device, the anode electrode AND can be made of only a transparent conductive material.

[0124] The bank BNK is disposed on the third planarization layer PNL3 and covers a part of the anode electrode AND. The bank BNK can be provided to cover a part of the edge of the anode electrode AND, and the part of the anode electrode AND exposed from the bank BNK can correspond to the light-emitting region. The bank BNK can be provided at the boundary between a plurality of sub-pixels SPX and suppress color mixing of light beams from the plurality of sub-pixels SPX. The bank BNK can include an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as a benzocyclobutene (BCB)-based resin, an acrylic resin, or a polyimide. For example, the bank BNK can be formed of a black resin. However, the present disclosure is not limited thereto.

[0125] The light-emitting layer EML is disposed on the bank BNK and the anode electrode AND. The light-emitting layer EML can be adjacent to the part of the anode electrode exposed from the bank BNK. The light-emitting layer EML can be disposed on the front surface of the rigid region RA where the first plate pattern PP1 is provided. The light-emitting layer EML can also include organic material layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0126] The cathode electrode CAD is disposed on the light-emitting layer EML. Similar to the light-emitting layer EML, the cathode electrode CAD can also be disposed on the front surface of the rigid region RA where the first plate pattern PP1 is provided. Since the cathode electrode CAD supplies electrons to the light-emitting layer EML, the cathode electrode CAD can be made of a conductive material having a low work function. For example, the cathode electrode CAD can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an alloy of ytterbium (Yb). The cathode electrode CAD can also include a metal doping layer. However, the present disclosure is not limited thereto.

[0127] The first encapsulation layer EC1 is disposed on the light-emitting element LD. The first encapsulation layer EC1 has a structure in which an inorganic encapsulation layer and an organic encapsulation layer are alternately stacked, so that the first encapsulation layer EC1 can protect the light-emitting element LD while suppressing the infiltration of moisture or oxygen into the light-emitting element LD. For example, the first encapsulation layer EC1 may have a multi-insulating film structure in which an organic film and an inorganic film are alternately stacked. The inorganic film can block the penetration of moisture or oxygen. The organic film can planarize the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture or oxygen can be longer than that of a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect the light-emitting layer EML. For example, the first encapsulation layer EC1 includes a first inorganic encapsulation layer PAS1, a first organic encapsulation layer PCL1, and a second inorganic encapsulation layer PAS2 stacked in sequence. For example, the first encapsulation layer EC1 includes a first inorganic encapsulation layer PAS1, a first organic encapsulation layer PCL1, a second inorganic encapsulation layer PAS2, a second organic encapsulation layer PCL2, and a third inorganic encapsulation layer PAS3 stacked in sequence. However, the present disclosure is not limited thereto.

[0128] The first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 can be used to block the penetration of moisture or oxygen. The first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 can be made of an inorganic material, such as an inorganic material such as silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlOx). However, the present disclosure is not limited thereto.

[0129] The first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 can each completely cover the upper and side surfaces of the components disposed in the rigid region RA. For example, the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 can cover the upper part of the light-emitting element LD disposed above the first plate pattern PP1. The first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 can be disposed between the light-emitting element LD and the first plate pattern PP1 and cover the exposed side surfaces of the plurality of insulating layers and the fifth conductive layer SD3 disposed on the side surfaces of the plurality of insulating layers. The first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 can extend to the boundary between the rigid region RA and the flexible region SA.

[0130] In addition, the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 may be adjacent to each other at the boundary between the rigid region RA and the flexible region SA and seal the first organic encapsulation layer PCL1 and the second organic encapsulation layer PCL2. For example, the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may be adjacent to each other on the outer peripheral portion of the rigid region RA while sealing the first organic encapsulation layer PCL1, and the second inorganic encapsulation layer PAS2 and the third inorganic encapsulation layer PAS3 may be adjacent to each other on the outer peripheral portion of the rigid region RA while sealing the second organic encapsulation layer PCL2.

[0131] The first organic encapsulation layer PCL1 is disposed between the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2, and the second organic encapsulation layer PCL2 is disposed between the second inorganic encapsulation layer PAS2 and the third inorganic encapsulation layer PAS3. The first organic encapsulation layer PCL1 and the second organic encapsulation layer PCL2 may each have a greater thickness than each of the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 in order to adsorb or block particles that may be generated during the manufacturing process of the display device 100. The first organic encapsulation layer PCL1 and the second organic encapsulation layer PCL2 may fill cracks that may form in the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2. The first organic encapsulation layer PCL1 and the second organic encapsulation layer PCL2 may flatten the upper portions of the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 by covering the particles on the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2, respectively. For example, the first organic encapsulation layer PCL1 may flatten the upper portion of the first inorganic encapsulation layer PAS1 by covering the particles on the first inorganic encapsulation layer PAS1. For example, the second organic encapsulation layer PCL2 may flatten the upper portion of the second inorganic encapsulation layer PAS2 by covering the particles on the second inorganic encapsulation layer PAS2. The first organic encapsulation layer PCL1 and the second organic encapsulation layer PCL2 may be made of an organic material, and for example, an epoxy polymer, an acrylic polymer, etc. may be used. However, the present disclosure is not limited thereto.

[0132] In addition, the first encapsulation layer EC1 is not limited to three layers or five layers. For example, it may include n layers in which inorganic encapsulation layers and organic encapsulation layers are alternately stacked (where n is an integer greater than 3).

[0133] Next, a second encapsulation layer EC2 is provided on the connection line CL in the flexible region SA. The second encapsulation layer EC2 can be provided to cover the connection line CL and protect the connection line CL so that the connection line CL is not oxidized and damaged by moisture, oxygen, etc. The second encapsulation layer EC2 can be made of a material different from that of the first encapsulation layer EC1. For example, the second encapsulation layer EC2 can be made of a material such as polyimide having insulation and flexibility. The second encapsulation layer EC2 can include a polyimide layer (PI). Therefore, the second encapsulation layer EC2 can be made of a flexible material and ensure the stretchability and reliability of the stretchable line.

[0134] In addition, referring to Figure 3 and Figure 4 , during the process of forming the second encapsulation layer EC2, a fluorine-based residual film FL can be formed on the front surface of the lower substrate SUB having the first encapsulation layer EC1 and the second encapsulation layer EC2. For example, a photoresist pattern PR is formed to cover the rigid region RA, that is, the remaining region except for the flexible region SA where the second encapsulation layer EC2 is to be formed. The photoresist pattern PR can have an inverted cone shape to disconnect the polyimide layer PI' on the photoresist pattern PR and the polyimide layer PI formed in the region where the photoresist pattern PR does not exist. For example, as the photoresist pattern PR gradually moves away from the lower substrate SUB, the cross-sectional area of the photoresist pattern PR in the direction parallel to the lower substrate SUB becomes larger and larger. The photoresist pattern PR can be made of a fluorine-based material. The photoresist pattern PR can be provided to cover the entire rigid region RA formed to the first encapsulation layer EC1.

[0135] In addition, a material constituting the second encapsulation layer EC2 can be formed on the front surface of the lower substrate SUB on which the photoresist pattern PR is formed. For example, the polyimide layers PI and PI' as the material constituting the second encapsulation layer EC2 can be formed on the front surface of the lower substrate SUB. The polyimide layers PI and PI' can be provided to cover the photoresist pattern PR in the rigid region RA (for example, the region where the photoresist pattern PR is formed). The polyimide layers PI and PI' can be provided to cover the connection line CL, etc. in the flexible region SA (for example, the region where the photoresist pattern PR is not formed). In this case, as described above, the photoresist pattern PR can have an inverted cone shape so that the polyimide layers PI and PI' can be disconnected at the edge of the photoresist pattern PR. For example, the polyimide layers PI and PI' formed on the front surface of the lower substrate SUB are disconnected at the edge of the photoresist pattern PR having an inverted cone shape so that the polyimide layers PI and PI' can be divided into the polyimide layer PI' provided on the photoresist pattern PR and the polyimide layer PI provided in the region where the photoresist pattern PR does not exist.

[0136] In addition, the photoresist pattern PR can be removed by using a fluorine-based solution. In this process, the polyimide layer PI' formed on the photoresist pattern PR can be removed together with the photoresist pattern PR, and the polyimide layer PI provided in the flexible region SA and not formed on the photoresist pattern PR can remain intact and become the second encapsulation layer EC2.

[0137] Specifically, the fluorine-based solution can be applied to the front surface of the lower substrate SUB when removing the photoresist pattern PR. Thus, the fluorine-based residual film FL can be formed by the fluorine-based solution and cover the front surface of the lower substrate SUB having the first encapsulation layer EC1 and the second encapsulation layer EC2. The fluorine-based residual film FL can be a composite polymer or a single molecule having a plurality of fluorine-based materials included in a carbon-carbon main chain. The fluorine-based material can have solvent orthogonality and allow the organic material and the moisture layer to separate and exclude each other, which can inhibit the movement of the organic material and the moisture layer to different layers. Therefore, forming the fluorine-based residual film FL on the front surface of the lower substrate SUB having the first encapsulation layer EC1 and the second encapsulation layer EC2 can delay the penetration of moisture and the like into other components below the first encapsulation layer EC1 and the second encapsulation layer EC2.

[0138] In addition, a part of the connection line CL can sometimes be exposed from the second encapsulation layer EC2 near the boundary between the rigid region RA and the flexible region SA. The first encapsulation layer EC1 and the second encapsulation layer EC2 are formed by different processes and made of different materials, such that the first encapsulation layer EC1 and the second encapsulation layer EC2 may not be connected to each other. In this case, a part of the connection line CL may be exposed in the space between the first encapsulation layer EC1 and the second encapsulation layer EC2. In this case, the fluorine-based residual film FL can also cover a part of the connection line CL while being formed to cover the front surface of the lower substrate SUB having the first encapsulation layer EC1 and the second encapsulation layer EC2. That is, even if a part of the connection line CL is exposed from the second encapsulation layer EC2, the fluorine-based residual film FL can cover the remaining exposed part of the connection line CL and protect the connection line CL from external moisture and the like. Therefore, the fluorine-based residual film FL together with the second encapsulation layer EC2 can protect the connection line CL.

[0139] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the first encapsulation layer EC1 is disposed in the rigid region RA to protect the light-emitting element LD, and the second encapsulation layer EC2 is disposed in the flexible region SA to protect the connection line CL, which can protect the display device 100 from moisture and oxygen. The first encapsulation layer EC1 can be disposed to seal the light-emitting element LD disposed in the rigid region RA and protect the light-emitting element LD so that the light-emitting element LD is not deteriorated by moisture, oxygen, etc. In addition, the second encapsulation layer EC2 can be disposed to cover the connection line CL and protect the connection line CL to suppress damage to the connection line CL, such as suppressing oxidation of the connection line CL. In this case, the second encapsulation layer EC2 can be configured to have a flexible polyimide layer PI so that the connection line CL can be easily stretched, but the present disclosure is not limited thereto.

[0140] In addition, in the display device 100 according to an exemplary embodiment of the present disclosure, a fluorine-based residual film FL can be formed on the front surface of the display device 100 by using a fluorine-based solution as a solution for removing the photoresist pattern PR when forming the second encapsulation layer EC2. The photoresist pattern PR can be removed by applying a fluorine-based solution on the front surface of the lower substrate SUB on which the first encapsulation layer EC1 and the second encapsulation layer EC2 are formed. In addition, the fluorine-based residual film FL applied on the front surface of the lower substrate SUB having the first encapsulation layer EC1 and the second encapsulation layer EC2 with a very small thickness can be formed by the fluorine-based solution. The fluorine-based residual film FL can protect the constituent elements of the display device 100 by delaying the penetration of moisture to the first encapsulation layer EC1 and the second encapsulation layer EC2 below the fluorine-based residual film FL. Therefore, through the fluorine-based residual film FL formed on the first encapsulation layer EC1 and the second encapsulation layer EC2, the display device 100 according to an exemplary embodiment of the present disclosure can protect its constituent elements so that the light-emitting element LD is not deteriorated by moisture, oxygen, etc.

[0141] Figure 5 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Figure 6 is a cross-sectional view for explaining a process of manufacturing a second encapsulation layer of a display device according to another exemplary embodiment of the present disclosure. Except for the second encapsulation layer EC2, Figure 5 and Figure 6 the shown display device 500 is basically the same in configuration as Figures 1 to 4 the shown display device 100. Therefore, repeated descriptions of the same components will be omitted.

[0142] Refer to Figure 5, the second encapsulation layer EC2 may include multiple layers and, for example, include a first wire encapsulation layer PIa, a second wire encapsulation layer EMLa, a third wire encapsulation layer CADa, a fourth wire encapsulation layer PAS1a, a fifth wire encapsulation layer PAS2a, and a sixth wire encapsulation layer PAS3a.

[0143] The first wire encapsulation layer PIa may be arranged to cover the flexible area SA in which the connection wire CL is provided. The first wire encapsulation layer PIa may be a polyimide layer and be adjacent to the connection wire CL. For example, the first wire encapsulation layer PIa may be directly provided on the connection wire CL, but is not limited thereto.

[0144] The second wire encapsulation layer EMLa is provided on the first wire encapsulation layer PIa. The light-emitting layer EML of the light-emitting element LD provided in the rigid area RA may extend into the flexible area SA, thereby defining the second wire encapsulation layer EMLa. The light-emitting layer EML may be formed on the front surface of the lower substrate SUB, and the portion of the light-emitting layer EML provided in the flexible area SA may become the second wire encapsulation layer EMLa.

[0145] The third wire encapsulation layer CADa is provided on the second wire encapsulation layer EMLa. The third wire encapsulation layer CADa may be a layer formed together with the cathode electrode CAD. The cathode electrode CAD may be formed on the front surface of the lower substrate SUB, and the portion of the cathode electrode CAD provided in the flexible area SA may be used as the third wire encapsulation layer CADa.

[0146] The fourth wire encapsulation layer PAS1a is provided on the third wire encapsulation layer CADa. The fourth wire encapsulation layer PAS1a may be integrated with the first inorganic encapsulation layer PAS1 of the first encapsulation layer EC1. The first inorganic encapsulation layer PAS1 may extend from the rigid area RA to the flexible area SA, thereby defining the fourth wire encapsulation layer PAS1a. The material constituting the first inorganic encapsulation layer PAS1 may be formed on the front surface of the lower substrate SUB such that the first inorganic encapsulation layer PAS1 and the fourth wire encapsulation layer PAS1a may be formed together, but is not limited thereto.

[0147] The fifth wire encapsulation layer PAS2a is provided on the fourth wire encapsulation layer PAS1a. The fifth wire encapsulation layer PAS2a may be integrated with the second inorganic encapsulation layer PAS2 of the first encapsulation layer EC1. The second inorganic encapsulation layer PAS2 may extend from the rigid area RA to the flexible area SA, thereby defining the fifth wire encapsulation layer PAS2a. The material constituting the second inorganic encapsulation layer PAS2 may be formed on the front surface of the lower substrate SUB such that the second inorganic encapsulation layer PAS2 and the fifth wire encapsulation layer PAS2a may be formed together, but is not limited thereto.

[0148] The sixth wire encapsulation layer PAS3a is disposed on the fifth wire encapsulation layer PAS2a. The sixth wire encapsulation layer PAS3a can be integrated with the third inorganic encapsulation layer PAS3 of the first encapsulation layer EC1. The third inorganic encapsulation layer PAS3 can extend from the rigid region RA to the flexible region SA, thereby defining the sixth wire encapsulation layer PAS3a. The material constituting the third inorganic encapsulation layer PAS3 can be formed on the front surface of the lower substrate SUB such that the third inorganic encapsulation layer PAS3 and the sixth wire encapsulation layer PAS3a can be formed together, but is not limited thereto. Alternatively, when the second organic encapsulation layer PCL2 and the third inorganic encapsulation layer PAS3 are not present in the first encapsulation layer EC1, the sixth wire encapsulation layer PAS3a may not be provided.

[0149] Therefore, in the process of forming the light-emitting element LD and the first encapsulation layer EC1, the second wire encapsulation layer EMLa, the third wire encapsulation layer CADa, the fourth wire encapsulation layer PAS1a, the fifth wire encapsulation layer PAS2a, and the sixth layer of the second encapsulation layer EC2 can be formed together, enabling the process of forming the second encapsulation layer EC2 to be simplified. In addition, the second encapsulation layer EC2 provided in the flexible region SA includes multiple layers, which can minimize the penetration of moisture and oxygen into the connection line CL.

[0150] In addition, since the light-emitting layer EML and the cathode electrode CAD of the light-emitting element LD and the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 of the first encapsulation layer EC1 are formed on the front surface of the lower substrate SUB, the process of patterning the light-emitting element LD and the first encapsulation layer EC1 may not be included, enabling the process of manufacturing the display device 500 to be simplified.

[0151] In addition, the fourth wire encapsulation layer PAS1a, the fifth wire encapsulation layer PAS2a, and the sixth wire encapsulation layer PAS3a of the second encapsulation layer EC2 can be formed by continuously extending the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 of the first encapsulation layer EC1 to the flexible region SA, such that the first encapsulation layer EC1 and the second encapsulation layer EC2 can cover the entire front surface of the lower substrate SUB. Therefore, the space not sealed by the first encapsulation layer EC1 and the second encapsulation layer EC2 can be eliminated, and all the constituent elements in the rigid region RA and the flexible region SA can be protected from moisture and oxygen.

[0152] In addition, referring to Figure 6, during the process of forming the first encapsulation layer PIa of the second encapsulation layer EC2, the fluorine-based residual film FL can be formed on the front surface of the lower substrate SUB. Specifically, before the process of forming the light-emitting layer EML or the second encapsulation layer EMLa, a photoresist pattern PR is formed to cover the rigid region RA. After forming the anode electrode AND and the bank BNK, a photoresist pattern PR can be formed to cover the rigid region RA. In addition, the material of the first encapsulation layer PIa that constitutes the second encapsulation layer EC2 (for example, the polyimide layer PI) can be formed on the front surface of the lower substrate SUB. In addition, the photoresist pattern PR can be removed by applying a fluorine-based solution to the front surface of the lower substrate SUB, and a part of the fluorine-based solution is applied to the front surface of the lower substrate SUB to define the fluorine-based residual film FL. Therefore, the fluorine-based residual film FL can be formed above the bank BNK, the anode electrode AND exposed from the bank BNK, the side surface of the third planarization layer PNL3, the side surface of the fifth conductive layer SD3, the first connection line CL1, and the first encapsulation layer PIa. The fluorine-based residual film FL can delay the penetration of moisture and oxygen to the part below the fluorine-based residual film FL.

[0153] In a display device 500 according to another exemplary embodiment of the present disclosure, components of the light-emitting element LD and the first encapsulation layer EC1 extend into the flexible region SA, such that multiple layers of the second encapsulation layer EC2 can be easily formed. For example, a second wire encapsulation layer EMLa, a third wire encapsulation layer CADa, a fourth wire encapsulation layer PAS1a, a fifth wire encapsulation layer PAS2a, and a sixth wire encapsulation layer PAS3a of the second encapsulation layer EC2 can be formed by the same processes as the light-emitting layer EML, the cathode electrode CAD, the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3, respectively, and made of the same materials as those. For example, the second wire encapsulation layer EMLa of the second encapsulation layer EC2 can be formed by the same process as the light-emitting layer EML and made of the same material as that. For example, the third wire encapsulation layer CADa of the second encapsulation layer EC2 can be formed by the same process as the cathode electrode CAD and made of the same material as that. For example, the fourth wire encapsulation layer PAS1a of the second encapsulation layer EC2 can be formed by the same process as the first inorganic encapsulation layer PAS1 and made of the same material as that. For example, the fifth wire encapsulation layer PAS2a of the second encapsulation layer EC2 can be formed by the same process as the second inorganic encapsulation layer PAS2 and made of the same material as that. For example, the sixth wire encapsulation layer PAS3a of the second encapsulation layer EC2 can be formed by the same process as the third inorganic encapsulation layer PAS3 and made of the same material as that. Accordingly, the second encapsulation layer EC2 is formed as a multi-layer, which can improve the performance of the second encapsulation layer EC2 and simplify the process of forming the second encapsulation layer EC2. In addition, since the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 of the first encapsulation layer EC1 are integrated with the fourth wire encapsulation layer PAS1a, the fifth wire encapsulation layer PAS2a, and the sixth wire encapsulation layer PAS3a of the second encapsulation layer EC2, respectively, portions not sealed by the first encapsulation layer EC1 and the second encapsulation layer EC2 can be minimized or reduced, and gaps between the first encapsulation layer EC1 and the second encapsulation layer EC2 can be removed or reduced, which can reduce the penetration of moisture and oxygen.

[0154] Figure 7 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure. Except for the second encapsulation layer EC2, Figure 7 the display device 700 in Figure 5 is substantially the same in configuration as the display device 500 in Figure 6 and

[0155] Reference Figure 7, at least some of the second wire encapsulation layer EMLa, the third wire encapsulation layer CADa, the fourth wire encapsulation layer PAS1a, the fifth wire encapsulation layer PAS2a, and the sixth wire encapsulation layer PAS3a of the second encapsulation layer EC2 can be disconnected from the light-emitting element LD and the first encapsulation layer EC1. Some layers among the first encapsulation layer EC1, the light-emitting element LD, and the second encapsulation layer EC2 can be separated from each other near the edge of the first wire encapsulation layer PIa of the second encapsulation layer EC2 (i.e., the disconnection area DCA at the boundary between the rigid area RA and the flexible area SA). The disconnection area DCA can be an area adjacent to the end of the first wire encapsulation layer PIa, and the disconnection area DCA can be adjacent to the boundary between the rigid area RA and the flexible area SA. For example, the light-emitting layer EML and the second wire encapsulation layer EMLa can be separated from each other in the disconnection area DCA near the end of the first wire encapsulation layer PIa. Near the end of the first wire encapsulation layer PIa, the cathode electrode CAD and the third wire encapsulation layer CADa can also be separated from each other, the first inorganic encapsulation layer PAS1 and the fourth wire encapsulation layer PAS1a can also be separated from each other, the second inorganic encapsulation layer PAS2 and the fifth wire encapsulation layer PAS2a can also be separated from each other, and the third inorganic encapsulation layer PAS3 and the sixth wire encapsulation layer PAS3a can also be separated from each other.

[0156] In particular, the cathode electrode CAD of the light-emitting element LD can be separated from the third wire encapsulation layer CADa of the second encapsulation layer EC2, so that the light-emitting element LD can emit light only in the rigid area RA. Among the conductive layers formed in the flexible area SA and the rigid area RA, only the conductive layer formed in the rigid area RA can substantially serve as the cathode electrode CAD, so that light can be emitted only in the rigid area RA.

[0157] In this case, at least some of the second wire encapsulation layer EMLa, the third wire encapsulation layer CADa, the fourth wire encapsulation layer PAS1a, the fifth wire encapsulation layer PAS2a, and the sixth wire encapsulation layer PAS3a of the second encapsulation layer EC2 may be disconnected due to the thickness of the first wire encapsulation layer PIa and the shape of the end portion of the first wire encapsulation layer PIa. For example, the height difference between the first wire encapsulation layer PIa and the connection line CL increases as the thickness of the first wire encapsulation layer PIa increases. Therefore, the second wire encapsulation layer EMLa, the third wire encapsulation layer CADa, the fourth wire encapsulation layer PAS1a, the fifth wire encapsulation layer PAS2a, and the sixth wire encapsulation layer PAS3a of the second encapsulation layer EC2 can be easily disconnected at the end portion of the first wire encapsulation layer PIa. In addition, when the inclination of the end portion of the first wire encapsulation layer PIa has an inverted cone shape (for example, the width of the upper surface of the first wire encapsulation layer PIa is greater than the width of the lower surface of the first wire encapsulation layer PIa), the second wire encapsulation layer EMLa, the third wire encapsulation layer CADa, the fourth wire encapsulation layer PAS1a, the fifth wire encapsulation layer PAS2a, and the sixth wire encapsulation layer PAS3a of the second encapsulation layer EC2 can be easily disconnected at the end portion of the first wire encapsulation layer PIa having an inverted cone shape. Therefore, the remaining components of the second encapsulation layer EC2 can be disconnected by adjusting the thickness of the first wire encapsulation layer PIa and designing the end portion of the first wire encapsulation layer PIa to have an inverted cone shape.

[0158] In addition, in the disconnection region DCA, the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 may be provided to cover the end portions of the light-emitting layer EML and the cathode electrode CAD. Therefore, even if the second encapsulation layer EC2 and the first encapsulation layer EC1 are disconnected from each other in the disconnection region DCA, the exposure of the light-emitting layer EML to the outside can be minimized, so that the light-emitting element LD can be easily protected from moisture and oxygen.

[0159] In addition, similar to Figure 5 the display device 500 in Figure 7 the display device 700 in Figure 7the reliability of the display device 700 in

[0160] Figure 8 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Figure 9 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Figure 10 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Except that the second encapsulation layer EC2 further includes a seventh wire encapsulation layer PCL1a and an eighth wire encapsulation layer PCL2a, Figures 8 to 10 the display devices 800, 900, and 1000 in Figure 5 and Figure 6 are substantially the same as the display device 500 shown in

[0161] Referring to Figures 8 to 10 , the second encapsulation layer EC2 may include multiple layers, and for example, includes a first wire encapsulation layer PIa, a second wire encapsulation layer EMLa, a third wire encapsulation layer CADa, a fourth wire encapsulation layer PAS1a, a fifth wire encapsulation layer PAS2a, a sixth wire encapsulation layer PAS3a, a seventh wire encapsulation layer PCL1a, and an eighth wire encapsulation layer PCL2a.

[0162] In the flexible region SA, the seventh wire encapsulation layer PCL1a is disposed between the fourth wire encapsulation layer PAS1a and the fifth wire encapsulation layer PAS2a. The seventh wire encapsulation layer PCL1a may be formed by the same process as the first organic encapsulation layer PCL1. The seventh wire encapsulation layer PCL1a may fill cracks in the fourth wire encapsulation layer PAS1a or cover particles formed on the fourth wire encapsulation layer PAS1a. The fourth wire encapsulation layer PAS1a, the seventh wire encapsulation layer PCL1a, and the fifth wire encapsulation layer PAS2a may be formed by sequentially performing the process of forming the first inorganic encapsulation layer PAS1 and the fourth wire encapsulation layer PAS1a, the process of forming the first organic encapsulation layer PCL1 and the seventh wire encapsulation layer PCL1a, and the process of forming the second inorganic encapsulation layer PAS2 and the fifth wire encapsulation layer PAS2a.

[0163] In the flexible region SA, an eighth wire encapsulation layer PCL2a is disposed between a fifth wire encapsulation layer PAS2a and a sixth wire encapsulation layer PAS3a. The eighth wire encapsulation layer PCL2a can be formed by the same process as the second organic encapsulation layer PCL2. The eighth wire encapsulation layer PCL2a can fill cracks in the fifth wire encapsulation layer PAS2a or cover particles formed on the fifth wire encapsulation layer PAS2a. The fifth wire encapsulation layer PAS2a, the eighth wire encapsulation layer PCL2a, and the sixth wire encapsulation layer PAS3a can be formed by sequentially performing the process of forming the second inorganic encapsulation layer PAS2 and the fifth wire encapsulation layer PAS2a, the process of forming the second organic encapsulation layer PCL2 and the eighth wire encapsulation layer PCL2a, and the process of forming the third inorganic encapsulation layer PAS3 and the sixth wire encapsulation layer PAS3a.

[0164] In addition, the thickness of each of the seventh wire encapsulation layer PCL1a and the eighth wire encapsulation layer PCL2a can be greater than the thickness of any one of the first wire encapsulation layer PIa, the second wire encapsulation layer EMLa, the third wire encapsulation layer CADa, the fourth wire encapsulation layer PAS1a, the fifth wire encapsulation layer PAS2a, and the sixth wire encapsulation layer PAS3a. However, the present disclosure is not limited thereto.

[0165] The light-emitting layer EML, the cathode electrode CAD, and the first encapsulation layer EC1 in the rigid region RA and the second wire encapsulation layer to the eighth wire encapsulation layer EMLa, CADa, PAS1a, PAS2a, PAS3a, PCL1a, and PCL2a of the second encapsulation layer EC2 in the flexible region SA are formed by the same process, so that the second encapsulation layer EC2 can be formed more easily. In addition, since the second encapsulation layer EC2 includes a plurality of layers, the plurality of layers including the first encapsulation layer to the eighth wire encapsulation layer PIa, EMLa, CADa, PAS1a, PAS2a, PAS3a, PCL1a, and PCL2a, moisture and oxygen permeation from the second encapsulation layer EC2 to the connection line CL can be minimized or reduced.

[0166] In this case, the layers formed in common on the light-emitting layer EML, the cathode electrode CAD, and the first encapsulation layer EC1 in the rigid region RA and the second encapsulation layer EC2 in the flexible region SA can be connected and integrated with each other, and at least some of the layers formed in common can be separated from each other in the disconnection region DCA.

[0167] Reference Figure 8, some components of the light-emitting layer EML, the cathode electrode CAD, and the first encapsulation layer EC1, as well as some components of the second encapsulation layer EC2, can be connected and integrated with each other. For example, the light-emitting layer EML and the second wire encapsulation layer EMLa can be connected and integrated with each other, the cathode electrode CAD and the third wire encapsulation layer CADa can be connected and integrated with each other, the first inorganic encapsulation layer PAS1 and the fourth wire encapsulation layer PAS1a can be connected and integrated with each other, the second inorganic encapsulation layer PAS2 and the fifth wire encapsulation layer PAS2a can be connected and integrated with each other, and the third inorganic encapsulation layer PAS3 and the sixth wire encapsulation layer PAS3a can be connected and integrated with each other.

[0168] Reference Figure 9 , some components of the light-emitting layer EML, the first encapsulation layer EC1, and the second encapsulation layer EC2 can be connected and integrated with each other. For example, the light-emitting layer EML and the second wire encapsulation layer EMLa can be connected and integrated with each other, the first inorganic encapsulation layer PAS1 and the fourth wire encapsulation layer PAS1a can be connected and integrated with each other, the second inorganic encapsulation layer PAS2 and the fifth wire encapsulation layer PAS2a can be connected and integrated with each other, and the third inorganic encapsulation layer PAS3 and the sixth wire encapsulation layer PAS3a can be connected and integrated with each other. In addition, the cathode electrode CAD and the third wire encapsulation layer CADa can be separated from each other in the disconnection region DCA. The cathode electrode CAD can be formed to be separated from the third wire encapsulation layer CADa such that only the conductive layer provided in the rigid region RA can be used as the cathode electrode CAD, and light can be emitted in the rigid region RA.

[0169] Reference Figure 10 , the second encapsulation layer EC2 can be formed to be separated from the components in the rigid region RA. Some components of the second encapsulation layer EC2 formed together with the light-emitting layer EML, the cathode electrode CAD, and the first encapsulation layer EC1 can be separated from the light-emitting layer EML, the cathode electrode CAD, and the first encapsulation layer EC1 in the disconnection region DCA. For example, in the disconnection region DCA, the light-emitting layer EML and the second wire encapsulation layer EMLa can be separated from each other, the cathode electrode CAD and the third wire encapsulation layer CADa can be separated from each other, the first inorganic encapsulation layer PAS1 and the fourth wire encapsulation layer PAS1a can be separated from each other, the second inorganic encapsulation layer PAS2 and the fifth wire encapsulation layer PAS2a can be separated from each other, and the third inorganic encapsulation layer PAS3 and the sixth wire encapsulation layer PAS3a can be separated from each other.

[0170] In addition, referring together to Figure 9 and Figure 10, by adjusting the thickness of the first line encapsulation layer PIa of the second encapsulation layer EC2 and adjusting the shape of the end portion of the first line encapsulation layer PIa of the second encapsulation layer EC2, some components of the second encapsulation layer EC2 can be formed to be separated from the components in the rigid region RA in the disconnection region DCA. For example, the first line encapsulation layer PIa is formed to have a large thickness so that at least some of the second line encapsulation layer to the eighth line encapsulation layer EMLa, CADa, PAS1a, PAS2a, PAS3a, PCL1a, and PCL2a of the second encapsulation layer EC2 can be disconnected from the components in the rigid region RA. For example, the end portion of the first line encapsulation layer PIa located in the disconnection region DCA is formed in an inverted cone shape (for example, the width of the upper surface of the first line encapsulation layer PIa is greater than the width of the lower surface of the first line encapsulation layer PIa), so that at least some of the second line encapsulation layer to the eighth line encapsulation layer EMLa, CADa, PAS1a, PAS2a, PAS3a, PCL1a, and PCL2a of the second encapsulation layer EC2 can be disconnected from the components in the rigid region RA.

[0171] In addition, similar to the display devices 500 and 800 in Figure 5 and Figure 8 , all the display devices 800, 900, and 1000 in Figures 8 to 10 can each include a fluorine-based residual film FL formed during the process of forming the first line encapsulation layer PIa. For example, in the rigid region RA, the fluorine-based residual film FL can be formed on the bottom surface of the light-emitting layer EML, such as the portion between the light-emitting layer EML and the anode electrode AND, the portion between the light-emitting layer EML and the bank BNK, and the portion between the light-emitting layer EML and the fifth conductive layer SD3. In the flexible region SA, the fluorine-based residual film FL can be formed between the first line encapsulation layer PIa and the second line encapsulation layer EMLa. The fluorine-based residual film FL can protect other components by minimizing or reducing the penetration of moisture and the like to other components below the fluorine-based residual film FL, so that the reliability of the display devices 800, 900, and 1000 in Figures 8 to 10 can be improved.

[0172] Accordingly, in display devices 800, 900, and 1000 according to another exemplary embodiment of the present disclosure, some layers of the second encapsulation layer EC2 are formed by the same process as the light-emitting element LD and the first encapsulation layer EC1, which can simplify the process of forming the second encapsulation layer EC2. For example, the second wire encapsulation layer EMLa and the third wire encapsulation layer CADa of the second encapsulation layer EC2 can be formed together when forming the light-emitting layer EML and the cathode electrode CAD of the light-emitting element LD. The fourth to eighth wire encapsulation layers PAS1a, PAS2a, PAS3a, PCL1a, and PCL2a of the second encapsulation layer EC2 can be formed together when forming the first inorganic encapsulation layer PAS1, the first organic encapsulation layer PCL1, the second inorganic encapsulation layer PAS2, the second organic encapsulation layer PCL2, and the third inorganic encapsulation layer PAS3 of the first encapsulation layer EC1. Accordingly, the second encapsulation layer EC2 can be easily formed into multiple layers while simplifying the process of forming the second encapsulation layer EC2.

[0173] Figure 11 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. In addition to the lower substrate SUB, the pattern layer PTL, and the connection line CL, Figure 11 the display device 1100 in Figures 1 to 4 is substantially the same in configuration as the display device 100 in

[0174] Referring to Figure 11 , the lower substrate SUB includes a first lower substrate SUBa, a second lower substrate SUBb, and a third lower substrate SUBc. The second lower substrate SUBb is disposed on the first lower substrate SUBa, and the third lower substrate SUBc is disposed on the second lower substrate SUBb.

[0175] The first lower substrate SUBa and the third lower substrate SUBc may be substrates configured to support components formed on the lower substrate SUB. The first lower substrate SUBa and the third lower substrate SUBc may be flexible substrates made of a plastic material. In this case, flexibility may be interpreted in the same manner as bendable, non-breakable, rollable, foldable characteristics, etc.

[0176] For example, the first lower substrate SUBa and the third lower substrate SUBc may include plastic. In this case, the first lower substrate SUBa and the third lower substrate SUBc may be referred to as a plastic film or a plastic substrate. For example, the first lower substrate SUBa and the third lower substrate SUBc may include at least one selected from the group consisting of polyester-based polymers, silicon-based polymers, acrylic-based polymers, polyolefin-based polymers, and their polymers. For example, the first lower substrate SUBa and the third lower substrate SUBc may be polyimide substrates made of polyimide (PI). However, the present disclosure is not limited thereto.

[0177] The second lower substrate SUBb may include an inorganic insulating material. The second lower substrate SUBb may be an inorganic film formed between the first lower substrate SUBa and the third lower substrate SUBc. For example, the second lower substrate SUBb may be configured as a single layer or multiple layers made of silicon nitride (SiNx) or silicon oxide (SiOx). For example, the second lower substrate SUBb may be formed by a single layer or multiple layers of an inorganic film. For example, the single layer of the inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of the inorganic film may be formed by alternately laminating one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si). However, the present disclosure is not limited thereto.

[0178] In addition, in the case where the lower substrate SUB includes polyimide, moisture may pass through the substrate made of polyimide and penetrate into thin film transistors and the like included in the pixel PX, which may deteriorate the reliability of the pixel PX and the performance of the display device 1100.

[0179] Therefore, the lower substrate SUB may include a double polyimide substrate, that is, the first lower substrate SUBa and the third lower substrate SUBc. In addition, in order to suppress the penetration of moisture, the lower substrate SUB may be configured such that the second lower substrate SUBb made of an inorganic material may also be provided between the first lower substrate SUBa and the third lower substrate SUBc which are polyimide substrates. Therefore, the second lower substrate SUBb may be formed to suppress moisture from being introduced into the display device 1100 through the first lower substrate SUBa and the third lower substrate SUBc which are polyimide substrates, thereby further improving the performance and reliability of the product. In addition, since the second lower substrate SUBb as an inorganic film is formed between the first lower substrate SUBa and the third lower substrate SUBc which are polyimide substrates, charges charged on the polyimide substrate may be blocked, which may further improve the reliability of the product. In addition, the number of layers of the lower substrate SUB is not limited to 3 layers. For example, the lower substrate SUB may include n layers of polyimide substrates and n - 1 layers of inorganic films interposed therebetween, where n is an integer greater than 1, but the present disclosure is not limited thereto.

[0180] In addition, the pattern layer PTL may only include a plurality of plate patterns PP. The pattern layer PTL may include a plurality of first plate patterns PP1 and a plurality of second plate patterns PP2. In addition, instead of a plurality of line patterns LP, the lower substrate SUB may support and protect a plurality of connection lines CL in the flexible area SA.

[0181] Specifically, multiple connection lines CL can be provided in the lower substrate SUB instead of on the multiple line patterns LP. The multiple connection lines CL can be provided between the first lower substrate SUBa and the third lower substrate SUBc. For example, the multiple connection lines CL can be provided between the second lower substrate SUBb and the third lower substrate SUBc. In addition, the multiple connection lines CL can also be provided between the first lower substrate SUBa and the second lower substrate SUBb. In this case, the third lower substrate SUBc and the first lower substrate SUBa can be used as a packaging layer to protect the multiple connection lines CL from external moisture and oxygen. In particular, the third lower substrate SUBc can be provided to cover the upper portion of the connection lines CL and protect the connection lines CL from moisture and oxygen.

[0182] In addition, a fifth conductive layer SD3 extending from the rigid region RA toward the connection lines CL can be electrically connected to the multiple connection lines CL through a contact hole formed in the third lower substrate SUBc. In this case, in a state where the second planarization layer PNL2 is formed, the fifth conductive layer SD3 and the contact hole through which the connection lines CL are connected to the third lower substrate SUBc can be formed. In addition, after the contact hole is formed, the fifth conductive layer SD3 and the second shielding pattern SM can be formed together. The fifth conductive layer SD3 can be formed in the contact hole of the third lower substrate SUBc and connected to the connection lines CL. In addition, the third planarization layer PNL3, the bank BNK, the light-emitting element LD, and the first encapsulation layer EC1 are sequentially formed on the fifth conductive layer SD3, so that a Figure 11 display device 1100 can be formed.

[0183] In this case, the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 of the first encapsulation layer EC1 can extend to be adjacent to the top surface of the third lower substrate SUBc, thereby sealing all components in the rigid region RA. The first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 can extend from the rigid region RA to the flexible region SA and be adjacent to the top surface of the third lower substrate SUBc. In particular, the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 can extend toward the third lower substrate SUBc and cover the entire fifth conductive layer SD3, and the fifth conductive layer SD3 can be sealed without being exposed to the outside. Therefore, the components in the rigid region RA can be sealed in the space between the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, the third inorganic encapsulation layer PAS3, and the third lower substrate SUBc and protected from damage by moisture and oxygen.

[0184] Accordingly, in the display device 1100 according to another exemplary embodiment of the present disclosure, the connection line CL may be disposed between the first lower substrate SUBa and the third lower substrate SUBc, and the third lower substrate SUBc may serve as a encapsulation layer for protecting the connection line CL. The third lower substrate SUBc may be disposed to cover all the connection lines CL and protect the connection lines CL such that the connection lines CL are not exposed to moisture and oxygen. Accordingly, since there is no need to form a separate encapsulation layer for protecting the connection line CL in the flexible area SA, the structure of the display device 1100 may be simplified. In addition, since the fifth conductive layer SD3 and the connection line CL are connected through a contact hole formed in the third lower substrate SUBc, the fifth conductive layer SD3 or the connection line CL may not be exposed to the outside.

[0185] Figure 12 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure. Except that the display device 1200 further includes a plurality of touch electrodes TE, a plurality of bridge electrodes BRG, a third buffer layer BUF3, a fourth interlayer insulating layer ILD4, and a protective layer PAC, Figure 12 the display device 1200 in Figure 11 is substantially the same as the display device 1100 in

[0186] Referring to Figure 12 , the touch sensor is disposed on the first encapsulation layer EC1 in the rigid area RA. The touch sensor may sense a touch input applied from the outside by a user's finger, a stylus, or the like. The touch sensor includes a plurality of touch electrodes TE, a plurality of bridge electrodes BRG, a third buffer layer BUF3, a fourth interlayer insulating layer ILD4, and a protective layer PAC.

[0187] First, the third buffer layer BUF3 is disposed on the first encapsulation layer EC1. The third buffer layer BUF3 is an insulating layer for protecting surrounding components (e.g., the first encapsulation layer EC1, the light-emitting element LD, the touch electrode TE, and the bridge electrode BRG) during the process of forming the touch sensor. For example, the third buffer layer BUF3 may minimize the penetration of moisture or solution related to the process of the touch sensor from the outside into the light-emitting layer EML of the light-emitting element LD. In addition, the third buffer layer BUF3 may protect the first encapsulation layer EC1 such that the first encapsulation layer EC1 is not damaged when the display device 1200 is stretched and deformed. The third buffer layer BUF3 may protect the touch electrode TE or the bridge electrode BRG of the touch sensor such that the touch electrode TE or the bridge electrode BRG does not break when the display device 1200 is stretched and deformed.

[0188] To suppress damage to the emission layer EML that is vulnerable to high-temperature processes, the third buffer layer BUF3 can be made of an insulating material that can be formed by a low-temperature process. For example, the third buffer layer BUF3 can be made of at least one of an acrylic-based material, an epoxy-based material, and a siloxane-based material.

[0189] The fourth interlayer insulating layer ILD4 is disposed on the third buffer layer BUF3. The fourth interlayer insulating layer ILD4 can be disposed between the plurality of bridging electrodes BRG and the plurality of touch electrodes TE, and insulate some of the bridging electrodes BRG and some of the touch electrodes TE. The fourth interlayer insulating layer ILD4 can be configured as a single layer or multiple layers made of silicon nitride (SiNx) or silicon oxide (SiOx). For example, the fourth interlayer insulating layer ILD4 can be formed by a single layer or multiple layers of inorganic films. For example, the single layer of inorganic film can be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multiple layers of inorganic films can be formed by alternately laminating one or more layers of silicon oxide (SiOx) films, one or more layers of silicon nitride (SiNx) films, and one or more layers of amorphous silicon (a-Si). However, the present disclosure is not limited thereto.

[0190] The plurality of touch electrodes TE are disposed on the fourth interlayer insulating layer ILD4. The plurality of touch electrodes TE can be used to sense touch inputs in various ways. For example, in the case where the touch sensor senses touch inputs by using mutual capacitance, the plurality of touch electrodes TE of the plurality of touch sensors can include drive electrodes to which touch drive signals are applied and sensing electrodes configured to generate capacitance of the drive electrodes. In addition, touch inputs can be sensed based on capacitance changes between the drive electrodes and the sensing electrodes. Also, for example, in the case where the touch sensor senses touch inputs in a self-capacitance manner, the plurality of touch electrodes TE of the touch sensor can be used as drive electrodes or sensing electrodes. In addition, touch drive signals can be applied to the touch electrodes TE, and touch inputs can be sensed based on capacitance changes of the touch electrodes TE according to the presence or absence of touch. The touch sensing method of the touch sensor is presented only for illustrative purposes, and the touch electrodes TE can be used in various ways according to the touch sensing method of the touch sensor. However, the present disclosure is not limited thereto.

[0191] In addition, the plurality of touch electrodes TE can have a grid structure. Light emitted from the light-emitting element LD can propagate to the outside through the opening portions of the grid structure of the plurality of touch electrodes TE. In addition, since the plurality of touch electrodes TE have a grid structure, the parasitic capacitance with other electrodes around the touch electrodes TE can be reduced. Additionally, since the plurality of touch electrodes TE have a grid structure, the plurality of touch electrodes TE can have high flexibility.

[0192] A plurality of bridge electrodes BRG are disposed between the fourth interlayer insulating layer ILD4 and the third buffer layer BUF3. A plurality of touch electrodes TE can be connected to each other through the plurality of bridge electrodes BRG. For example, some of the plurality of touch electrodes TE can be connected to the bridge electrodes BRG through contact holes in the fourth interlayer insulating layer ILD4. In addition, the bridge electrodes BRG can also be connected to another touch electrode TE. Two touch electrodes TE can be electrically connected to each other through the bridge electrodes BRG.

[0193] The plurality of touch electrodes TE and the plurality of bridge electrodes BRG can each be configured as a layered structure made of a metal material such as copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni) or a metal material such as titanium / aluminum / titanium (Ti / Al / Ti). However, the present disclosure is not limited thereto.

[0194] In addition, although not shown in the figure, the plurality of touch electrodes TE can be electrically connected to the touch electrodes TE in the adjacent rigid region RA through any one of the plurality of connection lines CL. For example, one of the plurality of touch electrodes TE can extend along the top surface of the fourth interlayer insulating layer ILD4 provided on the upper and side portions of the light-emitting element LD to the top surface of the third lower substrate SUBc adjacent to the flexible region SA. In addition, the touch electrode TE can be electrically connected to any one of the connection lines CL formed in the third lower substrate SUBc through a contact hole formed in the third lower substrate SUBc.

[0195] Next, a protective layer PAC is provided on the plurality of touch electrodes TE. The protective layer PAC can be provided to cover all of the plurality of touch electrodes TE and the fourth interlayer insulating layer ILD4 and protect the plurality of touch electrodes TE and the fourth interlayer insulating layer ILD4. For example, the protective layer PAC can be an organic insulating film made of a material such as an epoxy-based polymer or an acrylic-based polymer. In addition, the protective layer PAC can include an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx). However, the present disclosure is not limited thereto.

[0196] In addition, the insulating layers (e.g., the third buffer layer BUF3, the fourth interlayer insulating layer ILD4, and the protective layer PAC) included in the touch sensor may extend from the upper portion of the first encapsulation layer EC1 to the top surface of the third lower substrate SUBc adjacent to the flexible region SA. Thus, the third buffer layer BUF3, the fourth interlayer insulating layer ILD4, and the protective layer PAC may seal the components in the rigid region RA together with the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 of the first encapsulation layer EC1. The third buffer layer BUF3, the fourth interlayer insulating layer ILD4, the protective layer PAC, the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 may extend from the rigid region RA toward the flexible region SA and abut the top surface of the third lower substrate SUBc. In this case, all connection portions between the connection line CL and the fifth conductive layer SD3 may be sealed by the third buffer layer BUF3, the fourth interlayer insulating layer ILD4, the protective layer PAC, the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3, so that the penetration of moisture and oxygen into the fifth conductive layer SD3 and the connection line CL can be minimized.

[0197] In addition, in addition to Figure 11 the display device 1100 in Figure 12 the touch sensor in Figures 1 to 10 can also be applied to Figure 12 the display devices 100, 500, 700, 800, 900, and 1000 in Figures 1 to 4 For example, when the touch sensor in Figure 12 is applied to Figure 5 the display device 100 in Figure 7 the third buffer layer BUF3, the fourth interlayer insulating layer ILD4, and the protective layer PAC of the touch sensor may extend toward the flexible region SA and cover a part of the connection line CL together with the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3. As another example, when the touch sensor in Figure 8 is applied to Figure 9 the display device 500 in Figure 10 the display device 700 in

[0198] Thus, in the display device 1200 according to another exemplary embodiment of the present disclosure, the insulating layer of the touch sensor may be provided to cover the top surface of the third lower substrate SUBc, thereby protecting the fifth conductive layer SD3 and the connection line CL. For example, the touch sensor may include insulating layers such as a third buffer layer BUF3, a fourth interlayer insulating layer ILD4, and a protective layer PAC. In addition, similar to the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 of the first encapsulation layer EC1, the third buffer layer BUF3, the fourth interlayer insulating layer ILD4, and the protective layer PAC of the touch sensor may also extend from the rigid region RA toward the flexible region SA and seal the components in the rigid region RA. Therefore, in the structure where the touch sensor is disposed on the first encapsulation layer EC1, the insulating layer of the touch sensor may also extend to seal the components in the rigid region RA, which may improve the reliability of the display device 1200.

[0199] The exemplary embodiments of the present disclosure may also be described as follows:

[0200] According to an exemplary embodiment of the present disclosure, the display device includes: a lower substrate including a rigid region and a flexible region; a light-emitting element disposed above the lower substrate in the rigid region; a connection line disposed at the lower substrate in the flexible region and electrically connected to the light-emitting element; and an encapsulation layer including a first encapsulation layer covering the light-emitting element in the rigid region and a second encapsulation layer covering the connection line in the flexible region.

[0201] According to an exemplary embodiment of the present disclosure, the connection line is disposed on the lower substrate in the flexible region, or the connection line is disposed in the lower substrate in the flexible region.

[0202] According to an exemplary embodiment of the present disclosure, the first encapsulation layer includes a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer, a second organic encapsulation layer, and a third inorganic encapsulation layer sequentially stacked on the light-emitting element.

[0203] According to an exemplary embodiment of the present disclosure, the first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer cover the upper and side surfaces of the light-emitting element and seal the first organic encapsulation layer and the second organic encapsulation layer.

[0204] According to an exemplary embodiment of the present disclosure, each of the first organic encapsulation layer and the second organic encapsulation layer has a greater thickness than each of the first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer.

[0205] According to an exemplary embodiment of the present disclosure, the second encapsulation layer includes a material different from that of the first encapsulation layer.

[0206] According to an exemplary embodiment of the present disclosure, the second encapsulation layer includes a polyimide layer.

[0207] According to an exemplary embodiment of the present disclosure, the second encapsulation layer is more flexible than the first encapsulation layer.

[0208] According to an exemplary embodiment of the present disclosure, the second encapsulation layer includes a first line encapsulation layer disposed on the connection line.

[0209] According to an exemplary embodiment of the present disclosure, the first line encapsulation layer is made of polyimide.

[0210] According to an exemplary embodiment of the present disclosure, the second encapsulation layer further includes a second line encapsulation layer, a third line encapsulation layer, a fourth line encapsulation layer, a fifth line encapsulation layer, and a sixth line encapsulation layer that are sequentially stacked on the first line encapsulation layer.

[0211] According to an exemplary embodiment of the present disclosure, the display device further includes a fluorine-based residual film formed between the second line encapsulation layer and the first line encapsulation layer.

[0212] According to an exemplary embodiment of the present disclosure, the second line encapsulation layer is integrally formed with the light-emitting layer of the light-emitting element, the third line encapsulation layer is integrally formed with the cathode electrode of the light-emitting element, the fourth line encapsulation layer is integrally formed with the first inorganic encapsulation layer, the fifth line encapsulation layer is integrally formed with the second inorganic encapsulation layer, and the sixth line encapsulation layer is integrally formed with the third inorganic encapsulation layer.

[0213] According to an exemplary embodiment of the present disclosure, in a disconnection region adjacent to an end of the first line encapsulation layer: the second line encapsulation layer is separated from the light-emitting layer of the light-emitting element, the third line encapsulation layer is separated from the cathode electrode of the light-emitting element, the fourth line encapsulation layer is separated from the first inorganic encapsulation layer, the fifth line encapsulation layer is separated from the second inorganic encapsulation layer, and the sixth line encapsulation layer is separated from the third inorganic encapsulation layer.

[0214] According to an exemplary embodiment of the present disclosure, an end of the first line encapsulation layer is formed to have an inverted cone shape.

[0215] According to an exemplary embodiment of the present disclosure, in the disconnection region, the first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer are disposed to cover ends of the light-emitting layer and the cathode electrode.

[0216] According to an exemplary embodiment of the present disclosure, the second encapsulation layer further includes a seventh wire encapsulation layer and an eighth wire encapsulation layer. The seventh wire encapsulation layer is disposed between the fourth wire encapsulation layer and the fifth wire encapsulation layer, and the seventh wire encapsulation layer is formed by the same process as the first organic encapsulation layer. The eighth wire encapsulation layer is disposed between the fifth wire encapsulation layer and the sixth wire encapsulation layer, and the eighth wire encapsulation layer is formed by the same process as the second organic encapsulation layer.

[0217] According to an exemplary embodiment of the present disclosure, the second wire encapsulation layer is integrally formed with the light-emitting layer of the light-emitting element, the fourth wire encapsulation layer is integrally formed with the first inorganic encapsulation layer, the fifth wire encapsulation layer is integrally formed with the second inorganic encapsulation layer, and the sixth wire encapsulation layer is integrally formed with the third inorganic encapsulation layer. In a disconnection region adjacent to an end portion of the first wire encapsulation layer, the third wire encapsulation layer and the cathode electrode of the light-emitting element are separated from each other.

[0218] According to an exemplary embodiment of the present disclosure, the lower substrate includes a first lower substrate, a second lower substrate, and a third lower substrate. Among them, the first lower substrate and the third lower substrate are configured as plastic substrates, and the second lower substrate is configured as an inorganic layer interposed between the first lower substrate and the third lower substrate.

[0219] According to an exemplary embodiment of the present disclosure, the first lower substrate and the third lower substrate are configured as polyimide substrates.

[0220] According to an exemplary embodiment of the present disclosure, the connection line is disposed between the first lower substrate and the third lower substrate.

[0221] According to an exemplary embodiment of the present disclosure, the display device further includes an insulating layer of a touch sensor disposed on a top surface of the third lower substrate.

[0222] According to an exemplary embodiment of the present disclosure, the display device further includes a conductive layer disposed between the connection line and the light-emitting element. The conductive layer extends to a side surface of the insulating layer located below the conductive layer and is connected to the connection line.

[0223] According to an exemplary embodiment of the present disclosure, the conductive layer is connected to the connection line through a contact hole formed in the lower substrate.

[0224] According to an exemplary embodiment of the present disclosure, the display device further includes a conductive layer disposed between the connection line and the light-emitting element. The conductive layer extends to a side surface of the insulating layer located below the conductive layer and is connected to the connection line, and the first encapsulation layer covers the conductive layer.

[0225] According to an exemplary embodiment of the present disclosure, the display device further includes a fluorine-based residual film, and the fluorine-based residual film is formed to cover a front surface of the lower substrate where the encapsulation layer is provided and a part of the connection line.

[0226] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be understood to fall within the scope of the present disclosure.

[0227] Cross-reference to related applications

[0228] This application claims the benefit of priority of Korean Patent Application No. 10-2023-0182785, filed on December 15, 2023, with the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference herein for all purposes.

Claims

1. A display device, comprising: A lower substrate, the lower substrate comprising a rigid area and a flexible area; a light emitting element, the light emitting element being disposed in the rigid region above the lower substrate; a connection line disposed in the flexible region at the lower substrate and electrically connected to the light emitting element; The encapsulation layer includes a first encapsulation layer covering the light emitting element in the rigid region and a second encapsulation layer covering the connecting wire in the flexible region.

2. The display device according to claim 1, wherein: The connection line is disposed in the flexible region on the lower substrate, or the connection line is disposed in the flexible region in the lower substrate.

3. The display device according to claim 1, wherein: The first encapsulation layer includes a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer, a second organic encapsulation layer, and a third inorganic encapsulation layer sequentially stacked on the light emitting element.

4. The display device according to claim 3, wherein: The first, second, and third inorganic encapsulating layers cover an upper portion and side surfaces of the light emitting element, and seal the first and second organic encapsulating layers.

5. The display device according to claim 4, wherein: The first organic encapsulating layer and the second organic encapsulating layer each have a thickness greater than each of the first inorganic encapsulating layer, the second inorganic encapsulating layer, and the third inorganic encapsulating layer.

6. The display device according to claim 1, wherein: The second encapsulation layer includes a material different from that of the first encapsulation layer.

7. The display device according to claim 6, wherein: The second encapsulation layer includes a polyimide layer.

8. The display device according to claim 1, wherein: The flexibility of the second encapsulation layer is greater than that of the first encapsulation layer.

9. The display device according to claim 3, wherein: The second encapsulation layer includes a first line encapsulation layer disposed on the connection line.

10. The display device according to claim 9, wherein: The first wire encapsulation layer is made of polyimide.

11. The display device according to claim 9, wherein: The second encapsulation layer further includes a second line encapsulation layer, a third line encapsulation layer, a fourth line encapsulation layer, a fifth line encapsulation layer and a sixth line encapsulation layer sequentially stacked on the first line encapsulation layer. 12 . The display device of claim 11 , further comprising a fluorine-based residual film formed between the second line encapsulation layer and the first line encapsulation layer.

13. The display device according to claim 11, wherein: The second wire encapsulation layer is formed integrally with the light-emitting layer of the light-emitting element, The third line encapsulation layer is formed integrally with the cathode electrode of the light emitting element, The fourth linear encapsulation layer is formed integrally with the first inorganic encapsulation layer, The fifth linear encapsulation layer is formed integrally with the second inorganic encapsulation layer, and The sixth line encapsulation layer is formed integrally with the third inorganic encapsulation layer.

14. The display device according to claim 11, wherein: In a disconnection region adjacent to an end of the first line encapsulation layer: The second wire encapsulation layer is separated from the light-emitting layer of the light-emitting element. The third line encapsulation layer and the cathode electrode of the light emitting element are separated from each other, The fourth line encapsulation layer and the first inorganic encapsulation layer are separated from each other, The fifth line encapsulation layer and the second inorganic encapsulation layer are separated from each other, and The sixth line encapsulation layer and the third inorganic encapsulation layer are separated from each other.

15. The display device according to claim 14, wherein: The end portion of the first wire encapsulation layer is formed to have an inverted tapered shape.

16. The display device according to claim 14, wherein: In the disconnection region, the first inorganic encapsulating layer, the second inorganic encapsulating layer, and the third inorganic encapsulating layer are disposed to cover an end portion of the light emitting layer and an end portion of the cathode electrode.

17. The display device according to claim 11, wherein: The second encapsulation layer further includes a seventh line encapsulation layer and an eighth line encapsulation layer, The seventh line encapsulation layer is disposed between the fourth line encapsulation layer and the fifth line encapsulation layer, and the seventh line encapsulation layer is formed by the same process as the first organic encapsulation layer, and The eighth line encapsulation layer is disposed between the fifth line encapsulation layer and the sixth line encapsulation layer, and the eighth line encapsulation layer is formed by the same process as the second organic encapsulation layer.

18. The display device according to claim 17, wherein: The second line encapsulation layer is formed integrally with the light emitting layer of the light emitting element, the fourth line encapsulation layer is formed integrally with the first inorganic encapsulation layer, the fifth line encapsulation layer is formed integrally with the second inorganic encapsulation layer, and the sixth line encapsulation layer is formed integrally with the third inorganic encapsulation layer, and Wherein, in a disconnection region adjacent to an end of the first wire encapsulation layer, the third wire encapsulation layer and a cathode electrode of the light emitting element are separated from each other.

19. The display device according to claim 1, wherein: The lower substrate includes a first lower substrate, a second lower substrate and a third lower substrate, The first lower substrate and the third lower substrate are configured as plastic substrates, and the second lower substrate is configured as an inorganic layer interposed between the first lower substrate and the third lower substrate.

20. The display device according to claim 19, wherein: The first lower substrate and the third lower substrate are configured as polyimide substrates.

21. The display device according to claim 19, wherein: The connection line is disposed between the first lower substrate and the third lower substrate. 22 . The display device of claim 21 , further comprising an insulating layer of a touch sensor disposed on a top surface of the third lower substrate.

23. The display device according to claim 21, further comprising a conductive layer disposed between the connecting line and the light emitting element, in, The conductive layer extends to a side surface of the insulating layer located below the conductive layer and is connected to the connection line.

24. The display device according to claim 23, wherein: The conductive layer is connected to the connection line through a contact hole formed in the lower substrate.

25. The display device according to claim 1, further comprising a conductive layer disposed between the connecting line and the light emitting element, in, The conductive layer extends to a side surface of the insulating layer located below the conductive layer and is connected to the connection line, and Wherein, the first packaging layer covers the conductive layer. 26 . The display device of claim 1 , further comprising a fluorine-based residual film formed to cover a front surface of the lower substrate provided with the encapsulation layer and a portion of the connection line.

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