Display device

Abstract

A display device is provided. The display device includes a base substrate, a transistor on the base substrate and including a semiconductor pattern and a gate electrode, a gate insulating pattern layer on the semiconductor pattern, a connection electrode on the gate insulating pattern layer and connected to the semiconductor pattern via a contact hole, and an insulating layer on the base substrate, an insulating layer is on the connection electrode and the transistor, where the connection electrode is in the same layer as the gate electrode, and the insulating layer includes a low-transmissivity layer having a light transmissivity of 30% or more and 65% or less.

Description

Technical Field

[0001] Aspects of some embodiments of the present disclosure relate to a display device. Background Art

[0002] Multimedia display devices such as televisions, mobile phones, computers (e.g., tablet computers), navigation units, and gaming units include a display panel to display an image. The display panel includes a plurality of pixels configured to display an image, and each of the plurality of pixels includes a light-emitting element that emits light and a driving element connected to the light-emitting element.

[0003] The light-emitting element and the driving element of the display panel may be formed by stacking a plurality of thin layers and patterning the plurality of thin layers using a mask. Since the display panel manufacturing process using a mask generates a large amount of cost, it is desirable to reduce the number of masks used for manufacturing the display device by simplifying the display panel manufacturing process. In addition, it is desirable to reliably manufacture the display panel while relatively simplifying the manufacturing process.

[0004] The above information disclosed in this background art section is only for enhancing the understanding of the background, and thus the information discussed in this background art section does not necessarily constitute the prior art. Summary of the Invention

[0005] Aspects of some embodiments of the present disclosure relate to a display device. For example, aspects of some embodiments of the present disclosure relate to a display device having relatively improved reliability.

[0006] Aspects of some embodiments of the present disclosure include a display device having a relatively simplified manufacturing process and relatively improved display quality.

[0007] According to some embodiments of the present disclosure, a display device includes a base substrate, a transistor on the base substrate and including a semiconductor pattern and a gate electrode, a gate insulating pattern layer on the semiconductor pattern, a connection electrode on the gate insulating pattern layer and connected to the semiconductor pattern via a contact hole, and an insulating layer on the connection electrode and the transistor. According to some embodiments, the connection electrode and the gate electrode are in the same layer, and the insulating layer includes a low-transmission layer having a light transmittance equal to or greater than about 30% and equal to or less than about 65%.

[0008] According to some embodiments, the low-transmission layer contains silicon atoms and nitrogen atoms, and the proportion of silicon atoms in the low-transmission layer is greater than the proportion of nitrogen atoms in the low-transmission layer.

[0009] According to some embodiments, the proportion of silicon atoms in the low-transmission layer is equal to or greater than about 55% and equal to or less than about 70%, and the proportion of nitrogen atoms in the low-transmission layer is equal to or greater than about 30% and equal to or less than about 45%.

[0010] According to some embodiments, the low-transmission layer has a thickness equal to or greater than about 1500 angstroms and equal to or less than about 3000 angstroms.

[0011] According to some embodiments, the insulating layer further includes a first high-transmission layer on the low-transmission layer, and the first high-transmission layer has a light transmittance equal to or greater than about 80% and equal to or less than about 95%.

[0012] According to some embodiments, the first high-transmission layer contains silicon atoms and nitrogen atoms, and the proportion of nitrogen atoms in the first high-transmission layer is greater than the proportion of silicon atoms in the first high-transmission layer.

[0013] According to some embodiments, the insulating layer further includes a second high-transmission layer under the low-transmission layer, and the second high-transmission layer has a light transmittance equal to or greater than about 80% and equal to or less than about 95%.

[0014] According to some embodiments, the insulating layer further includes a stable layer under the second high-transmission layer, the stable layer contains silicon atoms, nitrogen atoms and oxygen atoms, and the proportion of oxygen atoms in the stable layer is greater than each of the proportion of silicon atoms in the stable layer and the proportion of nitrogen atoms in the stable layer.

[0015] According to some embodiments, the insulating layer further includes a third high-transmission layer between the second high-transmission layer and the stable layer, and the third high-transmission layer has a light transmittance equal to or greater than about 80% and equal to or less than about 95%.

[0016] According to some embodiments, the insulating layer has a thickness equal to or greater than about 2500 angstroms and equal to or less than about 5000 angstroms.

[0017] According to some embodiments, the semiconductor pattern includes a source region, a drain region, and an active region, the connection electrodes include a first connection electrode connected to the drain region and a second connection electrode connected to the source region, and the first connection electrode and the second connection electrode are in the same layer as the gate electrode.

[0018] According to some embodiments, the first connection electrode and the second connection electrode include the same material as the gate electrode.

[0019] According to some embodiments, the display device further includes a first conductive pattern and a second conductive pattern that are between the base substrate and the transistor and are spaced apart from each other in the plane (or in the plan view). According to some embodiments, the first conductive pattern is electrically connected to the drain region through the first connection electrode, and the second conductive pattern is electrically connected to the source region through the second connection electrode.

[0020] According to some embodiments, the gate insulating pattern layer includes a first insulating pattern, a second insulating pattern, and a third insulating pattern, the first insulating pattern overlaps with the first connection electrode, the second insulating pattern overlaps with the gate electrode, and the third insulating pattern overlaps with the second connection electrode.

[0021] According to some embodiments, the first connection electrode is connected to the first conductive pattern via a first contact hole defined by a first insulating pattern, and the second connection electrode is connected to the second conductive pattern via a second contact hole defined by a third insulating pattern.

[0022] According to some embodiments, the display device further includes a light-emitting element that is on the first connection electrode and the second connection electrode and includes a first electrode, a light-emitting layer, and a second electrode. According to some embodiments, the first electrode is electrically connected to the transistor through the first connection electrode.

[0023] According to some embodiments of the present disclosure, a display device includes a base substrate, a transistor on the base substrate and including a semiconductor pattern and a gate electrode, a gate insulating pattern layer on the semiconductor pattern, a connection electrode on the gate insulating pattern layer and connected to the semiconductor pattern via a contact hole, and an insulating layer on the connection electrode and the transistor. According to some embodiments, the insulating layer includes a low-transmission layer having a first light transmittance, and a high-transmission layer having a second light transmittance greater than the first light transmittance and located above or below the low-transmission layer.

[0024] According to some embodiments, the first light transmittance is equal to or greater than about 30% and equal to or less than about 65%, and the second light transmittance is equal to or greater than about 80% and equal to or less than about 95%.

[0025] According to some embodiments, the high-transmission layer includes a first high-transmission layer above the low-transmission layer and a second high-transmission layer below the low-transmission layer, and each of the first high-transmission layer and the second high-transmission layer has the second light transmittance.

[0026] According to some embodiments, the insulating layer further includes a third high-transmission layer below the second high-transmission layer and a stable layer below the third high-transmission layer.

[0027] According to some embodiments, the insulating layer has a thickness equal to or greater than about 2500 angstroms and equal to or less than about 5000 angstroms.

[0028] According to some embodiments, the low-transmission layer contains silicon atoms and nitrogen atoms, and the proportion of silicon atoms in the low-transmission layer is greater than the proportion of nitrogen atoms in the low-transmission layer.

[0029] According to some embodiments, the proportion of silicon atoms in the low-transmission layer is equal to or greater than about 55% and equal to or less than about 70%, and the proportion of nitrogen atoms in the low-transmission layer is equal to or greater than about 30% and equal to or less than about 45%.

[0030] According to some embodiments, the low-transmission layer has a thickness equal to or greater than about 1500 angstroms and equal to or less than about 3000 angstroms.

[0031] According to some embodiments of the present disclosure, a display device includes a low transmittance layer and also includes an insulating layer positioned on a connection electrode and a transistor. According to some embodiments, the light transmittance of the low transmittance layer may be set to be equal to or greater than about 30% and equal to or less than about 65%. Additionally, the number of dangling bonds included in the low transmittance layer is set to be equal to or less than about 5×10 18 spins / cm 3 。Accordingly, the deterioration of the transistor caused by external light can be relatively reduced by the low transmittance layer, no charge traps occur in the insulating layer, and image retention that occurs when the display panel is in operation is not visible from the outside. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects of embodiments of the present disclosure will become apparent from the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a perspective view of a display device according to some embodiments of the present disclosure;

[0034] Figure 2A is an exploded perspective view of a display device according to some embodiments of the present disclosure;

[0035] Figure 2B is a cross-sectional view of a display module according to some embodiments of the present disclosure;

[0036] Figure 3 is a plan view of a display panel according to some embodiments of the present disclosure;

[0037] Figure 4 is along Figure 3 a cross-sectional view taken along line I-I';

[0038] Figure 5A and Figure 5B are plan views corresponding to the circuit layer shown in Figure 4 ;

[0039] Figure 6 is Figure 4 an enlarged view of region AA' shown in;

[0040] Figure 7A is a graph showing the relationship between the content of nitrogen atoms included in a specific material and the light transmittance of the specific material;

[0041] Figure 7B is a graph showing the relationship between the light transmittance of a specific material and the number of dangling bonds included in the specific material;

[0042] Figures 8A to 8DAn enlarged view of a part of a display panel according to some embodiments of the present disclosure; and

[0043] Figure 9 A cross-sectional view of a display panel according to some embodiments of the present disclosure. Detailed Description

[0044] The present disclosure can be variously modified and implemented in many different forms, and thus aspects of some embodiments will be shown in the drawings and described in more detail below. However, the embodiments of the present disclosure are not limited to the specifically disclosed forms and should be construed to include all modifications, equivalents, or substitutions within the spirit and scope of the embodiments of the present disclosure.

[0045] In the present disclosure, it should be understood that when an element (or region, layer, or part) is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or there may be intervening elements or layers.

[0046] Throughout the specification, like reference numerals indicate like elements. In the drawings, the thickness, proportion, and dimensions of components are exaggerated for effective description of the technical content.

[0047] As used herein, the term "and / or" may include any and all combinations of one or more of the related listed items.

[0048] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" as used herein are also intended to include the plural forms.

[0049] Spatial relative terms such as "beneath", "below", "lower", "above", "upper", and the like may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features as shown in the various figures.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0051] It should also be understood that when the terms "include" and / or "including" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0052] Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0053] Figure 1 is a perspective view of a display device DD according to some embodiments of the present disclosure.

[0054] Referring to Figure 1 , the display device DD can be activated in response to an electrical signal and can display an image IM. The display device DD can include various embodiments that provide the image IM to a user. As an example, the display device DD can be applied to large electronic devices such as televisions, outdoor billboards, etc., and small and medium-sized electronic devices such as displays, mobile phones, tablet computers, navigation units, game units, etc. However, these are only examples, and the display device DD can be applied to other electronic devices as long as it does not deviate from the concept of the present disclosure.

[0055] The display device DD can have a generally rectangular shape including a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, the shape of the display device DD should not be limited to a rectangular shape, and the display device DD can have various shapes such as a circular shape, other polygonal shapes other than a rectangular shape, etc.

[0056] The display device DD can display the image IM through a display surface IS in a third direction DR3 perpendicular to the plane defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface IS can be parallel to the third direction DR3. The display surface IS on which the image IM is displayed can correspond to the front surface of the display device DD. The image IM can include a still image as well as a video. Figure 1 Shows an application icon as a representative example of the image IM.

[0057] In the present embodiment, the front (or upper) surface and the rear (or lower) surface of each component of the display device DD may be defined with respect to the third direction DR3. The front surface and the rear surface face each other along the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. The separation distance in the third direction DR3 between the front surface and the rear surface of each component may correspond to the thickness of the component in the third direction DR3.

[0058] In the present disclosure, the expression "when observed in a plane" or "in a plan view" may mean a state of observation from the third direction DR3 or along the third direction DR3. In the present disclosure, the expression "when observed in a cross section" may mean a state of observation in the first direction DR1 or the second direction DR2. At the same time, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are related to each other, and thus the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be changed to other directions.

[0059] Figure 1 As a representative example, a display device DD including a flat display surface IS is shown. However, the shape of the display surface IS of the display device DD should not be limited to this or restricted thereby, and the display surface IS may have a bent or three-dimensional shape.

[0060] The display device DD may be flexible. The term "flexible" used herein refers to the property of being able to bend, from a fully bent structure to a structure bent at the scale of a few nanometers. For example, the display device DD may be a bendable display device or a foldable display device. However, the embodiments according to the present disclosure are not limited to this or restricted thereby. According to some embodiments, the display device DD may be rigid.

[0061] The display surface IS of the display device DD may include a display portion D-DA and a non-display portion D-NDA. The display portion D-DA may be a portion where an image IM is displayed within the front surface of the display device DD, and a user may view the image IM through the display portion D-DA. According to some embodiments, the display portion D-DA having a quadrilateral shape in a plane (or in a plan view) is shown as a representative example. However, the display portion D-DA may have various shapes according to the design of the display device DD.

[0062] The non-display part D-NDA can be a part within the front surface of the display device DD where an image IM is not displayed. The non-display part D-NDA can have a color (e.g., a set or predetermined color) and can block light. The non-display part D-NDA can be positioned adjacent to the display part D-DA. As an example, the non-display part D-NDA can be positioned outside the display part D-DA and can surround the display part D-DA. However, this is only an example. The non-display part D-NDA can be defined as adjacent to only one side of the display part D-DA, or can be defined in the side surface of the display device DD rather than in the front surface. According to some embodiments, the non-display part D-NDA can be omitted.

[0063] According to some embodiments, the display device DD can sense an external input applied to it from the outside. The external input can include various external inputs provided from the outside, such as pressure, heat, light, etc. The external input can include a proximity input (e.g., a hover input) applied when approaching or being adjacent to the display device DD at a certain distance (e.g., a set or predetermined distance) and a touch input (e.g., a touch by a user's hand or pen).

[0064] Figure 2A is an exploded perspective view of a display device DD according to some embodiments of the present disclosure. Figure 2B is a cross-sectional view of a display module DM according to some embodiments of the present disclosure.

[0065] Referring to Figure 2A and Figure 2B As shown in FIGS. and, the display device DD can include a window WM, a display module DM, and a housing HAU. The display module DM can include a display panel DP and a light control member LCM positioned on the display panel DP.

[0066] The window WM can be coupled to the housing HAU to form the appearance of the display device DD and provide an internal space for accommodating components of the display device DD (e.g., the display module DM).

[0067] The window WM can be positioned on the display module DM. The window WM can protect the display module DM from external impacts and prevent damage to the components of the display device DD. The front surface of the window WM can correspond to the display surface IS of the display device DD. The front surface of the window WM can include a transmissive region TA and a border region BA.

[0068] The transmissive region TA of the window WM can be an optically transparent region. The window WM can transmit the image provided from the display module DM through the transmissive region TA, and the user can view the image. The transmissive region TA of the window WM can correspond to the display part D-DA of the display device DD.

[0069] The window WM may include an optically transparent insulating material. As an example, the window WM may include glass, sapphire, or a plastic material. The window WM may have a single-layer or multi-layer structure. The window WM may also include functional layers positioned on the optically transparent substrate, such as an anti-fingerprint layer, a phase control layer, a hard coating, etc.

[0070] The border area BA of the window WM may be obtained by depositing, coating, or printing a material having a color (e.g., a set or predetermined color) on the transparent substrate. The border area BA of the window WM may prevent or reduce the visibility from the outside of components of the display module DM arranged to overlap with the border area BA. The border area BA may correspond to the non-display portion D-NDA of the display device DD.

[0071] The display module DM may be positioned between the window WM and the housing HAU. The display module DM may display an image in response to an electrical signal. The display module DM may include a display area DA and a non-display area NDA defined adjacent to the display area DA (e.g., outside the periphery or coverage area of the display area DA).

[0072] The display area DA may be activated in response to an electrical signal and may display an image. The display area DA of the display module DM may overlap with the transmissive area TA of the window WM. In the present disclosure, the expression "an area / portion overlaps with another area / portion" should not be limited to the meaning of "the area / portion has the same dimensions and / or shape as the other area / portion". The image provided from the display area DA may be viewed from the outside through the transmissive area TA.

[0073] The non-display area NDA may be defined adjacent to the display area DA. As an example, the non-display area NDA may surround the display area DA, however, it should not be limited thereto or thereby. According to some embodiments, the non-display area NDA may be defined in various shapes. A driving circuit or driving lines for driving elements positioned in the display area DA, various signal lines for providing electrical signals to the elements, and pads may be positioned in the non-display area NDA. The non-display area NDA of the display module DM may overlap with the border area BA of the window WM, and the visibility from the outside of components of the display module DM positioned in the non-display area NDA may be prevented or reduced by the border area BA.

[0074] The display panel DP according to some embodiments may be a light-emitting type display panel, however, it should not be particularly limited. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and / or quantum rods. Hereinafter, the organic light-emitting display panel will be described as a representative example of the display panel DP.

[0075] The display panel DP may include a base substrate BS, a circuit layer DP-CL, a display element layer DP-OL, and a packaging layer TFE.

[0076] The base substrate BS may provide a base surface on which the circuit layer DP-CL is positioned. The base substrate BS may be a rigid substrate or a flexible substrate.

[0077] The circuit layer DP-CL may be positioned on the base substrate BS. The circuit layer DP-CL may include driving elements such as transistors, signal lines, and signal pads. The display element layer DP-OL may include light-emitting elements arranged to overlap with a display area DA. The light-emitting elements of the display element layer DP-OL may be electrically connected to the driving elements of the circuit layer DP-CL and may emit light through the display area DA in response to signals from the driving elements.

[0078] The packaging layer TFE may be positioned on the display element layer DP-OL and may encapsulate the light-emitting elements. The packaging layer TFE may include a plurality of thin layers. The thin layers of the packaging layer TFE may improve the optical efficiency of the light-emitting elements or may protect the light-emitting elements.

[0079] The light control member LCM may be positioned on the display panel DP. The light control member LCM may be coupled to the display panel DP by a coupling process using a sealing member SML after being provided on the display panel DP.

[0080] However, according to some embodiments, the light control member LCM may be directly positioned on the display panel DP. In the present disclosure, a structure in which one layer, component, member, or the like is formed on another layer, component, member, or the like by a continuous process without using a separate adhesive layer or adhesive member will be referred to as "directly positioned". As an example, the statement "the light control member LCM is directly positioned on the display panel DP" means that the light control member LCM is formed on the base surface of the display panel DP by a continuous process without using a separate adhesive layer after the display panel DP is formed.

[0081] The light control member LCM may selectively convert the wavelength of light (i.e., source light) provided from the display panel DP or may selectively transmit the source light. For example, the light control member LCM may include a light conversion pattern that converts the optical properties of the source light provided from the display panel DP. The light control member LCM may control the color purity or color reproducibility of the light emitted from the display device DD and may prevent or reduce the reflection of external light incident on it from the outside of the display device DD.

[0082] The light control member LCM may include a base layer BL, a color filter layer CFL, and a light control layer CCL. The base layer BL may be arranged to face the base substrate BS of the display panel DP, and the color filter layer CFL and the light control layer CCL positioned on the base layer BL may be positioned between the display panel DP and the base layer BL.

[0083] The light control layer CCL may include quantum dots that convert the wavelength of the source light provided from the display panel DP, or may further include a transmissive portion that transmits the source light. The source light passing through the quantum dots included in the light control layer CCL may be emitted as colored light having a color different from the color of the source light.

[0084] The color filter layer CFL may include color filters, and the color filters may transmit or absorb the light passing through the light control layer CCL according to their colors. The color filter layer CFL may absorb the light not converted by the light control layer CCL, and thus may prevent or reduce the decrease in color purity of the display device DD. In addition, the color filter layer CFL may filter external light to have the same color as the color provided by the pixels, and may relatively reduce the reflection of external light.

[0085] The sealing member SML may be positioned in the non-display area NDA which is an external area of the display module DM, and may prevent or reduce the entry of contaminants or foreign substances (such as oxygen or moisture) from the outside of the display module DM into the display module DM. The sealing member SML may be formed of a sealant including a curable resin.

[0086] The display module DM may further include a filling layer FML positioned between the display panel DP and the light control member LCM. The filling layer FML may fill the space between the display panel DP and the light control member LCM. The filling layer FML may serve as a buffer between the display panel DP and the light control member LCM. According to some embodiments, the filling layer FML may absorb impacts and may increase the strength of the display module DM.

[0087] The filling layer FML may be formed of a filling resin including a polymer resin. As an example, the filling layer FML may include an acrylic-based resin or an epoxy-based resin. However, according to some embodiments, the light control member LCM may be directly positioned on the display panel DP, and the filling layer FML and the sealing member SML may be omitted. In the case where the light control member LCM is directly positioned on the display panel DP, the base layer BL of the light control member LCM may be omitted.

[0088] The housing HAU can be positioned below the display module DM and can accommodate the display module DM. The housing HAU can absorb the impact applied to the display module DM from the outside (thereby preventing or reducing damage to the internal components of the display device DD) and can prevent or reduce the entry of contaminants or foreign substances (such as moisture) into the display module DM, and thus, the display module DM can be protected by the housing HAU. According to some embodiments, the housing HAU can be provided in a form obtained by coupling a plurality of accommodating members.

[0089] Meanwhile, the display device DD may further include an input sensing module. The input sensing module can obtain coordinate information of an external input applied to it from the outside of the display device DD. The input sensing module of the display device DD can be driven in various ways such as a capacitive method, a resistive method, an infrared method, a pressure method, or a similar method, and it should not be particularly limited.

[0090] The input sensing module can be positioned on the display module DM. The input sensing module can be directly positioned on the display module DM through a continuous process, or can be attached to the display module DM through an adhesive layer after being separately manufactured from the display module DM. However, the present disclosure should not be limited to this or be restricted thereby. According to some embodiments, the input sensing module can be positioned between components of the display module DM. As an example, the input sensing module can be positioned between the display panel DP and the light control member LCM.

[0091] Figure 3 is a plan view of a display panel DP according to some embodiments of the present disclosure.

[0092] Referring to Figure 3 , the display panel DP may include pixels PX11 to PXnm positioned in the display area DA, and signal lines SL1 to SLn and DL1 to DLm electrically connected to the pixels PX11 to PXnm, where n and m are positive integers greater than 0. The display panel DP may include a driving circuit GDC and pads PD positioned in the non-display area NDA.

[0093] Each of the pixels PX11 to PXnm may include a pixel driving circuit configured to include a light-emitting element, a plurality of transistors (such as a switching transistor, a driving transistor, etc.) connected to the light-emitting element, and a capacitor. Each of the pixels PX11 to PXnm can emit light in response to an electrical signal applied to it. Figure 3 Pixels PX11 to PXnm arranged in a matrix form are shown as a representative example, however, the arrangement of the pixels PX11 to PXnm should not be limited to this or be restricted thereby.

[0094] The signal lines SL1 to SLn and DL1 to DLm may include the scan lines SL1 to SLn and the data lines DL1 to DLm. Each of the pixels PX11 to PXnm may be connected to a corresponding one of the scan lines SL1 to SLn and a corresponding one of the data lines DL1 to DLm. At the same time, depending on the configuration of the pixel driving circuits for the pixels PX11 to PXnm, more types of signal lines may also be provided in the display panel DP.

[0095] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate gate signals and may sequentially output the gate signals to the scan lines SL1 to SLn. The gate driving circuit may also output another control signal to the pixel driving circuits of the pixels PX11 to PXnm.

[0096] The driving circuit GDC and the pixels PX11 to PXnm may include a plurality of transistors formed by a process (e.g., a low temperature polycrystalline silicon (LTPS) process, a low temperature polycrystalline oxide (LTPO) process, or an oxide semiconductor process).

[0097] The pads PD may be arranged in the non-display area NDA in one direction. The pads PD may be connected to a circuit board. Each of the pads PD may be connected to a corresponding one of the signal lines SL1 to SLn and DL1 to DLm and may be connected to a corresponding one of the pixels PX11 to PXnm via the corresponding signal line. The pads PD may be provided integrally with the signal lines SL1 to SLn and DL1 to DLm, however, they should not be limited thereto or thereby. According to some embodiments, the pads PD may be positioned in a layer different from the signal lines SL1 to SLn and DL1 to DLm and may be connected to the signal lines SL1 to SLn and DL1 to DLm via contact holes.

[0098] Figure 4 is a cross-sectional view taken along the Figure 3 line I-I'. Figure 5A and Figure 5B are plan views corresponding to the circuit layers shown in Figure 4 . Specifically, Figure 5A is a plan view showing the connection electrodes CNE1 and CNE2 and the transistor TR, and Figure 5B is a plan view showing the first conductive pattern CPT1 and the second conductive pattern CPT2 in addition to Figure 5A the connection electrodes CNE1 and CNE2 and the transistor TR. Hereinafter, the display panel DP will be described with reference to Figure 4 , Figure 5A and Figure 5B .

[0099] Referring to Figure 4, the display panel DP may include a base substrate BS, a circuit layer DP-CL, a display element layer DP-OL, and a packaging layer TFE.

[0100] The circuit layer DP-CL may include conductive patterns CPT1 and CPT2 positioned on the base substrate BS, transistors TR, connection electrodes CNE1 and CNE2, a buffer layer BFL, a gate insulating pattern layer GIL, and insulating layers INS1 and INS2.

[0101] Each of the first conductive pattern CPT1 and the second conductive pattern CPT2 may have a multi-layer structure. The first conductive pattern CPT1 and the second conductive pattern CPT2 may be formed of the same material and may have the same stacking structure. As an example, each of the first conductive pattern CPT1 and the second conductive pattern CPT2 may include a first pattern layer PT1 and a second pattern layer PT2 stacked on the base substrate BS in the thickness direction. However, the embodiments according to the present disclosure are not limited to this or restricted thereby. According to some embodiments, each of the first conductive pattern CPT1 and the second conductive pattern CPT2 may have a single-layer structure, or may have a multi-layer structure in which the number of stacked pattern layers is greater than Figure 4 the number of pattern layers shown in

[0102] The first pattern layer PT1 and the second pattern layer PT2 may have different thicknesses from each other. As an example, the thickness of the first pattern layer PT1 may be less than the thickness of the second pattern layer PT2. However, the embodiments according to the present disclosure are not limited to this or restricted thereby.

[0103] Each of the first pattern layer PT1 and the second pattern layer PT2 may include one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, the first pattern layer PT1 may include titanium (Ti), and the second pattern layer PT2 may include copper (Cu). However, the embodiments according to the present disclosure are not limited to this or restricted thereby.

[0104] The buffer layer BFL may be positioned on the base substrate BS to cover the first conductive pattern CPT1 and the second conductive pattern CPT2. The buffer layer BFL may include at least one inorganic layer.

[0105] Referring to Figure 4 and Figure 5A , the transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be positioned on the buffer layer BFL. The adhesion between the semiconductor pattern SP and the base substrate BS may be relatively improved by the buffer layer BFL. The semiconductor pattern SP may include a semiconductor material such as polysilicon, single-crystal silicon, or metal oxide.

[0106] The source region S-A, the active region A-A, and the drain region D-A of the transistor TR can be formed from the semiconductor pattern SP. The semiconductor pattern SP can have different electrical properties depending on whether it is doped or the metal oxide is reduced. The source region S-A and the drain region D-A of the semiconductor pattern SP having relatively high conductivity can be used as electrodes or signal lines. The undoped portion, the portion doped with a low doping concentration, or the unreduced portion of the semiconductor pattern SP can correspond to the active region A-A having relatively low conductivity.

[0107] The conductive regions CA can be spaced apart from each other with a non-conductive region NCA interposed therebetween. The conductive regions CA can correspond to the source region S-A and the drain region D-A of the semiconductor pattern SP, and the non-conductive region NCA can correspond to the channel region of the semiconductor pattern SP.

[0108] At least one hole HO can be defined through the semiconductor pattern SP. The hole HO can be formed during an etching process for forming the connection electrodes CNE1 and CNE2 and the gate electrode GE. Figure 4 A structure in which the holes HO are formed through the semiconductor pattern SP and spaced apart from each other is shown as a representative example. Among the holes HO, when viewed in a plane (or in a plan view), one hole HO can be surrounded by the source region S-A, and the other hole HO can be surrounded by the drain region D-A. However, the present disclosure should not be limited to this or restricted thereby. According to some embodiments, depending on the process for forming the circuit layer DP-CL, the hole HO may not be formed through the semiconductor pattern SP.

[0109] The gate insulating pattern layer GIL can be positioned on the buffer layer BFL. The gate insulating pattern layer GIL can include at least one inorganic layer. The gate insulating pattern layer GIL can include a first insulating pattern GI1, a second insulating pattern GI2, and a third insulating pattern GI3 that are spaced apart from each other. The first insulating pattern GI1 can cover a portion of the drain region D-A and can be positioned above the first conductive pattern CPT1. The second insulating pattern GI2 can be positioned in the active region A-A. The third insulating pattern GI3 can cover a portion of the source region S-A and can be positioned above the second conductive pattern CPT2.

[0110] Refer to Figure 4 and Figure 5B, the connection electrodes CNE1 and CNE2 may include a first connection electrode CNE1 and a second connection electrode CNE2. The first connection electrode CNE1 may be positioned on the first insulating pattern GI1. The first connection electrode CNE1 may be connected to the first conductive pattern CPT1 via a first contact hole CH1 defined by the buffer layer BFL and the first insulating pattern GI1. The first connection electrode CNE1 may contact a part of the drain region D-A and may be connected to the drain region D-A. The drain region D-A and the first conductive pattern CPT1 may be electrically connected to each other through the first connection electrode CNE1. As the first conductive pattern CPT1 with high conductivity is connected to the drain region D-A, the current transmission characteristics may be improved.

[0111] The second connection electrode CNE2 may be positioned on the third insulating pattern GI3. The second connection electrode CNE2 may be connected to the second conductive pattern CPT2 via a second contact hole CH2 defined by the buffer layer BFL and the third insulating pattern GI3. The second connection electrode CNE2 may contact a part of the source region S-A and may be connected to the source region S-A. The source region S-A and the second conductive pattern CPT2 may be electrically connected to each other through the second connection electrode CNE2. The second connection electrode CNE2 may be connected to a power line that supplies power to the light-emitting element OL, and thus may supply a first voltage to the transistor TR.

[0112] The gate electrode GE may be positioned on the second insulating pattern GI2. The gate electrode GE may overlap with the active region A-A when viewed in a plane (or in a plan view), and may be spaced apart from the semiconductor pattern SP by the second insulating pattern GI2 interposed therebetween in the thickness direction.

[0113] When viewed in a plane (or in a plan view), the connection electrodes CNE1 and CNE2 may be spaced apart from the gate electrode GE. Each of the connection electrodes CNE1 and CNE2 and the gate electrode GE may have a multilayer structure in which conductive layers ML1, ML2, and ML3 including materials different from each other are stacked. The conductive layers ML1, ML2, and ML3 may include a first conductive layer ML1, a second conductive layer ML2, and a third conductive layer ML3. The first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may be stacked by a sputtering process. However, the present disclosure should not be limited to this or restricted thereby.

[0114] Each of the first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may include a metallic material. As an example, each of the first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In addition, each of the first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may include indium tin oxide (ITO). The first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may include different metallic materials from each other. The second conductive layer ML2 may include a metallic material having high conductivity, and the first conductive layer ML1 and the third conductive layer ML3 respectively positioned under and above the second conductive layer ML2 may include metallic materials having corrosion resistance. As an example, the first conductive layer ML1 may include titanium (Ti), the second conductive layer ML2 may include copper (Cu), and the third conductive layer ML3 may include indium tin oxide (ITO). However, the present disclosure should not be limited to this or be restricted thereby.

[0115] The first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may have different thicknesses from each other. As an example, the second conductive layer ML2 including a metallic material having high conductivity may have the maximum thickness among the first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3. Accordingly, the connection electrodes CNE1 and CNE2 and the gate electrode GE formed from the first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may have low resistance and high conductivity.

[0116] In Figure 4 , the connection electrodes CNE1 and CNE2 and the gate electrode GE having a multilayer structure (e.g., a three-layer structure) are shown as representative examples. However, the present disclosure should not be limited to this or be restricted thereby. According to some embodiments, the connection electrodes CNE1 and CNE2 and the gate electrode GE may have a multilayer structure with fewer or more than three layers, or may have a single-layer structure.

[0117] The connection electrodes CNE1 and CNE2 and the gate electrode GE may be formed substantially simultaneously through the same process. The connection electrodes CNE1 and CNE2 and the gate electrode GE may have the same stacking structure as each other. As an example, the connection electrodes CNE1 and CNE2 and the gate electrode GE may have a three-layer structure of Ti / Cu / ITO. However, the present disclosure should not be limited to this or be restricted thereby. As the connection electrodes CNE1 and CNE2 and the gate electrode GE are formed substantially simultaneously through the same process, the manufacturing process of the display panel DP may be simplified.

[0118] The first insulating layer INS1 may be positioned on the gate insulating pattern layer GIL to cover the connection electrodes CNE1 and CNE2 and the gate electrode GE. The second insulating layer INS2 (or insulating layer) may be positioned on the first insulating layer INS1. Each of the first insulating layer INS1 and the second insulating layer INS2 may include at least one inorganic layer or organic layer. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the present disclosure should not be limited to this or restricted thereby. The organic layer may include a phenolic polymer, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a parylene polymer, a vinyl alcohol polymer, or a blend thereof. However, the materials for the organic layer should not be limited to this or restricted thereby.

[0119] According to some embodiments, at least one of the first insulating layer INS1 and the second insulating layer INS2 may include a low transmission layer LTL (refer to Figure 6 ). As an example, the second insulating layer INS2 may include the low transmission layer LTL. The low transmission layer LTL will be described in detail later.

[0120] The display element layer DP-OL may be positioned on the circuit layer DP-CL. The display element layer DP-OL may include a pixel defining layer PDL and a light emitting element OL. As an example, the light emitting element OL may include an organic light emitting element, an inorganic light emitting element, a quantum dot light emitting element, a micro LED, or a nano LED. However, the present disclosure should not be limited to this or restricted thereby. The light emitting element OL may include various embodiments as long as it generates light or controls the amount of light according to an electrical signal.

[0121] The pixel defining layer PDL may be positioned on the second insulating layer INS2 of the circuit layer DP-CL. The pixel defining layer PDL may include a polymer resin. As an example, the pixel defining layer PDL may include a polyacrylate-based resin or a polyimide-based resin. In addition to the polymer resin, the pixel defining layer PDL may further include an inorganic material. According to some embodiments, the pixel defining layer PDL may include an inorganic material. As an example, the pixel defining layer PDL may include silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ).

[0122] The pixel defining layer PDL may include a light absorbing material. The pixel defining layer PDL may include a black colorant. The black colorant may include a black pigment or a black dye. The black colorant may include a metal material such as chromium or its oxide. In addition, the black colorant may include carbon black. However, the pixel defining layer PDL should not be limited to this or restricted thereby.

[0123] The light-emitting element OL may include a first electrode AE, a hole transport region HCL, a light-emitting layer EML, an electron transport region ECL, and a second electrode CE that are sequentially stacked.

[0124] The first electrode AE may be positioned on a second insulating layer INS2 of a circuit layer DP-CL. The first electrode AE may be connected to a first connection electrode CNE1 via a contact hole CHa defined through a first insulating layer INS1 and the second insulating layer INS2. As the first electrode AE is connected to the first connection electrode CNE1, a drain region D-A may be connected to the light-emitting element OL through the first connection electrode CNE1.

[0125] The pixel defining layer PDL may be provided with a light-emitting opening PX-OP defined therethrough to expose at least a portion of the first electrode AE. The portion of the first electrode AE exposed through the light-emitting opening PX-OP may correspond to a light-emitting region PXA. The region where the pixel defining layer PDL is located may correspond to a non-light-emitting region NPXA. The non-light-emitting region NPXA may surround the light-emitting region PXA.

[0126] The hole transport region HCL may be positioned on the first electrode AE. The hole transport region HCL may include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer. According to some embodiments, the hole transport region HCL may include a plurality of hole transport layers.

[0127] The light-emitting layer EML may be positioned on the hole transport region HCL. The light-emitting layer EML may have a single-layer structure of a single material, a single-layer structure of different materials, or a multi-layer structure including layers of different materials. According to some embodiments, the light-emitting layer EML may generate blue light as a light source. However, the present disclosure should not be limited to this or be restricted thereby. The display element layer DP-OL may include a plurality of light-emitting elements OL each including a plurality of light-emitting layers EML that emit light having different wavelengths from each other.

[0128] The light-emitting layer EML may be provided in the form of a light-emitting pattern to be placed in a region corresponding to the light-emitting opening PX-OP. However, the present disclosure should not be limited to this or be restricted thereby. According to some embodiments, the light-emitting layer EML may be provided as a common layer overlapping the light-emitting region PXA and the non-light-emitting region NPXA.

[0129] The electron transport region ECL may be positioned on the light-emitting layer EML. The electron transport region ECL may include at least one of a hole blocking layer, an electron transport layer, and an electron injection layer. However, the present disclosure should not be limited to this or be restricted thereby.

[0130] The hole transport layer HCL, the light emitting layer EML, and the electron transport layer ECL can be formed by various methods such as vacuum deposition methods, spin coating methods, casting methods, LB (Langmuir - Blodgett) methods, inkjet printing methods, laser printing methods, LITI (laser induced thermal imaging) methods, etc.

[0131] The second electrode CE can be positioned on the electron transport layer ECL. The second electrode CE can be a common electrode. That is, the second electrode CE can be provided as a common layer to overlap the entire area of the light emitting region PXA and the non - light emitting region NPXA.

[0132] The encapsulation layer TFE can cover the light emitting element OL. The encapsulation layer TFE can encapsulate the display element layer DP - OL. The encapsulation layer TFE can include at least one insulating layer. According to some embodiments, the encapsulation layer TFE can include at least one inorganic layer (hereinafter referred to as the encapsulation inorganic layer). According to some embodiments, the encapsulation layer TFE can include a plurality of encapsulation inorganic layers and at least one organic layer (hereinafter referred to as the encapsulation organic layer) positioned between the plurality of encapsulation inorganic layers.

[0133] The encapsulation inorganic layer can protect the display element layer DP - OL from moisture and oxygen, and the encapsulation organic layer can protect the display element layer DP - OL from foreign substances such as dust particles. The encapsulation inorganic layer can include silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide, however, it should not be limited thereto or thereby. The encapsulation organic layer can include acrylic - based compounds, epoxy - based compounds, or the like. The encapsulation organic layer can include a photopolymerizable organic material and should not be particularly limited.

[0134] Figure 6 Yes Figure 4 is an enlarged view of the region AA' shown in Figure 7A is a graph showing the relationship between the content of nitrogen atoms contained in a specific material and the light transmittance of the specific material, and Figure 7B is a graph showing the relationship between the light transmittance of a specific material and the number of dangling bonds contained in the specific material.

[0135] Refer to Figure 6 According to , the second insulating layer INS2 can include a low - transmittance layer LTL and a high - transmittance layer HTL. The high - transmittance layer HTL can be positioned on the low - transmittance layer LTL.

[0136] According to some embodiments, the low transmittance layer LTL may have a lower light transmittance than the high transmittance layer HTL. The light transmittance of the low transmittance layer LTL may be referred to as the first light transmittance, and the light transmittance of the high transmittance layer HTL may be referred to as the second light transmittance. The first light transmittance may be equal to or greater than 30% (or about 30%) and equal to or less than 65% (or about 65%), and the second light transmittance may be equal to or greater than 80% (or about 80%) and equal to or less than 95% (or about 95%). The light transmittance is a value indicating the degree to which a material layer absorbs light. Specifically, the light transmittance is expressed as a value obtained by dividing the intensity of the transmitted light from the outside by the intensity of the incident light.

[0137] The low transmittance layer LTL may include silicon atoms (Si) and nitrogen atoms (N). According to some embodiments, the proportion of silicon atoms (Si) contained in the low transmittance layer LTL may be greater than the proportion of nitrogen atoms (N) contained in the low transmittance layer LTL. As an example, the proportion of silicon atoms in the low transmittance layer LTL may be equal to or greater than 55% (or about 55%) and equal to or less than 70% (or about 70%), and the proportion of nitrogen atoms in the low transmittance layer LTL may be equal to or greater than 30% (or about 30%) and equal to or less than 45% (or about 45%). The ratio of ammonia (NH3) gas to silane (SiH4) gas used in the process of forming the low transmittance layer LTL may be equal to or greater than 0.5:1 (or about 0.5:1) and equal to or less than 1.3:1 (or about 1.3:1). That is, the value obtained by dividing the proportion of ammonia (NH3) gas by the proportion of silane (SiH4) gas may be equal to or greater than 0.5 (or about 0.5) and equal to or less than 1.3 (or about 1.3). As a result, the proportion of silicon atoms in the low transmittance layer LTL may be equal to or greater than 55% (or about 55%) and equal to or less than 70% (or about 70%), and the proportion of nitrogen atoms in the low transmittance layer LTL may be equal to or greater than 30% (or about 30%) and equal to or less than 45% (or about 45%).

[0138] The present disclosure should not be limited to this or restricted thereby, and the low transmittance layer LTL may include an organic material. The organic material may include a phenolic polymer, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a parylene polymer, a vinyl alcohol polymer, or a blend thereof. However, the organic material should not be limited to this or restricted thereby.

[0139] Referring to Figure 7A , it is observed that the content ratio of nitrogen atoms in a specific material and the light transmittance of the specific material are directly proportional to each other. That is, as the content ratio of nitrogen atoms contained in a specific material increases, the light transmittance of the specific material may increase. Referring to Figure 6 and Figure 7AWhen the proportion of nitrogen atoms in the low transmittance layer LTL is set to be equal to or greater than 30% (or about 30%) and equal to or less than 45% (or about 45%), the first light transmittance can be equal to or greater than 30% (or about 30%) and equal to or less than 65% (or about 65%).

[0140] Refer to Figure 7B It has been observed that the light transmittance of a specific material and the number of dangling bonds contained in the specific material are inversely proportional to each other. That is, as the light transmittance of the specific material increases, the number of dangling bonds in the specific material can gradually decrease. A dangling bond refers to an atom separated from a covalent bond pair, thus leaving a vacancy where a silicon atom (Si) does not form a bond and remains unpaired in a surface bonding manner. When the number of dangling bonds increases, a large amount of electron scattering occurs due to the dangling bonds during electron flow, making it difficult for the current to flow smoothly. Additionally, when the number of dangling bonds increases, charge traps may appear, thereby trapping electrons and holes in the corresponding trap regions. As a result, the electrons or holes trapped in the trap regions can be blocked from moving and are prevented from recombining with opposite charges to form electron / hole pairs.

[0141] When Figure 4 When the number of dangling bonds in the first insulating layer INS1 or the second insulating layer INS2 shown in increases and charge traps are generated, an electric field can be formed even when the display panel DP is not operating. Therefore, image retention that appears when the display panel DP is operating can be visible from the outside. When the number of dangling bonds is equal to or less than 5×10 18 spins / cm 3 (or about 5×10 18 spins / cm 3 ), charge traps may not be generated. Accordingly, an electric field may not be formed when the display panel DP is not operating, and image retention that appears when the display panel DP is operating may not be visible from the outside. Additionally, when the light transmittance is equal to or less than 65% (or about 65%), the deterioration of the transistor TR caused by external light can be relatively reduced.

[0142] Refer to Figures 6 to 7B When the proportion of nitrogen atoms contained in the low transmittance layer LTL is set to be equal to or greater than 30% (or about 30%) and equal to or less than 45% (or about 45%), the first light transmittance can be set to be equal to or greater than 30% (or about 30%) and equal to or less than 65% (or about 65%). Additionally, when the first light transmittance is set to be equal to or greater than 30% (or about 30%) and equal to or less than 65% (or about 65%), the number of dangling bonds contained in the low transmittance layer LTL can be set to be equal to or greater than 3×10 18 spins / cm 3 (or about 3×1018 spins / cm 3 ) and is equal to or less than 5×10 18 spins / cm 3 (or approximately 5×10 18 spins / cm 3 ). That is, the deterioration of the transistor TR caused by external light can be relatively reduced through the low-transmission layer LTL included in the second insulating layer INS2, and charge traps may not be generated in the second insulating layer INS2. Accordingly, image sticking that occurs when the display panel DP is in operation may not be visible to the outside. As a result, the reliability of the display panel DP can be improved.

[0143] According to some embodiments, the low-transmission layer LTL may have a hydrogen emission amount equal to or less than 5×10 21 moles / cm 3 (or approximately 5×10 21 moles / cm 3 ). As an example, the hydrogen emission amount of the low-transmission layer LTL may be equal to or greater than 1×10 21 moles / cm 3 (or approximately 1×10 21 moles / cm 3 ) and equal to or less than 5×10 21 moles / cm 3 (or approximately 5×10 21 moles / cm 3 ). The hydrogen gas used in the process of forming the low-transmission layer LTL may be set to be greater than 0 sccm (or approximately 0 sccm) and equal to or less than 2000 sccm (or approximately 2000 sccm), and the reference voltage (RF power) may be set to be equal to or greater than 8000 W (or approximately 8000 W) and equal to or less than 15000 W (or approximately 15000 W) to form a low-transmission layer LTL having a hydrogen emission amount equal to or greater than 1×10 21 moles / cm 3 (or approximately 1×10 21 moles / cm 3 ) and equal to or less than 5×10 21 moles / cm 3 (or approximately 5×10 21 moles / cm 3 ). The RF power refers to the power used to generate plasma to form the low-transmission layer LTL.

[0144] According to some embodiments, the low-transmission layer LTL may have an amount equal to or greater than (or approximately ) and equal to or less than (or approximately ) the thickness d1. As an example, it is preferable that the thickness d1 of the low-transmission layer LTL, which can be required for relatively reducing the deterioration of the transistor TR caused by external light, is equal to or greater than (or about ).

[0145] The high-transmission layer HTL can be positioned between the low-transmission layer LTL and the first electrode AE. The high-transmission layer HTL can protect the transistor TR (refer to Figure 4 ) positioned below the first insulating layer INS1 from moisture and oxygen. The high-transmission layer HTL can contain silicon atoms (Si) and nitrogen atoms (N). According to some embodiments, the proportion of nitrogen atoms in the high-transmission layer HTL can be equal to or greater than 45% (or about 45%). According to some embodiments, the proportion of nitrogen atoms in the high-transmission layer HTL can be greater than the proportion of silicon atoms in the high-transmission layer HTL. However, the embodiments according to the present disclosure are not limited to this or restricted thereby, and the high-transmission layer HTL can include an organic material. The organic material can include phenolic polymers, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, vinyl alcohol polymers, or blends thereof. However, the organic material should not be limited to this or restricted thereby.

[0146] According to the present disclosure, as the proportion of nitrogen atoms contained in the high-transmission layer HTL is set to be equal to or greater than 45% (or about 45%), the second light transmittance can be set to be equal to or greater than 75% (or about 75%). For example, the second light transmittance can be equal to or greater than 80% (or about 80%) and equal to or less than 95% (or about 95%). As the second light transmittance is set to be equal to or greater than 80% (or about 80%) and equal to or less than 95% (or about 95%), the number of dangling bonds contained in the high-transmission layer HTL can be set to be equal to or greater than 1×10 18 spins / cm 3 (or about 1×10 18 spins / cm 3 ) and equal to or less than 2×10 18 spins / cm 3 (or about 2×10 18 spins / cm 3 ).

[0147] According to the present disclosure, the high-transmission layer HTL can have a hydrogen emission amount equal to or less than 5×10 21 mol / cm 3 (or about 5×10 21 mol / cm 3 ). As an example, the hydrogen emission amount of the high-transmission layer HTL can be equal to or greater than 1×10 21 mol / cm 3(or about 1×10 21 mol / cm 3 ) and equal to or less than 5×10 21 mol / cm 3 (or about 5×10 21 mol / cm 3 ). The second insulating layer INS2 including the low-transmission layer LTL and the high-transmission layer HTL may have a thickness d2 equal to or greater than (or about ) and equal to or less than (or about ).

[0148] Figures 8A to 8D is an enlarged view of a part of a display panel according to some embodiments of the present disclosure. In Figures 8A to 8D , the same reference numerals represent Figures 1 to 6 the same elements in, and thus detailed descriptions of the same elements will be omitted.

[0149] Referring to Figure 8A , the second insulating layer INS2a may include a stable layer STL, a low-transmission layer LTL, and a high-transmission layer HTL. The low-transmission layer LTL and the high-transmission layer HTL may include configurations substantially the same as those of the low-transmission layer LTL and the high-transmission layer HTL described with reference to Figure 6 .

[0150] The stable layer STL may contain silicon atoms (Si), oxygen atoms (O), and nitrogen atoms (N). The proportion of oxygen atoms in the stable layer STL may be greater than each of the proportion of silicon atoms in the stable layer STL and the proportion of nitrogen atoms in the stable layer STL. As an example, the proportion of oxygen atoms in the stable layer STL may be equal to or greater than 45% (or about 45%) and equal to or less than 60% (or about 60%), the proportion of silicon atoms in the stable layer STL may be equal to or greater than 20% (or about 20%) and equal to or less than 35% (or about 35%), and the proportion of nitrogen atoms in the stable layer STL may be equal to or greater than 10% (or about 10%) and equal to or less than 25% (or about 25%). The stable layer STL may be formed by a deposition process such as a chemical vapor deposition process. The stable layer STL may increase the adhesion between the first insulating layer INS1 and the low-transmission layer LTL.

[0151] According to some embodiments, the stable layer STL may have a hydrogen emission amount equal to or less than 7×10 21 mol / cm 3 (or about 7×10 21 mol / cm 3 ). As an example, the hydrogen emission amount of the stable layer STL may be equal to or greater than 5×10 21 mol / cm 3 (or about 5×1021 mol / cm 3 ) and is equal to or less than 7×10 21 mol / cm 3 (or approximately 7×10 21 mol / cm 3 ).

[0152] Referring to Figure 8B , the second insulating layer INS2b may include a stable layer STL, a low-transmission layer LTL, and first, second, and third high-transmission layers HTL1, HTL2, and HTL3. The first high-transmission layer HTL1 positioned on the low-transmission layer LTL may include a configuration substantially the same as the high-transmission layer HTL described with reference to Figure 6 .

[0153] The second high-transmission layer HTL2 and the third high-transmission layer HTL3 may be positioned between the low-transmission layer LTL and the stable layer STL. The second high-transmission layer HTL2 and the third high-transmission layer HTL3 may protect the transistor TR positioned under the first insulating layer INS1 (refer to Figure 4 ) from moisture and oxygen. Each of the second high-transmission layer HTL2 and the third high-transmission layer HTL3 may have a light transmittance equal to or greater than 80% and equal to or less than 95%. The second high-transmission layer HTL2 and the third high-transmission layer HTL3 may contain silicon atoms (Si) and nitrogen atoms (N). According to some embodiments, the proportion of nitrogen atoms in each of the second high-transmission layer HTL2 and the third high-transmission layer HTL3 may be equal to or greater than 45% (or approximately 45%). Specifically, the proportion of nitrogen atoms in the second high-transmission layer HTL2 may be equal to or greater than 45% (or approximately 45%), and the proportion of nitrogen atoms in the third high-transmission layer HTL3 may be equal to or greater than 50% (or approximately 50%). The proportion of nitrogen atoms in the third high-transmission layer HTL3 may be greater than the proportion of silicon atoms in the third high-transmission layer HTL3. Each of the second high-transmission layer HTL2 and the third high-transmission layer HTL3 may include an organic material. The organic material may include a phenolic polymer, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a parylene polymer, a vinyl alcohol polymer, or a blend thereof. However, the organic material should not be limited thereto or thereby.

[0154] Referring to Figure 8C , the second insulating layer INS2c may include a stable layer STL, first and second high-transmission layers HTL1 and HTL2, and first and second low-transmission layers LTL1 and LTL2. When compared with the second insulating layer INS2b shown in Figure 8B , the second insulating layer INS2c may include a second low-transmission layer LTL2 instead of the third high-transmission layer HTL3 (refer to Figure 8B ).

[0155] The second low transmittance layer LTL2 can be positioned between the stable layer STL and the second high transmittance layer HTL2. The second low transmittance layer LTL2 can include a configuration substantially the same as that of the first low transmittance layer LTL1. Each of the first low transmittance layer LTL1 and the second low transmittance layer LTL2 can contain silicon atoms (Si) and nitrogen atoms (N). The proportion of silicon atoms contained in each of the first low transmittance layer LTL1 and the second low transmittance layer LTL2 can be greater than the proportion of nitrogen atoms (N) contained in each of the first low transmittance layer LTL1 and the second low transmittance layer LTL2.

[0156] Each of the first low transmittance layer LTL1 and the second low transmittance layer LTL2 can have a first light transmittance. As an example, the first light transmittance can be equal to or greater than 30% (or about 30%) and equal to or less than 65% (or about 65%). The number of dangling bonds contained in each of the first low transmittance layer LTL1 and the second low transmittance layer LTL2 can be set to be equal to or greater than 3×10 18 spins / cm 3 (or about 3×10 18 spins / cm 3 ) and equal to or less than 5×10 18 spins / cm 3 (or about 5×10 18 spins / cm 3 ). As the second insulating layer INS2c includes the first low transmittance layer LTL1 and the second low transmittance layer LTL2, the deterioration of the transistor TR (refer to Figure 4 ) caused by external light can be relatively reduced. The components contained in the second insulating layer INS2c should not be limited to Figure 8C the components shown in, and the second insulating layer INS2c can also include a third low transmittance layer and a third high transmittance layer.

[0157] Refer to Figure 8D , the second insulating layer INS2d can include a first stable layer STL1, a first low transmittance layer LTL1a, and a first high transmittance layer HTL1, a second high transmittance layer HTL2, and a third high transmittance layer HTL3, and the first insulating layer INS1a can include a second stable layer STL2 and a second low transmittance layer LTL2a. The materials contained in the second insulating layer INS2d can be substantially the same as those of the second insulating layer INS2b shown in Figure 8B .

[0158] The second lowest transmission layer LTL2a may have a light transmittance equal to or greater than 30% (or about 30%) and equal to or less than 65% (or about 65%). The second lowest transmission layer LTL2a may include silicon atoms (Si) and nitrogen atoms (N). According to some embodiments, the proportion of silicon atoms included in the second lowest transmission layer LTL2a may be greater than the proportion of nitrogen atoms included in the second lowest transmission layer LTL2a. As an example, the proportion of silicon atoms in the second lowest transmission layer LTL2a may be equal to or greater than 55% (or about 55%) and equal to or less than 70% (or about 70%), and the proportion of nitrogen atoms in the second lowest transmission layer LTL2a may be equal to or greater than 30% (or about 30%) and equal to or less than 45% (or about 45%). The number of dangling bonds included in the second lowest transmission layer LTL2a may be equal to or greater than 3×10 18 spins / cm 3 (or about 3×10 18 spins / cm 3 ) and equal to or less than 5×10 18 spins / cm 3 (or about 5×10 18 spins / cm 3 ). The description of the second lowest transmission layer LTL2a may equally apply to the first lowest transmission layer LTL1a.

[0159] The second stable layer STL2 may include silicon atoms (Si), oxygen atoms (O), and nitrogen atoms (N). According to some embodiments, the proportion of oxygen atoms in the second stable layer STL2 may be greater than each of the proportion of silicon atoms and the proportion of nitrogen atoms in the second stable layer STL2. As an example, the proportion of oxygen atoms in the second stable layer STL2 may be equal to or greater than 45% (or about 45%) and equal to or less than 60% (or about 60%), the proportion of silicon atoms in the second stable layer STL2 may be equal to or greater than 20% (or about 20%) and equal to or less than 35% (or about 35%), and the proportion of nitrogen atoms in the second stable layer STL2 may be equal to or greater than 10% (or about 10%) and equal to or less than 25% (or about 25%). The second stable layer STL2 may be formed by a deposition process such as a chemical vapor deposition process. The second stable layer STL2 may increase the adhesion between the third conductive layer ML3 and the second lowest transmission layer LTL2a. The description of the second stable layer STL2 may equally apply to the first stable layer STL1.

[0160] According to some embodiments, as the first insulating layer INS1a includes the second lowest transmission layer LTL2a, the deterioration of the transistor TR (refer to Figure 4 ) caused by external light may be relatively reduced. In addition, since no charge traps occur in the first insulating layer INS1a, in the display panel DP (refer to Figure 4)Image residue generated during operation may be invisible to the outside.

[0161] Figure 9 It is a cross-sectional view of a display panel DPa according to some embodiments of the present disclosure.

[0162] Referring to Figure 9 , a conductive pattern CPT may be positioned on a base substrate BS. The conductive pattern CPT may receive a bias voltage. The conductive pattern CPT may receive a first voltage. The conductive pattern CPT may prevent or reduce the potential influence on the transistor TR caused by the polarization phenomenon. The conductive pattern CPT may prevent or reduce the situation where external light reaches the transistor TR. According to some embodiments, the conductive pattern CPT may be a floating electrode isolated from other electrodes or lines. The conductive pattern CPT may be arranged to correspond to the transistor TR. The conductive pattern CPT may include a metal material, for example, molybdenum.

[0163] A first connection electrode CNE1a may be positioned on a first insulating layer INS1b. The first connection electrode CNE1a may be connected to the conductive pattern CPT via a first contact hole CH1a defined through a buffer layer BFL and the first insulating layer INS1b. Additionally, the first connection electrode CNE1a may contact a part of the drain region D-A and may be connected to the drain region D-A. The drain region D-A and the conductive pattern CPT may be electrically connected to each other via the first connection electrode CNE1a. As the highly conductive conductive pattern CPT is connected to the drain region D-A, current transmission characteristics may be improved.

[0164] A second connection electrode CNE2a may be positioned on the first insulating layer INS1b. The second connection electrode CNE2a may be connected to the source region S-A via a second contact hole CH2a defined through the first insulating layer INS1b. The second connection electrode CNE2a may be connected to a power line that supplies power to the light-emitting element OL and may supply a first voltage to the transistor TR.

[0165] Each of the first connection electrode CNE1a and the second connection electrode CNE2a may have a multilayer structure in which conductive layers ML1a, ML2a, and ML3a including materials different from each other are stacked. The conductive layers ML1a, ML2a, and ML3a may include a first conductive layer ML1a, a second conductive layer ML2a, and a third conductive layer ML3a. The first conductive layer ML1a, the second conductive layer ML2a, and the third conductive layer ML3a may be stacked by a sputtering process. However, the present disclosure should not be limited to this or restricted thereby.

[0166] Each of the first conductive layer ML1a, the second conductive layer ML2a, and the third conductive layer ML3a may include a metallic material. For example, each of the first conductive layer ML1a, the second conductive layer ML2a, and the third conductive layer ML3a may include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In addition, each of the first conductive layer ML1a, the second conductive layer ML2a, and the third conductive layer ML3a may include indium tin oxide (ITO). The first conductive layer ML1a, the second conductive layer ML2a, and the third conductive layer ML3a may include different metallic materials from each other. The second conductive layer ML2a may include a metallic material having high conductivity, and the first conductive layer ML1a and the third conductive layer ML3a respectively positioned under and above the second conductive layer ML2a may include metallic materials having corrosion resistance. For example, the first conductive layer ML1a may include titanium (Ti), the second conductive layer ML2a may include copper (Cu), and the third conductive layer ML3a may include indium tin oxide (ITO). However, the present disclosure should not be limited to this or be restricted thereby.

[0167] The gate electrode GE may be positioned on the gate insulating pattern layer GIL. The gate electrode GE may overlap with the active region A-A when viewed in a plane (or in a plan view), and may be spaced apart from the active region A-A by the intervening gate insulating pattern layer GIL in the thickness direction.

[0168] When viewed in a plane (or in a plan view), the connection electrodes CNE1a and CNE2a may be spaced apart from the gate electrode GE. The connection electrodes CNE1a and CNE2a and the gate electrode GE may include different materials from each other. That is, Figure 4 different from the connection electrodes CNE1 and CNE2 and the gate electrode GE shown in, the connection electrodes CNE1a and CNE2a may be formed by a process separate from the gate electrode GE.

[0169] The first electrode AE can be positioned on the third insulating layer INS3 of the circuit layer DP-CL. The first electrode AE can be connected to the first connection electrode CNE1a via a contact hole CHb defined by the second insulating layer INS2e and the third insulating layer INS3. As the first electrode AE is connected to the first connection electrode CNE1a, the drain region D-A can be connected to the light-emitting element OL through the first connection electrode CNE1a. The third insulating layer INS3 can include at least one inorganic layer or organic layer. The inorganic layer can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the present disclosure should not be limited to this or restricted thereby. The organic layer can include a phenolic polymer, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a parylene polymer, a vinyl alcohol polymer, or a blend thereof. However, the material for the organic layer should not be limited to this or restricted thereby.

[0170] According to the present disclosure, at least one of the first insulating layer INS1b and the second insulating layer INS2e can include a low-transmission layer LTL (refer to Figure 6 ). As a result, the deterioration of the transistor TR caused by external light can be relatively reduced, and since no charge trapping occurs in the first insulating layer INS1b or the second insulating layer INS2e, the image residue generated when the display panel DPa is in operation can be invisible to the outside. Therefore, the reliability of the display panel DPa can be improved.

[0171] Although aspects of some embodiments of the present disclosure have been described, it should be understood that the embodiments according to the present disclosure should not be limited to these embodiments, but various changes and modifications can be made by those of ordinary skill in the art within the spirit and scope of the present disclosure as defined in the appended claims.

[0172] Therefore, the subject matter disclosed should not be limited to any single embodiment described herein, and the scope of the embodiments according to the present disclosure should be determined according to the appended claims and their equivalents.

Claims

1. A display device, comprising: base substrate; a transistor on the base substrate and including a semiconductor pattern and a gate electrode; a gate insulating pattern layer, the gate insulating pattern layer being on the semiconductor pattern; a connecting electrode on the gate insulating pattern layer and connected to the semiconductor pattern via a contact hole; as well as An insulating layer is on the connection electrode and the transistor, wherein the connection electrode is on the same layer as the gate electrode, and the insulating layer includes a low-transmittance layer having a light transmittance equal to or greater than 30% and equal to or less than 65%.

2. The display device according to claim 1, wherein: The low-transmittance layer includes silicon atoms and nitrogen atoms, and a ratio of the silicon atoms of the low-transmittance layer is greater than a ratio of the nitrogen atoms of the low-transmittance layer.

3. The display device according to claim 2, wherein: The ratio of the silicon atoms of the low-transmission layer is equal to or greater than 55% and equal to or less than 70%, and the ratio of the nitrogen atoms of the low-transmission layer is equal to or greater than 30% and equal to or less than 45%.

4. The display device according to claim 1, wherein: The low transmission layer has a thickness equal to or greater than 1500 angstroms and equal to or less than 3000 angstroms.

5. The display device according to claim 1, wherein: The insulating layer further includes a first high-transmission layer on the low-transmission layer, and the first high-transmission layer has a light transmittance equal to or greater than 80% and equal to or less than 95%.

6. The display device according to claim 5, wherein: The first high-transmittance layer includes silicon atoms and nitrogen atoms, and a ratio of the nitrogen atoms in the first high-transmittance layer is greater than a ratio of the silicon atoms in the first high-transmittance layer.

7. The display device according to claim 5, wherein: The insulating layer further includes a second high-transmission layer under the low-transmission layer, and the second high-transmission layer has a light transmittance equal to or greater than 80% and equal to or less than 95%.

8. The display device according to claim 7, wherein: The insulating layer further includes a stabilization layer under the second high-transmittance layer, the stabilization layer including silicon atoms, nitrogen atoms, and oxygen atoms, and a ratio of the oxygen atoms in the stabilization layer is greater than each of a ratio of the silicon atoms in the stabilization layer and a ratio of the nitrogen atoms in the stabilization layer.

9. The display device according to claim 8, wherein: The insulating layer further includes a third high-transmittance layer between the second high-transmittance layer and the stabilization layer, and the third high-transmittance layer has a light transmittance equal to or greater than 80% and equal to or less than 95%.

10. The display device according to claim 9, wherein: The insulating layer has a thickness equal to or greater than 2500 angstroms and equal to or less than 5000 angstroms.

11. The display device according to claim 1, wherein: The semiconductor pattern includes a source region, a drain region and an active region, and the connecting electrode includes: a first connection electrode connected to the drain region; and A second connection electrode is provided, the second connection electrode is connected to the source region, and the first connection electrode and the second connection electrode are at the same layer as the gate electrode.

12. The display device according to claim 11, wherein: The first connection electrode and the second connection electrode include the same material as the gate electrode.

13. The display device according to claim 11, further comprising: A first conductive pattern and a second conductive pattern, the first conductive pattern and the second conductive pattern are between the base substrate and the transistor and are spaced apart from each other in a plan view, wherein the first conductive pattern is electrically connected to the drain region through the first connecting electrode, and the second conductive pattern is electrically connected to the source region through the second connecting electrode.

14. The display device according to claim 13, wherein: The gate insulating pattern layer includes a first insulating pattern, a second insulating pattern, and a third insulating pattern, the first insulating pattern overlaps the first connecting electrode, the second insulating pattern overlaps the gate electrode, and the third insulating pattern overlaps the second connecting electrode.

15. The display device according to claim 14, wherein: The first connection electrode is connected to the first conductive pattern via a first contact hole defined by the first insulating pattern, and the second connection electrode is connected to the second conductive pattern via a second contact hole defined by the third insulating pattern.

16. The display device according to claim 11, further comprising: A light emitting element is provided on the first connection electrode and the second connection electrode and includes a first electrode, a light emitting layer, and a second electrode, wherein the first electrode is electrically connected to the transistor through the first connection electrode.

17. A display device, comprising: base substrate; a transistor on the base substrate and including a semiconductor pattern and a gate electrode; a gate insulating pattern layer, the gate insulating pattern layer being on the semiconductor pattern; a connecting electrode on the gate insulating pattern layer and connected to the semiconductor pattern via a contact hole; as well as an insulating layer, the insulating layer being on the connecting electrode and the transistor, the insulating layer comprising: a low-transmittance layer having a first light transmittance; as well as A high-transmittance layer has a second light transmittance greater than the first light transmittance and is on or under the low-transmittance layer.

18. The display device according to claim 17, wherein: The first light transmittance is equal to or greater than 30% and equal to or less than 65%, and the second light transmittance is equal to or greater than 80% and equal to or less than 95%.

19. The display device according to claim 17, wherein: The high transmission layer comprises: a first high-transmittance layer, the first high-transmittance layer being on the low-transmittance layer; and A second high-transmittance layer is below the low-transmittance layer, and each of the first high-transmittance layer and the second high-transmittance layer has the second light transmittance.

20. The display device according to claim 19, wherein: The insulating layer also includes: a third high-transmittance layer, the third high-transmittance layer being below the second high-transmittance layer; and A stabilizing layer is provided below the third high-transmittance layer.

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