Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a substrate which comprises a display area and a frame area surrounding the display area; a plurality of sub-pixels located in the display area; the multiple grid lines are located in the display area and the frame area and electrically connected with the multiple sub-pixels, and the multiple grid lines are configured to provide grid signals for the multiple sub-pixels; the grid driving circuit is located in the frame area and is connected with the plurality of grid lines; the at least one electrostatic protection unit is located in the frame area and connected with the grid line, the at least one electrostatic protection unit is configured to release static electricity in the preparation process of the display substrate, the electrostatic protection unit comprises at least one tip structure, and the extending direction of the tip structure intersects with the plane where the substrate is located.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, display technologies, and particularly to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, thin and light, bendable, and low cost. With the continuous development of display technologies, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and controlled by Thin Film Transistors (TFT) have become the mainstream products in the current display field.

[0003] Currently, when preparing a display substrate, the yield of transistors is not high. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of protection of the claims.

[0005] This disclosure provides a display substrate and a display device, which can solve the problem of low yield of transistors when preparing the display substrate.

[0006] In a first aspect, an embodiment of this disclosure provides a display substrate, including: a substrate including a display area and a border area surrounding the display area; a plurality of sub-pixels located in the display area; a plurality of gate lines located in the display area and the border area and electrically connected to the plurality of sub-pixels, the plurality of gate lines being configured to provide gate signals to the plurality of sub-pixels; a gate driving circuit located in the border area and connected to the plurality of gate lines; at least one electrostatic protection unit located in the border area and connected to the gate lines, the at least one electrostatic protection unit being configured to release static electricity during the preparation process of the display substrate, the electrostatic protection unit including at least one tip structure, and the extending direction of the tip structure intersecting with the plane where the substrate is located.

[0007] In an exemplary embodiment, one of the multiple gate lines includes a first line segment, a second line segment, and a third line segment, the first line segment and the second line segment are located in the border area, the third line segment is located in the display area, and the at least one electrostatic protection unit is connected to at least one of the first line segment or the second line segment; the display substrate also includes a transition structure, which is located between the first line segment and the second line segment and connects the first line segment and the second line segment.

[0008] In an exemplary embodiment, the at least one electrostatic protection unit is multiple in number, and the multiple electrostatic protection units are respectively located on both sides of the switching structure and are respectively connected to the first line segment and the second line segment.

[0009] In an exemplary embodiment, the multiple gate lines include a first gate line and a second gate line, the first gate line and the second gate line are adjacent to each other; an electrostatic protection unit connected to a first line segment of the first gate line and an electrostatic protection unit connected to a first line segment of the second gate line are both located between the first gate line and the second gate line; and / or an electrostatic protection unit connected to a second line segment of the first gate line and an electrostatic protection unit connected to a second line segment of the second gate line are both located between the first gate line and the second gate line.

[0010] In an exemplary embodiment, the top angle of the tip structure is set to be greater than or equal to 0 degrees and less than or equal to 160 degrees.

[0011] In an exemplary embodiment, the electrostatic protection unit includes a plurality of the tip structures, and at least some of the tip structures in the plurality of the tip structures have the same top angle.

[0012] In an exemplary embodiment, the tip structure extends in a direction perpendicular to a plane in which the substrate is located.

[0013] In an exemplary embodiment, the display substrate includes a driving circuit layer arranged on the base, and a light-emitting structure layer arranged on a side of the driving circuit layer away from the base, the sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit drives the light-emitting element to emit light, the pixel circuit is located in the driving circuit layer, and the light-emitting element is located in the light-emitting structure layer.

[0014] In an exemplary embodiment, the driving circuit layer of the display area includes a first insulating layer, a first active layer, a second insulating layer, a first gate electrode, a third insulating layer, and a source-drain electrode layer, which are sequentially arranged in a direction away from the substrate; the electrostatic protection unit includes a first protection layer, a third protection layer, and a fourth protection layer, which are sequentially arranged in a direction away from the substrate; wherein, the first protection layer and the first insulating layer are arranged in the same layer, the third protection layer and the second insulating layer are arranged in the same layer, and the fourth protection layer and the first gate electrode are arranged in the same layer.

[0015] In an exemplary embodiment, the electrostatic protection unit further includes a sixth protection layer, and at least one of a second protection layer and a fifth protection layer; wherein, the second protection layer and the first active layer are arranged in the same layer, the fifth protection layer and the third insulating layer are arranged in the same layer, and the sixth protection layer and the source-drain electrode layer are arranged in the same layer.

[0016] In an exemplary embodiment, the driving circuit layer of the display area further includes a light-shielding electrode, and the light-shielding electrode is located on a side of the first insulating layer close to the substrate; the border area includes a light-shielding portion arranged in the same layer as the light-shielding electrode, and the light-shielding portion is located on a side of the electrostatic protection unit close to the substrate.

[0017] In an exemplary embodiment, in a direction away from the substrate, the light-emitting structure layer of the display area includes a planarization layer and a light-emitting device disposed on the planarization layer, and the electrostatic protection unit includes a seventh protection layer, an eighth protection layer, a ninth protection layer, and a tenth protection layer arranged in sequence; the tip structure is located in the seventh protection layer, the eighth protection layer, the ninth protection layer, and the tenth protection layer; wherein, the seventh protection layer and the planarization layer are arranged in the same layer, the eighth protection layer and the anode of the light-emitting device are arranged in the same layer, the ninth protection layer and the organic light-emitting layer of the light-emitting device are arranged in the same layer, and the tenth protection layer and the cathode of the light-emitting device are arranged in the same layer.

[0018] In an exemplary embodiment, the electrostatic protection unit further includes a first color filter, a second color filter, and a third color filter stacked in sequence; the third color filter is located on a side of the seventh protection layer close to the substrate.

[0019] In an exemplary embodiment, the electrostatic protection unit further includes an electrostatic discharge transistor, and the electrostatic discharge transistor is disposed in the driving circuit layer.

[0020] In an exemplary embodiment, in a direction perpendicular to the substrate, the distance between the surface of the tenth protective layer away from the substrate and the substrate is a first distance, and the distance between the surface of the cathode away from the substrate and the substrate is a second distance; the difference between the first distance and the second distance is set to be greater than or equal to 2.7 microns and less than or equal to 6.6 microns.

[0021] In an exemplary embodiment, the border area includes a circuit area, and the circuit area includes a gate driving circuit; wherein at least one of the electrostatic protection units is located on a side of the circuit area close to the display area, or at least one of the electrostatic protection units is arranged to surround the display area and the circuit area.

[0022] In an exemplary embodiment, the transition structure includes a tip serration, and an extension direction of the tip serration is located in a plane where the base is located.

[0023] In a second aspect, an embodiment of the present disclosure provides a display device, comprising the display substrate as described above.

[0024] The display substrate proposed in the embodiment of the present disclosure has at least one electrostatic protection unit disposed in the frame area, and the electrostatic protection unit includes at least one tip structure. The electrostatic protection unit can release static electricity in the display substrate during the preparation process, thereby facilitating timely release of static electricity accumulated in the process of preparing transistors, avoiding damage to transistors caused by static electricity, and thus improving the production yield of transistors when preparing the display substrate. The problem of low yield of transistors when preparing the display substrate is solved.

[0025] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0027] Figure 1 is a structural schematic diagram of a display device;

[0028] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0029] Figure 3 It is a schematic diagram of the planar structure of a display area in a display substrate;

[0030] Figure 4 A schematic diagram of the cross-sectional structure of a display area in a display substrate;

[0031] Figure 5 It is a schematic equivalent circuit diagram of a pixel driving circuit;

[0032] Figure 6 It is a top view of a display substrate provided by an exemplary embodiment;

[0033] Figure 7 It is a top view of a display substrate provided by another exemplary embodiment;

[0034] Figure 8 In an exemplary embodiment Figure 6 is an enlarged view of the dashed area E;

[0035] Figure 9 In an exemplary embodiment Figure 6 is a cross-sectional view taken along the line B-B;

[0036] Figure 10 For Figure 8 is a cross-sectional view of the tip structure of the electrostatic protection unit;

[0037] Figure 11 It is a schematic diagram of a display substrate after forming a light-shielding layer pattern in an exemplary embodiment;

[0038] Figure 12 It is a schematic diagram of a display substrate after forming a first insulating layer pattern in an exemplary embodiment;

[0039] Figure 13 It is a schematic diagram of a display substrate after forming a semiconductor layer pattern in an exemplary embodiment;

[0040] Figure 14 It is a schematic diagram of a display substrate after forming a gate layer pattern in an exemplary embodiment;

[0041] Figure 15 It is a schematic diagram of a display substrate after forming a third insulating layer pattern in an exemplary embodiment;

[0042] Figure 16 In another exemplary embodiment Figure 6 is a cross-sectional view taken along the line B-B. Detailed implementation manners

[0043] The present disclosure describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be apparent to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope encompassed by the embodiments described in the present disclosure. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be used in combination with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0044] The present disclosure includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements already disclosed in the present disclosure can also be combined with any conventional features or elements to form unique inventive solutions defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present disclosure can be implemented alone or in any suitable combination. Therefore, the embodiments are not limited except as restricted by the appended claims and their equivalents. In addition, various modifications and changes can be made within the scope of the appended claims.

[0045] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the specific order of steps described. As will be understood by those of ordinary skill in the art, other step sequences are possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can easily understand that these orders can vary and still remain within the spirit and scope of the embodiments of the present disclosure.

[0046] In the drawings, sometimes for clarity, the sizes of one or more constituent elements, the thickness of layers, or regions are exaggerated. In addition, the drawings schematically show ideal examples, and one aspect of the present disclosure is not limited to the shapes, values, etc. shown in the drawings.

[0047] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of constituent elements and are not intended to limit in terms of quantity. "Multiple" in the present disclosure means two or more in number.

[0048] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of the components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of the components is appropriately changed according to the direction of the described components. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the situation.

[0049] In this specification, unless otherwise clearly defined and limited, the terms "mounted", "connected", and "coupled" shall be construed broadly. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection, an indirect connection through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0050] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0051] In this specification, the first pole may be the drain electrode and the second pole may be the source electrode, or the first pole may be the source electrode and the second pole may be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged with each other, and the "source terminal" and "drain terminal" can be interchanged with each other.

[0052] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transmit electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0053] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus also includes a state where the angle is more than -5° and less than 5°. Additionally, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus also includes an angle state of more than 85° and less than 95°.

[0054] In this specification, "film" and "layer" can be interchanged with each other. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0055] In this specification, triangles, rectangles, trapezoids, pentagons, hexagons, etc. are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There can be some small deformations caused by tolerances, and there can be chamfers, arc edges, and deformations, etc.

[0056] "About" in this disclosure means not strictly limiting the boundary and allowing values within the range of process and measurement errors.

[0057] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0058] Figure 1 It is a schematic structural diagram of a display device. As Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line, the light-emitting signal line, and the data signal line. The light-emitting unit may include a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light-emitting driver to the light-emitting driver. The data driver may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3,..., and Dn. For example, the data driver may sample the gray value using a clock signal and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, and n may be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3,..., and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having conductive level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and may generate scan signals in a manner of sequentially transmitting a scan start signal provided in the form of a conductive level pulse to the next-stage circuit under the control of a clock signal, and m may be a natural number. The light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3,..., and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light-emitting driver may sequentially provide emission signals having cut-off level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver may be configured in the form of a shift register and may generate emission signals in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to the next-stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, the pixel array may be disposed on a display substrate.

[0059] Figure 2 is a schematic plan view of a display substrate. As Figure 2As shown, in an exemplary embodiment, the display substrate includes a display area 100 and a border area 300 disposed around the display area 100. The border area 300 may include a bonding area 200 located on one side of the display area 100 along the second direction Y. The display area 100 at least includes a plurality of pixel units arranged regularly. For example, the plurality of pixel units may be arranged in an array along the first direction X and the second direction Y. The first direction X and the second direction Y intersect, the first direction X may be the row direction, and the second direction Y may be the column direction. The plurality of pixel units are configured to display dynamic pictures or still images, and the display area 100 may be referred to as the active area (AA). In an exemplary embodiment, the display substrate may be deformable, such as curling, bending, folding, or rolling up.

[0060] In an exemplary embodiment, the shape of the display area 100 may be quadrilateral, circular, oval, a polygon of other shapes, or an irregular shape, etc. The corner shape of the display area 100 may be a rounded corner, and the present disclosure does not limit this.

[0061] In an exemplary embodiment, the bonding area 200 may include a fan-out area, a bending area, a driving chip area, and a bonding pin area arranged in sequence along the direction away from the display area 100. The fan-out area is connected to the display area 100 and may at least include a plurality of mutually parallel data lead-out lines. The bending area is connected to the fan-out area and may include a composite insulating layer provided with a groove, which is configured to bend the bonding area to the back of the display area. The driving chip area may at least include an integrated circuit (IC), which is configured to be connected to a plurality of data fan-out lines. The bonding pin area may at least include a plurality of bonding pads, which are configured to be bonded and connected to an external flexible printed circuit (FPC).

[0062] In an exemplary embodiment, the border area 300 may include a circuit area. The circuit area may be disposed on both sides of the display area 100 along the first direction X and may be connected to the display area 100. The circuit area may at least include a gate driving circuit 301, and the gate driving circuit 301 is connected to the scanning signal line and the light-emitting signal line of the pixel driving circuit in the display area 100.

[0063] Figure 3 It is a schematic plan view of the display area in a display substrate. As Figure 3As shown, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits light of a first color, a second sub-pixel P2 that emits light of a second color, and a third sub-pixel P3 that emits light of a third color. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may at least include a pixel driving circuit, and the pixel driving circuit is respectively connected to a scanning signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting units in each sub-pixel are respectively connected to the pixel driving circuit of the corresponding sub-pixel, and the light-emitting unit is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0064] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixel may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or pyramid-like manner, etc., which is not limited in the present disclosure.

[0065] In an exemplary embodiment, the pixel unit may include four sub-pixels. For example, the four sub-pixels may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel (W) that emits white light. Alternatively, the four sub-pixels may include a red sub-pixel, a blue sub-pixel, and two green sub-pixels. In an exemplary embodiment, the four sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, square, or diamond-shaped manner, etc., which is not limited in the present disclosure.

[0066] Figure 4 It is a schematic cross-sectional structure diagram of a display area in a display substrate, showing the structures of three sub-pixels in the display area. As Figure 4 shown, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and a packaging structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementation manners, the display substrate may include other film layers, such as a touch control structure layer, etc., which is not limited in the present disclosure.

[0067] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, and each circuit unit may at least include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. Figure 4A single transistor K of the pixel driving circuit is schematically shown in the dashed-line area. The transistor K can be, for example, a driving transistor. The transistor K may include a bottom gate electrode, an active layer, a top gate electrode, a source electrode, and a drain electrode. The light-emitting structure layer 103 may include a plurality of light-emitting units. Each light-emitting unit may at least include an anode 131, a pixel defining layer 132, an organic light-emitting layer 133, and a cathode 134. The anode 131 is connected to the pixel driving circuit. The organic light-emitting layer 133 is connected to the anode 131. The cathode 134 is connected to the organic light-emitting layer 133. The organic light-emitting layer 133 emits light of a corresponding color under the drive of the anode 131 and the cathode 134. The encapsulation structure layer 104 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials. The second encapsulation layer 142 may be made of an organic material. The second encapsulation layer 142 is disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to form an inorganic material / organic material / inorganic material stacked structure, which can prevent external moisture from entering the light-emitting structure layer 103.

[0068] Figure 5 It is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure, or may adopt other structures, and the present disclosure does not limit this. As Figure 5 shown, the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to seven signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a light-emitting signal line E, an initial signal line INIT, a first power supply line VDD, and a second power supply line VSS).

[0069] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. Among them, the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5. The second node N2 is respectively connected to the second pole of the first transistor, the first pole of the second transistor T2, the control pole of the third transistor T3, and the second end of the storage capacitor C. The third node N3 is respectively connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6.

[0070] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control pole of the third transistor T3.

[0071] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When a conduction-level scan signal is applied to the second scan signal line S2, the first transistor T1 transfers an initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount at the control electrode of the third transistor T3.

[0072] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3.

[0073] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.

[0074] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D into the pixel driving circuit.

[0075] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0076] The control electrode of the seventh transistor T7 is connected to the second scan signal line S2. The first electrode of the seventh transistor T7 is connected to the initial signal line INIT. The second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conduction-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize the electric charge accumulated in the first electrode of the light-emitting device or to release the electric charge accumulated in the first electrode of the light-emitting device.

[0077] In an exemplary embodiment, the light-emitting device may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode), or may be an LED.

[0078] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuously provided high-level signal. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n - 1). The second scan signal line S2 of the current display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and realize a narrow border of the display panel.

[0079] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors, or may be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0080] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be made of low-temperature polysilicon thin-film transistors, or may be made of oxide thin-film transistors, or may be made of a combination of low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS for short), and the active layer of the oxide thin-film transistor is made of oxide semiconductor. The low-temperature polysilicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can utilize the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0081] In some technologies, taking a transistor with a top-gate structure as an example, the usual manufacturing process includes: sequentially forming an active layer and a gate on a substrate, then forming an interlayer insulating layer, which includes source vias and drain vias. The source vias and drain vias respectively expose both ends of the active layer. Subsequently, a source and a drain are formed. The source is connected to one end of the active layer through the source via, and the drain is connected to the other end of the active layer through the drain via, thereby forming a transistor. After forming the transistor, a passivation layer is formed above the source and the drain, and the preparation of the display substrate continues. The inventors of the present application have found that during the process of forming the interlayer insulating layer above the gate, when depositing the insulating film and forming vias on the insulating film, static electricity will be generated on the surface of the gate. And during the dry etching of the passivation layer, static electricity will be generated on the surfaces of the source and the drain. The accumulation of this static electricity is likely to damage the transistor, affect the device performance, cause poor GDS, and reduce the production yield of the transistor.

[0082] An embodiment of the present disclosure provides a display substrate, including: a substrate including a display area and a border area surrounding the display area; a plurality of sub-pixels located in the display area; a plurality of gate lines located in the display area and the border area and electrically connected to the plurality of sub-pixels, the plurality of gate lines being configured to provide gate signals to the plurality of sub-pixels; a gate driving circuit located in the border area and connected to the plurality of gate lines; at least one electrostatic protection unit located in the border area and connected to the gate lines, the at least one electrostatic protection unit being configured to release the static electricity generated during the preparation of the display substrate, and the electrostatic protection unit includes at least one tip structure, and the extending direction of the tip structure intersects with the plane where the substrate is located.

[0083] The display substrate proposed in the embodiment of the present disclosure has at least one electrostatic protection unit arranged in the frame area, and the electrostatic protection unit includes at least one tip structure. The electrostatic protection unit can be used to release static electricity in the display substrate during the preparation process, thereby facilitating timely release of static electricity accumulated in the process of preparing transistors, avoiding damage to transistors caused by static electricity, thereby improving the production yield of transistors when preparing display substrates.

[0084] In an exemplary embodiment, one of the multiple gate lines includes a first line segment, a second line segment, and a third line segment, the first line segment and the second line segment are located in the border area, the third line segment is located in the display area, and the at least one electrostatic protection unit is connected to at least one of the first line segment or the second line segment; the display substrate also includes a transition structure, which is located between the first line segment and the second line segment and connects the first line segment and the second line segment.

[0085] In an exemplary embodiment, the at least one electrostatic protection unit is multiple in number, and the multiple electrostatic protection units are respectively located on both sides of the switching structure and are respectively connected to the first line segment and the second line segment.

[0086] In an exemplary embodiment, the driving circuit layer of the display area includes a first insulating layer, a first active layer, a second insulating layer, a first gate electrode, a third insulating layer and a source-drain electrode layer arranged in sequence along a direction away from the substrate; the electrostatic protection unit includes a first protective layer, a third protective layer and a fourth protective layer arranged in sequence along a direction away from the substrate; wherein the first protective layer and the first insulating layer are arranged on the same layer, the third protective layer and the second insulating layer are arranged on the same layer, and the fourth protective layer and the first gate electrode are arranged on the same layer.

[0087] In an exemplary embodiment, the electrostatic protection unit also includes a sixth protection layer, and at least one of a second protection layer and a fifth protection layer; wherein the second protection layer and the first active layer are arranged on the same layer, the fifth protection layer and the third insulating layer are arranged on the same layer, and the sixth protection layer and the source-drain electrode layer are arranged on the same layer.

[0088] In an exemplary embodiment, in a direction away from the substrate, the light-emitting structure layer of the display area includes a flat layer and a light-emitting device arranged on the flat layer, and the electrostatic protection unit includes a seventh protection layer, an eighth protection layer, a ninth protection layer and a tenth protection layer arranged in sequence; the tip structure is located at the seventh protection layer, the eighth protection layer, the ninth protection layer and the tenth protection layer; wherein the seventh protection layer and the flat layer are arranged on the same layer, the eighth protection layer and the anode of the light-emitting device are arranged on the same layer, the ninth protection layer and the organic light-emitting layer of the light-emitting device are arranged on the same layer, and the tenth protection layer and the cathode of the light-emitting device are arranged on the same layer.

[0089] In an exemplary embodiment, the electrostatic protection unit further includes a first color film, a second color film and a third color film stacked in sequence; the third color film is located on a side of the seventh protection layer close to the substrate.

[0090] In an exemplary embodiment, the electrostatic protection unit further includes an electrostatic discharge transistor, and the electrostatic discharge transistor is disposed in the driving circuit layer.

[0091] In an exemplary embodiment, in a direction perpendicular to the substrate, the distance between the surface of the tenth protective layer away from the substrate and the substrate is a first distance, and the distance between the surface of the cathode away from the substrate and the substrate is a second distance; the difference between the first distance and the second distance is set to be greater than or equal to 2.7 microns and less than or equal to 6.6 microns.

[0092] In an exemplary embodiment, the top angle of the tip structure is set to be greater than or equal to 0 degrees and less than or equal to 160 degrees.

[0093] In an exemplary embodiment, the transition structure includes a tip serration, and an extension direction of the tip serration is located in a plane where the base is located.

[0094] Figure 6 FIG. 1 is a top view of a display substrate provided by an exemplary embodiment, and other structures of the display substrate are omitted for illustration. Figure 6As shown, the display substrate may include a display area 100 and a border area 300 surrounding the display area 100. The border area 300 includes a bonding area 200 located on one side of the display area 100 along the second direction Y, and two circuit areas 301 respectively located on both sides of the display area 100 along the first direction X. A gate driving circuit is provided in the circuit area 301. The display area 100 at least includes a plurality of regularly arranged sub-pixels Pxij. The plurality of sub-pixels Pxij may include a plurality of sub-pixel rows arranged along the first direction X and a plurality of sub-pixel columns arranged along the second direction Y. The display substrate includes a plurality of gate lines 310. A single gate line 310 may be connected to a plurality of sub-pixels Pxij within a single sub-pixel row and connected to the gate driving circuit. The plurality of gate lines 310 are configured to provide gate signals to the plurality of sub-pixels Pxij. The display substrate includes a plurality of data lines 320. A single data line 320 may be connected to a plurality of sub-pixels Pxij within a single sub-pixel column and connected to the bonding area 200. The plurality of data lines 320 may be connected to an integrated circuit provided in the bonding area 200 to provide data signals to the plurality of sub-pixels Pxij. The display substrate includes at least one electrostatic protection unit 302. The electrostatic protection unit 302 is located in the border area 300 and connected to the gate line 310. The electrostatic protection unit 302 includes at least one tip structure. The extending direction of the tip structure intersects with the plane where the display area 100 is located, and is set to release the static electricity of the display substrate during the manufacturing process, which helps to improve the yield of the transistors of the display substrate during the manufacturing process and can improve the display effect.

[0095] In an exemplary embodiment, the electrostatic protection unit 302 may be provided between the circuit area 301 and the display area 100. In other embodiments, at least one electrostatic protection unit 302 may be provided to surround the circuit area 301 and the display area 100, and the present disclosure does not limit this. The electrostatic protection unit 302 can release the static electricity generated during the manufacturing process of the display area 100 and the circuit area 301. It can not only release the static electricity of the transistors in the display area 100, but also release the static electricity of the transistors in the gate driving circuit of the circuit area 301.

[0096] In an exemplary embodiment, the display area 100 may be rectangular. Four electrostatic protection units 302 may be provided at the four corners of the display area 100, or the number and distribution of the electrostatic protection units 302 may be set as needed, and the present disclosure does not limit this.

[0097] Figure 7 A top view of the display substrate provided for another exemplary embodiment, with other structures of the display substrate omitted for illustration. Figure 7 and Figure 6 The difference lies in the number and distribution of the electrostatic protection units 302, and the remaining structures may refer to the above description of Figure 6The description of is not repeated here. Figure 7 As shown, a plurality of electrostatic protection units 302 may be arranged around the display area 100, and the plurality of electrostatic protection units 302 may be evenly distributed around the display area 100. By increasing the number of electrostatic protection units 302 and evenly distributing the plurality of electrostatic protection units 302, it helps to improve the electrostatic discharge effect and avoid static electricity accumulation in the display substrate, thereby improving the display effect of the display substrate.

[0098] Figure 8 In an exemplary embodiment Figure 6 The enlarged view of the dotted line area E of FIG. 2 , omitting other structures of the display substrate. Figure 8 As shown, a gate line 310 may include a first line segment 311, a second line segment 312 and a third line segment 313, wherein the first line segment 311 and the second line segment 312 are located in the frame area 300, and the third line segment 313 is located in the display area 100, and at least one electrostatic protection unit 302 is connected to at least one of the first line segment 311 or the second line segment 312. The display substrate further includes a switching structure 314, which is located between the first line segment 311 and the second line segment 312 and connects the first line segment 311 and the second line segment 312. For example, the first line segment 311 and the second line segment 312 may be located in different conductive layers arranged in a direction away from the substrate, and may be connected through the switching structure 314. At least one electrostatic protection unit 302 may be distributed on the same side or both sides of the switching structure 314 along the first direction X, and the present disclosure does not limit this.

[0099] In an exemplary embodiment, the electrostatic protection unit 302 located on adjacent gate lines 310 may be disposed between the two adjacent gate lines 310; or, a plurality of electrostatic protection units 302 may be located on the same side of the gate line 310 connected to the same gate line 310 along the second direction Y; or, a plurality of electrostatic protection units 302 connected to the first line segment 311 may be located on one side of the first line segment 311 in the second direction Y, and a plurality of electrostatic protection units 302 connected to the second line segment 312 may be located on the other side of the second line segment 312 in the second direction Y, and the present disclosure does not limit this. Two gate lines 310 being adjacent means that no other gate lines are included between the two gate lines 310. Figure 8 Two adjacent gate lines 310 are shown in the figure. The gate line 310 located at the top along the second direction Y can be called the first gate line, and the other can be called the second gate line. The electrostatic protection unit connected to the first line segment of the first gate line and the electrostatic protection unit connected to the first line segment of the second gate line can be located between the first gate line and the second gate line at the same time. The electrostatic protection unit connected to the second line segment of the first gate line and the electrostatic protection unit connected to the second line segment of the second gate line can be located between the first gate line and the second gate line at the same time. The present disclosure does not limit this.

[0100] In an exemplary embodiment, the transition structure 314 may include at least one tip serration 333 , and the extension direction of the tip serration 333 may be located within the plane where the substrate is located. Figure 8 The figure shows that a plurality of tip saw teeth 333 are provided on both sides of the adapter structure 314 along the second direction Y. Any number of tip saw teeth 333 can be provided on at least one side of the adapter structure 314 along the second direction Y as required. By providing the tip saw teeth, static electricity can be discharged in the plane where the tip saw teeth are located, which helps to improve the static electricity discharge effect in the process of preparing the display substrate.

[0101] In an exemplary embodiment, the first line segment 311 and the second line segment 312 are respectively located in different conductive layers arranged in a direction away from the substrate, and the tip serration 333 of the transition structure 314 can be arranged in the same layer as at least one of the first line segment 311 or the second line segment 312 .

[0102] Figure 9 In an exemplary embodiment Figure 6 The BB-direction cross-sectional view of the display substrate is omitted and other structures of the display substrate are shown. Figure 9 As shown, the display substrate may include a base 10 and a driving circuit layer disposed on the base 10 , the driving circuit layer of the display area 100 may include a plurality of circuit units, and the electrostatic protection unit 302 may be disposed in the driving circuit layer of the frame area 300 . Figure 9, a first transistor K1 of a single pixel driving circuit is schematically shown, and the first transistor K1 may include a light shielding electrode 11, a first active layer 13, a first gate electrode 15, a first source electrode 17, and a first drain electrode 18. The electrostatic protection unit 302 may be prepared together with the first transistor K1, and the electrostatic protection unit 302 may include, for example, a first protective layer 22, a second protective layer 23, a third protective layer 24, a fourth protective layer 25, a fifth protective layer 26, and a sixth protective layer 27, which are sequentially arranged on the side of the light shielding portion 21 away from the substrate 10, wherein the first protective layer 22 may be arranged in the same layer as the first insulating layer 12, the second protective layer 23 may be arranged in the same layer as the first active layer 13, the third protective layer 24 may be arranged in the same layer as the second insulating layer 14, the fourth protective layer 25 may be arranged in the same layer as the first gate electrode 15, the fifth protective layer 26 may be arranged in the same layer as the third insulating layer 16, and the sixth protective layer 27 may be arranged in the same layer as the first source electrode 17 and the first drain electrode 18. The light shielding portion 21 may be arranged in the same layer as the light shielding electrode 11. In the process of preparing the display substrate, for example, when depositing inorganic film layers and performing dry etching, static electricity is generated due to the action of plasma. By simultaneously preparing the electrostatic protection unit 302 in the frame area 300, the electrostatic protection unit 302 includes a plurality of tip structures, which can concentrate the static electricity in the preparation process at the tip of the electrostatic protection unit for release, thereby avoiding the accumulation of static electricity in the display substrate during the preparation process, improving the yield of the transistors of the display substrate during the preparation process, and improving the display effect.

[0103] In an exemplary embodiment, the electrostatic protection unit 302 may only include the first protection layer 22 , the third protection layer 24 , and the fourth protection layer 25 , and other protection layers may be provided as needed, which is not limited in the present disclosure.

[0104] In an exemplary embodiment, the first line segment 311 can be set in the same layer as the first gate electrode 15, the second line segment 312 can be set in the same layer as the first source electrode 17 or the first drain electrode 18, and the tip serration 333 of the transfer structure 314 can be set in the same layer as at least one of the first line segment 311 or the second line segment 312.

[0105] Figure 10 for Figure 9 The cross-sectional view of the tip structure of the electrostatic protection unit in FIG. 2 , omitting other structures of the display substrate. Figure 10 As shown, the electrostatic protection unit 302 may include at least one tip structure, Figure 10The dashed line indicates the extension direction of the tip structure. In an exemplary embodiment, the extension direction of the tip structure may be perpendicular to the plane where the substrate 10 is located. The tip structure may have an apex angle a, and the apex angle a is the angle between the tip structure and the substrate 10. The apex angle a may be set to be greater than or equal to 0 degrees and less than or equal to 160 degrees. The smaller the apex angle a, the sharper the tip structure. The apex angles a of different tip structures may be equal or unequal. The number of tip structures included in the electrostatic protection unit 302 and the size of the apex angle a of a single tip structure may be set as needed, and the present disclosure does not limit this.

[0106] The preparation process of the display substrate will be exemplarily described below. The "patterning process" as mentioned in the present disclosure, for metal materials, inorganic materials or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as coating organic materials, mask exposure, and development. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be any one or more of spraying, spin coating, and inkjet printing. Etching can be any one or more of dry etching and wet etching, and the present disclosure does not limit this. A "thin film" refers to a thin film made of a certain material on a substrate by using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are disposed in the same layer" as mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. The "thickness" of a film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In an exemplary embodiment of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0107] In an exemplary embodiment, Figure 9 the preparation process of the shown display substrate may include the following steps.

[0108] (1) Form a light-shielding layer pattern. In an exemplary embodiment, forming a light-shielding layer pattern may include:

[0109] Deposit a first conductive thin film on the substrate 10, pattern the first conductive thin film through a patterning process, and form a light-shielding layer pattern in the display area 100 and the border area 300. The light-shielding layer pattern in the display area 100 may at least include a light-shielding electrode 11, and the light-shielding layer pattern in the border area 300 may at least include a light-shielding portion 21, as Figure 11 shown.

[0110] In an exemplary embodiment, the light-shielding electrode 11 can serve as a gate electrode of a first transistor to be formed subsequently and also has the function of shielding light for the first transistor. In an exemplary embodiment, the first transistor can be, for example, a driving transistor.

[0111] In an exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate. The rigid substrate can be made of materials such as glass or quartz, and the flexible substrate can be made of materials such as polyimide (PI). The flexible substrate can be a single-layer structure or a laminated structure composed of an inorganic material layer and a flexible material layer. The present disclosure does not limit this. The light-shielding layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0112] (2) Form a first insulating layer pattern. In an exemplary embodiment, forming the first insulating layer pattern can include:

[0113] Deposit a first insulating thin film on the substrate 10 on which the above pattern is formed, and pattern the first insulating thin film located in the border region 300 through a patterning process to form a first insulating layer pattern. The first insulating layer pattern can include a first insulating layer 12 located in the display region 100 and a first protective layer 22 located in the border region 300. The first insulating layer 12 can cover the substrate 10 and have a flat surface, and the surface of the first protective layer 22 can have a plurality of protruding tips, such as Figure 12 as shown.

[0114] In an exemplary embodiment, a micro-lens array (MLA) process can be used to form an uneven structure on the first insulating thin film in the border region 300. The cross-sectional shape of the uneven structure can be, for example, serrated.

[0115] In an exemplary embodiment, the material of the first insulating thin film can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single-layer, double-layer, or multi-layer structure. The first insulating layer 12 can be referred to as a buffer layer.

[0116] (3) Form a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern can include:

[0117] A semiconductor thin film is deposited on the substrate 10 on which the above-mentioned pattern is formed, and the semiconductor thin film is patterned through a patterning process to form a semiconductor layer pattern. The semiconductor layer pattern may at least include a first active layer 13 located in the display area 100 and a second protective layer 23 located in the border area 300, as Figure 13 shown. The semiconductor thin film deposited in the border area 300 may maintain the surface shape of the first protective layer 22, so that the second protective layer 23 can be formed in the border area 300.

[0118] In an exemplary embodiment, the orthographic projection of the first active layer 13 on the substrate 10 may be within the range of the orthographic projection of the light-shielding electrode 11 on the substrate 10.

[0119] In an exemplary embodiment, the semiconductor layer may be made of materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxide nitride (ZnON), indium zinc tin oxide (IZTO), etc., and the present disclosure does not limit this here.

[0120] (4) Form a gate layer pattern. In an exemplary embodiment, forming the gate layer pattern may include:

[0121] On the substrate 10 on which the above-mentioned pattern is formed, a second insulating thin film and a second conductive thin film are sequentially deposited, and the second conductive thin film in the display area 100 is patterned through a patterning process to form a second insulating layer 14 and a gate layer pattern provided on the second insulating layer 14 in the display area 100. The gate layer pattern in the display area 100 may at least include a first gate electrode 15. The second insulating thin film and the second conductive thin film deposited in the border area 300 may maintain the surface shape of the first protective layer 22, so that a third protective layer 24 and a fourth protective layer 25 are formed in the border area 300, as Figure 14 shown.

[0122] Subsequently, the first active layer 13 may be conductorized with the first gate electrode 15 as an obstruction, and the present disclosure does not limit this.

[0123] In an exemplary embodiment, the material of the second insulating layer thin film may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single-layer, double-layer, or multi-layer structure. The second insulating layer 14 may be referred to as a gate insulating (GI) layer.

[0124] (5) Form a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include:

[0125] A third insulating film is deposited on the substrate 10 on which the above-mentioned pattern is formed. The third insulating film in the display area 100 is patterned through a patterning process to form a third insulating layer 16 in the display area 100. The third insulating film deposited in the border area 300 can maintain the surface shape of the fourth protective layer 25, so as to form a fifth protective layer 26 in the border area 300. The third insulating layer 16 may include at least two active vias, and the two active vias may respectively expose both ends of the first active layer 13, as Figure 15 shown.

[0126] Since the fourth protective layer 26 in the border area 300 has a tip structure, the static electricity generated on the first gate electrode 15 in this step can be released from the tip located in the border area 300 of the display substrate, thereby avoiding the accumulation of static electricity on the first gate electrode 15.

[0127] In an exemplary embodiment, the material of the second insulating layer film may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single-layer, double-layer, or multi-layer structure. The third insulating layer 16 may be referred to as an interlayer dielectric (ILD) layer.

[0128] (6) Form a source-drain electrode layer pattern. In an exemplary embodiment, forming a source-drain electrode layer may include:

[0129] A third conductive film is deposited on the substrate 10 on which the above-mentioned pattern is formed. The third conductive film is patterned through a patterning process to form a source-drain electrode layer pattern in the display area 100. The source-drain electrode layer pattern at least includes a first source electrode 17 and a first drain electrode 18. The first source electrode 17 and the first drain electrode 18 are respectively connected to both ends of the first active layer 13 through two active vias. The third conductive film deposited in the border area 300 can maintain the surface shape of the fifth protective layer 26, so as to form a sixth protective layer 27 in the border area 300, as Figure 9 shown.

[0130] In an exemplary embodiment, the source-drain electrode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-nd alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0131] Subsequently, structures such as a passivation layer, a light-emitting structure layer, and a packaging structure layer can be continuously formed on the substrate 10 on which the above-mentioned pattern is formed. The static electricity generated during these manufacturing processes can be released through the static electricity protection unit 302 located in the border area 300, which can improve the yield of transistors when manufacturing the display substrate. During subsequent manufacturing processes, the static electricity protection unit 302 can form more protection layers, or the present disclosure does not limit this.

[0132] Figure 16 In yet another exemplary embodiment Figure 6 is a cross-sectional view taken along line B-B, omitting other structures of the display substrate for illustration. As Figure 16 shown, the display substrate may include a substrate 10, a driving circuit layer 102 disposed on the substrate 10, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 10, and a packaging structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 10. The driving circuit layer 102 in the border area 300 may be provided with a static electricity release transistor K2, and the static electricity release transistor K2 can be fabricated synchronously with the first transistor K1 in the driving circuit layer 102 in the display area 100. Figure 16 The reference numerals of some film layers are omitted for illustration and can be referred to the above description of Figure 9 and will not be elaborated here. The driving circuit layer 102 may further include a passivation layer 30 disposed on the side of the source-drain electrode layer away from the substrate 10. In the direction away from the substrate 10, the light-emitting structure layer 103 in the display area 100 may include a color filter layer, a planarization layer 34, an anode layer 35, a pixel definition layer 36, an organic light-emitting layer 37, and a cathode layer 38 arranged in sequence. The anode layer 35 can be connected to the drain electrode of the corresponding first transistor K1 through a via hole. The color filter layer may include color filters of multiple different colors. Taking the display substrate including three different color sub-pixels as an example, the color filter layer may include a first color filter 31, a second color filter 32, and a third color filter 33, and the color filters of different colors are respectively located in different color sub-pixel regions. In the direction away from the substrate 10, the light-emitting structure layer 103 in the border area 300 may include a color filter layer, a seventh protection layer 40, an eighth protection layer 41, a ninth protection layer 42, and a tenth protection layer 43 arranged in sequence. Among them, the color filter layer in the border area 300 may include the first color filter 31, the second color filter 32, and the third color filter 33 stacked in sequence. The seventh protection layer 40 can be arranged on the same layer as the planarization layer 34, the eighth protection layer 41 can be arranged on the same layer as the anode layer 35, the ninth protection layer 42 can be arranged on the same layer as the organic light-emitting layer 37, and the tenth protection layer 43 can be arranged on the same layer as the cathode layer 38. The seventh protection layer 40, the eighth protection layer 41, the ninth protection layer 42, and the tenth protection layer 43 may include a plurality of tip structures.

[0133] As Figure 16As shown, the electrostatic protection unit 302 may include an electrostatic discharge transistor K2, a passivation layer 30, a first color film 31, a second color film 32, and a third color film 33 stacked in sequence, as well as a seventh protection layer 40, an eighth protection layer 41, a ninth protection layer 42, and a tenth protection layer 43. As Figure 16 shown, in the direction perpendicular to the substrate 10, the distance between the surface (i.e., the tip position) on the side of the tenth protection layer 43 away from the substrate 10 and the substrate 10 is a first distance H1, and the distance between the surface on the side of the cathode layer 38 away from the substrate 10 and the substrate 10 is a second distance H2. In an exemplary embodiment, the difference between the first distance H1 and the second distance H2 may be set to be greater than or equal to 2.7 micrometers and less than or equal to 6.6 micrometers. For example, the difference between the first distance H1 and the second distance H2 may be set to be greater than or equal to 3 micrometers and less than or equal to 6 micrometers. This height difference makes the tip of the tenth protection layer 43 at a higher position from the substrate 10, which can play a role similar to a lightning rod. During the preparation process of the display substrate, the static electricity of each film layer can be concentrated and released through the multiple tip structures of the electrostatic protection unit 302, improving the yield of the transistor.

[0134] During Figure 16 the preparation process of the shown display substrate, after forming the passivation layer 30, the first color film 31, the second color film 32, and the third color film 33 may be formed in sequence in the display area 100, and multiple color film layers in the border area 300 may be retained. Subsequently, a planarizing film is coated, a planarization layer 34 is formed in the display area 100, and in the border area 300, multiple tip structures may be formed on the surface of the planarizing film by using the MLA process to form the seventh protection layer 40. Subsequently, the formed eighth protection layer 41, ninth protection layer 42, and tenth protection layer 43 may maintain the surface morphology of the seventh protection layer 40. The preparation process may refer to the description of the preparation process in Figure 9 above, and will not be elaborated here.

[0135] An embodiment of the present disclosure also provides a method for preparing a display substrate. The method includes: forming a plurality of sub-pixels, a gate driving circuit, a plurality of gate lines, and at least one electrostatic protection unit on a substrate; the at least one electrostatic protection unit is configured to release the static electricity during the preparation process of the display substrate, the electrostatic protection unit includes at least one tip structure, and the extending direction of the tip structure intersects with the plane where the substrate is located; wherein, the substrate includes a display area and a border area surrounding the display area; the plurality of sub-pixels are located in the display area; the plurality of gate lines are located in the display area and the border area and are electrically connected to the plurality of sub-pixels, and the plurality of gate lines are configured to provide gate signals to the plurality of sub-pixels; the gate driving circuit is located in the border area and is connected to the plurality of gate lines; the at least one electrostatic protection unit is located in the border area and is connected to the gate lines.

[0136] An embodiment of the present disclosure further provides a display device, including the display substrate described in any of the above embodiments. The display device may be: an OLED display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function. The embodiments of the present disclosure are not limited thereto.

[0137] Although the disclosed embodiments of the present invention are as above, the described content is only an embodiment adopted for facilitating the understanding of the present invention and is not intended to limit the present invention. Any person skilled in the art within the scope of the present invention may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present invention. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that, include: A substrate, comprising a display area and a frame area surrounding the display area; A plurality of sub-pixels are located in the display area; a plurality of gate lines, located in the display area and the frame area and electrically connected to the plurality of sub-pixels, the plurality of gate lines being configured to provide gate signals to the plurality of sub-pixels; A gate driving circuit is located in the frame area and connected to the plurality of gate lines; At least one electrostatic protection unit is located in the frame area and connected to the gate line, and the at least one electrostatic protection unit is configured to release static electricity on the display substrate during the preparation process. The electrostatic protection unit includes at least one tip structure, and the extension direction of the tip structure intersects with the plane where the base is located.

2. The display substrate according to claim 1, characterized in that, One of the plurality of gate lines comprises a first line segment, a second line segment and a third line segment, the first line segment and the second line segment are located in the frame area, the third line segment is located in the display area, and the at least one electrostatic protection unit is connected to at least one of the first line segment or the second line segment; The display substrate further includes a transition structure, which is located between the first line segment and the second line segment and connects the first line segment and the second line segment.

3. The display substrate according to claim 2, characterized in that, The number of the at least one electrostatic protection unit is multiple, and the multiple electrostatic protection units are respectively located on both sides of the switching structure and are respectively connected to the first line segment and the second line segment.

4. The display substrate according to claim 2, characterized in that, The plurality of gate lines include a first gate line and a second gate line, wherein the first gate line and the second gate line are adjacent to each other; The electrostatic protection unit connected to the first line segment of the first gate line and the electrostatic protection unit connected to the first line segment of the second gate line are both located between the first gate line and the second gate line; and / or, The electrostatic protection unit connected to the second line segment of the first gate line and the electrostatic protection unit connected to the second line segment of the second gate line are both located between the first gate line and the second gate line.

5. The display substrate according to claim 1, characterized in that, The top angle of the tip structure is set to be greater than or equal to 0 degree and less than or equal to 160 degrees.

6. The display substrate according to claim 5, characterized in that, The electrostatic protection unit includes a plurality of the tip structures, and at least some of the tip structures in the plurality of the tip structures have the same top angle.

7. The display substrate according to claim 1, characterized in that, The extending direction of the tip structure is perpendicular to the plane where the base is located.

8. The display substrate according to claim 3, characterized in that, The display substrate includes a driving circuit layer arranged on the base, and a light-emitting structure layer arranged on a side of the driving circuit layer away from the base. The sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit drives the light-emitting element to emit light. The pixel circuit is located in the driving circuit layer, and the light-emitting element is located in the light-emitting structure layer.

9. The display substrate according to claim 8, characterized in that, The driving circuit layer of the display area comprises a first insulating layer, a first active layer, a second insulating layer, a first gate electrode, a third insulating layer and a source-drain electrode layer which are sequentially arranged in a direction away from the substrate; The electrostatic protection unit comprises a first protection layer, a third protection layer and a fourth protection layer which are sequentially arranged in a direction away from the substrate; The first protective layer and the first insulating layer are arranged on the same layer, the third protective layer and the second insulating layer are arranged on the same layer, and the fourth protective layer and the first gate electrode are arranged on the same layer.

10. The display substrate according to claim 9, characterized in that, The electrostatic protection unit further includes a sixth protection layer, and at least one of the second protection layer and the fifth protection layer; Among them, the second protective layer and the first active layer are arranged in the same layer, the fifth protective layer and the third insulating layer are arranged in the same layer, and the sixth protective layer and the source-drain electrode layer are arranged in the same layer.

11. The display substrate according to claim 9, characterized in that, The driving circuit layer of the display area also includes a light-shielding electrode, which is located on a side of the first insulating layer close to the substrate; the frame area includes a light-shielding portion arranged in the same layer as the light-shielding electrode, and the light-shielding portion is located on a side of the electrostatic protection unit close to the substrate.

12. The display substrate according to claim 9, characterized in that, In a direction away from the substrate, the light emitting structure layer of the display area includes a flat layer and a light emitting device arranged on the flat layer, the electrostatic protection unit includes a seventh protection layer, an eighth protection layer, a ninth protection layer and a tenth protection layer arranged in sequence; the tip structure is located in the seventh protection layer, the eighth protection layer, the ninth protection layer and the tenth protection layer; Among them, the seventh protective layer and the flat layer are arranged on the same layer, the eighth protective layer and the anode of the light-emitting device are arranged on the same layer, the ninth protective layer and the organic light-emitting layer of the light-emitting device are arranged on the same layer, and the tenth protective layer and the cathode of the light-emitting device are arranged on the same layer.

13. The display substrate according to claim 12, characterized in that, The electrostatic protection unit further includes a first color film, a second color film and a third color film which are stacked in sequence; the third color film is located on a side of the seventh protection layer close to the substrate.

14. The display substrate according to claim 13, characterized in that, The electrostatic protection unit further includes an electrostatic release transistor, and the electrostatic release transistor is arranged on the driving circuit layer.

15. The display substrate according to claim 14, wherein In a direction perpendicular to the substrate, the distance between the surface of the tenth protective layer away from the substrate and the substrate is a first distance, and the distance between the surface of the cathode away from the substrate and the substrate is a second distance; the difference between the first distance and the second distance is set to be greater than or equal to 2.7 microns and less than or equal to 6.6 microns.

16. The display substrate according to claim 2, wherein The transition structure comprises a tip sawtooth, and the extension direction of the tip sawtooth is located in the plane where the base is located.

17. A display device, wherein The invention comprises the display substrate as claimed in any one of claims 1 to 16.

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