Display panel motherboard, display panel and display device

Abstract

The application discloses a display panel motherboard, a display panel and a display device. The display panel motherboard has at least two panel regions. The display panel motherboard comprises: a plurality of sub-pixels, each of the panel regions is provided with a plurality of sub-pixels, and the arrangement of the sub-pixels in the at least two panel regions is different; a plurality of test signal terminals, each of the panel regions is provided with a plurality of test signal terminals, the test signal terminals in the panel regions are electrically connected with corresponding sub-pixels, the test signal terminals are used for participating in driving the sub-pixels to emit light, and the arrangement of the test signal terminals in each of the panel regions is the same.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular relates to a display panel motherboard, a display panel, and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and flat-panel displays based on technologies such as light-emitting diodes (LEDs) are widely used in a variety of consumer electronics products, including mobile phones, televisions, laptops, and desktop computers, due to their advantages of high image quality, power efficiency, thin design, and wide application range. They have become the mainstream display device market. Traditionally, the production process of display panels typically uses a fine mask mask (FMM) to pattern the luminous pixels. While FMM technology is mature and boasts extensive mass production experience, it also suffers from limited precision, high development costs, and long development cycles. Maskless technology eliminates the limitations of traditional OLED processes on display size, resolution, and other performance characteristics, offering the advantages of high performance, full-scale scalability, and agile delivery. Patents CN118251982A, CN115666161A, CN116648095A, CN117062489A, CN117580403A, CN118678743A, CN118660490A, CN118678724A, CN118678806A, CN118742084A, and CN118946184A describe the relevant contents of the maskless technology for reference.

[0003] However, the process performance of current OLED display products needs to be improved. Summary of the Invention

[0004] Embodiments of the present application provide a display panel motherboard, a display panel, and a display device, aiming to improve the testing efficiency of the display panel motherboard.

[0005] An embodiment of the first aspect of the present application provides a display panel motherboard, which has at least two panel areas. The display panel motherboard includes: multiple sub-pixels, each panel area is provided with multiple sub-pixels, and the arrangement of the sub-pixels in at least two panel areas is different; multiple test signal terminals, each panel area is provided with multiple test signal terminals, the test signal terminals in the panel area are electrically connected to the corresponding sub-pixels, and the test signal terminals are used to participate in driving the sub-pixels to emit light, wherein the arrangement of the test signal terminals in each panel area is the same.

[0006] An embodiment of a second aspect of the present application provides a display panel, which is prepared from the display panel motherboard of the above embodiment.

[0007] An embodiment of a third aspect of the present application provides a display device, comprising the display panel of the above embodiment.

[0008] In a display panel motherboard provided in an embodiment of the present application, the display panel motherboard has at least two panel regions. The display panel motherboard includes multiple sub-pixels and multiple test signals. Each panel region is provided with multiple sub-pixels, which can be used to achieve a light-emitting display. The sub-pixels in at least two panel regions are arranged differently, so that different panel regions with different sub-pixel arrangements can be used to form display panels with different sub-pixel arrangements. That is, a single display panel motherboard can be used to form at least two display panels with different sub-pixel arrangements, which can facilitate improving the production efficiency of display panels.

[0009] Multiple test signal terminals are provided in each panel area. The test signal terminals in the panel area are electrically connected to the corresponding sub-pixels. The test signal terminals can be used to drive the sub-pixels to emit light, so that the display panel motherboard can be tested through the test signal terminals.

[0010] By setting the arrangement of the test signal terminals in each panel area to be the same, during the testing process of the display panel motherboard, the same set of testing equipment can be used to test each panel area with different sub-pixel arrangements in the display panel motherboard, thereby effectively improving the preparation efficiency of the display panel motherboard and effectively reducing the cost of the testing equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 is a partial cross-sectional view of a display panel provided in an embodiment of the present application;

[0013] Figure 2 This is a structural diagram of a display panel motherboard and a testing device provided in an embodiment of the present application;

[0014] Figure 3 This is a partial structural diagram of a display panel motherboard and a testing device provided in an embodiment of the present application;

[0015] Figure 4 This is a partial structural diagram of a display panel motherboard and a testing device provided in another embodiment of the present application;

[0016] Figure 5This is a schematic diagram of a partial structure of a display panel motherboard provided in an embodiment of the present application;

[0017] Figure 6 This is a schematic diagram of a partial structure of a display panel motherboard provided by another embodiment of the present application;

[0018] Figure 7 This is a schematic timing diagram of a test driving method for a display panel motherboard provided in an embodiment of the present application;

[0019] Figure 8 This is a flow chart of a method for testing a display panel motherboard provided in an embodiment of the present application;

[0020] Figure 9 This is a schematic diagram of the partial structure of a display panel motherboard provided in yet another embodiment of the present application.

[0021] Description of reference numerals:

[0022] 10. Display panel motherboard;

[0023] 100, substrate; 110, underlay; 120, first insulating layer; 130, second insulating layer; 140, third insulating layer;

[0024] 200, pixel definition layer; 201, pixel opening

[0025] 300, isolation structure; 301, isolation opening; 301a, first opening; 301b, second opening; 301c, third opening; 310, first isolation portion; 320, second isolation portion; 330, conductive portion;

[0026] 400, sub-pixel; 400a, pixel group; 401, first type of sub-pixel; 402, second type of sub-pixel; 403, third type of sub-pixel; 410, driving circuit; 411, transistor; 411a, gate; 411b, source and drain; 412, storage capacitor; 412a, first plate; 412b, second plate; 420, light-emitting device; 421, first electrode; 422, light-emitting functional layer; 423, second electrode;

[0027] 500, test signal terminal; 500a, test group; 501, control terminal group; 502, switch terminal group; 503, lighting terminal group; 510, first type test signal terminal; 511, first type control signal terminal; 512, first type switch signal terminal; 513, first type lighting signal terminal; 520, second type test signal terminal; 521, second type control signal terminal; 522, second type switch signal terminal; 523, second type lighting signal terminal; 530, third type test signal terminal; 531, third type control signal terminal; 532, third type switch signal terminal; 533, third type lighting signal terminal;

[0028] 600, test control transistor; 610, first type control transistor; 620, second type control transistor; 630, third type control transistor;

[0029] 700, test switch transistor; 700a, switch group; 710, first type switch transistor; 720, second type switch transistor; 730, third type switch transistor;

[0030] DL, data signal line;

[0031] CL, connecting line;

[0032] SL1, control signal line; SL1a, first type control signal line; SL1b, second type control signal line; SL1c, third type control signal line; SL2, switch signal line; SL2a, first type switch signal line; SL2b, second type switch signal line; SL2c, third type switch signal line; SL3, lighting signal line; SL3a, first type lighting signal line; SL3b, second type lighting signal line; SL3c, third type lighting signal line;

[0033] PA, panel area; PA1, first type panel area; PA2, second type panel area;

[0034] TD, test device; TD1, main body; TD2, transfer part; TD21, signal transmission end; TD21a, first type control transmission end; TD21b, second type control transmission end; TD21c, third type control transmission end; TD21d, first type switch transmission end; TD21e, second type switch transmission end; TD21f, third type switch transmission end; TD21g, first type lighting transmission end; TD21h, second type lighting transmission end; TD21i, third type lighting transmission end;

[0035] X, first direction;

[0036] Y, second direction;

[0037] Z, thickness direction. DETAILED DESCRIPTION

[0038] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0039] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0040] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the component is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0041] Embodiments of the present application provide a display panel motherboard, a display panel, and a display device. The following describes various embodiments of the display panel motherboard, the display panel, and the display device in conjunction with the accompanying drawings.

[0042] Figure 1 is a partial cross-sectional view of a display panel provided in an embodiment of the present application. Figure 2 1 is a structural diagram of a display panel motherboard 10 and a testing device TD provided in an embodiment of the present application. Figure 3 1 is a partial structural diagram of a display panel motherboard 10 and a testing device TD provided in an embodiment of the present application. Figure 4This is a partial structural diagram of a display panel motherboard 10 and a testing device TD, provided in another embodiment of the present application. The X direction in the figure may be denoted as the first direction X, the Y direction in the figure may be denoted as the second direction Y, and the Z direction in the figure may be denoted as the thickness direction Z of the display panel motherboard 10. The first direction X, the second direction Y, and the thickness direction Z of the display panel motherboard 10 may intersect with each other. For example, the first direction X, the second direction Y, and the thickness direction Z of the display panel motherboard 10 may be perpendicular to each other.

[0043] like Figures 1 to 4 As shown, an embodiment of the first aspect of the present application provides a display panel motherboard 10, the display panel motherboard 10 has at least two panel areas PA, and the display panel motherboard 10 includes: a plurality of sub-pixels 400, each panel area PA is provided with a plurality of sub-pixels 400, and the arrangement of the sub-pixels 400 in at least two panel areas PA is different; a plurality of test signal terminals 500, each panel area PA is provided with a plurality of test signal terminals 500, the test signal terminals 500 in the panel area PA are electrically connected to the corresponding sub-pixels 400, and the test signal terminals 500 are used to participate in driving the sub-pixels 400 to emit light, wherein the arrangement of the test signal terminals 500 in each panel area PA is the same.

[0044] In a display panel motherboard 10 provided in an embodiment of the present application, the display panel motherboard 10 has at least two panel areas PA.

[0045] Optionally, the display panel motherboard 10 can be used to prepare a display panel. For example, the display panel motherboard 10 can be used to prepare a display panel that utilizes the light-emitting principle of an organic light-emitting diode to realize light emission.

[0046] Optionally, adjacent panel areas PA may be spaced apart, and a single panel area PA may be used to form a single display panel, that is, the display panel motherboard 10 may be used to form multiple display panels. Multiple display panels may be formed by cutting or other processing techniques on the display panel motherboard 10.

[0047] For example, the display panel motherboard 10 can be processed by cutting or other processing techniques to separate the panel areas PA, and a single panel area PA can be used to form a single display panel. A complete single panel area PA can be used to form a single complete display panel. Alternatively, after separating the panel area PA, some structures within the panel area PA can be removed (for example, the test signal terminal 500 within the panel area PA described below can be removed) to allow the remaining structures within the single panel area PA to form a single complete display panel.

[0048] Optionally, the plurality of display panel areas PA may be arranged in an array in the first direction X and the second direction Y. For example, the plurality of display panel areas PA may be arranged at intervals in the first direction X. For another example, the plurality of display panel areas PA may be arranged at intervals in the second direction Y.

[0049] The display panel motherboard 10 includes a plurality of sub-pixels 400 and a plurality of test signal terminals 500. A plurality of sub-pixels 400 are provided in each panel area PA, and the sub-pixels 400 can be used to realize light-emitting display.

[0050] Optionally, after the display panel motherboard 10 is processed by cutting or other processing techniques to prepare a plurality of display panels, the sub-pixels 400 may be retained in the prepared display panels, and the sub-pixels 400 may be used to realize luminous display of the display panels.

[0051] Optionally, the sub-pixel 400 may utilize the light-emitting principle of an organic light-emitting diode to realize light-emitting display.

[0052] Optionally, the sub-pixel 400 may include a light-emitting device 420 and a driving circuit 410 connected to the light-emitting device 420 , and the driving circuit 410 may be used to drive the light-emitting device 420 to emit light.

[0053] Optionally, the display panel motherboard 10 may further include a substrate 100 , the driving circuit 410 may be disposed in the substrate 100 , and the light emitting device 420 may be disposed on one side of the substrate 100 .

[0054] Optionally, the driving circuit 410 may include a transistor 411, a storage capacitor 412, and signal lines for connecting various devices in the driving circuit 410. For example, the transistor 411 may include a semiconductor, a gate 411a, and a source and drain 411b. The storage capacitor 412 may include a first plate 412a and a second plate 412b.

[0055] Optionally, the substrate 100 may include a first insulating layer 120, a second insulating layer 130, and a third insulating layer 140 that are stacked. As an example, the gate 411a and the first electrode 412a may be located on the side of the first insulating layer 120 facing the substrate 110, the second electrode 412b may be located between the first insulating layer 120 and the second insulating layer 130, and the source and drain 411b may be located between the second insulating layer 130 and the third insulating layer 140.

[0056] Optionally, in a direction away from the substrate 100 , the light emitting device 420 may include a first electrode 421 , a light emitting functional layer 422 and a second electrode 423 stacked in sequence.

[0057] Optionally, the light-emitting functional layer 422 may include a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting structure, an electron injection layer (EIL), and an electron transport layer (ETL).

[0058] Optionally, the first electrode 421 and the second electrode 423 can serve as pixel electrodes, one of which can serve as an anode and the other as a cathode to drive the light-emitting functional layer 422 to emit light. In the embodiment of the present application, the first electrode 421 is used as the anode and the second electrode 423 is used as the cathode.

[0059] Optionally, the plurality of sub-pixels 400 include a first type of sub-pixel 401, a second type of sub-pixel 402, and a third type of sub-pixel 403, each emitting different luminous colors, so that the display panel formed using the display panel motherboard 10 can achieve color display. For example, the first type of sub-pixel 401 emits red luminous color, the second type of sub-pixel 402 emits green luminous color, and the third type of sub-pixel 403 emits blue luminous color.

[0060] Optionally, a single first-type sub-pixel 401, a single second-type sub-pixel 402, and a single third-type sub-pixel 403 constitute a single pixel group 400a. There may be multiple pixel groups 400a, and the multiple pixel groups 400a may be arranged in an array in the first direction X and the second direction Y. For example, the multiple pixel groups 400a may be arranged at intervals in the first direction X. For another example, the multiple pixel groups 400a may be arranged at intervals in the second direction Y.

[0061] The arrangement of the sub-pixels 400 in at least two panel areas PA is different, so that different panel areas PA with different arrangements of the sub-pixels 400 can be used to form display panels with different arrangements of the sub-pixels 400, that is, a single display panel motherboard 10 can be used to form at least two display panels with different arrangements of the sub-pixels 400, which can facilitate improving the production efficiency of the display panels.

[0062] Optionally, the display panel motherboard 10 may have a panel area PA with two different arrangements of sub-pixels 400, or may have more than two different arrangements of sub-pixels 400. For ease of description, the following embodiments will be described using an example in which the display panel motherboard 10 has a panel area PA with two different arrangements of sub-pixels 400.

[0063] Exemplarily, the panel area PA includes a first-type panel area PA1 and a second-type panel area PA2 . The arrangement of the sub-pixels 400 in the first-type panel area PA1 may be different from the arrangement of the sub-pixels 400 in the second-type panel area PA2 .

[0064] Optionally, the arrangement of the sub-pixels 400 in at least two panel areas PA is different, which may mean that the relative positions of the first type of sub-pixels 401, the second type of sub-pixels 402 and the third type of sub-pixels 403 in the pixel group 400a in at least two panel areas PA are different.

[0065] Optionally, the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402 and the third type of sub-pixels 403 in the first type of panel area PA1 is different from the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402 and the third type of sub-pixels 403 in the second type of panel area PA2.

[0066] Optionally, in the pixel groups 400a within the first type of panel area PA1 and the second type of panel area PA2, the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 are spaced apart in the first direction X. The different arrangements of the sub-pixels 400 within at least two panel areas PA may mean that the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 within the first type of panel area PA1 in the first direction X is different from the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 within the second type of panel area PA2 in the first direction X.

[0067] For example, in the pixel group 400a in the first type panel area PA1, the first type sub-pixel 401, the second type sub-pixel 402 and the third type sub-pixel 403 are sequentially arranged along the first direction X, for example, Figure 3 As shown, in the pixel group 400a within the first type of panel area PA1, the first type of sub-pixel 401, the second type of sub-pixel 402 and the third type of sub-pixel 403 are arranged in sequence from left to right; in the pixel group 400a within the second type of panel area PA2, the second type of sub-pixel 402, the first type of sub-pixel 401 and the third type of sub-pixel 403 are arranged in sequence along the first direction X, for example, Figure 4 As shown, in the pixel group 400a within the second type panel area PA2, the second type sub-pixel 402, the first type sub-pixel 401 and the third type sub-pixel 403 are arranged in sequence from left to right.

[0068] Optionally, the shapes of the panel areas PA with different sub-pixel 400 arrangements may also differ. For example, the shapes of the first type panel area PA1 and the second type panel area PA2 may differ. For example, the first type panel area PA1 may be square, and the second type panel area PA2 may be circular.

[0069] Optionally, the arrangement density of the sub-pixels 400 in each panel area PA having a different arrangement of the sub-pixels 400 may also be different. For example, the arrangement density of the sub-pixels 400 in the first type panel area PA1 may be different from the arrangement density of the sub-pixels 400 in the second type panel area PA2. For example, the arrangement density of the sub-pixels 400 in the first type panel area PA1 may be lower than the arrangement density of the sub-pixels 400 in the second type panel area PA2.

[0070] Optionally, the arrangement density of the sub-pixels 400 in a certain panel area PA may refer to the ratio between the number of sub-pixels 400 in the certain panel area PA and the area of ​​the panel area PA.

[0071] Optionally, the display panel may further include an isolation structure 300 disposed on one side of the substrate 100. The isolation structure 300 may enclose an isolation opening 301. The light-emitting device 420 may be at least partially located within the isolation opening 301. The isolation structure 300 may be used to divide the display panel into sub-pixels 400. For example, the second electrode 423 and the light-emitting functional layer 422 of the light-emitting device 420 may be at least partially located within the isolation opening 301.

[0072] Optionally, the isolation opening 301 may include a first opening 301a, a second opening 301b and a third opening 301c, the first type of sub-pixel 401 may be at least partially located in the first opening 301a, the second type of sub-pixel 402 may be at least partially located in the second opening 301b, and the third type of sub-pixel 403 may be at least partially located in the third opening 301c.

[0073] Optionally, since the sub-pixels 400 and the isolation openings 301 are arranged corresponding to each other, that is, the arrangement of the first opening 301a, the second opening 301b, and the third opening 301c in any panel area PA can be the same as the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 in the panel area PA. Therefore, the arrangement of the isolation openings 301 in each panel area PA with different arrangements of sub-pixels 400 can also be different. For example, the arrangement of the first opening 301a, the second opening 301b, and the third opening 301c in the first type of panel area PA1 is different from the arrangement of the first opening 301a, the second opening 301b, and the third opening 301c in the second type of panel area PA2.

[0074] Optionally, the isolation structure 300 includes a first isolation portion 310 and a second isolation portion 320 located on a side of the first isolation portion 310 facing away from the substrate 100 . The second isolation portion 320 is disposed protruding from the first isolation portion 310 toward the isolation opening 301 .

[0075] By arranging the second isolation portion 320 to protrude from the first isolation portion 310 toward the isolation opening 301, when preparing the light-emitting device 420, part of the material of the light-emitting device 420 (for example, the material of the light-emitting functional layer 422 and the material of the second electrode 423) can be directly evaporated on the entire surface. The second isolation portion 320 can block at least part of the material used to prepare the light-emitting device 420 to separate the material of the light-emitting device 420 between adjacent sub-pixels 400, so as to form a plurality of light-emitting devices 420 that are spaced apart and located in different isolation openings 301, so that when preparing the light-emitting device 420, there is no need to set a mask with high precision. For example, when evaporating part of the material of the light-emitting device 420, there is no need to set a high-precision metal mask (Fine Metal Mask, FMM), thereby effectively reducing the production and preparation cost of the display panel motherboard 10.

[0076] At the same time, since there is no need to set a mask with high precision when preparing the light-emitting device 420, when preparing sub-pixels 400 with different arrangements in different panel areas PA in the display panel motherboard 10, there is no need to set a plurality of mask plates with high precision corresponding to each panel area PA with different arrangements of sub-pixels 400, thereby facilitating the formation of at least two panel areas PA with different arrangements of sub-pixels 400 on a single display panel motherboard 10, thereby effectively reducing the preparation cost of the display panel motherboard 10.

[0077] Optionally, the material of the isolation structure 300 may include a conductive material, and the second electrode 423 may be connected to the isolation structure 300 , so that the second electrodes 423 of adjacent sub-pixels 400 can be electrically connected through the isolation structure 300 to facilitate control of the second electrodes 423 .

[0078] Optionally, the second electrode 423 may be connected to the first isolation portion 310 , so that the second electrodes 423 of adjacent sub-pixels 400 may be electrically connected through the first isolation portion 310 .

[0079] Optionally, the isolation structure 300 further includes a conductive portion 330 disposed on the side of the first isolation portion 310 facing the substrate 100. The conductive portion 330 may be disposed protruding from the first isolation portion 310 toward the isolation opening 301, and the second electrode 423 may be connected to the conductive portion 330. By disposing the conductive portion 330 protruding from the first isolation portion 310 toward the isolation opening 301, a larger area is provided on the conductive portion 330, which facilitates connection with the second electrode 423, thereby facilitating electrical connection between the second electrode 423 and the isolation structure 300.

[0080] Optionally, the display panel may further include a pixel definition layer 200 disposed on one side of the substrate 100. The pixel definition layer 200 may have a pixel opening 201 that communicates with the isolation opening 301. A portion of the structure of the light-emitting device 420 may be located within the pixel opening 201, and another portion of the light-emitting device 420 may be located within the isolation opening 301. The pixel definition layer 200 may also be used to participate in dividing the sub-pixels 400 of the display panel. Exemplarily, the second electrode 423 and the light-emitting functional layer 422 of the light-emitting device 420 may extend from within the pixel opening 201 into the isolation opening 301, and at least a portion of the surface of the first electrode 421 on the side facing away from the substrate 100 may be exposed from the pixel opening 201 and connected to the light-emitting functional layer 422 within the pixel opening 201.

[0081] Optionally, the number of the isolation openings 301 and the number of the pixel openings 201 may be multiple, and a single isolation opening 301 may be connected to a single pixel opening 201 .

[0082] Optionally, there are many ways to set the relative position between the pixel definition layer 200 and the isolation structure 300, for example, Figure 1 As shown, the isolation structure 300 can be disposed on the side of the pixel definition layer 200 facing away from the substrate 100, that is, the isolation structure 300 can be disposed directly on the pixel definition layer 200. Alternatively, for example, the pixel definition layer 200 can be provided with a groove structure (not shown in the figure), and at least a portion of the isolation structure 300 can be located within the groove structure. This reduces the height of the isolation structure 300 relative to the substrate 100, thereby effectively reducing the thickness of the display panel motherboard 10. For ease of description, the following embodiments will be described using the example of the isolation structure 300 being disposed on the side of the pixel definition layer 200 facing away from the substrate 100.

[0083] Multiple test signal terminals 500 are provided in each panel area PA. The test signal terminals 500 in the panel area PA are electrically connected to the corresponding sub-pixels 400. The test signal terminals 500 can be used to drive the sub-pixels 400 to emit light, so that the display panel motherboard 10 can be tested through the test signal terminals 500.

[0084] Optionally, the test signal terminal 500 may be connected to the driving circuit 410 in the sub-pixel 400, so that the test signal terminal 500 can drive the light-emitting device 420 to emit light through the driving circuit 410. Exemplarily, the test signal terminal 500 may be used to transmit a data signal (Data signal) to the driving circuit 410 in the sub-pixel 400 to participate in driving the sub-pixel 400 to emit light.

[0085] Optionally, the test signal terminal 500 can be used to participate in testing the display effect of the display panel motherboard 10. Exemplarily, the test signal terminal 500 can be used to participate in the lighting test of the display panel motherboard 10 to test the display effect of the display panel motherboard 10 after lighting (for example, spectrum, chromaticity, color difference, dark spots, bright spots, bright lines, etc.).

[0086] Optionally, a test device TD can be connected to the test signal terminal 500 so that the test device TD can transmit a data signal to the sub-pixel 400 through the test signal terminal 500 to drive the sub-pixel 400 to emit light, thereby realizing testing of the display panel motherboard 10.

[0087] Optionally, the test device TD may include a main part TD1 and a transition part TD2, and the transition part TD2 may be arranged on at least one side of the main part TD1 in the second direction Y. For example, in a single test device TD, the transition part TD2 may be arranged on the same side of the main part TD1 in the second direction Y.

[0088] Optionally, a single transfer portion TD2 can be used to transmit data signals to a single panel area PA to drive the sub-pixels 400 within the single panel area PA to emit light. Exemplarily, a single transfer portion TD2 can have multiple signal transmission terminals TD21, where a single signal transmission terminal TD21 can be connected to a single test signal terminal 500. The main portion TD1 can be used to send a signal to the test signal terminal 500 via the signal transmission terminal TD21, so that the test signal terminal 500 can be used to transmit data signals to the driving circuit 410 in the sub-pixel 400 to drive the sub-pixel 400 to emit light, thereby implementing testing of the display panel motherboard 10.

[0089] Optionally, the test signal terminal 500 may be disposed on one side of the substrate 100 , or a slot structure may be provided in the substrate 100 , and the test signal terminal 500 may be exposed from the slot structure in the substrate 100 to facilitate connection between the test device TD and the test signal terminal 500 .

[0090] Optionally, there may be multiple transfer portions TD2 , and the multiple transfer portions TD2 may be spaced apart in the first direction X, so that a single testing device TD can test multiple panel areas PA spaced apart in the first direction X at the same time.

[0091] Optionally, the transfer portion TD2 may include a flexible printed circuit (FPC) so that the transfer portion TD2 has good deformability, so as to facilitate connection between the signal transmission terminal TD21 in the transfer portion TD2 and the test signal terminal 500 in the display panel motherboard 10 .

[0092] Optionally, the spacing between adjacent display panel areas PA may be the same or different, and this application does not impose any specific limitations thereon. When the spacing between adjacent display panel areas PA is different, the transfer portion TD2 including the flexible circuit board may deform to facilitate connection between each transfer portion TD2 in the test device TD and each panel area PA.

[0093] Optionally, the testing device TD may also include an optical instrument, which can be used to obtain optical information of the display panel motherboard 10 after the transfer part TD2 drives at least part of the sub-pixels 400 in the display panel motherboard 10 to emit light, so as to realize the detection of the display effect of the display panel motherboard 10.

[0094] Optionally, the optical instrument may include a camera, an optical probe, or other instrument for acquiring optical information. The optical instrument may be used to acquire optical information such as spectrum, chromaticity, color difference, dark spots, bright spots, and bright lines of the sub-pixels 400 in the display panel motherboard 10.

[0095] Optionally, there are many ways to arrange the first type panel area PA1 and the second type panel area PA2. Figure 2 As shown, the first type panel areas PA1 can all be located on the same side of the second type panel areas PA2 in the first direction X, so that the first type panel areas PA1 can be arranged more concentratedly in one area, and the second type panel areas PA2 can be arranged more concentratedly in one area, which is conducive to the optical instrument to more independently obtain optical information from different display panel areas PA. Or for example, the first type panel areas PA1 and the second type panel areas PA2 can be alternately distributed in the first direction X (not shown in the figure), so that when the shapes of the first type panel areas PA1 and the second type panel areas PA2 are different, by arranging the first type panel areas PA1 and the second type panel areas PA2 to be alternately distributed in the first direction X, it can be beneficial to improve the arrangement density of the first type panel areas PA1 and the second type panel areas PA2 in the display panel motherboard 10.

[0096] By setting the arrangement of the test signal terminals 500 in each panel area PA to be the same, during the testing process of the display panel motherboard 10, the same set of testing equipment TD can be used to test each panel area PA with different sub-pixel 400 arrangements in the display panel motherboard 10, thereby better improving the preparation efficiency of the display panel motherboard 10 and better reducing the cost of the testing equipment TD.

[0097] For example, by setting the arrangement of the test signal terminals 500 in each panel area PA to be the same, during the test process of the display panel motherboard 10, the arrangement of the signal transmission terminals TD21 of each transfer part TD2 in the test device TD can be made the same, so that the same set of test devices TD can be used to test the various panel areas PA with different sub-pixel 400 arrangements in the display panel motherboard 10, so that during the test process of the display panel motherboard 10, the various panel areas PA in the display panel motherboard 10 can be normally lit to present a picture of the required color, and no cross-color will occur between the various panel areas PA with different sub-pixel 400 arrangements, thereby better improving the preparation efficiency of the display panel motherboard 10 and better reducing the cost of the test device TD.

[0098] Figure 5 1 is a partial structural diagram of a display panel motherboard 10 provided in an embodiment of the present application. Figure 6 It is a partial structural diagram of a display panel motherboard 10 provided in another embodiment of the present application.

[0099] like Figures 3 to 6 As shown, in some optional embodiments, the multiple test signal terminals 500 include a first type of test signal terminal 510 set corresponding to the first type of sub-pixel 401, a second type of test signal terminal 520 set corresponding to the second type of sub-pixel 402, and a third type of test signal terminal 530 set corresponding to the third type of sub-pixel 403. The arrangement between the first type of test signal terminal 510, the second type of test signal terminal 520 and the third type of test signal terminal 530 in the first type of panel area PA1 is the same as the arrangement between the first type of test signal terminal 510, the second type of test signal terminal 520 and the third type of test signal terminal 530 in the second type of panel area PA2.

[0100] Optionally, the first type of test signal terminal 510 set corresponding to the first type of sub-pixel 401 may refer to the first type of test signal terminal 510 that can be used to participate in driving the first type of sub-pixel 401 to emit light. For example, the first type of test signal terminal 510 can be used to transmit a data signal to the first type of sub-pixel 401 to participate in driving the first type of sub-pixel 401 to emit light.

[0101] The second type of test signal terminal 520 set corresponding to the second type of sub-pixel 402 may refer to the second type of test signal terminal 520 that can be used to participate in driving the second type of sub-pixel 402 to emit light. For example, the second type of test signal terminal 520 can be used to transmit a data signal to the second type of sub-pixel 402 to participate in driving the second type of sub-pixel 402 to emit light.

[0102] The third type of test signal terminal 530 set corresponding to the third type of sub-pixel 403 may refer to the third type of test signal terminal 530 that can be used to participate in driving the third type of sub-pixel 403 to emit light. For example, the third type of test signal terminal 530 can be used to transmit a data signal to the third type of sub-pixel 403 to participate in driving the third type of sub-pixel 403 to emit light.

[0103] In these optional embodiments, by setting the arrangement between the first type of test signal terminal 510, the second type of test signal terminal 520 and the third type of test signal terminal 530 in the first type of panel area PA1 to be the same as the arrangement between the first type of test signal terminal 510, the second type of test signal terminal 520 and the third type of test signal terminal 530 in the second type of panel area PA2, during the testing process of the display panel motherboard 10, the same set of testing equipment TD can be used to test the first type of panel area PA1 and the second type of panel area PA2 in the display panel motherboard 10, thereby better improving the preparation efficiency of the display panel motherboard 10 and better reducing the cost of the testing equipment TD.

[0104] In some optional embodiments, a single first-type test signal terminal 510, a single second-type test signal terminal 520, and a single third-type test signal terminal 530 constitute a single test group 500a. In the test group 500a within the first-type panel area PA1 and the second-type panel area PA2, the first-type test signal terminal 510, the second-type test signal terminal 520, and the third-type test signal terminal 530 are spaced apart in the first direction X.

[0105] Optionally, the arrangement between the first type of test signal terminal 510, the second type of test signal terminal 520 and the third type of test signal terminal 530 in the first type of panel area PA1 is the same as the arrangement between the first type of test signal terminal 510, the second type of test signal terminal 520 and the third type of test signal terminal 530 in the second type of panel area PA2, which may mean that the arrangement between the first type of test signal terminal 510, the second type of test signal terminal 520 and the third type of test signal terminal 530 in the first type of panel area PA1 in the first direction X may be the same as the arrangement between the first type of test signal terminal 510, the second type of test signal terminal 520 and the third type of test signal terminal 530 in the second type of panel area PA2 in the first direction X.

[0106] Illustratively, in the test group 500a within the first type panel area PA1 and the second type panel area PA2, the first type test signal end 510, the second type test signal end 520, and the third type test signal end 530 are all arranged sequentially along the first direction X. For example, as shown in the aforementioned figures, in the test group 500a within the first type panel area PA1 and the second type panel area PA2, the first type test signal end 510, the second type test signal end 520, and the third type test signal end 530 are all arranged sequentially from left to right.

[0107] Optionally, the plurality of signal transmission ends TD21 in a single transfer portion TD2 may be arranged at intervals in the first direction X.

[0108] In these optional embodiments, by setting the first type test signal terminal 510, the second type test signal terminal 520 and the third type test signal terminal 530 in the test group 500a within the first type panel area PA1 and the second type panel area PA2 to be spaced apart in the first direction X, the signal transmission terminal TD21 of each transfer part TD2 in the test device TD can be spaced apart along the first direction X, so that the first type panel area PA1 and the second type panel area PA2 in the display panel motherboard 10 can be tested using the same set of test devices TD, thereby better improving the preparation efficiency of the display panel motherboard 10.

[0109] In some optional embodiments, the first type of test signal terminal 510, the second type of test signal terminal 520 and the third type of test signal terminal 530 all include a control signal terminal, a switch signal terminal and a lighting signal terminal, and the display panel motherboard 10 also includes a test control transistor 600, a test switch transistor 700 and a connecting line CL. Test control transistors 600 and test switch transistors 700 are provided in each panel area PA. In a single panel area PA, the control end of the test control transistor 600 is connected to the control signal end, the sub-pixel 400 is connected to the first end of the test control transistor 600, the second end of the test control transistor 600 is connected to the first end of the test switch transistor 700, the control end of the test switch transistor 700 is connected to the switch signal end, and the second end of the test switch transistor 700 is connected to the lighting signal end.

[0110] Optionally, the control terminal of any transistor described in the embodiments of the present application may refer to the gate of the transistor.

[0111] Optionally, among the first end and the second end of any transistor described in the embodiments of the present application, one may refer to the source in the source-drain of the transistor, and the other may refer to the drain in the source-drain of the transistor, and the present application does not make any specific limitations on this.

[0112] Optionally, any transistor described in the embodiments of the present application may be a P-type transistor or an N-type transistor, which is not specifically limited in the present application.

[0113] Optionally, the test control transistor 600 , the test switch transistor 700 and the connection line CL may be disposed in the substrate 100 .

[0114] In these optional embodiments, the test control transistor 600 can be used as a demultiplexer circuit (demux circuit) in the panel area PA. Under the action of the test device TD, the control signal end can provide a signal to the control end of the test control transistor 600 to control the conduction and cutoff of the test control transistor 600. The switch signal end can provide a signal to the control end of the test switch transistor 700 to control the conduction and cutoff of the test switch transistor 700. When the test control transistor 600 and the test switch transistor 700 are both turned on, the lighting signal end can provide a data signal to the sub-pixel 400 via the test switch transistor 700 and the test control transistor 600 to drive the sub-pixel 400 to emit light, thereby realizing the test of the display panel motherboard 10.

[0115] In some optional embodiments, the test signal terminal 500, the test control transistor 600, the test switch transistor 700 and the connecting line CL are all arranged on the same side of the sub-pixel 400 in the second direction Y, and multiple sub-pixels 400 with the same luminous color are arranged at intervals in the second direction Y, and the sub-pixels 400 located in the same column in the second direction Y are connected to the first end of the same test control transistor 600.

[0116] Optionally, within a single panel area PA, the sub-pixels 400 located in the same column in the second direction Y may emit the same light color.

[0117] Optionally, the display panel further includes a data signal line DL, and the sub-pixels 400 located in the same column in the second direction Y are connected to the first end of the same test control transistor 600 through the single data signal line DL.

[0118] Optionally, the data signal line DL at least partially extends along the second direction Y.

[0119] In these optional embodiments, by arranging the test signal terminal 500, the test control transistor 600, the test switch transistor 700, and the connection line CL on the same side of the sub-pixel 400 in the second direction Y, it is possible to facilitate the test device TD to drive the sub-pixels 400 in the panel area PA to emit light from one side of the panel area PA in the second direction Y. By arranging the test signal terminal 500, the test control transistor 600, the test switch transistor 700, and the connection line CL on the same side of the sub-pixel 400 in the second direction Y, and by connecting the sub-pixels 400 in the same column in the second direction Y to the first end of the same test control transistor 600, a single test control transistor 600 can be used to control the light emission of the sub-pixels 400 of the same color in the same column in the second direction Y, thereby facilitating testing of the display panel motherboard 10.

[0120] In some optional embodiments, the first type of test signal terminal 510 includes a first type of control signal terminal 511, a first type of switch signal terminal 512 and a first type of lighting signal terminal 513, the second type of test signal terminal 520 includes a second type of control signal terminal 521, a second type of switch signal terminal 522 and a second type of lighting signal terminal 523, the third type of test signal terminal 530 includes a third type of control signal terminal 531, a third type of switch signal terminal 532 and a third type of lighting signal terminal 533, the test control transistor 600 includes a first type of control transistor 610, a second type of control transistor 620 and a third type of control transistor 630, and the test switch transistor 700 includes a first type of switch transistor 710, a second type of switch transistor 720 and a third type of switch transistor 730.

[0121] A single first-class sub-pixel 401, a single second-class sub-pixel 402 and a single third-class sub-pixel 403 constitute a single pixel group 400a, and a single first-class control transistor 610, a single first-class switching transistor 710, a single second-class switching transistor 720 and a single third-class switching transistor 730 constitute a single switch group 700a.

[0122] In a single panel area PA, the control end of the first type of control transistor 610 is connected to the first type of control signal end 511, the control end of the second type of control transistor 620 is connected to the second type of control signal end 521, the control end of the third type of control transistor 630 is connected to the third type of control signal end 531, the first type of sub-pixel 401 is connected to the first end of the first type of control transistor 610, the second type of sub-pixel 402 is connected to the first end of the second type of control transistor 620, the third type of sub-pixel 403 is connected to the first end of the third type of control transistor 630, and the first end of each test control transistor 600 connected to the sub-pixel 400 in the same pixel group 400a. Both ends are connected to the first end of each test switch transistor 700 in the switch group 700a through the same connecting line CL, the control end of the first type switch transistor 710 is connected to the first type switch signal end 512, the control end of the second type switch transistor 720 is connected to the second type switch signal end 522, the control end of the third type switch transistor 730 is connected to the third type switch signal end 532, the second end of the first type switch transistor 710 is connected to the first type lighting signal end 513, the second end of the second type switch transistor 720 is connected to the second type lighting signal end 523, and the second end of the third type switch transistor 730 is connected to the third type lighting signal end 533.

[0123] Optionally, the control signal terminals described in the aforementioned embodiments may include a first-type control signal terminal 511, a second-type control signal terminal 521, and a third-type control signal terminal 531. The switch signal terminals described in the aforementioned embodiments may include a first-type switch signal terminal 512, a second-type switch signal terminal 522, and a third-type switch signal terminal 532. The lighting signal terminals described in the aforementioned embodiments may include a first-type lighting signal terminal 513, a second-type lighting signal terminal 523, and a third-type lighting signal terminal 533.

[0124] Optionally, the signal transmission terminal TD21 may include a first-type control transmission terminal TD21a, a second-type control transmission terminal TD21b, a third-type control transmission terminal TD21c, a first-type switch transmission terminal TD21d, a second-type switch transmission terminal TD21e, a third-type switch transmission terminal TD21f, a first-type lighting transmission terminal TD21g, a second-type lighting transmission terminal TD21h, and a third-type lighting transmission terminal TD21i.

[0125] The first-type control transmission terminal TD21a can be connected to the first-type control signal terminal 511 to control the on / off state of the first-type control transistor 610 via the first-type control signal terminal 511. The second-type control transmission terminal TD21b can be connected to the second-type control signal terminal 521 to control the on / off state of the second-type control transistor 620 via the second-type control signal terminal 521. The third-type control transmission terminal TD21c can be connected to the third-type control signal terminal 531 to control the on / off state of the third-type control transistor 630 via the third-type control signal terminal 531.

[0126] The first-type switch transmission terminal TD21d can be connected to the first-type switch signal terminal 512 to control the on / off state of the first-type switch transistor 710 via the first-type switch signal terminal 512. The second-type switch transmission terminal TD21e can be connected to the second-type switch signal terminal 522 to control the on / off state of the second-type switch transistor 720 via the second-type switch signal terminal 522. The third-type switch transmission terminal TD21f can be connected to the third-type switch signal terminal 532 to control the on / off state of the third-type switch transistor 730 via the third-type switch signal terminal 532.

[0127] The first-type lighting transmission terminal TD21g can be used to connect to the first-type lighting signal terminal 513 to provide a data signal to the first-type sub-pixel 401 via the first-type lighting signal terminal 513. The second-type lighting transmission terminal TD21h can be used to connect to the second-type lighting signal terminal 523 to provide a data signal to the second-type sub-pixel 402 via the second-type lighting signal terminal 523. The third-type lighting transmission terminal TD21i can be used to connect to the third-type lighting signal terminal 533 to provide a data signal to the third-type sub-pixel 403 via the third-type lighting signal terminal 533.

[0128] In these optional embodiments, under the action of the test device TD, the first type of control signal terminal 511, the second type of control signal terminal 521 and the third type of control signal terminal 531 can respectively provide signals to the control terminals of the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 to respectively control the conduction and cutoff of the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630, and the first type of switch signal terminal 512, the second type of switch signal terminal 522 and the third type of switch signal terminal 532 can provide signals to the control ends of the first type switching transistor 710, the second type switching transistor 720 and the third type switching transistor 730 respectively to control the conduction and cutoff of the first type switching transistor 710, the second type switching transistor 720 and the third type switching transistor 730 respectively, so that during the test of the display panel motherboard 10, the various panel areas PA in the display panel motherboard 10 can be normally lit to present the required color picture, and no cross-color will occur between the various panel areas PA with different sub-pixel 400 arrangements.

[0129] When the first-type control transistor 610 and the first-type switching transistor 710 are both turned on, the first-type lighting signal terminal 513 can provide a data signal to the first-type sub-pixel 401 via the first-type switching transistor 710 and the first-type control transistor 610 to drive the first-type sub-pixel 401 to emit light. At this time, the second-type control transistor 620, the second-type switching transistor 720, the third-type control transistor 630 and the third-type switching transistor 730 can all be in the cut-off state, and the second-type lighting signal terminal 523 may not transmit the data signal (for example, at this time, the signal in the second-type lighting signal terminal 523 may be a non-data signal, and the non-data signal may cause the sub-pixel 400 not to emit light), and the third-type lighting signal terminal 533 may not transmit the data signal (for example, at this time, the signal in the third-type lighting signal terminal 533 may be a non-data signal), so that the panel area PA can present a red picture, which can facilitate the test device TD to detect the display effect of the first-type sub-pixel 401 in the display panel motherboard 10.

[0130] When the second-type control transistor 620 and the second-type switching transistor 720 are both turned on, the second-type lighting signal terminal 523 can provide a data signal to the second-type sub-pixel 402 via the second-type switching transistor 720 and the second-type control transistor 620 to drive the second-type sub-pixel 402 to emit light. At this time, the first-type control transistor 610, the first-type switching transistor 710, the third-type control transistor 630 and the third-type switching transistor 730 can all be in the cut-off state, and the first-type lighting signal terminal 513 may not transmit the data signal (for example, the signal in the first-type lighting signal terminal 513 may be a non-data signal at this time), and the third-type lighting signal terminal 533 may not transmit the data signal (for example, the signal in the third-type lighting signal terminal 533 may be a non-data signal at this time), so that the panel area PA can present a green picture, which can facilitate the test device TD to detect the display effect of the second-type sub-pixel 402 in the display panel motherboard 10.

[0131] When the third-type control transistor 630 and the third-type switching transistor 730 are both turned on, the third-type lighting signal terminal 533 can provide a data signal to the third-type sub-pixel 403 via the third-type switching transistor 730 and the third-type control transistor 630 to drive the third-type sub-pixel 403 to emit light. At this time, the first-type control transistor 610, the first-type switching transistor 710, the second-type control transistor 620 and the second-type switching transistor 720 can all be in the cut-off state, and the first-type lighting signal terminal 513 may not transmit the data signal (for example, the signal in the first-type lighting signal terminal 513 may be a non-data signal at this time), and the second-type lighting signal terminal 523 may not transmit the data signal (for example, the signal in the second-type lighting signal terminal 523 may be a non-data signal at this time), so that the panel area PA can present a blue picture, which can facilitate the test device TD to detect the display effect of the third-type sub-pixel 403 in the display panel motherboard 10.

[0132] Among them, by setting the second ends of each test control transistor 600 connected to the sub-pixel 400 in the same pixel group 400a to be connected to the first ends of each test switch transistor 700 in the switch group 700a through the same connection line CL, the space occupied by the signal line in the panel area PA can be effectively reduced, which can facilitate the display panel motherboard 10 to be used to prepare a display panel in a wearable device with a smaller size.

[0133] Figure 7 1 is a schematic timing diagram of a test driving method for a display panel motherboard 10 provided in an embodiment of the present application. Figure 7 T1 in the figure may indicate a test state, T1a may indicate a first stage, T1b may indicate a second stage, and T1c may indicate a third stage.

[0134] like Figure 7As shown, in some optional embodiments, the display panel motherboard 10 has a test state, and the test state has a first stage, a second stage, and a third stage.

[0135] Optionally, the first stage, the second stage, and the third stage may not overlap, and this application does not specifically limit the order of the first stage, the second stage, and the third stage. For example, the first stage may be before the second stage, and the third stage may be after the second stage; or, the first stage may be before the third stage, and the second stage may be after the third stage; or, the second stage may be before the first stage, and the third stage may be after the first stage; or, the second stage may be before the third stage, and the first stage may be after the third stage; or, the third stage may be before the first stage, and the second stage may be after the first stage; or, the third stage may be before the second stage, and the first stage may be after the second stage.

[0136] Optionally, a single test state of the display panel motherboard 10 may have multiple first stages, multiple second stages, and multiple third stages, wherein the first stage, the second stage, and the third stage may be performed alternately.

[0137] In these optional embodiments, in the test state, the test device TD can light up each panel area PA in the display panel motherboard 10 to test the display effect of the display panel motherboard 10. In the first stage, the second stage, and the third stage, the panel area PA in the display panel motherboard 10 can present different display images.

[0138] In some optional embodiments, in the first stage, the first type of control signal terminal 511 in the first type of panel area PA1 and the second type of panel area PA2 is used to control the conduction of the first type of control transistor 610, and the first type of switching signal terminal 512 in the first type of panel area PA1 and the second type of panel area PA2 is used to control the conduction of the first type of switching transistor 710.

[0139] Illustratively, in the first stage, the signal provided by the first type control signal terminal 511 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the first type control transistor 610 jumps to a valid level to turn on the first type control transistor 610, and the signal provided by the first type switching signal terminal 512 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the first type switching transistor 710 jumps to a valid level to turn on the first type switching transistor 710.

[0140] Optionally, in the first stage, the first type lighting signal terminal 513 in the first type panel area PA1 and the second type panel area PA2 can be used to provide a data signal to the first type sub-pixel 401 via the first type switching transistor 710 and the first type control transistor 610 to drive the first type sub-pixel 401 to emit light.

[0141] Optionally, in the first stage, the second type of control signal terminal 521 in the first type panel area PA1 and the second type panel area PA2 is used to control the cutoff of the second type control transistor 620, the third type of control signal terminal 531 in the first type panel area PA1 and the second type panel area PA2 is used to control the cutoff of the third type control transistor 630, the second type of switching signal terminal 522 in the first type panel area PA1 and the second type panel area PA2 is used to control the cutoff of the second type switching transistor 720, and the third type of switching signal terminal 532 in the first type panel area PA1 and the second type panel area PA2 is used to control the cutoff of the third type switching transistor 730.

[0142] Exemplarily, in the first stage, the signal provided by the second-type control signal terminal 521 in the first-type panel area PA1 and the second-type panel area PA2 to the control terminal of the second-type control transistor 620 jumps to an invalid level to turn off the second-type control transistor 620, the signal provided by the third-type control signal terminal 531 in the first-type panel area PA1 and the second-type panel area PA2 to the control terminal of the third-type control transistor 630 jumps to an invalid level to turn off the third-type control transistor 630, and the signal provided by the second-type switch signal terminal 522 in the first-type panel area PA1 and the second-type panel area PA2 to the control terminal of the second-type switch transistor 720 jumps to an invalid level to turn off the second-type switch transistor 720, and the signal provided by the third-type switch signal terminal 532 in the first-type panel area PA1 and the second-type panel area PA2 to the control terminal of the third-type switch transistor 730 jumps to an invalid level to turn off the third-type switch transistor 730.

[0143] Optionally, in the first stage, the second-type lighting signal terminal 523 in the first-type panel area PA1 and the second-type panel area PA2 can stop providing data signals to the second-type sub-pixel 402, and the third-type lighting signal terminal 533 in the first-type panel area PA1 and the second-type panel area PA2 can stop providing data signals to the third-type sub-pixel 403.

[0144] In these optional embodiments, in the first stage, the first type of sub-pixels 401 in the first type of panel area PA1 and the second type of panel area PA2 are both illuminated, and the second type of sub-pixels 402 and the third type of sub-pixels 403 in the first type of panel area PA1 and the second type of panel area PA2 are not illuminated, so that the first type of panel area PA1 and the second type of panel area PA2 of the display panel motherboard 10 can both present red images, which can facilitate the test device TD to simultaneously detect the display effects of the first type of sub-pixels 401 in the first type of panel area PA1 and the second type of panel area PA2 in the display panel motherboard 10 under the same test drive timing.

[0145] In some optional embodiments, in the second stage, the second type of control signal terminal 521 in the first type panel area PA1 and the second type panel area PA2 is used to control the conduction of the second type control transistor 620, and the second type of switching signal terminal 522 in the first type panel area PA1 and the second type panel area PA2 is used to control the conduction of the second type switching transistor 720.

[0146] Illustratively, in the second stage, the signal provided by the second type control signal terminal 521 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the second type control transistor 620 jumps to a valid level to turn on the second type control transistor 620, and the signal provided by the second type switching signal terminal 522 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the second type switching transistor 720 jumps to a valid level to turn on the second type switching transistor 720.

[0147] Optionally, in the second stage, the second type lighting signal terminal 523 in the first type panel area PA1 and the second type panel area PA2 is used to provide a data signal to the second type sub-pixel 402 via the second type switching transistor 720 and the second type control transistor 620 to drive the second type sub-pixel 402 to emit light.

[0148] Optionally, in the second stage, the first type of control signal terminal 511 in the first type panel area PA1 and the second type panel area PA2 can be used to control the cutoff of the first type control transistor 610, the third type of control signal terminal 531 in the first type panel area PA1 and the second type panel area PA2 can be used to control the cutoff of the third type control transistor 630, the first type of switching signal terminal 512 in the first type panel area PA1 and the second type panel area PA2 can be used to control the cutoff of the first type switching transistor 710, and the third type of switching signal terminal 532 in the first type panel area PA1 and the second type panel area PA2 can be used to control the cutoff of the third type switching transistor 730.

[0149] Illustratively, in the second stage, the signal provided by the first type control signal terminal 511 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the first type control transistor 610 jumps to an invalid level to turn off the first type control transistor 610, the signal provided by the third type control signal terminal 531 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the third type control transistor 630 jumps to an invalid level to turn off the third type control transistor 630, and the signal provided by the first type switch signal terminal 512 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the first type switch transistor 710 jumps to an invalid level to turn off the first type switch transistor 710, and the signal provided by the third type switch signal terminal 532 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the third type switch transistor 730 jumps to an invalid level to turn off the third type switch transistor 730.

[0150] Optionally, in the second state, the first type of lighting signal terminal 513 in the first type of panel area PA1 and the second type of panel area PA2 can stop providing data signals to the first type of sub-pixel 401, and the third type of lighting signal terminal 533 in the first type of panel area PA1 and the second type of panel area PA2 can stop providing data signals to the third type of sub-pixel 403.

[0151] In these optional embodiments, in the second stage, the second type of sub-pixels 402 in the first type of panel area PA1 and the second type of panel area PA2 are both illuminated, and the first type of sub-pixels 401 and the third type of sub-pixels 403 in the first type of panel area PA1 and the second type of panel area PA2 are not illuminated, so that the first type of panel area PA1 and the second type of panel area PA2 of the display panel motherboard 10 can both present a green screen, which can facilitate the test device TD to simultaneously detect the display effects of the second type of sub-pixels 402 in the first type of panel area PA1 and the second type of panel area PA2 in the display panel motherboard 10 under the same test drive timing.

[0152] In some optional embodiments, in the third stage, the third type of control signal terminal 531 in the first type panel area PA1 and the second type panel area PA2 is used to control the conduction of the third type control transistor 630, and the third type of switching signal terminal 532 in the first type panel area PA1 and the second type panel area PA2 is used to control the conduction of the third type switching transistor 730.

[0153] Illustratively, in the third stage, the signal provided by the third type control signal terminal 531 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the third type control transistor 630 jumps to a valid level to turn on the third type control transistor 630, and the signal provided by the third type switching signal terminal 532 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the third type switching transistor 730 jumps to a valid level to turn on the third type switching transistor 730.

[0154] Optionally, in the third stage, the third type lighting signal terminal 533 in the first type panel area PA1 and the second type panel area PA2 can be used to provide a data signal to the third type sub-pixel 403 via the third type switching transistor 730 and the third type control transistor 630 to drive the third type sub-pixel 403 to emit light.

[0155] Optionally, in the third stage, the first type of control signal terminal 511 in the first type panel area PA1 and the second type panel area PA2 is used to control the cutoff of the first type control transistor 610, the second type of control signal terminal 521 in the first type panel area PA1 and the second type panel area PA2 is used to control the cutoff of the second type control transistor 620, the first type of switching signal terminal 512 in the first type panel area PA1 and the second type panel area PA2 is used to control the cutoff of the first type switching transistor 710, and the second type of switching signal terminal 522 in the first type panel area PA1 and the second type panel area PA2 is used to control the cutoff of the second type switching transistor 720.

[0156] Exemplarily, in the third stage, the signal provided by the first type control signal terminal 511 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the first type control transistor 610 jumps to an invalid level to turn off the first type control transistor 610, the signal provided by the second type control signal terminal 521 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the second type control transistor 620 jumps to an invalid level to turn off the second type control transistor 620, and the signal provided by the first type switch signal terminal 512 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the first type switch transistor 710 jumps to an invalid level to turn off the first type switch transistor 710, and the signal provided by the second type switch signal terminal 522 in the first type panel area PA1 and the second type panel area PA2 to the control terminal of the second type switch transistor 720 jumps to an invalid level to turn off the second type switch transistor 720.

[0157] Optionally, in the third stage, the first-type lighting signal terminal 513 in the first-type panel area PA1 and the second-type panel area PA2 can stop providing data signals to the first-type sub-pixel 401, and the second-type lighting signal terminal 523 in the first-type panel area PA1 and the second-type panel area PA2 can stop providing data signals to the second-type sub-pixel 402.

[0158] In these optional embodiments, in the third stage, the third type of sub-pixels 403 in the first type of panel area PA1 and the second type of panel area PA2 are both illuminated, and the first type of sub-pixels 401 and the second type of sub-pixels 402 in the first type of panel area PA1 and the second type of panel area PA2 are not illuminated, so that the first type of panel area PA1 and the second type of panel area PA2 of the display panel motherboard 10 can both present a blue screen, which can facilitate the test device TD to simultaneously detect the display effect of the third type of sub-pixels 403 in the first type of panel area PA1 and the second type of panel area PA2 in the display panel motherboard 10 under the same test drive timing.

[0159] In some optional embodiments, the first direction X may be the row direction in which the sub-pixels 400 are arranged, and the second direction Y may be the column direction in which the sub-pixels 400 are arranged. In a test state, a scanning signal may be provided to each row of sub-pixels 400 row by row so as to light up each row of sub-pixels 400 row by row.

[0160] Optionally, the test state further includes a scanning phase. The scanning phases of each row of sub-pixels 400 may not overlap, and the present application does not specifically limit the order of the scanning phases of each row of sub-pixels 400. For example, the scanning phase of the i-th row of sub-pixels 400 may precede the scanning phase of the i+1-th row of sub-pixels 400, where i is a positive integer and i≥1.

[0161] Optionally, the scanning phase of any row of sub-pixels 400 may at least partially overlap with at least one first phase, at least one second phase, and at least one third phase, so that when a scanning signal is provided to any row of sub-pixels 400, any sub-pixel 400 in the row of sub-pixels 400 may be illuminated (for example, when a row of sub-pixels 400 is in the scanning phase and is in the first phase of the test state, the first type of sub-pixels 401 in the row of sub-pixels 400 may be illuminated).

[0162] Figure 8 This is a flow chart of a method for testing a display panel motherboard provided in an embodiment of the present application.

[0163] like Figure 8As shown, based on the display panel motherboard 10 in the test state described in the aforementioned embodiment, the embodiment of the present application further provides a display panel motherboard testing method. The display panel motherboard testing method can be used to test the display panel motherboard 10 in any of the aforementioned embodiments. The display panel motherboard testing method includes:

[0164] Step S10: Provide an effective level to the control terminal of the first type control transistor 610 through the first type control signal terminal 511 in the first type panel area PA1 and the second type panel area PA2 to turn on the first type control transistor 610, and provide an effective level to the control terminal of the first type switching transistor 710 through the first type switch signal terminal 512 in the first type panel area PA1 and the second type panel area PA2 to turn on the first type switching transistor 710.

[0165] Optionally, when the first type of control transistor 610 is controlled to be turned on by the first type of control signal terminal 511 in the first type of panel area PA1 and the second type of panel area PA2, and the first type of switching transistor 710 is controlled to be turned on by the first type of switching signal terminal 512 in the first type of panel area PA1 and the second type of panel area PA2, the display panel motherboard 10 can be in the first stage of any of the aforementioned embodiments.

[0166] Optionally, step S10 may further include providing a data signal to the first-type lighting signal terminal 513 in the first-type panel area PA1 and the second-type panel area PA2. By providing the data signal to the first-type lighting signal terminal 513 in the first-type panel area PA1 and the second-type panel area PA2, the data signal can drive the first-type sub-pixel 401 to emit light via the first-type switching transistor 710 and the first-type control transistor 610.

[0167] Step S20: Provide an effective level to the control end of the second type control transistor 620 through the second type control signal end 521 in the first type panel area PA1 and the second type panel area PA2 to turn on the second type control transistor 620, and provide an effective level to the control end of the second type switching transistor 720 through the second type switching signal end 522 in the first type panel area PA1 and the second type panel area PA2 to turn on the second type switching transistor 720.

[0168] Optionally, when the second type of control transistor 620 is controlled to be turned on by the second type of control signal terminal 521 in the first type of panel area PA1 and the second type of panel area PA2, and the second type of switching transistor 720 is controlled to be turned on by the second type of switching signal terminal 522 in the first type of panel area PA1 and the second type of panel area PA2, the display panel motherboard 10 can be in the second stage of any of the aforementioned embodiments.

[0169] Optionally, step S20 may further include providing a data signal to the second-type lighting signal terminals 523 in the first-type panel area PA1 and the second-type panel area PA2. The data signal is provided through the second-type lighting signal terminals 523 in the first-type panel area PA1 and the second-type panel area PA2, so that the data signal can drive the second-type sub-pixel 402 to emit light via the second-type switching transistor 720 and the second-type control transistor 620.

[0170] Step S30: Provide an effective level to the control end of the third type control transistor 630 through the third type control signal end 531 in the first type panel area PA1 and the second type panel area PA2 to turn on the third type control transistor 630, and provide an effective level to the control end of the third type switch transistor 730 through the third type switch signal end 532 in the first type panel area PA1 and the second type panel area PA2 to turn on the third type switch transistor 730.

[0171] Optionally, when the third type of control transistor 630 is controlled to be turned on by the third type of control signal terminal 531 in the first type of panel area PA1 and the second type of panel area PA2, and the third type of switching transistor 730 is controlled to be turned on by the first type of panel area PA1 and the second type of panel area PA2, the display panel motherboard 10 can be in the third stage of any of the aforementioned embodiments.

[0172] Optionally, step S30 may further include providing a data signal to the third-type lighting signal terminal 533 in the first-type panel area PA1 and the second-type panel area PA2. By providing the data signal to the third-type lighting signal terminal 533 in the first-type panel area PA1 and the second-type panel area PA2, the data signal can drive the third-type sub-pixel 403 to emit light via the third-type switching transistor 730 and the third-type control transistor 630.

[0173] In some optional embodiments, the arrangement between the first type of control signal terminal 511, the second type of control signal terminal 521 and the third type of control signal terminal 531 in the first type of panel area PA1 is the same as the arrangement between the first type of control signal terminal 511, the second type of control signal terminal 521 and the third type of control signal terminal 531 in the second type of panel area PA2.

[0174] The arrangement between the first type of switch signal terminal 512, the second type of switch signal terminal 522 and the third type of switch signal terminal 532 in the first type of panel area PA1 is the same as the arrangement between the first type of switch signal terminal 512, the second type of switch signal terminal 522 and the third type of switch signal terminal 532 in the second type of panel area PA2.

[0175] The arrangement between the first type lighting signal terminal 513, the second type lighting signal terminal 523 and the third type lighting signal terminal 533 in the first type panel area PA1 is the same as the arrangement between the first type lighting signal terminal 513, the second type lighting signal terminal 523 and the third type lighting signal terminal 533 in the second type panel area PA2.

[0176] In these optional embodiments, by setting the arrangement of each test signal terminal 500 in the first type panel area PA1 and the second type panel area PA2 to be the same, during the testing process of the display panel motherboard 10, the same set of testing equipment TD can be used to test the first type panel area PA1 and the second type panel area PA2 in the display panel motherboard 10, thereby better improving the preparation efficiency of the display panel motherboard 10 and better reducing the cost of the testing equipment TD.

[0177] In some optional embodiments, in the first type panel area PA1 and the second type panel area PA2 , the first type control signal end 511 , the second type control signal end 521 and the third type control signal end 531 are spaced apart in the first direction X.

[0178] Optionally, the arrangement between the first type of control signal terminal 511, the second type of control signal terminal 521 and the third type of control signal terminal 531 in the first type of panel area PA1 is the same as the arrangement between the first type of control signal terminal 511, the second type of control signal terminal 521 and the third type of control signal terminal 531 in the second type of panel area PA2, which may mean that the arrangement between the first type of control signal terminal 511, the second type of control signal terminal 521 and the third type of control signal terminal 531 in the first type of panel area PA1 in the first direction X is the same as the arrangement between the first type of control signal terminal 511, the second type of control signal terminal 521 and the third type of control signal terminal 531 in the second type of panel area PA2 in the first direction X.

[0179] Illustratively, in the first type panel area PA1 and the second type panel area PA2, the first type control signal terminal 511, the second type control signal terminal 521, and the third type control signal terminal 531 are all arranged sequentially along the first direction X. For example, as shown in the aforementioned figures, in the first type panel area PA1 and the second type panel area PA2, the first type control signal terminal 511, the second type control signal terminal 521, and the third type control signal terminal 531 are all arranged sequentially from left to right.

[0180] In some optional embodiments, in the first type panel area PA1 and the second type panel area PA2, the first type switch signal terminal 512, the second type switch signal terminal 522 and the third type switch signal terminal 532 are spaced apart in the first direction X.

[0181] Optionally, the arrangement between the first type of switch signal terminal 512, the second type of switch signal terminal 522 and the third type of switch signal terminal 532 in the first type of panel area PA1 is the same as the arrangement between the first type of switch signal terminal 512, the second type of switch signal terminal 522 and the third type of switch signal terminal 532 in the second type of panel area PA2, which may mean that the arrangement between the first type of switch signal terminal 512, the second type of switch signal terminal 522 and the third type of switch signal terminal 532 in the first type of panel area PA1 in the first direction X is the same as the arrangement between the first type of switch signal terminal 512, the second type of switch signal terminal 522 and the third type of switch signal terminal 532 in the second type of panel area PA2 in the first direction X.

[0182] Exemplarily, in the first type panel area PA1 and the second type panel area PA2, the first type switch signal terminal 512, the second type switch signal terminal 522, and the third type switch signal terminal 532 are all arranged sequentially along the first direction X. For example, as shown in the aforementioned figures, in the first type panel area PA1 and the second type panel area PA2, the first type switch signal terminal 512, the second type switch signal terminal 522, and the third type switch signal terminal 532 are all arranged sequentially from left to right.

[0183] In some optional embodiments, in the first type panel area PA1 and the second type panel area PA2, the first type lighting signal end 513, the second type lighting signal end 523 and the third type lighting signal end 533 are arranged at intervals in the first direction X.

[0184] Optionally, the arrangement between the first type of lighting signal terminal 513, the second type of lighting signal terminal 523 and the third type of lighting signal terminal 533 in the first type of panel area PA1 is the same as the arrangement between the first type of lighting signal terminal 513, the second type of lighting signal terminal 523 and the third type of lighting signal terminal 533 in the second type of panel area PA2, which may mean that the arrangement between the first type of lighting signal terminal 513, the second type of lighting signal terminal 523 and the third type of lighting signal terminal 533 in the first type of panel area PA1 in the first direction X is the same as the arrangement between the first type of lighting signal terminal 513, the second type of lighting signal terminal 523 and the third type of lighting signal terminal 533 in the second type of panel area PA2 in the first direction X.

[0185] For example, in the first type panel area PA1 and the second type panel area PA2, the first type lighting signal terminal 513, the second type lighting signal terminal 523, and the third type lighting signal terminal 533 are all arranged sequentially along the first direction X. For example, as shown in the aforementioned figures, in the first type panel area PA1 and the second type panel area PA2, the first type lighting signal terminal 513, the second type lighting signal terminal 523, and the third type lighting signal terminal 533 are all arranged sequentially from left to right.

[0186] In some optional embodiments, a single first-class control signal terminal 511, a single second-class control signal terminal 521 and a single third-class control signal terminal 531 constitute a control terminal group 501, a single first-class switch signal terminal 512, a single second-class switch signal terminal 522 and a single third-class switch signal terminal 532 constitute a switch terminal group 502, a single first-class lighting signal terminal 513, a single second-class lighting signal terminal 523 and a single third-class lighting signal terminal 533 constitute a lighting terminal group 503, and the arrangement between the control terminal group 501, the switch terminal group 502 and the lighting terminal group 503 in the first-class panel area PA1 is the same as the arrangement between the control terminal group 501, the switch terminal group 502 and the lighting terminal group 503 in the second-class panel area PA2.

[0187] Optionally, the test group 500 a described in the aforementioned embodiment may include a control end group 501 , a switch end group 502 and a lighting end group 503 .

[0188] In these optional embodiments, by setting the arrangement between the control end group 501, the switch end group 502 and the lighting end group 503 in the first type panel area PA1 to be the same as the arrangement between the control end group 501, the switch end group 502 and the lighting end group 503 in the second type panel area PA2, during the testing process of the display panel motherboard 10, the same set of testing equipment TD can be used to test the first type panel area PA1 and the second type panel area PA2 in the display panel motherboard 10, thereby better improving the preparation efficiency of the display panel motherboard 10 and better reducing the cost of the testing equipment TD.

[0189] In some optional embodiments, in the first type panel area PA1 and the second type panel area PA2 , the control end group 501 , the switch end group 502 , and the lighting end group 503 are arranged at intervals in the first direction X.

[0190] Optionally, the arrangement between the control end group 501, the switch end group 502 and the lighting end group 503 in the first type panel area PA1 is the same as the arrangement between the control end group 501, the switch end group 502 and the lighting end group 503 in the second type panel area PA2, which may mean that the arrangement between the control end group 501, the switch end group 502 and the lighting end group 503 in the first type panel area PA1 in the first direction X is the same as the arrangement between the control end group 501, the switch end group 502 and the lighting end group 503 in the second type panel area PA2 in the first direction X.

[0191] For example, in the first type panel area PA1 and the second type panel area PA2, the lighting end group 503, the switch end group 502, and the control end group 501 are all arranged sequentially along the first direction X. For example, as shown in the aforementioned figures, in the first type panel area PA1 and the second type panel area PA2, the lighting end group 503, the switch end group 502, and the control end group 501 are all arranged sequentially from left to right.

[0192] In some optional embodiments, the spacing between adjacent first-type test signal terminals 510 and second-type test signal terminals 520 in the first-type panel area PA1 is equal to the spacing between adjacent first-type test signal terminals 510 and second-type test signal terminals 520 in the second-type panel area PA2, and / or the spacing between adjacent first-type test signal terminals 510 and third-type test signal terminals 530 in the first-type panel area PA1 is equal to the spacing between adjacent first-type test signal terminals 510 and third-type test signal terminals 530 in the second-type panel area PA2, and / or the spacing between adjacent second-type test signal terminals 520 and third-type test signal terminals 530 in the first-type panel area PA1 is equal to the spacing between adjacent second-type test signal terminals 520 and third-type test signal terminals 530 in the second-type panel area PA2.

[0193] Optionally, the spacing between adjacent first-type control signal terminals 511 and second-type control signal terminals 521 in the first-type panel area PA1 is equal to the spacing between adjacent first-type control signal terminals 511 and second-type control signal terminals 521 in the second-type panel area PA2.

[0194] Optionally, the distance between adjacent second-type control signal terminals 521 and third-type control signal terminals 531 in the first-type panel area PA1 is equal to the distance between adjacent second-type control signal terminals 521 and third-type control signal terminals 531 in the second-type panel area PA2.

[0195] Optionally, the spacing between adjacent first-type switch signal terminals 512 and second-type switch signal terminals 522 in the first-type panel area PA1 is equal to the spacing between adjacent first-type switch signal terminals 512 and second-type switch signal terminals 522 in the second-type panel area PA2.

[0196] Optionally, the distance between adjacent second-type switch signal terminals 522 and third-type switch signal terminals 532 in the first-type panel area PA1 is equal to the distance between adjacent second-type switch signal terminals 522 and third-type switch signal terminals 532 in the second-type panel area PA2.

[0197] Optionally, the spacing between adjacent first-type lighting signal terminals 513 and second-type lighting signal terminals 523 in the first-type panel area PA1 is equal to the spacing between adjacent first-type lighting signal terminals 513 and second-type lighting signal terminals 523 in the second-type panel area PA2.

[0198] Optionally, the distance between adjacent second-type lighting signal terminals 523 and third-type lighting signal terminals 533 in the first-type panel area PA1 is equal to the distance between adjacent second-type lighting signal terminals 523 and third-type lighting signal terminals 533 in the second-type panel area PA2.

[0199] In these optional embodiments, by setting the spacing between the two corresponding adjacent test signal terminals 500 in the first type panel area PA1 and the second type panel area PA2 to be equal, during the testing process of the display panel motherboard 10, the same set of testing equipment TD can be used to test the first type panel area PA1 and the second type panel area PA2 in the display panel motherboard 10, thereby better improving the preparation efficiency of the display panel motherboard 10 and better reducing the cost of the testing equipment TD.

[0200] In some optional embodiments, the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 are spaced apart in the first direction X, and / or the first type of switching transistor 710, the second type of switching transistor 720 and the third type of switching transistor 730 are spaced apart in the first direction X.

[0201] In this optional embodiment, by setting the test control transistors 600 to be spaced apart in the first direction X, and setting the test switch transistors 700 to be spaced apart in the first direction X, it is possible to facilitate connection between each test control transistor 600 and multiple columns of sub-pixels 400 spaced apart in the first direction X.

[0202] In some optional embodiments, the arrangement of the first type of switching transistor 710, the second type of switching transistor 720 and the third type of switching transistor 730 in the first type of panel area PA1 is the same as the arrangement of the first type of switching transistor 710, the second type of switching transistor 720 and the third type of switching transistor 730 in the second type of panel area PA2.

[0203] Optionally, the arrangement of the first type switching transistor 710, the second type switching transistor 720 and the third type switching transistor 730 in the first type panel area PA1 is the same as the arrangement of the first type switching transistor 710, the second type switching transistor 720 and the third type switching transistor 730 in the second type panel area PA2, which may mean that the arrangement of the first type switching transistor 710, the second type switching transistor 720 and the third type switching transistor 730 in the first type panel area PA1 in the first direction X is the same as the arrangement of the first type switching transistor 710, the second type switching transistor 720 and the third type switching transistor 730 in the second type panel area PA2 in the first direction X.

[0204] Exemplarily, in the first type panel area PA1 and the second type panel area PA2, the first type switching transistor 710, the second type switching transistor 720, and the third type switching transistor 730 are all arranged sequentially along the first direction X. For example, as shown in the aforementioned figures, in the first type panel area PA1 and the second type panel area PA2, the first type switching transistor 710, the second type switching transistor 720, and the third type switching transistor 730 are all arranged sequentially from left to right.

[0205] In this optional embodiment, by setting the arrangement of the first type switching transistor 710, the second type switching transistor 720 and the third type switching transistor 730 in the first type panel area PA1 to be the same as the arrangement of the first type switching transistor 710, the second type switching transistor 720 and the third type switching transistor 730 in the second type panel area PA2, it is possible to facilitate the connection of each test signal terminal 500 and each test switching transistor 700 in the first type panel area PA1 and the second type panel area PA2 when the arrangement of the test signal terminal 500 in each panel area PA is the same.

[0206] like Figure 5 and Figure 6 As shown, in some optional embodiments, the arrangement of the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the first type of panel area PA1 is different from the arrangement of the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the second type of panel area PA2.

[0207] Optionally, the arrangement of the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the first type of panel area PA1 is different from the arrangement of the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the second type of panel area PA2. This may mean that the arrangement of the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the first type of panel area PA1 in the first direction X is different from the arrangement of the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the second type of panel area PA2 in the first direction X.

[0208] For example, when in the pixel group 400a within the first type of panel area PA1, the first type of sub-pixel 401, the second type of sub-pixel 402 and the third type of sub-pixel 403 are arranged in sequence along the first direction X, and in the pixel group 400a within the second type of panel area PA2, the second type of sub-pixel 402, the first type of sub-pixel 401 and the third type of sub-pixel 403 are arranged in sequence along the first direction X, in the first type of panel area PA1, the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 are all arranged in sequence along the first direction X, and in the second type of panel area PA2, the second type of control transistor 620, the first type of control transistor 610 and the third type of control transistor 630 are all arranged in sequence along the first direction X.

[0209] In these optional embodiments, since the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402 and the third type of sub-pixels 403 in the first type of panel area PA1 is different from the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402 and the third type of sub-pixels 403 in the second type of panel area PA2, the arrangement of the first type of control transistors 610, the second type of control transistors 620 and the third type of control transistors 630 in the first type of panel area PA1 is different from the arrangement of the first type of control transistors 610, the second type of control transistors 620 and the third type of control transistors 630 in the second type of panel area PA2. The arrangements of the transistor 610, the second-type control transistor 620, and the third-type control transistor 630 are different, so that the arrangements of the first-type control transistor 610, the second-type control transistor 620, and the third-type control transistor 630 in the first-type panel area PA1 can be set according to the arrangements of the first-type sub-pixels 401, the second-type sub-pixels 402, and the third-type sub-pixels 403 in the first-type panel area PA1, thereby facilitating the connection between each test control transistor 600 in the first-type panel area PA1 and the corresponding sub-pixel 400. Furthermore, the arrangements of the first-type control transistor 610, the second-type control transistor 620, and the third-type control transistor 630 in the second-type panel area PA2 can be set according to the arrangements of the first-type sub-pixels 401, the second-type sub-pixels 402, and the third-type sub-pixels 403 in the second-type panel area PA2, thereby facilitating the connection between each test control transistor 600 in the second-type panel area PA2 and the corresponding sub-pixel 400.

[0210] Figure 9 1 is a partial structural diagram of a display panel motherboard 10 provided in yet another embodiment of the present application.

[0211] like Figure 5 and Figure 9 As shown, in some optional embodiments, the arrangement between the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the first type of panel area PA1 is the same as the arrangement between the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the second type of panel area PA2.

[0212] Optionally, the arrangement between the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the first type of panel area PA1 is the same as the arrangement between the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the second type of panel area PA2, which may mean that the arrangement between the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the first type of panel area PA1 in the first direction X is the same as the arrangement between the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the second type of panel area PA2 in the first direction X.

[0213] For example, when in the pixel group 400a within the first type of panel area PA1, the first type of sub-pixel 401, the second type of sub-pixel 402 and the third type of sub-pixel 403 are arranged in sequence along the first direction X, and in the pixel group 400a within the second type of panel area PA2, the second type of sub-pixel 402, the first type of sub-pixel 401 and the third type of sub-pixel 403 are arranged in sequence along the first direction X, in the first type of panel area PA1 and the second type of panel area PA2, the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 are all arranged in sequence along the first direction X.

[0214] In these optional embodiments, by setting the arrangement between the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the first type of panel area PA1 to be the same as the arrangement between the first type of control transistor 610, the second type of control transistor 620 and the third type of control transistor 630 in the second type of panel area PA2, the design of the display panel motherboard 10 can be facilitated.

[0215] In some optional embodiments, the display panel further includes a control signal line SL1, a switching signal line SL2 and a lighting signal line SL3. In a single panel area PA, the control end of the test control transistor 600 is connected to the control signal end through the control signal line SL1, the control end of the test switch transistor 700 is connected to the switch signal end through the switching signal line SL2, and the second end of the test switch transistor 700 is connected to the lighting signal end through the lighting signal line SL3, wherein at least part of the control signal line SL1 extends along the first direction X, and / or at least part of the switching signal line SL2 extends along the first direction X, and / or at least part of the lighting signal line SL3 extends along the first direction X.

[0216] Optionally, the control signal line SL1 may include a first type of control signal line SL1a connected to the control end of the first type of control transistor 610, a second type of control signal line SL1b connected to the control end of the second type of control transistor 620, and a third type of control signal line SL1c connected to the control end of the third type of control transistor 630.

[0217] Optionally, the switching signal line SL2 may include a first switching signal line SL2a connected to the control end of the first switching transistor 710, a second switching signal line SL2b connected to the control end of the second switching transistor 720, and a third switching signal line SL2c connected to the control end of the third switching transistor 730.

[0218] Optionally, the lighting signal line SL3 may include a first lighting signal line SL3a connected to the second end of the first switching transistor 710, a second lighting signal line SL3b connected to the second end of the second switching transistor 720, and a third lighting signal line SL3c connected to the second end of the third switching transistor 730.

[0219] In these optional embodiments, by setting the control signal line SL1, the switch signal line SL2 and the lighting signal line SL3 to extend along the first direction X, it is possible to facilitate the connection of each signal line with each test control transistor 600 and each test switch transistor 700 arranged in the first direction X, thereby improving the routing efficiency in the display panel motherboard 10.

[0220] The embodiment of the second aspect of the present application provides a display panel, which can be manufactured from the display panel motherboard 10 of the above-described embodiment. Since the display panel provided by the embodiment of the second aspect of the present application can be manufactured from the display panel motherboard 10 of the above-described embodiment, the display panel provided by the embodiment of the second aspect of the present application has the same or similar beneficial effects as the display panel motherboard 10 of the corresponding embodiment of the first aspect, and no further details are given here.

[0221] Optionally, the display panel motherboard 10 of any of the aforementioned embodiments may be subjected to a processing technique such as cutting to separate the individual panel areas PA, so that a single panel area can be used to form a single display panel provided by an embodiment of the second aspect of the present application. A complete single panel area PA can be used to form a single complete display panel, or after separating the panel area PA, some structures within the panel area PA can be removed (for example, the test signal terminal 500 within the panel area PA in any of the aforementioned embodiments can be removed) to allow the remaining structures within the single panel area to form a single complete display panel.

[0222] The third aspect of the present application provides a display device, comprising a display panel according to any of the aforementioned embodiments. Since the display device provided by the third aspect of the present application includes the display panel according to any of the aforementioned second aspects, the display device provided by the third aspect of the present application has the beneficial effects of the display panel according to any of the aforementioned second aspects, and no further details are given here.

[0223] The display device in the embodiments of the present application includes but is not limited to wearable devices with display functions (for example, watches, headphones, clothing, etc. with display functions), mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, consoles, and other devices with display functions.

[0224] While the embodiments described above are not exhaustive, they do not limit the invention to specific embodiments. Clearly, numerous modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel motherboard, characterized in that: The display panel motherboard has at least two panel areas, wherein the panel areas include a first type of panel area and a second type of panel area. The display panel motherboard includes: a plurality of sub-pixels, each of the panel regions being provided with the plurality of sub-pixels, the plurality of sub-pixels comprising a first type of sub-pixels, a second type of sub-pixels, and a third type of sub-pixels having different luminous colors, and the sub-pixels in at least two of the panel regions being arranged differently; Multiple test signal terminals are provided in each of the panel regions, the test signal terminals in the panel region are electrically connected to the corresponding sub-pixels, and the test signal terminals are used to participate in driving the sub-pixels to emit light, and the multiple test signal terminals include a first type of test signal terminal corresponding to the first type of sub-pixels, a second type of test signal terminal corresponding to the second type of sub-pixels, and a third type of test signal terminal corresponding to the third type of sub-pixels. Among them, the arrangement of the test signal ends in each of the panel areas is the same, and the arrangement between the first type of test signal ends, the second type of test signal ends and the third type of test signal ends in the first type of panel area is the same as the arrangement between the first type of test signal ends, the second type of test signal ends and the third type of test signal ends in the second type of panel area.

2. The display panel motherboard according to claim 1, wherein: The arrangement of the first type of sub-pixels, the second type of sub-pixels, and the third type of sub-pixels in the first type of panel area is different from the arrangement of the first type of sub-pixels, the second type of sub-pixels, and the third type of sub-pixels in the second type of panel area; And / or, the arrangement density of the sub-pixels in the first type of panel area is different from the arrangement density of the sub-pixels in the second type of panel area.

3. The display panel motherboard according to claim 2, wherein: A single sub-pixel of the first type, a single sub-pixel of the second type, and a single sub-pixel of the third type constitute a single pixel group, and a plurality of the pixel groups are arranged at intervals in the first direction. In the pixel groups within the first type of panel area and the second type of panel area, the first type of sub-pixels, the second type of sub-pixels, and the third type of sub-pixels are spaced apart in the first direction; in the pixel groups within the first type of panel area, the first type of sub-pixels, the second type of sub-pixels, and the third type of sub-pixels are arranged in sequence along the first direction. In the pixel group within the second type of panel area, the second type of sub-pixels, the first type of sub-pixels, and the third type of sub-pixels are arranged in sequence along the first direction.

4. The display panel motherboard according to claim 1, wherein: A single first-type test signal terminal, a single second-type test signal terminal, and a single third-type test signal terminal constitute a single test group. In the test group within the first-type panel area and the second-type panel area, the first-type test signal terminal, the second-type test signal terminal, and the third-type test signal terminal are spaced apart in the first direction. In the test groups within the first type of panel area and the second type of panel area, the first type of test signal end, the second type of test signal end, and the third type of test signal end are sequentially arranged along the first direction.

5. The display panel motherboard according to claim 1, wherein: The spacing between the adjacent first-type test signal terminals and the second-type test signal terminals in the first-type panel area is equal to the spacing between the adjacent first-type test signal terminals and the second-type test signal terminals in the second-type panel area. and / or, the spacing between adjacent first-type test signal terminals and third-type test signal terminals in the first-type panel area is equal to the spacing between adjacent first-type test signal terminals and third-type test signal terminals in the second-type panel area, And / or, the spacing between adjacent second-type test signal terminals and third-type test signal terminals in the first-type panel area is equal to the spacing between adjacent second-type test signal terminals and third-type test signal terminals in the second-type panel area.

6. The display panel motherboard according to claim 1, wherein: The first type of test signal terminal, the second type of test signal terminal and the third type of test signal terminal all include a control signal terminal, a switch signal terminal and a lighting signal terminal. The display panel motherboard further includes a test control transistor, a test switch transistor and a connecting line. The test control transistor and the test switch transistor are provided in each panel area. In a single panel area, the control end of the test control transistor is connected to the control signal end, the sub-pixel is connected to the first end of the test control transistor, the second end of the test control transistor is connected to the first end of the test switch transistor, the control end of the test switch transistor is connected to the switch signal end, and the second end of the test switch transistor is connected to the lighting signal end.

7. The display panel motherboard according to claim 6, wherein: The test signal terminal, the test control transistor, the test switch transistor and the connecting line are all arranged on the same side of the sub-pixel in the second direction, and the multiple sub-pixels with the same luminous color are arranged at intervals in the second direction, and the sub-pixels located in the same column in the second direction are connected to the first end of the same test control transistor.

8. The display panel motherboard according to claim 6, wherein: The first type of test signal terminal includes a first type of control signal terminal, a first type of switch signal terminal and a first type of lighting signal terminal; the second type of test signal terminal includes a second type of control signal terminal, a second type of switch signal terminal and a second type of lighting signal terminal; the third type of test signal terminal includes a third type of control signal terminal, a third type of switch signal terminal and a third type of lighting signal terminal. The test control transistors include a first type of control transistor, a second type of control transistor, and a third type of control transistor; the test switch transistors include a first type of switch transistor, a second type of switch transistor, and a third type of switch transistor; A single first-type sub-pixel, a single second-type sub-pixel, and a single third-type sub-pixel constitute a single pixel group; a single first-type control transistor, a single first-type switching transistor, a single second-type switching transistor, and a single third-type switching transistor constitute a single switch group; In a single panel area, the control terminal of the first type of control transistor is connected to the first type of control signal terminal, the control terminal of the second type of control transistor is connected to the second type of control signal terminal, the control terminal of the third type of control transistor is connected to the third type of control signal terminal, the first type of sub-pixel is connected to the first terminal of the first type of control transistor, the second type of sub-pixel is connected to the first terminal of the second type of control transistor, and the third type of sub-pixel is connected to the first terminal of the third type of control transistor. The second terminal of each of the test control transistors connected to the sub-pixels in the same pixel group is connected to the first terminal of each of the test switch transistors in the switch group through the same connection line. The control end of the first type of switching transistor is connected to the first type of switching signal end, the control end of the second type of switching transistor is connected to the second type of switching signal end, the control end of the third type of switching transistor is connected to the third type of switching signal end, the second end of the first type of switching transistor is connected to the first type of lighting signal end, the second end of the second type of switching transistor is connected to the second type of lighting signal end, and the second end of the third type of switching transistor is connected to the third type of lighting signal end.

9. The display panel motherboard according to claim 8, characterized in that: The arrangement of the first type of control signal terminals, the second type of control signal terminals and the third type of control signal terminals in the first type of panel area is the same as the arrangement of the first type of control signal terminals, the second type of control signal terminals and the third type of control signal terminals in the second type of panel area. The arrangement of the first type of switch signal terminal, the second type of switch signal terminal and the third type of switch signal terminal in the first type of panel area is the same as the arrangement of the first type of switch signal terminal, the second type of switch signal terminal and the third type of switch signal terminal in the second type of panel area. The arrangement of the first type lighting signal terminal, the second type lighting signal terminal and the third type lighting signal terminal in the first type panel area is the same as the arrangement of the first type lighting signal terminal, the second type lighting signal terminal and the third type lighting signal terminal in the second type panel area.

10. The display panel motherboard according to claim 9, wherein: In the first type panel area and the second type panel area, the first type control signal end, the second type control signal end and the third type control signal end are spaced apart in the first direction. and / or, in the first type panel area and the second type panel area, the first type switch signal terminal, the second type switch signal terminal and the third type switch signal terminal are spaced apart in the first direction, And / or, in the first type panel area and the second type panel area, the first type lighting signal end, the second type lighting signal end and the third type lighting signal end are spaced apart in the first direction.

11. The display panel motherboard according to claim 8, wherein: A single first-type control signal terminal, a single second-type control signal terminal, and a single third-type control signal terminal constitute a control terminal group. A single first-type switch signal terminal, a single second-type switch signal terminal, and a single third-type switch signal terminal constitute a switch terminal group. A single first-type lighting signal terminal, a single second-type lighting signal terminal, and a single third-type lighting signal terminal constitute a lighting terminal group. The arrangement of the control end group, the switch end group and the lighting end group in the first type panel area is the same as the arrangement of the control end group, the switch end group and the lighting end group in the second type panel area.

12. The display panel motherboard according to claim 11, wherein: In the first type panel area and the second type panel area, the control end group, the switch end group, and the lighting end group are spaced apart in a first direction.

13. The display panel motherboard according to claim 8, wherein: The display panel motherboard has a test state, and the test state has a first stage, a second stage and a third stage. In the first stage, the first type of control signal terminals in the first type of panel area and the second type of panel area are both used to control the first type of control transistor to be turned on, and the first type of switch signal terminals in the first type of panel area and the second type of panel area are both used to control the first type of switch transistor to be turned on. In the second stage, the second-type control signal terminals in the first-type panel area and the second-type panel area are both used to control the conduction of the second-type control transistor, and the second-type switch signal terminals in the first-type panel area and the second-type panel area are both used to control the conduction of the second-type switch transistor. In the third stage, the third type of control signal ends in the first type of panel area and the second type of panel area are both used to control the conduction of the third type of control transistor, and the third type of switching signal ends in the first type of panel area and the second type of panel area are both used to control the conduction of the third type of switching transistor.

14. The display panel motherboard according to claim 8, wherein: The first type of control transistor, the second type of control transistor and the third type of control transistor are spaced apart in a first direction, And / or, the first type of switching transistor, the second type of switching transistor and the third type of switching transistor are spaced apart in the first direction.

15. The display panel motherboard according to claim 14, wherein: The arrangement of the first type of control transistors, the second type of control transistors and the third type of control transistors in the first type of panel area is the same as the arrangement of the first type of control transistors, the second type of control transistors and the third type of control transistors in the second type of panel area. Or, the arrangement of the first type of control transistor, the second type of control transistor and the third type of control transistor in the first type of panel area is different from the arrangement of the first type of control transistor, the second type of control transistor and the third type of control transistor in the second type of panel area.

16. The display panel motherboard according to claim 6, wherein: The display panel further includes a control signal line, a switch signal line, and a lighting signal line. In a single panel area, the control end of the test control transistor is connected to the control signal end via the control signal line, the control end of the test switch transistor is connected to the switch signal end via the switch signal line, and the second end of the test switch transistor is connected to the lighting signal end via the lighting signal line. At least part of the control signal lines extends along the first direction, and / or at least part of the switch signal lines extends along the first direction, and / or at least part of the lighting signal lines extends along the first direction.

17. The display panel motherboard according to any one of claims 1 to 16, characterized in that: The display panel includes a substrate and an isolation structure arranged on one side of the substrate, the isolation structure encloses an isolation opening, the sub-pixel includes a light-emitting device and a driving circuit connected to the light-emitting device, the light-emitting device is at least partially located in the isolation opening, the driving circuit is arranged in the substrate, the isolation structure includes a first isolation portion and a second isolation portion located on a side of the first isolation portion away from the substrate, the second isolation portion is arranged to protrude from the first isolation portion toward the isolation opening.

18. A display panel, characterized in that: The display panel is prepared from the display panel motherboard according to any one of claims 1 to 17.

19. A display device, characterized in that: Comprising the display panel as claimed in claim 18.

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