PCIe device fault alarm method, system, device, medium and product

Abstract

The present invention discloses a PCIe device fault alarm method, system, device, medium, and product, relating to the field of communication technology. The method includes: if the current prefetchable memory values of multiple PCIe devices are not all greater than or equal to a preset value and the current prefetchable memory values of multiple PCIe devices are not all less than or equal to the preset value, disabling at least one first PCIe device among the multiple PCIe devices whose current prefetchable memory value is greater than or equal to the preset value; obtaining, based on a baseboard management controller, a first hardware signal of at least one second PCIe device whose current prefetchable memory value is less than the preset value and a second hardware signal of at least one second PCIe device identified by a host system; and recording an abnormality log of at least one target PCIe device whose first and second hardware signals are inconsistent, thereby triggering an abnormality alarm. This improves server stability and optimizes the fault alarm and logging mechanisms.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a fault alarm method, system, device medium and product for PCIe devices. Background Art

[0002] In current AI server architectures, switch chips, as key components for expanding PCIe (Peripheral Component Interconnect Express) devices, play an indispensable role in connectivity and switching. They provide powerful expansion capabilities for the CPU (Central Processing Unit), enabling the CPU to easily connect to more devices and achieve efficient interconnection between PCIe devices. As server configurations become increasingly complex, PCIe switch chips, with their abundant port and channel resources, provide strong support for connecting and expanding multiple devices. In practical applications, PCIe switch chips need to connect to various PCIe devices with diverse functions and centrally manage the memory resources of the PCIe devices expanded by their downstream ports. However, the memory resources of these PCIe devices may require more than 4GB of memory, while others may require less than 4GB.

[0003] However, because the PCIe Switch can only allocate a unified address range when integrating the pre-fetchable memory resource space of downstream devices, and this address range is either above 4GB or below 4GB, when the PCIe devices connected to the PCIe Switch chip include both devices requiring more than 4GB of memory resource space and devices requiring less than 4GB of memory resource space, the PCIe Switch chip prioritizes reserving the memory resource space below 4GB. As a result, the PCIe devices requiring more than 4GB of memory resource space cannot obtain the required memory resources and cannot complete the initialization process, causing the server to crash at the startup logo interface. During this process, the system will not generate any relevant logs or alarm information, which undoubtedly makes it extremely difficult to quickly locate the problem. Summary of the Invention

[0004] The present invention provides a fault alarm method, system, device, medium and product for PCIe devices, which at least solves the problem that when an integration anomaly occurs in the prefetchable memory configuration space of a PCIe device connected to a switch chip, there are no logs or alarms, and the server crashes on the startup logo interface, which is not conducive to rapid problem location.

[0005] The present invention provides a fault alarm method for a PCIe device, comprising the following steps: obtaining current prefetchable memory values of multiple PCIe devices, and determining whether the current prefetchable memory values of the multiple PCIe devices are all greater than or equal to a preset value, or whether the current prefetchable memory values of the multiple PCIe devices are all less than or equal to the preset value; if the current prefetchable memory values of the multiple PCIe devices are not all greater than or equal to the preset value, and if the current prefetchable memory values of the multiple PCIe devices are not all less than or equal to the preset value, disabling at least one first PCIe device among the multiple PCIe devices whose current prefetchable memory value is greater than or equal to the preset value, obtaining a first hardware signal of at least one second PCIe device among the multiple PCIe devices whose current prefetchable memory value is less than the preset value based on a baseboard management controller, identifying a second hardware signal of the at least one second PCIe device based on a host system; determining at least one target PCIe device whose first hardware signal and second hardware signal are inconsistent, recording an abnormality log of the at least one target PCIe device, and triggering an abnormality alarm.

[0006] The present invention also provides a fault alarm system for PCIe devices, comprising: a judgment module, configured to obtain current prefetchable memory values of multiple PCIe devices, and determine whether the current prefetchable memory values of the multiple PCIe devices are all greater than or equal to a preset value, or whether the current prefetchable memory values of the multiple PCIe devices are all less than or equal to the preset value; an acquisition module, configured to disable at least one first PCIe device among the multiple PCIe devices whose current prefetchable memory value is greater than or equal to the preset value if the current prefetchable memory values of the multiple PCIe devices are not all greater than or equal to the preset value, and the current prefetchable memory values of the multiple PCIe devices are not all less than or equal to the preset value, and obtain, based on a baseboard management controller, a first hardware signal of at least one second PCIe device among the multiple PCIe devices whose current prefetchable memory value is less than the preset value, and identify, based on a host system, a second hardware signal of the at least one second PCIe device; and an alarm module, configured to determine at least one target PCIe device whose first hardware signal and second hardware signal are inconsistent, record an abnormality log of the at least one target PCIe device, and trigger an abnormality alarm.

[0007] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of the above-mentioned PCIe device fault alarm method when executing the computer program.

[0008] The present invention also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the fault alarm method of the PCIe device are implemented.

[0009] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the above-mentioned PCIe device fault alarm method.

[0010] According to the present invention, if the current prefetchable memory values of multiple PCIe devices are not all greater than or equal to the preset value, and the current prefetchable memory values of multiple PCIe devices are not all less than or equal to the preset value, then at least one first PCIe device among the multiple PCIe devices whose current prefetchable memory value is greater than or equal to the preset value is disabled, and based on the baseboard management controller, a first hardware signal of at least one second PCIe device among the multiple PCIe devices whose current prefetchable memory value is less than the preset value is obtained, and based on the host system, a second hardware signal of at least one second PCIe device is identified; at least one target PCIe device whose first hardware signal and second hardware signal are inconsistent is determined, and an abnormality log of at least one target PCIe device is recorded, and an abnormality alarm is triggered. Thus, the problem that when an integration abnormality occurs in the prefetchable memory configuration space of the PCIe device connected to the Switch chip, there is no log or alarm and the server crashes on the boot logo interface, which is not conducive to rapid problem location is solved. This not only significantly improves the stability and reliability of the server system, but also optimizes the fault alarm and log recording mechanism, reduces operation and maintenance costs, and improves overall operation and maintenance efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 This is a flowchart of a fault alarm method for a PCIe device provided according to an embodiment of the present invention;

[0013] Figure 2 A schematic diagram of the connection of hardware according to an embodiment of the present invention;

[0014] Figure 3 A schematic diagram of a flow chart of a fault alarm method for a PCIe device according to an embodiment of the present invention;

[0015] Figure 4A schematic diagram of a fault alarm system for a PCIe device according to an embodiment of the present invention;

[0016] Figure 5 FIG. 1 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention.

[0017] Figure numerals: 10 - fault alarm system of PCIe device, 100 - judgment module, 200 - acquisition module, 300 - alarm module, 503 - communication interface, 501 - memory, 502 - processor. DETAILED DESCRIPTION

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0019] It should be noted that, in the description of the present invention, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. The terms "first," "second," etc., in the present invention are used to distinguish similar objects, and are not used to describe a particular order or precedence.

[0020] Before specifically introducing the embodiments of the present invention, a brief introduction to PCIe devices is given.

[0021] A brief introduction to the PCIe device configuration space:

[0022] The PCIe configuration space is 4KB in total and is divided into multiple sections, each with specific functions. These sections primarily include the header, device-specific registers, and PCIe optional configuration space. Sections 0-3Fh (64 bytes) are the PCI-compatible configuration space header, which can be categorized as either a Type 0 or Type 1 configuration space header. Sections 40h-FFh (192 bytes) are the PCI / PCI-X (extended PCI) and PCIe extended configuration space, primarily storing capability structures related to the MSI (Message Signaled Interrupts) interrupt mechanism (a method of generating interrupts by writing information to memory) or MSI-X (an extension of MSI) and power management. Sections 100h-FFFh (3840 bytes) are the PCIe protocol extension's optional configuration space, primarily storing capability structures such as the AER, virtual channels, and device serial number. The prefetch address space Prefetchable Memory Base (used to store the low 32-bit information of the starting address of the prefetchable memory area), Prefetchable Memory Limit (used to store the low 32-bit information of the ending address of the prefetchable memory area), Prefetchable Base Upper 32 Bits (used to store the high 32-bit information of the ending address of the prefetchable memory area) and Prefetchable Limit Upper 32 Bits (used to store the high 32-bit information of the ending address of the prefetchable memory area) jointly determine the range of the prefetch address space.

[0023] The first related technology provides a PCIe component identification device, including a CPLD (Complex Programmable Logic Device). The CPLD is connected to a Baseboard Management (BMC) chip via an I2C link. The CPLD also communicates with a Programmable Counter Array (PCA) chip. The PCA chip, acting as an expansion unit, branches out multiple I2C links, each corresponding to an I2C port. These I2C ports are then connected to multiple PCIe connectors. The Baseboard Management Controller (BMC) chip is connected to the flash memory of the Basic Input / Output System (BIOS) chip via a KCS channel. The BMC chip reads the PCIe component asset information identified by the BIOS chip from the flash memory and then verifies the validity of this information. Once the verification is complete, the BMC chip transmits the verification results back to the CPLD via the same I2C link. To visually display the PCIe component status, the product structure also includes an indicator light electrically connected to the CPLD. This device can identify and manage illegal PCIe components.

[0024] The second related technology discloses a PCIE hot-swappable device, a status alarm method, and a readable storage medium. The method is applied to a PCIE hot-swappable device, comprising: upon receiving a PCIE device removal instruction through a processing module, determining whether the PCIE device is occupied; in response to the PCIE device not being occupied, uninstalling the driver of the PCIE device through the processing module, controlling an alarm device to issue a first alarm, and controlling a power supply to stop supplying power to the PCIE slot; or, in response to the PCIE device being occupied, controlling the alarm device through the processing module to issue a second alarm; wherein: the first alarm is used to notify a user that removal of the PCIE device is permitted, and the second alarm is used to notify a user that removal of the PCIE device is not permitted. The present invention allows a user to perceive the device status of the PCIE hot-swappable device, reducing the risk of damage to the PCIE device during the hot-swappable process due to the user's inability to perceive the device status in a timely manner.

[0025] However, the first related technology mainly focuses on obtaining PCIe component asset information through the I2C link after PCIe device enumeration is completed. It does not compare the hardware presence status of the PCIe device with the system's identification status of the PCIe device. It mainly realizes the identification and restriction of illegal PCIe components in the server, avoiding bugs caused by illegal components, but does not solve the complex scenario where the component is physically in place but not logically visible.

[0026] The second related technology mainly focuses on solving the problem of lack of notification mechanism during PCIe hot-plugging, which makes it impossible for operators to perceive the device status in time, increasing the risk of damage. Through the alarm mechanism, operators can perceive the device status in time and know whether it is safe to remove or connect the PCIE device, reducing the risk of device damage and improving the reliability and safety of the hot-plugging process.

[0027] In summary, current server PCIe error reporting is mainly divided into Baseline Error Reporting and Advanced Error Reporting (AER). When the prefetchable memory configuration space of the PCIe device attached to the switch cannot be integrated, there are no logs or alarms, and the server directly crashes in the boot log interface. Development and maintenance personnel are unable to determine the source of the problem and it is difficult to determine whether it is a hardware problem, component problem, or related software problem, which makes it very difficult for development and maintenance personnel to locate the problem.

[0028] To solve the above problem, an embodiment of the present invention provides a fault alarm method for a PCIe device.

[0029] like Figure 1 As shown, the fault alarm method of the PCIe device includes the following steps:

[0030] Step S101, obtaining current prefetchable memory values of multiple PCIe devices, and determining whether the current prefetchable memory values of the multiple PCIe devices are all greater than or equal to a preset value, or whether the current prefetchable memory values of the multiple PCIe devices are all less than or equal to the preset value.

[0031] Prefetchable memory refers to the memory area that allows the CPU to perform cache optimization. The current prefetchable memory value can be understood as the memory value required by the PCIe device for cache optimization.

[0032] The PCIe Switch chip connects multiple PCIe devices to upstream ports and configures resource allocation for each port. In an embodiment of the present invention, the preset value is 4G (4G refers to the upper limit of the 32-bit address space, and 4GB is 0xFFFFFFFF).

[0033] It should be understood that the embodiment of the present invention adds a pre-check design to the Switch firmware, that is, during the enumeration phase of multiple PCIe devices, it is detected whether the current pre-fetchable memory values of multiple PCIe devices are greater than or equal to a preset value.

[0034] Specifically, a memory resource predictor is integrated inside the Switch chip. When PCIe devices are enumerated, the base address registers BAR0 to BAR5 of multiple PCIe devices connected to the switch chip are read to traverse the memory resource space sizes of multiple PCIe devices connected to the downstream ports of the switch, automatically skipping ports to which no PCIe devices are connected, and obtaining the current prefetchable memory value of each PCIe device. The base address register BAR defines the location and size of the memory or I / O space required by the PCIe device.

[0035] Optionally, in some embodiments, obtaining the current prefetchable memory values of multiple PCIe devices includes: determining whether the preset flag bit of the base address register of the multiple PCIe devices is a prefetchable memory flag bit; if the preset flag bit is a prefetchable memory flag bit, obtaining the current prefetchable memory values of the multiple PCIe devices according to the received prefetchable memory request.

[0036] In the embodiment of the present invention, the preset flag bit of the base address register is bit 3. If bit 3 is 1, it is determined that the preset flag bit is a prefetchable memory flag bit.

[0037] Specifically, when the type of the base address register BAR of multiple PCIe devices is memory space (that is, bit 0 of the base address register BAR is 0), and the preset flag bit 3 is 1, the preset flag is determined to be a prefetchable memory flag, and the memory requests sent by multiple PCIe devices are determined to be prefetchable memory requests. At this time, the current prefetchable memory values of multiple PCIe devices can be obtained through the base address register BAR.

[0038] Through the above technical solution, based on the standard fields (bit0 and bit3) of the BAR register in the PCIe specification, the logic of detecting whether the memory requests of multiple PCIe devices are prefetchable memory requests is implemented. This adapts to devices from different manufacturers without modifying the hardware design, reducing the complexity of firmware development.

[0039] Step S102: If the current prefetchable memory values of the multiple PCIe devices are not all greater than or equal to the preset value, and the current prefetchable memory values of the multiple PCIe devices are not all less than or equal to the preset value, then disable at least one first PCIe device among the multiple PCIe devices whose current prefetchable memory value is greater than or equal to the preset value, and obtain a first hardware signal of at least one second PCIe device among the multiple PCIe devices whose current prefetchable memory value is less than the preset value based on the baseboard management controller, and identify a second hardware signal of the at least one second PCIe device based on the host system.

[0040] It is understandable that the current prefetchable memory values of multiple PCIe devices are not all greater than or equal to the preset value, and the current prefetchable memory values of multiple PCIe devices are not all less than or equal to the preset value, that is, among multiple PCIe devices, there are devices whose current prefetchable memory values are less than or equal to 4G and devices whose current prefetchable memory values are greater than or equal to 4G.

[0041] If multiple PCIe devices contain devices with a capacity greater than 4 GB and devices with a capacity less than 4 GB, the PCIe switch prioritizes reserving ports of memory resource space of at least one second PCIe device whose current prefetchable memory value is less than or equal to 4 GB, and disables ports of at least one first PCIe device whose current prefetchable memory value is greater than or equal to a preset value.

[0042] Furthermore, the host system BIOS (Basic Input / Output System) identifies second hardware signals of multiple PCIe devices (the second hardware signals are obtained through PCIe enumeration or ACPI tables). The first hardware signal of at least one second PCIe device is compared with the second hardware signal of the at least one second PCIe device identified by the host system to detect whether any of the at least one second PCIe devices has a signal conflict.

[0043] Optionally, in some embodiments, after disabling at least one first PCIe device among multiple PCIe devices whose current prefetchable memory value is greater than or equal to a preset value, it includes: sending a hot reset signal to a port corresponding to the at least one first PCIe device to reset the at least one first PCIe device.

[0044] It can be understood that after disabling at least one first PCIe device whose current prefetchable memory value is greater than or equal to a preset value, a PCIe hot reset signal is sent to the port corresponding to the at least one first PCIe device to reset the at least one first PCIe device and retain the complete configuration of the port of the memory resource space of at least one second PCIe device whose current prefetchable memory value is less than or equal to 4G.

[0045] Through the above technical solution, after disabling at least one first PCIe device, a PCIe hot reset signal is sent to the corresponding port to forcibly reset the device status, ensuring that the residual configuration does not interfere with the operation of other devices, while retaining the complete configuration of the legitimate device to avoid system restart.

[0046] Optionally, in some embodiments, after sending a hot reset signal to the port corresponding to at least one first PCIe device to reset at least one first PCIe device, it includes: re-enumerating at least one first PCIe device and detecting whether the current prefetchable memory value of at least one first PCIe device is less than a preset value; if the current prefetchable memory value of at least one first PCIe device is greater than the preset value, continuing to disable the port corresponding to at least one first PCIe device.

[0047] It should be understood that after the hot reset, the disabled at least one first PCIe device is re-enumerated, and the current prefetchable memory value of the at least one first PCIe device is detected again.

[0048] If it is detected that the current prefetchable memory value of at least one first PCIe device is still ≥4GB, its port will continue to be disabled to block its occupation of system resources, and the operation and maintenance personnel will be notified by sending a reminder message that at least one first PCIe device is still unavailable after hot reset.

[0049] If it is detected that the current prefetchable memory value of at least one first PCIe device is less than 4 GB, the device is re-enabled.

[0050] Through the above technical solution, after a hot reset, the host system re-enumerates the devices and reads the BAR register of at least one first PCIe device to implement a secondary check. If the device still does not meet the conditions, its port is directly disabled to prevent it from occupying system resources and to avoid recurrence of conflicts caused by the device restoring its original configuration after a hot reset.

[0051] Optionally, in some embodiments, when obtaining the first hardware signal of at least one second PCIe device whose current prefetchable memory value is less than a preset value among multiple PCIe devices based on the baseboard management controller, it includes: obtaining the first verification signal and the second verification signal based on the first existence pin and the second existence pin of the at least one second PCIe device respectively; if the first verification signal and the second verification signal of the at least one second PCIe device are consistent, generating the first hardware signal corresponding to the second PCIe device based on the first verification signal and the second verification signal of the at least one second PCIe device.

[0052] It can be understood that at least one second PCIe device has a presence pin (Present Pin), including a first presence pin (Present Pin 1) and a second presence pin (Present Pin 2). The baseboard management controller samples the first presence pin and the second presence pin multiple times within a fixed time window to obtain a first verification signal and a second verification signal respectively, and determines the first hardware signal by majority voting based on the first verification signal and the second verification signal.

[0053] Through the above technical solution, by collecting dual-channel signals (the first verification signal and the second verification signal) multiple times, errors caused by collecting single-channel signals are avoided. Through the majority voting mechanism, the generated hardware signal is ensured to be consistent with the actual status of the device, avoiding resource allocation conflicts or device malfunctions caused by signal errors.

[0054] Optionally, in some embodiments, after generating a first hardware signal corresponding to the second PCIe device based on the first verification signal and the second verification signal of at least one second PCIe device, it includes: using a preset interface of the baseboard management controller to obtain the first hardware signal generated by at least one second PCIe device through the input and output pins of the input and output expander (i.e., IO expander).

[0055] Specifically, if Figure 2 As shown, the Present PIN of the PCIe device is connected to the GPIO_IN (PIN X) of the IO expander (9555 chip). After powering on, the baseboard management controller (BMC) periodically reads the status of the 9555 GPIO through the I2C (Inter-Integrated Circuit) / SPI (Serial Peripheral Interface) (that is, the default interface), thereby obtaining the first hardware signal generated by the PCIe device.

[0056] In the embodiment of the present invention, a dual-path signal acquisition + cross-check design is adopted, connected to the GPIO pins of the 9555, specifically:

[0057] The first present pin Present Pin 1 of the PCIe device is connected to the input / output pin 9555_GPIO12, serving as the main path to collect the first verification signal. The second present pin Present Pin 2 is connected to the input / output pin 9555_GPIO13, serving as the verification path to collect the second verification signal.

[0058] This embodiment of the present invention also implements anti-jitter processing: filtering circuits or software de-jitter logic can be added to the 9555 or BMC side. Furthermore, this embodiment of the present invention is highly scalable, as the 9555 supports multiple GPIOs, making it suitable for monitoring multiple PCIe slots.

[0059] The above technical solution generates a reliable hardware signal through dual-path signal cross-verification, avoids device misjudgment, ensures signal stability, and reduces frequent BMC alarms or resource reallocation caused by signal jitter through anti-jitter processing, thereby improving the overall reliability of the system.

[0060] Optionally, in some embodiments, after obtaining the first verification signal and the second verification signal respectively based on the first existence pin and the second existence pin of at least one second PCIe device, it also includes: at least one verification-failed PCIe device based on the inconsistency between the first verification signal and the second verification signal of at least one second PCIe device; recording the signal conflict timestamp, device information, signal sampling data and signal verification result of at least one verification-failed second PCIe device, and sending an alarm message to a preset terminal.

[0061] It can be understood that if there is at least one verification-failed PCIe device in at least one second PCIe device whose first verification signal obtained through the first existence pin is inconsistent with the second verification signal obtained through the second existence pin, the error log of at least one verification-failed PCIe device is recorded and an alarm message is sent to the preset terminal, specifically recording the error log of at least one verification-failed PCIe device, including: conflict timestamp, PCIe device information involved (such as port number, device ID), signal sampling data and verification results.

[0062] Through the above technical solution, by recording the difference in the sampling signals of the two pins, operation and maintenance personnel do not need to check the devices one by one. They can directly locate the faulty device through the device ID and port number in the log, reducing the fault location time. Through real-time push of the preset terminal, operation and maintenance personnel can quickly receive an alarm after a signal conflict occurs.

[0063] Step S103: determining at least one target PCIe device in which the first hardware signal and the second hardware signal of at least one second PCIe device are inconsistent, recording an abnormality log of the at least one target PCIe device, and triggering an abnormality alarm.

[0064] Specifically, if Figure 3 As shown, the first hardware signal of at least one second PCIe device is compared with the second hardware signal of the host system for identifying at least one second PCIe device to detect whether there is a device with signal conflict in the at least one second PCIe device.

[0065] If at least one target PCIe device is detected in at least one second PCIe device where the first hardware signal and the second hardware signal are inconsistent, the abnormal log of at least one target PCIe device is recorded, including the IDL log (Inventory and Diagnostic Log) and the Switch error log, to trace the root cause of the fault, and trigger an abnormal alarm through the BMC. The abnormal log includes: conflict timestamp, PCIe device information involved (such as port number, device ID), signal sampling data, and abnormal alarm includes lighting up the fault indicator light and sending an alarm message to the preset terminal (that is, Figure 3 management platform in the .

[0066] It should be noted that abnormal alarms can not only be generated by lighting up the fault indicator light, but also by pushing email / SMS alarms to the operation and maintenance personnel’s mobile phone or mailbox.

[0067] As an embodiment of the present invention, specifically: monitoring the presence of a first hardware signal and a second hardware signal in at least one second PCIe device in real time, and triggering an alarm when inconsistency is detected between the first hardware signal and the second hardware signal.

[0068] The logic of the host system detecting the second hardware signal is: the host system enumerates at least one second PCIe device through the PCIe bus. If at least one second PCIe device responds, the output second hardware signal is an "in-place signal", and the "in-place signal" indicates that the PCIe device is in-place; otherwise, the output second hardware signal is an "out-of-place signal", and the "out-of-place signal" indicates that the PCIe device is not in-place.

[0069] The first hardware signal is used to store the hardware signal status of the port corresponding to the at least one second PCIe device detected, that is, the BMC periodically reads the 9555 GPIO status to obtain the Present PIN status of the at least one second PCIe device;

[0070] The second hardware signal refers to the status of at least one second PCIe device reported by the host system. This part of the BMC is that the BIOS transmits the obtained at least one second PCIe device to the BMC system after completing the PCIe enumeration. The BMC uses an update method to update the status of the at least one second PCIe device to the information obtained regularly.

[0071] If the first hardware signal and the second hardware signal are inconsistent, it indicates that a "ghost device" problem may exist. The "ghost device" is at least one target PCIe device. There are two possible situations: the first hardware signal obtained by the BMC shows that the device is in place, but the host system does not recognize it; or the host system recognizes the device, but the first hardware signal obtained by the BMC shows that the device is not in place. Both situations are conflicts.

[0072] If a conflict is detected, a BMC alarm is triggered and a detailed log is recorded, including: conflict timestamp, information about the PCIe devices involved (such as port number and device ID), signal sampling data, and verification results.

[0073] Optionally, in some embodiments, after the host system identifies the second hardware signal of at least one second PCIe device, it also includes: based on the first hardware signal and the second hardware signal of the at least one second PCIe device, determining whether there is a second PCIe device in the at least one second PCIe device whose first hardware signal and the second hardware signal are consistent; if there is a second PCIe device in the at least one second PCIe device whose first hardware signal and the second hardware signal are consistent, determining that the second PCIe device in the at least one second PCIe device whose first hardware signal and the second hardware signal are consistent is in a normal state.

[0074] It should be understood that when there is a second PCIe device in at least one second PCIe device whose first hardware signal is consistent with the second hardware signal, it indicates that the second PCIe device is in a normal state and no abnormal alarm action is required, and regular monitoring is sufficient.

[0075] Through the above technical solution, there is no need to perform abnormal alarm actions on normal PCIe devices, regular monitoring is performed, and resource usage is reduced.

[0076] Optionally, in some embodiments, after determining whether the current prefetchable memory values of multiple PCIe devices are all greater than or equal to a preset value, or whether the current prefetchable memory values of multiple PCIe devices are all less than or equal to the preset value, the following steps are included: if the current prefetchable memory values of multiple PCIe devices are all greater than or equal to the preset value, or the current prefetchable memory values of multiple PCIe devices are all less than or equal to the preset value, then the ports corresponding to the multiple PCIe devices are not disabled, and the third hardware signals of the multiple PCIe devices are obtained based on the baseboard management controller, and the fourth hardware signals of the multiple PCIe devices are identified based on the host system; at least one abnormal PCIe device whose third hardware signals and fourth hardware signals of the multiple PCIe devices are inconsistent is determined, and an abnormal log of at least one abnormal PCIe device is recorded, and an abnormal alarm is triggered.

[0077] It can be understood that if the current prefetchable memory values of multiple PCIe devices are greater than or equal to 4G, or the current prefetchable memory values of multiple PCIe devices are less than or equal to 4G, the ports corresponding to the multiple PCIe devices will not be disabled, and the third hardware signals of the multiple PCIe devices will be obtained through the baseboard management controller, and the fourth hardware signals of the multiple PCIe devices will be identified through the host system, and a corresponding judgment will be made based on the third hardware signals and the fourth hardware signals of the multiple PCIe devices to determine whether they are consistent.

[0078] It can be understood that the third hardware signals of multiple PCIe devices are obtained through the baseboard management controller BMC, and the fourth hardware signals of multiple PCIe devices are identified through the host system, so as to determine at least one abnormal PCIe device whose third hardware signals and fourth hardware signals of multiple PCIe devices are inconsistent, and record the abnormal log of at least one abnormal PCIe device, including IDL log (Inventory and Diagnostic Log) and Switch error log, to achieve fault root cause tracing, and trigger an abnormal alarm through the baseboard management controller. The abnormal log includes: conflict timestamp, PCIe device information involved (such as port number, device ID), signal sampling data and verification results. The abnormal alarm includes lighting up the fault indicator light and sending an alarm message to the preset terminal.

[0079] Through the above technical solution, the prefetchable memory values of multiple PCIe devices are used to determine that the port is enabled only when the memory values of multiple PCIe devices are consistent, avoiding system performance degradation due to resource conflicts. Dual signal verification filters out false alarms caused by abnormalities in a single signal channel, improving fault detection accuracy. It records the dual hardware signal data, timestamps and context information of abnormal devices, supporting operation and maintenance personnel to quickly trace the root cause of the fault.

[0080] Optionally, in some embodiments, after determining that there is a second PCIe device in at least one second PCIe device whose first hardware signal and second hardware signal are consistent and is in a normal state, it includes: using a hot-swap controller to poll and detect whether there is a newly inserted PCIe device; if there is a newly inserted PCIe device, reading the current prefetchable memory value of the newly inserted PCIe device; when the current prefetchable memory value of the newly inserted PCIe device is greater than a preset value, disabling the corresponding port of the newly inserted PCIe device, and recording a port disabling log of the newly inserted PCIe device.

[0081] Among them, the embodiment of the present invention ensures the default high level through a pull-up resistor. If the PCIe device is not inserted, the presence pin Present Pin of the corresponding PCIe device is high. When the PCIe device is inserted, the corresponding presence pin Present Pin is at a low level, thereby determining whether there is a newly inserted PCIe device.

[0082] It's important to understand that to address hot-plugging of PCIe devices, this embodiment of the present invention modifies the ACPI (Advanced Configuration and Power Interface) Hot Plug Controller (HPC) driver. The hot-plug controller or its driver polls the switch chip's status every 500 milliseconds to detect newly inserted or removed PCIe devices. This polling mechanism ensures the system can respond promptly to hot-plug events.

[0083] When a hot-swappable device is inserted into the downstream port of the PCIe Switch, it is determined that there is a newly inserted PCIe device. Before the newly inserted PCIe device is enumerated, a pre-check process is also performed. Specifically:

[0084] Determine whether the current prefetchable memory value of the newly inserted PCIe device is consistent with the current prefetchable memory value of at least one second PCIe device of the existing Switch downstream port, that is, determine whether the current prefetchable memory value of the newly inserted PCIe device is less than or equal to 4G. If the current prefetchable memory value of the newly inserted PCIe device is greater than 4G, it is necessary to disable the port of the newly inserted PCIe device. At the same time, the Switch chip records relevant information of the disabled port of the newly inserted PCIe device, such as port ID, pre-check result, disablement time and other information. If the current prefetchable memory value of the newly inserted PCIe device is less than or equal to 4G, the port corresponding to the newly inserted PCIe device is not disabled.

[0085] Through the above technical solution, newly inserted PCIe devices are intercepted before enumeration to avoid system crashes caused by resource allocation failures. Through the closed loop of logs and alarms, operation and maintenance personnel can quickly locate the root cause of hot-swap problems and shorten fault recovery time.

[0086] Optionally, in some embodiments, when the current prefetchable memory value of the newly inserted PCIe device is less than a preset value, it includes: obtaining the fifth hardware signal of the newly inserted PCIe device based on the baseboard management controller, and identifying the sixth hardware signal of the newly inserted PCIe device based on the host system, and judging whether the fifth hardware signal of the newly inserted PCIe device is consistent with the sixth hardware signal; if the fifth hardware signal is inconsistent with the sixth hardware signal, it is determined that the newly inserted PCIe device is in an abnormal state, and the abnormal log of the newly inserted PCIe device is recorded, and an abnormal alarm is triggered.

[0087] Specifically, when the current prefetchable memory value of the newly inserted PCIe device is less than 4G, the fifth hardware signal of the newly inserted PCIe device is obtained through the baseboard management controller, and the sixth hardware signal of the newly inserted PCIe device is identified based on the host system. If the fifth hardware signal and the sixth hardware signal of the newly inserted PCIe device are inconsistent, it is determined that the newly inserted PCIe device is in an abnormal state, indicating that the newly inserted PCIe device is a "ghost device."

[0088] At this time, the Switch chip records the exception log of the newly inserted PCIe device and triggers an exception alarm. The exception log includes: conflict timestamp, information about the PCIe device involved (such as port number, device ID), signal sampling data and verification results, etc., and sends an alarm message to the preset terminal and lights up the fault indicator to remind the operation and maintenance personnel that the newly inserted PCIe device is abnormal.

[0089] Through the above technical solution, false alarms caused by abnormalities in a single signal channel are filtered out through dual-signal cross-validation, the accuracy of alarms is improved, and fault location time is reduced through logging and alarms.

[0090] In order to enable those skilled in the art to further understand the fault alarm method of the PCIe device according to the embodiment of the present invention, it is described in detail below with reference to specific embodiments.

[0091] (1) The embodiment of the present invention sets BIOS (BIOS (Basic Input / Output System, Basic Input / Output System) / UEFI and UEFI (Unified Extensible Firmware Interface, Unified Extensible Firmware Interface) pre-check:

[0092] Specifically, the Switch firmware adds a pre-check feature. During device enumeration, it reads the BAR information for each PCIe device port to determine the device's current prefetchable memory capacity. If some PCIe devices have a current prefetchable memory capacity exceeding 4GB while others have a current prefetchable memory capacity less than 4GB, the port of the PCIe device with a capacity exceeding 4GB is disabled. Otherwise, no action is taken. This way, when both PCIe devices with a capacity exceeding 4GB and those with a capacity less than 4GB coexist, the Switch chip prioritizes the PCIe device with a current prefetchable memory capacity less than 4GB, ensuring optimal resource allocation.

[0093] (2) Hot-swap driver enhancement

[0094] When a newly inserted PCIe device exists on the downstream port of the PCIe Switch, a pre-check process is also performed before the newly inserted PCIe device is enumerated. If the current pre-fetchable memory value of the newly inserted PCIe device is consistent with that of the existing PCIe device on the downstream port of the Switch, for example, both are above 4G or below 4G, no processing is performed. If the current pre-fetchable memory value of the newly inserted PCIe device is inconsistent with that of the existing PCIe device on the downstream port of the Switch, that is, there are both PCIe devices above 4G and below 4G on the downstream port of the Switch, the PCIe port of the newly inserted PCIe device needs to be disabled. At the same time, the Switch chip records the relevant information of the port of the newly inserted PCIe device, such as the port ID, pre-check result, and disable time.

[0095] (3) The Switch adds a port fuse mechanism, adds a gating circuit to the physical layer of the Switch, and supports dynamic port disabling: When all PCIe devices under the Switch chip include PCIe devices with prefetchable memory values of more than 4G and PCIe devices with prefetchable memory values of less than 4G, the ports of all PCIe devices with prefetchable memory values of more than 4G are immediately disabled, and a PCIe hot reset signal is sent to the ports of PCIe devices with prefetchable memory values of more than 4G, while the complete configuration of the ports of PCIe devices with prefetchable memory values of less than 4G is retained.

[0096] (4) Connect the presence pin of the PCIe device to the GPIO_IN PIN of the IO expander 9555. After the power-on is complete, the BMC periodically reads the status of the 9555 GPIO through the I2C interface, obtains the first hardware signal of the PCIe device, and compares it with the second hardware signal of the PCIe device identified by the host system. When the first hardware signal of the PCIe device is consistent with the second hardware signal, the PCIe device is determined to be in a normal state and no action is required. Regular monitoring is sufficient. When the first hardware signal of the PCIe device is inconsistent with the second hardware signal, the BMC triggers an alarm, records the log of the abnormal PCIe device, lights up the fault indicator, and sends an alarm message to the preset terminal to alert the operation and maintenance personnel.

[0097] In summary, the technical effects brought about by the embodiments of the present invention are as follows:

[0098] (1) Through the 4GB memory threshold pre-check mechanism, potential resource conflicts are intercepted during the device initialization phase, avoiding system crashes caused by improper allocation of prefetchable memory, and fundamentally improving server reliability.

[0099] When the memory resources requested by a PCIe device exceed the threshold, the system automatically blocks the excess and disables the corresponding switch port to ensure normal server startup and resolve startup failures caused by resource conflicts.

[0100] (2) The physical signal of the PCIe device is obtained through the BMC and compared with the logical state after the host system is started, accurately identifying the "ghost device", greatly enhancing the reliability of the system.

[0101] (3) Combining BMC alarms, IDL logs (device initialization logs), and switch error logs, a three-level log system was established to quickly identify the root cause of the problem, reducing the average fault diagnosis time by over 80%. This significantly improved fault location efficiency, saved labor costs for reproducing the problem, and improved overall delivery efficiency and quality. Through multi-channel alarm push, including BMC alarms, email notifications, and indicator lights, fault handling was automated and standardized.

[0102] (4) After the PCIe device is hot-reset, the host system re-enumerates the device and reads the BAR register of the PCIe device to implement a secondary check. If the device still does not meet the conditions, its port is directly disabled to prevent it from occupying system resources and to avoid the recurrence of conflicts caused by the device restoring its original configuration after the hot reset.

[0103] (5) Generate reliable hardware signals through dual-path signal cross-verification to avoid equipment misjudgment and ensure signal stability. Through anti-jitter processing, reduce frequent BMC alarms or resource reallocation caused by signal jitter, and improve the overall reliability of the system.

[0104] (6) By collecting dual-channel signals (the first verification signal and the second verification signal) multiple times, errors caused by collecting single-channel signals are avoided, and through the majority voting mechanism, the generated hardware signal is ensured to be consistent with the actual status of the device, avoiding resource allocation conflicts or device malfunctions caused by signal errors.

[0105] According to an embodiment of the present invention, a PCIe device fault alarm method is proposed. If the current prefetchable memory values of multiple PCIe devices are not all greater than or equal to a preset value, and the current prefetchable memory values of multiple PCIe devices are not all less than or equal to the preset value, at least one first PCIe device among the multiple PCIe devices whose current prefetchable memory value is greater than or equal to the preset value is disabled, and a first hardware signal of at least one second PCIe device among the multiple PCIe devices whose current prefetchable memory value is less than the preset value is obtained based on a baseboard management controller, and a second hardware signal of the at least one second PCIe device is identified based on a host system; at least one target PCIe device is determined where the first hardware signal and the second hardware signal of the at least one second PCIe device are inconsistent, and an abnormality log of the at least one target PCIe device is recorded, and an abnormality alarm is triggered. Thus, the method solves the problem that when the prefetchable memory configuration space of the PCIe device connected to the switch chip has an integration abnormality, there is no log or alarm, and the server crashes on the boot logo interface, which is not conducive to rapid problem location. The method not only significantly improves the stability and reliability of the server system, but also optimizes the fault alarm and logging mechanism, reduces operation and maintenance costs, and improves overall operation and maintenance efficiency.

[0106] Next, a PCIe device fault alarm system according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0107] Figure 4 Schematic diagram of a fault alarm system for a PCIe device according to an embodiment of the present invention.

[0108] like Figure 4 As shown, the fault alarm system 10 of the PCIe device includes: a judgment module 100, an acquisition module 200 and an alarm module 300.

[0109] The determination module 100 is configured to obtain current prefetchable memory values of multiple PCIe devices and determine whether the current prefetchable memory values of the multiple PCIe devices are all greater than or equal to a preset value, or whether the current prefetchable memory values of the multiple PCIe devices are all less than or equal to the preset value;

[0110] an acquisition module 200 configured to, if current prefetchable memory values of the plurality of PCIe devices are not all greater than or equal to a preset value and current prefetchable memory values of the plurality of PCIe devices are not all less than or equal to the preset value, disable at least one first PCIe device among the plurality of PCIe devices whose current prefetchable memory value is greater than or equal to the preset value, acquire, based on a baseboard management controller, a first hardware signal of at least one second PCIe device among the plurality of PCIe devices whose current prefetchable memory value is less than the preset value, and identify, based on a host system, a second hardware signal of the at least one second PCIe device;

[0111] The alarm module 300 is configured to determine at least one target PCIe device where the first hardware signal and the second hardware signal of at least one second PCIe device are inconsistent, record an abnormality log of the at least one target PCIe device, and trigger an abnormality alarm.

[0112] Optionally, in some embodiments, after determining whether the current prefetchable memory values of multiple PCIe devices are all greater than or equal to a preset value, or whether the current prefetchable memory values of multiple PCIe devices are all less than or equal to the preset value, the judgment module 100 is also used to: if the current prefetchable memory values of multiple PCIe devices are all greater than or equal to the preset value, or the current prefetchable memory values of multiple PCIe devices are all less than or equal to the preset value, then the ports corresponding to the multiple PCIe devices are not disabled, and the third hardware signals of the multiple PCIe devices are obtained based on the baseboard management controller, and the fourth hardware signals of the multiple PCIe devices are identified based on the host system; determine at least one abnormal PCIe device whose third hardware signals and fourth hardware signals of the multiple PCIe devices are inconsistent, record an abnormal log of at least one abnormal PCIe device, and trigger an abnormal alarm.

[0113] Optionally, in some embodiments, the judgment module 100 is also used to: determine whether the preset flag bit of the base address register of multiple PCIe devices is a prefetchable memory flag bit; if the preset flag bit is a prefetchable memory flag bit, obtain the current prefetchable memory value of multiple PCIe devices according to the received prefetchable memory request.

[0114] Optionally, in some embodiments, the acquisition module 200 is further used to: obtain a first verification signal and a second verification signal based on a first existence pin and a second existence pin of at least one second PCIe device, respectively; if the first verification signal and the second verification signal of at least one second PCIe device are consistent, then generate a first hardware signal corresponding to the second PCIe device based on the first verification signal and the second verification signal of at least one second PCIe device.

[0115] Optionally, in some embodiments, after generating the first hardware signal corresponding to the second PCIe device based on the first verification signal and the second verification signal of at least one second PCIe device, the acquisition module 200 is further used to: use the preset interface of the baseboard management controller to obtain the first hardware signal generated by at least one second PCIe device through the input and output pins of the IO expander.

[0116] Optionally, in some embodiments, after respectively obtaining the first verification signal and the second verification signal based on the first existence pin and the second existence pin of at least one second PCIe device, the acquisition module 200 is further used to: verify at least one PCIe device that fails verification based on the inconsistency between the first verification signal and the second verification signal of at least one second PCIe device; record the signal conflict timestamp, device information, signal sampling data and signal verification result of at least one second PCIe device that fails verification, and send an alarm message to a preset terminal.

[0117] Optionally, in some embodiments, after disabling at least one first PCIe device among multiple PCIe devices whose current prefetchable memory value is greater than or equal to a preset value, the acquisition module 200 is further used to: send a hot reset signal to a port corresponding to the at least one first PCIe device to reset the at least one first PCIe device.

[0118] Optionally, in some embodiments, after sending a hot reset signal to the port corresponding to at least one first PCIe device to reset at least one first PCIe device, the acquisition module 200 is further used to: re-enumerate at least one first PCIe device and detect whether the current prefetchable memory value of at least one first PCIe device is less than a preset value; if the current prefetchable memory value of at least one first PCIe device is greater than the preset value, continue to disable the port corresponding to at least one first PCIe device.

[0119] Optionally, in some embodiments, after the host system identifies the second hardware signal of at least one second PCIe device, the acquisition module 200 is further used to: determine whether there is a second PCIe device in the at least one second PCIe device based on the first hardware signal and the second hardware signal of the at least one second PCIe device; if there is a second PCIe device in the at least one second PCIe device whose first hardware signal and the second hardware signal are consistent, then determine that the second PCIe device in the at least one second PCIe device whose first hardware signal and the second hardware signal are consistent is in a normal state.

[0120] Optionally, in some embodiments, after determining that there is a second PCIe device in at least one second PCIe device whose first hardware signal and second hardware signal are consistent and is in a normal state, the acquisition module 200 is also used to: use the hot-swap controller to poll and detect whether there is a newly inserted PCIe device; if there is a newly inserted PCIe device, read the current prefetchable memory value of the newly inserted PCIe device; when the current prefetchable memory value of the newly inserted PCIe device is greater than a preset value, disable the corresponding port of the newly inserted PCIe device, and record the port disabling log of the newly inserted PCIe device.

[0121] Optionally, in some embodiments, when the current prefetchable memory value of the newly inserted PCIe device is less than a preset value, the acquisition module 200 is also used to: obtain the fifth hardware signal of the newly inserted PCIe device based on the baseboard management controller, and identify the sixth hardware signal of the newly inserted PCIe device based on the host system, and determine whether the fifth hardware signal of the newly inserted PCIe device is consistent with the sixth hardware signal; if the fifth hardware signal is inconsistent with the sixth hardware signal, it is determined that the newly inserted PCIe device is in an abnormal state, and the abnormal log of the newly inserted PCIe device is recorded, and an abnormal alarm is triggered.

[0122] It should be noted that the description of the features in the embodiment corresponding to the fault alarm system of the PCIe device can refer to the relevant description of the embodiment corresponding to the fault alarm method of the PCIe device mentioned above, and will not be repeated here.

[0123] Figure 5 This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. The electronic device may include:

[0124] Memory 501 , processor 502 , and computer programs stored in the memory 501 and executable on the processor 502 .

[0125] When the processor 502 executes the program, the fault alarm method for the PCIe device provided in the above embodiment is implemented.

[0126] Furthermore, the electronic device further includes:

[0127] The communication interface 503 is used for communication between the memory 501 and the processor 502 .

[0128] The memory 501 is used to store computer programs that can be run on the processor 502 .

[0129] The memory 501 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0130] If the memory 501, processor 502, and communication interface 503 are implemented independently, the communication interface 503, memory 501, and processor 502 can be interconnected via a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be divided into address buses, data buses, control buses, etc. For ease of representation, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0131] Optionally, in a specific implementation, if the memory 501, the processor 502 and the communication interface 503 are integrated on a chip, the memory 501, the processor 502 and the communication interface 503 can communicate with each other through an internal interface.

[0132] The processor 502 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0133] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned PCIe device fault alarm method embodiments when running.

[0134] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0135] An embodiment of the present invention further provides a computer program product, including a computer program, which implements the above-mentioned PCIe device fault alarm method when executed by a processor.

[0136] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0137] The above is a detailed introduction to the fault alarm method, system, device, medium and product of a PCIe device provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A PCIe device fault alarm method, characterized in that: The following steps are involved: Obtaining current prefetchable memory values of a plurality of PCIe devices, and determining whether the current prefetchable memory values of the plurality of PCIe devices are all greater than or equal to a preset value, or whether the current prefetchable memory values of the plurality of PCIe devices are all less than or equal to the preset value; If the current prefetchable memory values of the multiple PCIe devices are not all greater than or equal to the preset value, and the current prefetchable memory values of the multiple PCIe devices are not all less than or equal to the preset value, disabling at least one first PCIe device among the multiple PCIe devices whose current prefetchable memory value is greater than or equal to the preset value, obtaining a first hardware signal of at least one second PCIe device among the multiple PCIe devices whose current prefetchable memory value is less than the preset value based on the baseboard management controller, and identifying a second hardware signal of the at least one second PCIe device based on the host system; determining at least one target PCIe device in which the first hardware signal and the second hardware signal of the at least one second PCIe device are inconsistent, recording an abnormality log of the at least one target PCIe device, and triggering an abnormality alarm; If the current prefetchable memory values of the multiple PCIe devices are all greater than or equal to the preset value, or if the current prefetchable memory values of the multiple PCIe devices are all less than or equal to the preset value, then the ports corresponding to the multiple PCIe devices are not disabled, and third hardware signals of the multiple PCIe devices are obtained based on the baseboard management controller, and fourth hardware signals of the multiple PCIe devices are identified based on the host system; At least one abnormal PCIe device in which the third hardware signal and the fourth hardware signal of the multiple PCIe devices are inconsistent is determined, an abnormality log of the at least one abnormal PCIe device is recorded, and an abnormality alarm is triggered.

2. The PCIe device fault alarm method according to claim 1, wherein: The obtaining of current prefetchable memory values of multiple PCIe devices includes: Determining whether the preset flag bits of the base address registers of the multiple PCIe devices are prefetchable memory flag bits; If the preset flag bits are all the prefetchable memory flag bits, current prefetchable memory values of the multiple PCIe devices are obtained according to the received prefetchable memory request.

3. The PCIe device fault alarm method according to claim 1, wherein: When obtaining, based on the baseboard management controller, a first hardware signal of at least one second PCIe device whose current prefetchable memory value is smaller than the preset value among the multiple PCIe devices, the method includes: Obtain a first verification signal and a second verification signal based on a first presence pin and a second presence pin of the at least one second PCIe device, respectively; If the first verification signal of the at least one second PCIe device is consistent with the second verification signal, a first hardware signal corresponding to the second PCIe device is generated based on the first verification signal of the at least one second PCIe device and the second verification signal.

4. The PCIe device fault alarm method according to claim 3, wherein: After generating a first hardware signal corresponding to the second PCIe device based on the at least one first verification signal of the second PCIe device and the second verification signal, the method includes: The first hardware signal generated by the at least one second PCIe device is acquired through the input and output pins of the IO expander using the preset interface of the baseboard management controller.

5. The PCIe device fault alarm method according to claim 3, wherein: After respectively acquiring a first verification signal and a second verification signal based on the first presence pin and the second presence pin of the at least one second PCIe device, the method further includes: at least one verification-failed PCIe device based on inconsistency between the first verification signal and the second verification signal of the at least one second PCIe device; The signal conflict timestamp, device information, signal sampling data and signal verification result of the at least one second PCIe device that fails verification are recorded, and an alarm message is sent to a preset terminal.

6. The PCIe device fault alarm method according to claim 1, wherein: After disabling at least one first PCIe device among the plurality of PCIe devices whose current prefetchable memory value is greater than or equal to the preset value, the method includes: Sending a hot reset signal to a port corresponding to the at least one first PCIe device to reset the at least one first PCIe device.

7. The PCIe device fault alarm method according to claim 6, characterized in that: After sending a hot reset signal to a port corresponding to the at least one first PCIe device to reset the at least one first PCIe device, the method further includes: Re-enumerating the at least one first PCIe device and detecting whether a current prefetchable memory value of the at least one first PCIe device is less than the preset value; If the current pre-fetchable memory value of the at least one first PCIe device is greater than the preset value, the port corresponding to the at least one first PCIe device continues to be disabled.

8. The PCIe device fault alarm method according to claim 1, wherein: After the host system identifies the second hardware signal of the at least one second PCIe device, the method further includes: Based on the first hardware signal and the second hardware signal of the at least one second PCIe device, determining whether there is a second PCIe device in the at least one second PCIe device whose first hardware signal and the second hardware signal are consistent; If there is a second PCIe device among the at least one second PCIe device whose first hardware signal is consistent with the second hardware signal, it is determined that the second PCIe device among the at least one second PCIe device whose first hardware signal is consistent with the second hardware signal is in a normal state.

9. The PCIe device fault alarm method according to claim 8, characterized in that: After determining that a second PCIe device among the at least one second PCIe device has the first hardware signal and the second hardware signal that are consistent and is in a normal state, the method includes: Use the hot-swap controller to poll and detect whether there is a newly inserted PCIe device; If the newly inserted PCIe device exists, reading the current prefetchable memory value of the newly inserted PCIe device; When the current prefetchable memory value of the newly inserted PCIe device is greater than the preset value, the port corresponding to the newly inserted PCIe device is disabled, and a port disabling log of the newly inserted PCIe device is recorded.

10. The PCIe device fault alarm method according to claim 9, characterized in that: When the current prefetchable memory value of the newly inserted PCIe device is less than the preset value, the method includes: Acquiring, based on the baseboard management controller, a fifth hardware signal of the newly inserted PCIe device, identifying, based on the host system, a sixth hardware signal of the newly inserted PCIe device, and determining whether the fifth hardware signal of the newly inserted PCIe device is consistent with the sixth hardware signal; If the fifth hardware signal is inconsistent with the sixth hardware signal, it is determined that the newly inserted PCIe device is in an abnormal state, an abnormality log of the newly inserted PCIe device is recorded, and an abnormality alarm is triggered.

11. A PCIe device fault alarm system, characterized in that: include: a determination module, configured to obtain current prefetchable memory values of a plurality of PCIe devices, and determine whether the current prefetchable memory values of the plurality of PCIe devices are all greater than or equal to a preset value, or whether the current prefetchable memory values of the plurality of PCIe devices are all less than or equal to the preset value; an acquisition module configured to, if current prefetchable memory values of the multiple PCIe devices are not all greater than or equal to the preset value and current prefetchable memory values of the multiple PCIe devices are not all less than or equal to the preset value, disable at least one first PCIe device among the multiple PCIe devices whose current prefetchable memory value is greater than or equal to the preset value, acquire, based on a baseboard management controller, a first hardware signal of at least one second PCIe device among the multiple PCIe devices whose current prefetchable memory value is less than the preset value, and identify, based on a host system, a second hardware signal of the at least one second PCIe device; If the current prefetchable memory values of the multiple PCIe devices are all greater than or equal to the preset value, or the current prefetchable memory values of the multiple PCIe devices are all less than or equal to the preset value, then the ports corresponding to the multiple PCIe devices are not disabled, and the third hardware signals of the multiple PCIe devices are obtained based on the baseboard management controller, and the fourth hardware signals of the multiple PCIe devices are identified based on the host system; an alarm module, configured to determine at least one target PCIe device in which the first hardware signal and the second hardware signal of the at least one second PCIe device are inconsistent, record an abnormality log of the at least one target PCIe device, and trigger an abnormality alarm; At least one abnormal PCIe device is determined, in which the third hardware signal and the fourth hardware signal of the plurality of PCIe devices are inconsistent, and an abnormality log of the at least one abnormal PCIe device is recorded, and an abnormality alarm is triggered.

12. An electronic device, characterized in that: The system comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the fault alarm method for a PCIe device as claimed in any one of claims 1 to 10.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the fault alarm method for a PCIe device according to any one of claims 1 to 10.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the fault alarm method for a PCIe device according to any one of claims 1 to 10 is implemented.

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