Reset signal generating circuit and display driving chip
By designing a current reference unit and a short pulse cancellation unit in the reset signal generation circuit, the problem that the pulse width of the short pulse signal is susceptible to temperature is solved, and accurate reset signal recognition and processing under different temperature conditions are achieved.
Patent Information
- Application Number
- CN202311725575.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-14
- Publication Date
- 2025-06-24
AI Technical Summary
When the existing reset signal generation circuit eliminates short pulse signals, the pulse width is easily affected by temperature, resulting in the inability to accurately identify the reset signal, which violates the specifications of the display driver chip.
A reset signal generation circuit is designed, including a current reference unit and a short pulse cancelling unit. The current reference unit generates a current reference signal according to the operating voltage, and the short pulse cancellation unit uses this signal to delay the initial reset signal to ensure that the pulse width of the short pulse signal is not affected by temperature.
Through this circuit structure, the pulse width of the eliminated short pulse signal remains unchanged and is not affected by temperature, thus meeting the strict specifications of the reset signal by the display driver chip.
Smart Images
Figure CN120199173A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuits, and more particularly, relates to a reset signal generation circuit and a display driver chip. Background Art
[0002] A display driver chip (Display Driver IC) can enter an idle, initialization, or stop state for all circuits on the chip through a reset signal. When this important reset signal is applied to the pad, it can contain pure signals and noise. In some cases, especially when the chip is tested for electrostatic discharge (ESD), many surges (or short pulse signals) are applied to the pad, making it difficult to meet the ESD test specifications. In this case, the reset signal with short pulse signals may cause software ESD failures.
[0003] In addition, when the chip is in a sleep state or a deep standby mode, the internal operations of the chip must be minimized to meet the leakage current specifications. Therefore, the configuration of the circuit for short pulse signal elimination is restricted, and the display driver chip has strict specifications for the reset signal, that is, a reset signal with a pulse width of about 5 μs or less is recognized as a noise signal and is not recognized as a reset signal.
[0004] In a typical reset signal generation circuit, there is a method of eliminating short pulses by using a delay unit. However, this circuit structure is vulnerable to temperature, so the pulse width of the eliminated short pulses may be inaccurate, resulting in violation of the specifications of the display driver chip. Summary of the Invention
[0005] In order to solve the above technical problems existing in the prior art, according to an embodiment of the present invention, a reset signal generation circuit and a display driver chip are provided.
[0006] The reset signal generation circuit provided by an aspect of the embodiments of the present invention includes: a current reference unit for receiving an operating voltage and generating a current reference signal according to the operating voltage; a short pulse elimination unit for receiving an initial reset signal and the current reference signal, and eliminating short pulse signals in the initial reset signal according to the current reference signal to generate and output a reset signal; wherein, the current reference signal is used to keep the pulse width of the short pulse signals eliminated by the short pulse elimination unit unchanged with temperature.
[0007] In an example of the reset signal generation circuit provided by the above aspect, the pulse width of the short pulse signal is less than or equal to 5 μs.
[0008] In an example of the reset signal generation circuit provided in the above aspect, the current reference unit includes: an initial current reference signal generation module for generating an initial current reference signal according to the operating voltage; a first proportional current source module for amplifying the current of the initial current reference signal to generate a first amplified current signal; and a second proportional current source module for further amplifying the current of the first amplified current signal to generate the current reference signal.
[0009] In an example of the reset signal generation circuit provided in the above aspect, the initial current reference signal generation module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a first resistor, and a second resistor. The source of the first PMOS transistor, the source of the second PMOS transistor, the gate of the first NMOS transistor, and one end of the first resistor are all connected to the operating voltage terminal. The source of the first NMOS transistor is connected to the common ground terminal. The drain of the first PMOS transistor, the drain of the first NMOS transistor, one end of the second resistor, and the gate of the second PMOS transistor are connected together. The gate of the first PMOS transistor, the other end of the first resistor, and the other end of the second resistor are connected together. The drain of the second PMOS transistor is connected to the first proportional current source module.
[0010] In an example of the reset signal generation circuit provided in the above aspect, the first proportional current source module includes a second NMOS transistor and a third NMOS transistor. The sources of the second NMOS transistor and the third NMOS transistor are connected to the common ground terminal. The gate of the second NMOS transistor, the gate of the third NMOS transistor, and the drain of the second NMOS transistor are connected together and connected to the initial current reference signal generation module. The drain of the third NMOS transistor is connected to the second proportional current source module.
[0011] In an example of the reset signal generation circuit provided in the above aspect, the second proportional current source module includes a third PMOS transistor and a fourth PMOS transistor. The sources of the third PMOS transistor and the fourth PMOS transistor are connected to the operating voltage terminal. The gate of the third PMOS transistor, the gate of the fourth PMOS transistor, and the drain of the third PMOS transistor are connected together and connected to the first proportional current source module. The drain of the fourth PMOS transistor is connected to the short pulse elimination unit.
[0012] In an example of the reset signal generation circuit provided according to the above aspect, the short pulse elimination unit includes: a delay module configured to receive an initial reset signal and the current reference signal, and delay the initial reset signal according to the current reference signal to generate a delayed reset signal as a trigger threshold signal; a Schmitt trigger module configured to output a reset signal according to the trigger threshold signal; wherein, the time for delaying the initial reset signal is the pulse width of the short pulse signal.
[0013] In an example of the reset signal generation circuit provided according to the above aspect, the delay module includes: a fifth PMOS transistor, a fourth NMOS transistor, and a capacitor; wherein, the source of the fifth PMOS transistor is connected to the second proportional current source module, the source of the fourth NMOS transistor and one end of the capacitor are both connected to a common ground terminal, the gates of the fifth PMOS transistor and the fourth NMOS transistor are both configured to receive the initial reset signal, and the drains of the fifth PMOS transistor and the fourth NMOS transistor and the other end of the capacitor are connected together and connected to the Schmitt trigger module.
[0014] In an example of the reset signal generation circuit provided according to the above aspect, the Schmitt trigger module includes: a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor.
[0015] A display driver chip provided according to another aspect of an embodiment of the present invention includes the above-mentioned reset signal generation circuit.
[0016] Advantageous effects: The pulse width of the short pulse signal eliminated by the reset signal generation circuit provided according to an embodiment of the present invention remains unchanged with temperature, and thus is not affected by the device temperature. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Through the following description in conjunction with the drawings, the above and other aspects, features, and advantages of the embodiments of the present invention will become clearer. In the drawings:
[0018] Figure 1 is a schematic diagram of a reset signal generation circuit according to an embodiment of the present invention;
[0019] Figure 2 is a block diagram of a current reference unit according to an embodiment of the present invention;
[0020] Figure 3 is a block diagram of a short pulse elimination unit according to an embodiment of the present invention;
[0021] Figure 4 is a circuit structure diagram of a reset signal generation circuit according to an embodiment of the present invention;
[0022] Figure 5 is a timing diagram of the operation of a reset signal generation circuit according to an embodiment of the present invention. Detailed implementation manners
[0023] The following detailed implementation manners are provided to assist the reader in obtaining a comprehensive understanding of the methods, apparatuses, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described herein will be apparent after understanding the disclosure of the present invention. In addition, descriptions of features known in the art may be omitted for greater clarity and conciseness.
[0024] The features described herein may be implemented in different forms and should not be construed as limited to the examples described herein. On the contrary, the examples described herein are provided only to illustrate some of the many possible ways of implementing the methods, apparatuses, and / or systems described herein, which will be apparent after understanding the disclosure of the present invention.
[0025] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more of them.
[0026] The terms used herein are for describing various examples only and are not intended to limit the disclosure. Unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. The terms "comprising," "including," and "having" specify the presence of the described features, quantities, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.
[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs after understanding the present invention. Unless explicitly defined as such herein, terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and should not be interpreted in an idealized or overly formal manner.
[0028] In addition, in the description of the examples, when a detailed description of a related structure or function that is considered well-known would cause an ambiguous interpretation of the present invention, such a detailed description will be omitted.
[0029] Figure 1 is a schematic diagram of a reset signal generation circuit according to an embodiment of the present invention.
[0030] Referring to Figure 1 , a reset signal generation circuit according to an embodiment of the present invention includes: a current reference unit 10 and a short pulse elimination unit 20.
[0031] Specifically, the current reference unit 10 is configured to receive the operating voltage VDD and generate a current reference signal according to the operating voltage VDD. The short pulse elimination unit 20 is configured to receive the initial reset signal RESX and the current reference signal, and eliminate the short pulse signal in the initial reset signal RESX according to the current reference signal to generate and output a reset signal RESET; wherein, the current reference signal is used to make the pulse width of the short pulse signal eliminated by the short pulse elimination unit 20 remain unchanged with temperature. In one example, the pulse width of the short pulse signal is less than or equal to 5 μs.
[0032] Figure 2 It is a block diagram of a current reference unit according to an embodiment of the present invention.
[0033] Refer to Figure 2 According to an embodiment of the present invention, the current reference unit 10 includes: an initial current reference signal generation module 11 configured to generate an initial current reference signal according to the operating voltage VDD; a first proportional current source module 12 configured to amplify the current of the initial current reference signal to generate a first amplified current signal; and a second proportional current source module 13 configured to amplify the current of the first amplified current signal again to generate the current reference signal.
[0034] Figure 3 It is a block diagram of a short pulse elimination unit according to an embodiment of the present invention.
[0035] Refer to Figure 3 According to an embodiment of the present invention, the short pulse elimination unit 20 includes: a delay module 21 configured to receive the initial reset signal RESX and the current reference signal, and delay the initial reset signal RESX according to the current reference signal to generate a delayed reset signal as a trigger threshold signal; and a Schmitt trigger module 22 configured to output the reset signal RESET according to the trigger threshold signal; wherein, the time for delaying the initial reset signal RESX is the pulse width of the short pulse signal.
[0036] Figure 4 It is a circuit structure diagram of a reset signal generation circuit according to an embodiment of the present invention.
[0037] Refer to Figure 4, the initial current reference signal generation module 11 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a first resistor R1, and a second resistor R2; wherein, the source of the first PMOS transistor MP1, the source of the second PMOS transistor MP2, the gate of the first NMOS transistor MN1, and one end of the first resistor R1 are all connected to the working voltage terminal (providing the working voltage VDD), the source of the first NMOS transistor MN1 is connected to the common ground terminal (providing the common ground voltage VSS), the drain of the first PMOS transistor MP1, the drain of the first NMOS transistor MN1, one end of the second resistor R2, and the gate of the second PMOS transistor MP2 are connected together, the gate of the first PMOS transistor MP1, the other end of the first resistor R1, and the other end of the second resistor R2 are connected together, and the drain of the second PMOS transistor MP2 is connected to the first proportional current source module 12.
[0038] The first proportional current source module 12 includes a second NMOS transistor MN2 and a third NMOS transistor MN3; wherein, the sources of the second NMOS transistor MN2 and the third NMOS transistor MN3 are connected to the common ground terminal VSS, the gate of the second NMOS transistor MN2, the gate of the third NMOS transistor MN3, and the drain of the second NMOS transistor MN2 are connected together and connected to the initial current reference signal generation module 11, and the drain of the third NMOS transistor MN3 is connected to the second proportional current source module 13.
[0039] The second proportional current source module 13 includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4; wherein, the sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the working voltage terminal (providing the working voltage VDD), the gate of the third PMOS transistor MP3, the gate of the fourth PMOS transistor MP4, and the drain of the third PMOS transistor MP3 are connected together and connected to the first proportional current source module 12, and the drain of the fourth PMOS transistor MP4 is connected to the short pulse elimination unit 20.
[0040] The delay module 21 includes: a fifth PMOS transistor MP5, a fourth NMOS transistor MN4, and a capacitor C1; wherein, the source of the fifth PMOS transistor MP5 is connected to the second proportional current source module, the source of the fourth NMOS transistor MN4 and one end of the capacitor C1 are both connected to the common ground terminal (providing the common ground voltage VSS), the gates of the fifth PMOS transistor MP5 and the fourth NMOS transistor MN4 are both used to receive the initial reset signal RESX, and the drains of the fifth PMOS transistor MP5 and the fourth NMOS transistor MN4 and the other end of the capacitor C1 are connected together and connected to the Schmitt trigger module 22.
[0041] The Schmitt trigger module 22 includes: a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7.
[0042] The working process of the reset signal generation circuit according to an embodiment of the present invention will be described below. Figure 5 It is a working timing diagram of the reset signal generation circuit according to an embodiment of the present invention.
[0043] Refer to together Figure 4 and Figure 5 When the initial reset signal RESX is at a low level, the fifth PMOS transistor MP5 conducts and the capacitor C1 is charged by the current I4. As a result, V1 starts to rise from the ground. After a certain period of time, when V1 reaches the threshold voltage of the Schmitt trigger module 22, a low-level reset signal RESET is output. Therefore, pulse widths less than the charging time will be eliminated. For example, if the threshold voltage is 0.77 volts and the capacitance is 1 pF, the current I4 should be less than 154 nA so that the circuit can eliminate a 5 μs pulse width.
[0044] In the first stage T1, the fourth PMOS transistor MP4 acts as a current source in the saturation region, and the fifth PMOS transistor MP5 acts as a small resistor in the linear region. The time constant in this first stage is dominated by I4. In the second stage T2, the fourth PMOS transistor MP4 enters the linear region, so the time constant in this second stage is affected by both the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5.
[0045] An embodiment of the present invention also provides a display driver chip, which includes the above-mentioned reset signal generation circuit.
[0046] In summary, the pulse width of the short pulse signal eliminated by the reset signal generation circuit provided by the embodiment of the present invention remains unchanged with temperature, and thus is not affected by the device temperature.
[0047] The specific embodiments of the present invention have been described in detail above. Although some embodiments have been shown and described, those skilled in the art should understand that without departing from the principles and spirit of the present invention defined by the claims and their equivalents, these embodiments can be modified and varied, and these modifications and variations should also be within the protection scope of the claims of the present invention.
Claims
1. A reset signal generation circuit, characterized in that, Comprising: A current reference unit, configured to receive a working voltage and generate a current reference signal according to the working voltage; A short pulse elimination unit, configured to receive an initial reset signal and the current reference signal, and eliminate a short pulse signal in the initial reset signal according to the current reference signal to generate and output a reset signal; Wherein, the current reference signal is used to make the pulse width of the short pulse signal eliminated by the short pulse elimination unit remain unchanged with temperature.
2. The reset signal generation circuit according to claim 1, wherein, The pulse width of the short pulse signal is less than or equal to 5 μs.
3. The reset signal generation circuit according to claim 1 or 2, characterized in that, The current reference unit includes: An initial current reference signal generation module, configured to generate an initial current reference signal according to the working voltage; A first proportional current source module, configured to perform current amplification on the initial current reference signal to generate a first amplified current signal; A second proportional current source module, configured to perform current amplification on the first amplified current signal again to generate the current reference signal.
4. The reset signal generating circuit according to claim 3, wherein The initial current reference signal generation module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a first resistor, and a second resistor; Wherein, the source of the first PMOS transistor, the source of the second PMOS transistor, the gate of the first NMOS transistor, and one end of the first resistor are all connected to the working voltage terminal, the source of the first NMOS transistor is connected to the common ground terminal, the drain of the first PMOS transistor, the drain of the first NMOS transistor, one end of the second resistor, and the gate of the second PMOS transistor are connected together, the gate of the first PMOS transistor, the other end of the first resistor, and the other end of the second resistor are connected together, and the drain of the second PMOS transistor is connected to the first proportional current source module.
5. The reset signal generation circuit according to claim 3, wherein, The first proportional current source module includes a second NMOS transistor and a third NMOS transistor; Wherein, the sources of the second NMOS transistor and the third NMOS transistor are connected to the common ground terminal, the gate of the second NMOS transistor, the gate of the third NMOS transistor, and the drain of the second NMOS transistor are connected together and connected to the initial current reference signal generation module, and the drain of the third NMOS transistor is connected to the second proportional current source module.
6. The reset signal generation circuit according to claim 3, wherein The second proportional current source module includes a third PMOS transistor and a fourth PMOS transistor; Wherein, the sources of the third PMOS transistor and the fourth PMOS transistor are connected to the working voltage terminal, the gate of the third PMOS transistor, the gate of the fourth PMOS transistor, and the drain of the third PMOS transistor are connected together and connected to the first proportional current source module, and the drain of the fourth PMOS transistor is connected to the short pulse elimination unit.
7. The reset signal generation circuit according to claim 1 or 2, characterized in that, The short pulse elimination unit includes: A delay module, configured to receive the initial reset signal and the current reference signal, and delay the initial reset signal according to the current reference signal to generate a delayed reset signal as a trigger threshold signal; A Schmitt trigger module, configured to output a reset signal according to the trigger threshold signal; Wherein, the time for delaying the initial reset signal is the pulse width of the short pulse signal.
8. The reset signal generating circuit according to claim 7, wherein The delay module includes a fifth PMOS transistor, a fourth NMOS transistor, and a capacitor; Among them, the source of the fifth PMOS transistor is connected to the second proportional current source module, the sources of the fourth NMOS transistor and one end of the capacitor are both connected to the common ground terminal, the gates of the fifth PMOS transistor and the fourth NMOS transistor are both used to receive the initial reset signal, and the drains of the fifth PMOS transistor and the fourth NMOS transistor and the other end of the capacitor are connected together and connected to the Schmitt trigger module.
9. The reset signal generating circuit according to claim 7, wherein The Schmitt trigger module includes: a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor.
10. A display driver chip, characterized in that, A reset signal generation circuit according to any one of claims 1 to 9 is included.