Display panel, driving controller and pixel circuit driving method

Abstract

The invention discloses a display panel, a driving controller and a pixel circuit driving method. The pixel circuit driving method includes: receiving an image signal through a control circuit, the image signal including a plurality of pixel values; obtaining a plurality of first voltage data of the plurality of pixel values corresponding to the first original frame by using a first lookup table; generating a plurality of first voltage combinations according to the plurality of first voltage data using a second lookup table, each of the plurality of first voltage combinations including a plurality of update voltages, and the plurality of first voltage combinations corresponding to a plurality of first update frames; generating, by a plurality of power generation circuits, the plurality of update voltages to a plurality of drive multiplexing circuits according to each of the plurality of first voltage combinations; and providing the plurality of update voltages as a plurality of driving voltages to a plurality of pixel circuits through the plurality of driving multiplexing circuits. Accordingly, the number of driving voltages required in the same update frame will be reduced.

Description

Technical Field

[0001] The present disclosure relates to the control and driving of pixel circuits, and particularly to a display panel, a driving controller, and a pixel circuit driving method. Background Art

[0002] In today's market of various consumer electronic products, "reflective display devices" are widely used to make display screens, such as electronic paper display devices. Reflective display devices mainly use incident light to irradiate a display medium layer to achieve the purpose of display, so power can be saved. However, in order to balance the display ability and production cost of reflective display devices, there is still much room for improvement in the internal circuit architecture and signal processing method of reflective display devices. Summary of the Invention

[0003] The present disclosure relates to a pixel circuit driving method, including: receiving an image signal through a control circuit, where the image signal includes a plurality of pixel values; obtaining a plurality of first voltage data corresponding to a first original frame for the plurality of pixel values by using a first look-up table; generating a plurality of first voltage combinations according to the plurality of first voltage data by using a second look-up table, where each of the plurality of first voltage combinations includes a plurality of update voltages, and the plurality of first voltage combinations correspond to a plurality of first update frames; generating the plurality of update voltages to a plurality of driving multiplexing circuits according to each of the plurality of first voltage combinations through a plurality of power generation circuits; and providing the plurality of update voltages as a plurality of driving voltages to a plurality of pixel circuits through the plurality of driving multiplexing circuits.

[0004] In one embodiment, the method of generating the plurality of first voltage combinations according to the plurality of first voltage data by using the second look-up table includes: using a part of the plurality of first voltage data as the plurality of update voltages corresponding to one of the plurality of first update frames, where the number of the part of the plurality of first voltage data is equal to the number of the plurality of power generation circuits.

[0005] In one embodiment, one of the plurality of update voltages is a reference voltage value of the plurality of pixel circuits.

[0006] In one embodiment, the plurality of update voltages of each of the plurality of first voltage combinations all include a reference voltage value.

[0007] In one embodiment, a method of obtaining the plurality of first voltage data corresponding to the plurality of pixel values for a first original frame by using a first look-up table includes: obtaining a plurality of original coding sequences corresponding to the plurality of pixel values, wherein each of the plurality of original coding sequences includes a plurality of voltage codings, the plurality of voltage codings sequentially corresponding to a plurality of original frames, and the plurality of original frames includes the first original frame; and using a part of the plurality of voltage codings corresponding to the first original frame as the plurality of first voltage data.

[0008] In one embodiment, a method of generating the plurality of first voltage combinations according to the plurality of first voltage data by using a second look-up table includes: using the second look-up table to generate a plurality of voltage combinations corresponding to a plurality of updated frames according to the plurality of original coding sequences, wherein the plurality of voltage combinations includes the plurality of first voltage combinations, and the plurality of updated frames includes the plurality of first updated frames.

[0009] In one embodiment, the pixel circuit driving method further includes: converting each of the plurality of original coding sequences into a plurality of updated coding sequences according to the plurality of voltage combinations, wherein the plurality of updated coding sequences are formed by the plurality of voltage combinations and are used to cause the plurality of power generation circuits to generate the plurality of updated voltages.

[0010] In one embodiment, a method of using the plurality of updated voltages as the plurality of driving voltages to be provided to the plurality of pixel circuits includes: receiving the plurality of updated voltages at the plurality of driving multiplexing circuits during the plurality of updated frames, and selectively outputting one of the plurality of updated voltages to a corresponding one of the plurality of pixel circuits.

[0011] In one embodiment, the method of using the plurality of updated voltages as the plurality of driving voltages to be provided to the plurality of pixel circuits further includes: sequentially generating a plurality of timing selection signals according to the plurality of updated coding sequences at the plurality of updated frames by a timing circuit in a control circuit, so as to cause the plurality of driving multiplexing circuits to selectively output one of the plurality of updated voltages.

[0012] The present disclosure also relates to a driving controller, including a control circuit, a memory, a power generation circuit, and a driving multiplexing circuit. The control circuit is configured to receive an image signal, where the image signal includes a plurality of pixel values. The memory is coupled to the control circuit and stores a first look-up table and a second look-up table. The first look-up table records the correspondence between the plurality of pixel values and a plurality of voltage data. The control circuit is configured to obtain, by using the first look-up table, a plurality of first voltage data corresponding to the plurality of pixel values for a first original frame. The control circuit is further configured to generate, by using the second look-up table, a plurality of first voltage combinations according to the plurality of first voltage data, each of the plurality of first voltage combinations including a plurality of updated voltages, and the plurality of first voltage combinations corresponding to a plurality of first updated frames. The power generation circuit is coupled to the control circuit and is configured to generate the plurality of updated voltages according to each of the plurality of first voltage combinations. The driving multiplexing circuit is coupled to the plurality of power generation circuits and a plurality of pixel circuits, and is configured to provide the plurality of updated voltages generated by the plurality of power generation circuits as a plurality of driving voltages to the plurality of pixel circuits.

[0013] The present disclosure also relates to a display panel, including a plurality of pixel circuits and a driving controller. The driving controller is coupled to the plurality of pixel circuits and is configured to receive an image signal. The image signal includes a plurality of pixel values, and the plurality of pixel values correspond to a plurality of voltage data in at least one original frame. The driving controller is configured to convert the plurality of voltage data into a plurality of voltage combinations in a plurality of updated frames, and is configured to generate a plurality of driving voltages according to the plurality of voltage combinations to drive the plurality of pixel circuits.

[0014] In one embodiment, the driving controller is configured to obtain a plurality of original coding sequences corresponding to the plurality of pixel values, where the plurality of original coding sequences are formed by the plurality of voltage data in a plurality of original frames. The driving controller is further configured to convert each of the plurality of original coding sequences into a plurality of updated coding sequences in the plurality of updated frames.

[0015] The present disclosure also relates to a display panel, including a plurality of pixel circuits and a driving controller. The driving controller is coupled to the plurality of pixel circuits and is configured to receive an image signal. The image signal includes a plurality of pixel values. The driving controller generates a plurality of driving voltages in a plurality of updated frames to drive the plurality of pixel circuits. In the same one of the plurality of updated frames, the plurality of driving voltages provided by the driving controller include a reference voltage value and multiple sets of symmetric voltages. Each of the plurality of symmetric voltages includes two voltages with the same value but opposite signs.

[0016] Accordingly, by dividing the original frame into a plurality of updated frames and converting the voltage data into combined voltages corresponding to each updated frame, the number of driving voltages required in the same updated frame can be reduced, making the internal circuit of the driving controller more streamlined. Description of the Drawings

[0017] Figure 1 Schematic diagram of a driving controller and a display panel according to some embodiments of the present disclosure;

[0018] Figure 2 Signal waveform diagram for driving a pixel circuit according to an original frame;

[0019] Figures 3A - 3C Signal waveform diagram for driving a pixel circuit according to an updated frame;

[0020] Figure 4 Signal waveform diagram in a driving controller according to some embodiments of the present disclosure;

[0021] Figure 5 Schematic diagram of a pixel circuit according to some embodiments of the present disclosure;

[0022] Figure 6 Flowchart of steps of a method for driving a pixel circuit according to some embodiments of the present disclosure.

[0023]

Reference Signs

[0024] 100: Driving controller

[0025] 110: Control circuit

[0026] 111: Timing circuit

[0027] 112: Data multiplexing circuit

[0028] 113: Shift register circuit

[0029] 120: Memory

[0030] 130: Power generation circuit

[0031] 140: Driving multiplexing circuit

[0032] 150: Receiving circuit

[0033] 200: Display panel

[0034] P: Pixel circuit

[0035] SA1 - SAn: Driving selection signals

[0036] SB1 - SBn: Timing selection signals

[0037] SL1 - SLn: Transmission lines

[0038] GL: Control line

[0039] GD: Scan controller

[0040] Vcom: Reference voltage

[0041] V01 - V03: Driving voltage

[0042] Vd1 - Vdn: Update voltage

[0043] Vs1 - Vsn: Driving voltage

[0044] CX: Capacitor

[0045] TX: Transistor switch

[0046] TB1: First look - up table

[0047] TB2: Second look - up table

[0048] S601 - S605: Steps Detailed implementation manners

[0049] The following will disclose multiple implementation manners of the present invention with the accompanying drawings. For the sake of clear illustration, many practical details will be described together in the following narrative. However, it should be understood that these practical details are not used to limit the present invention. That is to say, in some implementation manners of the present invention, these practical details are not necessary. In addition, for the purpose of simplifying the drawings, some conventional structures and elements will be shown in a simple schematic manner in the drawings.

[0050] In this article, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" can also be used to indicate the mutual cooperation operation or interaction between two or more elements. In addition, although terms such as "first", "second",... are used in this article to describe different elements, these terms are only used to distinguish elements or operations described with the same technical terms. Unless the context clearly indicates, these terms do not specifically refer to or imply an order or sequence, nor are they used to limit the present invention.

[0051] Figure 1 Shown is a schematic diagram of a display panel 200 according to some embodiments of the present disclosure. The display panel 200 can be applied to a reflective display device and includes a plurality of pixel circuits P and a driving controller 100. The driving controller 100 is coupled to the pixel circuits P through a plurality of transmission lines SL1 - SLn (source line) and a control line GL (gate line). The driving controller 100 is used to receive an image signal and provide a driving voltage corresponding to the image signal to the pixel circuits P so that the display panel 200 presents a corresponding picture. Since those skilled in the art can understand the driving principle of the display panel 200, it will not be elaborated herein.

[0052] In one embodiment, the driving controller 100 is disposed in the display panel 200 and includes a control circuit 110, a memory 120, a plurality of power generation circuits 130, and a plurality of driving multiplexing circuits 140. The control circuit 110 can be a timing controller and is coupled to the receiving circuit 150 to receive an image signal. The image signal is used to record data of a static image or a dynamic image and includes a plurality of pixel values corresponding to the pixel circuits P (e.g., grayscale values, ranging from 0 to 255). For ease of explanation, the "image signal" described in the subsequent paragraphs is the image data used by the display panel 200 in an update period. The update period can be divided into one or more original frames. The image signal includes pixel values corresponding to the plurality of pixel circuits P, and each pixel value corresponds to voltage data (e.g., voltage values, or voltage encodings corresponding to voltage values) required in one or more original frames.

[0053] In one embodiment, the image signal can be sent from a device host (not shown in the figure, such as a computer, a mobile phone, or a network server, etc.) to the driving controller 100. In another embodiment, the image signal can be generated by a processor of a reflective display device (e.g., an e-paper reader) and transmitted to the receiving circuit 150.

[0054] The memory 120 is coupled to the control circuit 110. The memory 120 includes a first look-up table TB1 and a second look-up table TB2. The first look-up table TB1 is used to record the correspondence between each pixel value and a plurality of voltage data, where the "voltage data" can include voltage values or voltage encodings. After receiving the image signal, the control circuit 110 can obtain the voltage data corresponding to each pixel value according to the first look-up table TB1.

[0055] For example, the control circuit 110 converts the pixel value "150" into voltage encodings "010, 001, 000" (here, the combination of a plurality of voltage encodings is called an "original encoding sequence"). These voltage encodings correspond to a plurality of original frames in sequence. For example, "010, 001, 000" means that the pixel circuit P must be applied with three different levels of voltages, namely "3V, -3V, 0V", respectively, between three original frames. The voltage encoding is a code for identification, and its encoding rule can be adjusted according to requirements.

[0056] The second look-up table TB2 is used to record the conversion relationship between voltage data (e.g., voltage encodings, voltage values, or original encoding sequences) and a plurality of update encoding sequences. The update encoding sequence includes a plurality of converted voltage data and corresponds to a plurality of update frames.

[0057] For example, one of the voltage codes "010" in the foregoing original coding sequence "010, 001, 000" can be converted into three new voltage codes to present "000, 010, 000" (i.e., the updated coding sequence). The other two voltage codes of the foregoing original coding sequence can also be respectively converted into updated coding sequences. Each updated coding sequence will respectively correspond to an updated frame. Therefore, the control circuit 110 will convert each original coding sequence into a plurality of updated coding sequences, and each original frame will correspond to a plurality of converted updated frames. The detailed conversion method will be described in detail in the following paragraphs.

[0058] From another perspective, the process of the driving controller 100 converting "a plurality of original coding sequences corresponding to a plurality of pixel values into a plurality of updated coding sequences" can also be regarded as the driving controller 100 converting the voltage data corresponding to the plurality of pixel values into a plurality of voltage combinations corresponding to a plurality of updated frames. Each "voltage combination" refers to a plurality of voltages at different levels corresponding to the same updated frame (hereinafter referred to as "updated voltages"). In other words, the driving controller 100 takes a plurality of voltage codes corresponding to the same updated frame in the plurality of updated coding sequences as a group of voltage combinations to sequentially drive the pixel circuit P.

[0059] For example, after obtaining the image signal, the control circuit 110 generates a plurality of voltage combinations according to the voltage data (such as a plurality of original coding strings) of the first original frame. Each voltage combination includes a plurality of updated voltages and respectively corresponds to an updated frame.

[0060] The power generation circuit 130 is coupled to the control circuit 110 and is used to sequentially generate a plurality of updated voltages Vd1 to Vd3 (such as three) according to each voltage combination generated by the control circuit 110 to drive the pixel circuit P. In an embodiment, the number of power generation circuits 130 will be the same as "the number of voltage codes of the voltage combination (such as three)", but less than "the number of all voltage codes in the same original frame".

[0061] The driving multiplexing circuit 140 is coupled to the power generation circuit 130 and the pixel circuit P and is used to apply the updated voltages Vd1 to Vdn generated by the power generation circuit 130 as driving voltages Vs1 to Vsn to the pixel circuit P. In an embodiment, each driving multiplexing circuit 140 will receive the updated voltages Vd1 to Vdn generated by the power generation circuit 130 at a plurality of updated frames and selectively use one of the updated voltages as the driving voltage to output to the corresponding pixel circuit P.

[0062] Since the pixel values of each pixel circuit P are not exactly the same and the required voltages are also different, if the traditional method is used to complete the update in the original frame, the driving controller 100 needs to generate driving voltages of different levels through a large number of power generation circuits 130. However, this method will require a large number of power generation circuits 130 to be configured, making it difficult to control the cost and volume of the driving controller 100.

[0063] The present disclosure divides "one original frame" into "multiple update frames". The driving controller 100 only needs to generate a smaller number of voltages in each update frame. In this way, it is not necessary to configure a large number of power generation circuits 130. For example, in the traditional method, if the video signal indicates that "in one original frame, 7 different driving voltages are required", then 7 power generation circuits need to be configured. In an embodiment of the present disclosure, the original frame is divided into multiple (e.g., three) update frames. Therefore, only three update voltages need to be generated in each update frame, and through three power generation circuits 130, the 7 pixel values corresponding to different voltages can be sequentially updated in multiple update frames.

[0064] In other words, each update frame corresponds to a respective voltage combination, and each voltage combination includes multiple (e.g., 3) update voltages. The update voltages within each voltage combination are not exactly the same, but can be partially the same (for example, all include the reference voltage "0V"). Therefore, the number of update voltages will be the same as the number of power generation circuits 130, but will be less than the number of driving voltages corresponding to all pixel values in the same original frame (e.g., 7).

[0065] In addition, in each update frame, the control circuit 110 is further configured to sequentially output a plurality of driving selection signals SA1~SAn to the plurality of driving multiplexing circuits according to the update coding sequences corresponding to the respective pixel values (pixel circuits P), so that each driving multiplexing circuit 140 selectively uses a corresponding one of the update voltages as the driving voltage to provide to the pixel circuit P according to the received driving selection signals SA1~SAn.

[0066] For ease of understanding, the following examples illustrate two methods of driving the pixel circuit P according to the traditional "original frame" and the "update frame" of the present invention as follows.

[0067] Figure 2 The signal diagram for driving the pixel circuit P according to the "original frame" is shown. In this embodiment, the second look-up table TB2 shown does not need to be used. For example, the video signal indicates that the pixel values of three pixel circuits P in the same column are to be updated to "120, 85, 60". Taking the pixel value "120" as an example, the display panel will be based on Figure 1 The second look-up table TB2 shown. For example, the video signal indicates that the pixel values of three pixel circuits P in the same column are to be updated to "120, 85, 60". Taking the pixel value "120" as an example, the display panel will be based on Figure 1For the first look-up table TB1 shown, find the corresponding multiple voltage codes "010, 001, 000" (taking three as an example here, but not limited to this). These voltage codes corresponding to the same pixel value are a set of "original code sequences" and can be recognized as multiple voltage values "3V, -3V, 0V". In other words, the display panel needs to sequentially provide voltages at different levels through the power generation circuit in three original frames F01, F02, and F03 (such as Figure 2 the signal V01 shown: "3V, -3V, 0V"). These voltages will be provided as the driving voltage V01 to the corresponding pixel circuit P so that the pixel circuit P can present the pixel value "120".

[0068] Both "voltage code" or "voltage value" can be used as the aforementioned voltage data. Although in some embodiments, the driving controller 100 internally transmits signals in the form of voltage codes, in other embodiments, the driving controller 100 can also directly transmit signals in the form of voltage values.

[0069] Similarly, taking the pixel value "85" as an example, the display panel, according to Figure 1 the first look-up table TB1 shown, finds the corresponding multiple voltage codes "001, 101, 000" (original code sequence), and can be recognized as multiple voltage values "2V, -2V, 0V". In other words, the display panel needs to sequentially provide voltages at different levels through a specific power generation circuit in three original frames F01, F02, and F03 (such as Figure 2 the driving voltage V02 shown: "2V, -2V, 0V") to enable the pixel circuit P to present the pixel value "85".

[0070] Similarly, taking the pixel value "60" as an example, the display panel, according to Figure 1 the first look-up table TB1 shown, finds the corresponding multiple voltage codes "011, 100, 000" (original code sequence), and can be recognized as multiple voltage values "1V, -1V, 0V". In other words, the display panel needs to sequentially provide voltages at different levels through a specific power generation circuit in three original frames F01, F02, and F03 (such as Figure 2 the driving voltage V03 shown: "1V, -1V, 0V") to enable the pixel circuit P to present the pixel value "60".

[0071] As described in the foregoing embodiments, in order to update the pixel values of a plurality of pixel circuits P simultaneously, in the first original frame F01, the driving controller 100 must simultaneously provide driving voltages of multiple different levels, namely "3V, 2V, 1V". Since in actual use, usually hundreds or thousands of pixel circuits P need to be updated in each original frame, therefore, the more driving voltages are required in each original frame. In this way, a large number of power generation circuits 130 will be needed, making the cost of the display panel 200 too high.

[0072] Figures 3A - 3C The following shows a signal diagram for driving the pixel circuit P according to the "update frame". In this embodiment, the following Figure 1 shown second look-up table TB2 will be used. After the control circuit 110 obtains the "voltage data of each of the original frames F01 to F03" corresponding to the pixel value by using the first look-up table TB1, the control circuit 110 will further use the second look-up table TB2 to generate a corresponding set of voltage combinations according to the multiple voltage data required in each original frame. This set of voltage combinations includes multiple update voltages and corresponds to multiple update frames.

[0073] In another perspective, the control circuit 110 uses the second look-up table TB2 to convert each original coding sequence into multiple update coding sequences in multiple update frames, so as to control the power generation circuit 130 to sequentially generate update voltages according to each update frame. In other words, the original coding sequence of the same original frame will be converted into multiple update coding sequences in multiple update frames.

[0074] For example, as Figure 3A shown, the original coding sequence "010, 001, 000" indicates that the power generation circuit 130 needs to sequentially generate three voltage values "3V, -3V, 0V" in three original frames F01 to F03. The control circuit 110 uses the second look-up table TB2 to convert the voltage coding in each original coding sequence into an update coding string. For example, the voltage coding "010" (corresponding to 3V) in the original frame F01 is converted into multiple update coding sequences "000, 010, 000" in multiple update frames F1A to F1C. Each driving coding in this update coding sequence is used to represent different update voltages, such as Figure 3A shown "0V, 3V, 0V".

[0075] Similarly, the voltage code "001" (corresponding to -3V) in the original frame F02 will be converted into a plurality of updated coding sequences "000, 001, 000" corresponding to the plurality of updated frames F2A to F2C, that is, the voltage values "0V, -3V, 0V". The voltage code "000" (corresponding to 0V) in the original frame F03 will be converted into a plurality of updated coding sequences "000, 000, 000" corresponding to the plurality of updated frames F3A to F3C, that is, the updated voltages "0V, 0V, 0V".

[0076] Similarly, as shown in FIGS. 3B and 3C, other original coding sequences (corresponding to different pixel circuits P) are also converted into a plurality of updated coding sequences corresponding to a plurality of updated frames in the same manner.

[0077] For ease of understanding, the driving voltages required for the two methods of "driving method according to the original frame" and "driving method according to the updated frame" are listed in a table as follows.

[0078] The following is the correspondence between pixel values and voltage data in the driving method according to the "original frame". In one embodiment, the image signal is used to indicate the pixel values of a plurality of pixel circuits P to be updated / displayed (only the first four pixel values are shown in the table).

[0079] Original frame F01 F02 F03 Pixel value 120 3V -3V 0V Pixel value 85 2V -2V 0V Pixel value 60 1V -1V 0V Pixel value 20 0V 0V 1V

[0080] The following is the correspondence between pixel values and voltage data in the driving method according to the "updated frame". In one embodiment, the image signal is used to indicate the pixel values of a plurality of pixel circuits P to be updated / displayed (only the first four pixel values are shown in the table).

[0081] Updated frame F1A F1B F1C F2A F2B F2C … Pixel value 120 3V 0V 0V -3V 0V 0V … Pixel value 85 0V 2V 0V 0V -2V 0V … Pixel value 60 0V 0V 1V 0V 0V -1V … Pixel value 20 0V 0V 0V 0V 0V 0V …

[0082] Figure 4The figure shows a signal diagram for driving the pixel circuit P according to an "update frame". Refer to FIGS. 1 and 4 and the above table. The control circuit 110 in the driving controller 100 converts the original coding sequence into a plurality of update coding sequences through the first look-up table TB1 and the second look-up table TB2. For example, the original coding sequence "3V, -3V, 0V" corresponding to the pixel value "120" is converted into three update coding sequences, namely, the first update coding sequence "3V, 0V, 0V" corresponding to the first update frames F1A to F1C, the second update coding sequence "-3V, 0V, 0V" corresponding to the second update frame, and the third update coding sequence "0V, 0V, 0V" corresponding to the third update frame (for ease of understanding, voltage values are shown here, but in fact, binary coding can be used to represent). The update voltages corresponding to each update frame in the above table are the "voltage combinations". For example, the voltage combination corresponding to the update frame F1A is "3V, 0V", which includes two update voltages (driving voltages).

[0083] As described above, the second look-up table TB2 may include the conversion relationship between voltage data (such as voltage coding, voltage value, or original coding sequence) and a plurality of update coding sequences. In one embodiment, the "conversion relationship" may be a conversion formula or a conversion rule. For example, when converting the voltage value (or voltage coding) corresponding to the same original frame into the voltage values corresponding to the update frames F1A to F1C, except for setting one of the update frames to the original voltage value (such as the update frame F1A corresponding to 3V), the remaining update frames use the reference voltage value (such as the update frames F1B and F1C corresponding to 0V). The number of voltage values used in the same update frame must be equal to or less than the "number of power generation circuits 130 in the driving controller 100". In addition, the conversion rule may also include the order of providing voltage values in the update coding sequence or voltage combination. For example, among the plurality of update frames F1A to F1C, the required voltage values are arranged from high to low (such as generating 3V at the update frame F1A, generating 2V at the update frame F1B, and generating 1V at the update frame F1C). The conversion relationship or conversion rule recorded in the second look-up table TB2 can be adjusted according to requirements, and is not limited to the foregoing embodiments.

[0084] The present disclosure transforms one original frame into a plurality of update frames. Accordingly, the number of update voltages Vd1 to Vdn (or driving voltages Vs1 to Vsn) required in the same update frame can be reduced. Refer to Figure 2 and Figure 4 , or refer to the above table. In the original frame F01, the driving controller 100 originally needed to simultaneously provide three driving voltages "3V, 2V, 1V", that is, three power generation circuits 130 were required. In contrast, in each of the update frames F1A to F1C, the driving controller 100 only needs to provide two update voltages. For example, in the update frame F1A, it is "3V, 0V". Compare Figure 2and Figure 4 It can be seen that the number of levels of the driving voltage required in each of the update frames F1A to F1C (two) is less than the number of levels of the driving voltages "3V, 2V, 1V" required in each original frame F01 (three).

[0085] In the foregoing embodiment, the driving method of the traditional "original frame" needs to generate three driving voltages simultaneously, while the driving method of the "update frame" needs to generate two driving voltages simultaneously. However, the foregoing embodiment is only a simplified example. In fact, the driving method of the traditional "original frame" may need to provide 5 to 10 or even more driving voltages in the same original frame, while the driving method of the "update frame" may only need to provide three driving voltages in the same update frame.

[0086] In one embodiment, in the same update frame, the driving voltages Vs1 to Vsn provided by the driving controller 100 include a reference voltage value and multiple sets of symmetric voltages. Each of the "symmetric voltages" includes two voltages with the same value but opposite polarities. For example, the update frame F1A includes symmetric voltages of "3V, 0V, -3V" ( Figure 4 only the driving voltages required for the first three pixel circuits P are shown). Similarly, the update frame F1B may include symmetric voltages of "2V, 0V, -2V", and the update frame F1C may include symmetric voltages of "1V, 0V, -1V".

[0087] In one embodiment, the control circuit 110 uses a part of the "voltage data corresponding to the same original frame" as the update voltages Vd1 to Vdn to generate the driving voltages Vs1 to Vsn, and the number of this part of the voltage data is equal to the number of power generation circuits 130 in the driving controller 100. As shown in the foregoing table, the control circuit 110 selects "3V, 0V" from the voltage data "3V, 2V, 1V, 0V..." of the original frame F01 as the update voltage corresponding to the update frame F1A. Similarly, the control circuit 110 also selects "2V, 0V" from the voltage data "3V, 2V, 1V, 0V..." as the update voltage corresponding to the update frame F1B.

[0088] Continuing from the above, in an update frame, the voltage combination may not include all the voltages required by the pixel circuits P. Therefore, the driving controller 100 uses the reference voltage of the pixel circuit P as one of the update voltages. Figure 5The figure shows a schematic diagram of a pixel circuit P according to some embodiments of the present disclosure. The pixel circuit P includes a transistor switch TX and at least one capacitor CX. When the scan controller GD in the driving controller 100 transmits a scan voltage to the control line GL to turn on the control terminal of the transistor switch TX, the transistor switch TX will receive the driving voltage provided by the driving controller 100 through the transmission line SLn. At this time, the driving voltage will charge the capacitor CX. The common voltage connected to one end of the capacitor CX is the reference voltage Vcom.

[0089] For example, in the original frame F01, the driving voltage required for the pixel circuit P corresponding to the pixel value "85" is 2V. However, after the original frame F01 is converted into multiple updated frames F1A to F1C, the driving controller 100 does not provide an updated voltage of 2V in the updated frame F1A. Therefore, at this time, the driving controller 100 can provide the reference voltage (i.e., 0V) to the pixel circuit P corresponding to the pixel value "85". In other words, each voltage combination may include the reference voltage "0V".

[0090] In one embodiment, the number of updated voltages in each updated frame (e.g., 2) is equal to the number of power generation circuits 130, but this number is less than the number of driving voltages required in the same original frame (e.g., the four driving voltages "3V, 2V, 1V, 0V" corresponding to the original frame F01 in the previous table).

[0091] Please refer to Figure 1 As shown, although each driving multiplexing circuit 140 receives all the updated voltages Vd1 to Vdn provided by the power generation circuit 130, each driving multiplexing circuit 140 will only selectively use one of the updated voltages Vd1 to Vdn as the driving voltage Vs1 to Vsn according to the corresponding driving selection signal. The control circuit 110 generates the driving selection signals SA1 to SAn corresponding to each updated frame according to the voltages required by the pixel circuit P in different updated frames.

[0092] In some embodiments, the control circuit 110 further includes a timing circuit 111, a data multiplexing circuit 112, and a shift register circuit 113. The timing circuit 111 is coupled to the memory 120 and the receiving circuit 150 to obtain the original coding sequence, the updated coding sequence corresponding to the pixel value, and the voltage combination corresponding to each updated frame according to the first look-up table TB1 and the second look-up table TB2. The timing circuit 111 is further configured to sequentially generate a plurality of timing selection signals SB1 to SBn at the updated frames F1A to F3C according to the updated coding sequence. The timing selection signals SB1 to SBn are used to enable the driving multiplexing circuit 140 to selectively output any one of the driving voltages Vs1 to Vs3 to the corresponding pixel circuit P.

[0093] The data multiplexing circuit 112 is coupled to the timing circuit 111. When updating frames F1A to F3C, the selection terminal of the data multiplexing circuit 112 is used to sequentially receive the timing selection signals SB1 to SBn, and the input terminal receives the voltage combination corresponding to the current update frame (or receives all voltage values / voltage encodings corresponding to the original frame). The data multiplexing circuit 112 outputs a plurality of drive selection signals SA1 to SAn according to the timing selection signals SB1 to SBn. Each of the drive selection signals SA1 to SAn corresponds to each drive multiplexing circuit 140. As Figure 1 shown, the drive selection signal SA1 corresponds to the transmission line SL1 (i.e., the pixel circuit P in the first row), and the drive selection signal SAn corresponds to the transmission line SLn. Since those skilled in the art can understand the method of using a multiplexer to select output signals, it will not be described in detail here.

[0094] The shift register circuit 113 (such as: shift register) is coupled to the data multiplexing circuit 112 and the drive multiplexing circuit 140, and is used to respectively distribute the plurality of drive selection signals SA1 to SAn to the corresponding drive multiplexing circuits 140. The drive multiplexing circuit 140 will sequentially receive all the update voltages generated by the power generation circuit 130 during the update frames F1A to F1C, and according to the drive selection signals SA1 to SAn, use one of the update voltages as the drive voltage to output the corresponding drive voltage to the corresponding pixel circuit P.

[0095] For example, in the first update frame F1A, the update voltage required by the pixel circuit P is 3V, and the update voltages provided by the power generation circuit 130 are 3V and 0V. The drive multiplexing circuit 140 will receive all the update voltages (3V, 0V) at the same time, but will only output "3V" corresponding to the update coding sequence according to the drive selection signals SA1 to SAn.

[0096] Figure 6 Shown is a schematic diagram of a pixel circuit driving method according to some embodiments of the present disclosure. In step S601, the timing circuit 111 of the control circuit 110 receives an image signal from the receiving circuit 150. In one embodiment, the image signal includes a plurality of pixel values corresponding to a plurality of pixel circuits P.

[0097] In step S602, the timing circuit 111 of the control circuit 110 uses the first look-up table TB1 to obtain a plurality of voltage data corresponding to the pixel values in each original frame, where each original frame corresponds to a plurality of voltage data. The first look-up table TB1 records the correspondence between each pixel value and the voltage data. As shown in the previous table, the voltage data corresponding to the pixel value 120 in the original frame F01 can be the voltage encoding "010" or the voltage value "3V".

[0098] In step S603, after obtaining the voltage data, the timing circuit 111 of the control circuit 110 further uses the second look-up table TB2 to generate, according to the voltage data, a plurality of voltage combinations corresponding to a plurality of update frames, and a plurality of update coding sequences corresponding to a plurality of update frames according to each original coding sequence. Each of the voltage combinations includes a plurality of update voltages and corresponds to a plurality of update frames.

[0099] "Generating voltage combinations" and "generating update coding sequences" are two sides of the same coin. In one embodiment, the timing circuit 111 first generates, according to the original coding sequence, voltage combinations corresponding to a plurality of update frames, and then forms an update coding sequence according to the update voltages corresponding to the same pixel value in the plurality of voltage combinations. In another embodiment, the timing circuit 111 may also first convert each original coding sequence into a plurality of update coding sequences respectively, and then use the update voltages corresponding to the same update frame in the update coding sequences as the voltage combinations.

[0100] Specifically, in the foregoing step 602, the timing circuit 111 first obtains a plurality of original coding sequences corresponding to a plurality of pixel values, and then uses a part of the original coding sequences (i.e., the voltage coding corresponding to the same original frame) as the voltage data to generate voltage combinations in the subsequent step S603. As shown in the foregoing table, the timing circuit 111 uses a plurality of voltage codings or voltage values corresponding to the original frame F01 (such as "3V, 2V, 1V, 0V") as the voltage data to generate voltage combinations corresponding to the update frames F1A to F1C.

[0101] Continuing from the above, the timing circuit 111 uses a part of the voltage data as the update voltages, and the number of this part is equal to the number of power generation circuits 130 in the drive controller 100. As shown in the foregoing table, among the plurality of drive voltages corresponding to the original frame F01, the drive controller 100 uses "3V, 0V" as the update voltages corresponding to the update frame F1A, and the update voltages include the reference voltage of the pixel circuit P. The reference voltage is not limited to "0V", and according to product requirements, it can also be other voltage levels, such as 1V or 2V. In addition, in one embodiment, all voltage combinations corresponding to all update frames F1A to F3C will include the reference voltage value.

[0102] In step S604, in the update frame, the timing circuit 111 of the control circuit 110 generates a plurality of timing selection signals SB1 to SBn to the selection terminals of the data multiplexing circuit 112 according to the update coding sequence, and provides the voltage combination corresponding to the current update frame (or all voltage values / voltage encodings corresponding to the original frame) to the input terminal of the data multiplexing circuit 112, so that the data multiplexing circuit 112 generates drive selection signals SA1 to SAn. The drive selection signals SA1 to SAn correspond to the respective drive multiplexing circuits 140, and are used to instruct each drive multiplexing circuit 140 to select the required drive voltage according to each update coding sequence in each update frame.

[0103] In step S605, the data multiplexing circuit 112 transmits the drive selection signals SA1 to SAn to the corresponding drive multiplexing circuits 140 through the shift register circuit 113. The power generation circuit 130 generates an update voltage according to each voltage combination and provides it to the drive multiplexing circuit 140. The drive multiplexing circuit 140 will selectively use one of the received update voltages as the drive voltage according to the drive selection signals SA1 to SAn and output it to the corresponding pixel circuit P. At the same time, the drive controller 100 transmits a scan signal to the control line GL through the scan controller GD to turn on the corresponding pixel circuit. Accordingly, the pixel circuit P can sequentially receive the drive voltage in the update frame and generate a pixel value that meets the expectations of the image signal.

[0104] The various elements, method steps, or technical features in the foregoing embodiments can be combined with each other, and are not limited by the order of the text description or the order of the figures presented in this disclosure.

[0105] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope defined by the appended claims.

Claims

1. A pixel circuit driving method, characterized in that, Comprising: Receiving an image signal through a control circuit, wherein the image signal includes a plurality of pixel values; Obtaining a plurality of first voltage data corresponding to a first original frame from the plurality of pixel values by using a first look-up table; Generating a plurality of first voltage combinations according to the plurality of first voltage data by using a second look-up table, wherein each of the plurality of first voltage combinations includes a plurality of updated voltages, and the plurality of first voltage combinations correspond to a plurality of first updated frames; Generating the plurality of updated voltages to a plurality of driving multiplexing circuits according to each of the plurality of first voltage combinations through a plurality of power generation circuits; And Providing the plurality of updated voltages as a plurality of driving voltages to a plurality of pixel circuits through the plurality of driving multiplexing circuits.

2. The pixel circuit driving method according to claim 1, wherein The method of generating the plurality of first voltage combinations according to the plurality of first voltage data by using the second look-up table includes: Taking a part of the plurality of first voltage data as the plurality of updated voltages corresponding to one of the plurality of first updated frames, wherein the number of the part of the plurality of first voltage data is equal to the number of the plurality of power generation circuits.

3. The pixel circuit driving method according to claim 2, wherein One of the plurality of updated voltages is a reference voltage value of the plurality of pixel circuits.

4. The pixel circuit driving method according to claim 3, wherein Each of the plurality of updated voltages of each of the plurality of first voltage combinations includes the reference voltage value.

5. The pixel circuit driving method according to claim 1, wherein The method of obtaining the plurality of first voltage data corresponding to the first original frame from the plurality of pixel values by using the first look-up table includes: Obtaining a plurality of original coding sequences corresponding to the plurality of pixel values, wherein each of the plurality of original coding sequences includes a plurality of voltage codings, the plurality of voltage codings sequentially correspond to a plurality of original frames, and the plurality of original frames include the first original frame; And Taking a part of the plurality of voltage codings corresponding to the first original frame as the plurality of first voltage data.

6. The pixel circuit driving method according to claim 5, characterized in that, The method of generating the plurality of first voltage combinations according to the plurality of first voltage data by using the second look-up table includes: Generating a plurality of voltage combinations corresponding to a plurality of updated frames according to the plurality of original coding sequences by using the second look-up table, wherein the plurality of voltage combinations include the plurality of first voltage combinations, and the plurality of updated frames include the plurality of first updated frames.

7. The pixel circuit driving method according to claim 6, characterized in that, Further comprising: Converting each of the plurality of original coding sequences into a plurality of updated coding sequences according to the plurality of voltage combinations, wherein the plurality of updated coding sequences are formed by the plurality of voltage combinations and are used to enable the plurality of power generation circuits to generate the plurality of updated voltages.

8. The pixel circuit driving method according to claim 7, wherein The method of providing the plurality of updated voltages as the plurality of driving voltages to the plurality of pixel circuits includes: Receiving the plurality of updated voltages at the plurality of updated frames through the plurality of driving multiplexing circuits, and selectively outputting one of the plurality of updated voltages to a corresponding one of the plurality of pixel circuits.

9. The pixel circuit driving method according to claim 8, wherein, The method of providing the plurality of updated voltages as the plurality of driving voltages to the plurality of pixel circuits further includes: Through a timing circuit in the control circuit, according to the multiple update coding sequences, multiple timing selection signals are sequentially generated at the multiple update frames, so that one of the multiple driving multiplexing circuits selectively outputs one of the multiple update voltages.

10. A drive controller, characterized in that, Comprising: A control circuit for receiving an image signal, wherein the image signal includes multiple pixel values; A memory coupled to the control circuit and storing a first look-up table and a second look-up table, wherein the first look-up table records the corresponding relationship between the multiple pixel values and multiple voltage data, and the control circuit is used to obtain multiple first voltage data corresponding to the multiple pixel values for a first original frame by using the first look-up table; Wherein the control circuit is further used to generate multiple first voltage combinations according to the multiple first voltage data by using the second look-up table, each of the multiple first voltage combinations includes multiple update voltages, and the multiple first voltage combinations correspond to multiple first update frames; Multiple power generation circuits coupled to the control circuit for generating the multiple update voltages according to each of the multiple first voltage combinations; And Multiple driving multiplexing circuits coupled to the multiple power generation circuits and multiple pixel circuits for using the multiple update voltages generated by the multiple power generation circuits as multiple driving voltages to provide to the multiple pixel circuits.

11. A display panel, characterized in that, Comprising: Multiple pixel circuits; and A driving controller coupled to the multiple pixel circuits and used to receive an image signal, wherein the image signal includes multiple pixel values, and the multiple pixel values correspond to multiple voltage data in at least one original frame; Wherein, the driving controller is used to convert the multiple voltage data into multiple voltage combinations in multiple update frames, and is used to generate multiple driving voltages according to the multiple voltage combinations to drive the multiple pixel circuits.

12. The display panel according to claim 11, wherein The driving controller is used to obtain multiple original coding sequences corresponding to the multiple pixel values, and the multiple original coding sequences are formed by the multiple voltage data in multiple original frames; and Wherein the driving controller is further used to convert each of the multiple original coding sequences into multiple update coding sequences in the multiple update frames.

13. A display panel, characterized in that, Comprising: Multiple pixel circuits; and A driving controller coupled to the multiple pixel circuits and used to receive an image signal, wherein The image signal includes multiple pixel values; Wherein, the driving controller generates multiple driving voltages in multiple update frames to drive the multiple pixel circuits; Wherein in the same one of the multiple update frames, the multiple driving voltages provided by the driving controller include a reference voltage value and multiple sets of symmetric voltages, and each of the multiple symmetric voltages includes two voltages with the same value but opposite signs.

Images