Gate driver, display device, and electronic device

Abstract

The invention relates to a gate driver, a display device and an electronic device. The gate driver includes a plurality of stages, each of the plurality of stages including: a delay circuit for receiving an input signal in response to a clock signal and outputting the input signal to a control node; a voltage limiting circuit for limiting a voltage of the control node based on the high limit voltage and the low limit voltage; the inverter circuit is used for inverting the voltage of the control node and outputting the inverted voltage to an inverted control node; a carry output circuit for outputting a first low gate voltage to a carry output node or outputting a first high gate voltage to the carry output node in response to a voltage of an inverting control node; and a gate output circuit for outputting a second low gate voltage lower than the first low gate voltage to the gate output node or outputting a second high gate voltage higher than the first high gate voltage to the gate output node.

Description

Technical Field

[0001] The present invention relates to a gate driver, a display device including the gate driver, and an electronic device including the display device, and more particularly, to a gate driver for reducing useless space, a display device including the gate driver, and an electronic device including the display device. Background Art

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel includes gate lines, data lines, emission lines, and pixels, and the display panel driver includes a gate driver for providing a gate signal to the gate lines, a data driver for providing a data voltage to the data lines, and a driving controller for controlling the gate driver and the data driver.

[0003] The gate driver may sequentially provide a gate signal to the pixels of the display panel row by row. The gate driver may also include a plurality of stages to sequentially provide a gate signal row by row.

[0004] Generally, each stage of the gate driver may include a single type of transistor (e.g., only P-type metal oxide semiconductor (PMOS) transistors). When each stage includes only PMOS transistors, a bootstrap operation needs to be performed to reduce the voltage of the internal node of each stage to a voltage level lower than the low voltage level in order to output a gate signal of the low voltage level.

[0005] To prevent the bootstrap operation, each stage may include complementary metal oxide semiconductor (CMOS) transistors.

[0006] When a part of the carry output circuit of each stage and a part of the gate output circuit of each stage are formed of N-type metal oxide semiconductor (NMOS) transistors, the threshold voltage of the NMOS transistors may shift in the negative direction, thereby reducing the operation reliability of the carry output circuit and the gate output circuit. In addition, when the carry output circuit and the gate output circuit are formed of NMOS transistors, due to insufficient mobility, the size of the NMOS transistors may increase, thereby increasing the useless space of the gate driver. Summary of the Invention

[0007] The present invention provides a gate driver that reduces useless space by forming a carry output circuit and a gate output circuit using PMOS transistors.

[0008] The present invention provides a display device including the gate driver.

[0009] The present invention provides an electronic device including the display device.

[0010] In an embodiment, a gate driver includes a plurality of stages, where each of the plurality of stages includes: a delay circuit configured to receive an input signal in response to a clock signal and output the input signal to a control node; a voltage limiting circuit configured to limit the voltage of the control node based on a high limit voltage and a low limit voltage; an inverter circuit configured to invert the voltage of the control node and output the inverted voltage to an inverted control node; a carry output circuit configured to output a first low gate voltage to a carry output node in response to the voltage of the control node, or output a first high gate voltage to the carry output node in response to the voltage of the inverted control node; and a gate output circuit configured to output a second low gate voltage lower than the first low gate voltage to a gate output node in response to the voltage of the control node, or output a second high gate voltage higher than the first high gate voltage to the gate output node in response to the voltage of the inverted control node.

[0011] In an embodiment, the voltage swing width between the first high gate voltage and the first low gate voltage may be less than the voltage swing width between the second high gate voltage and the second low gate voltage.

[0012] In an embodiment, the delay circuit may include a first transistor, and the first transistor includes a gate electrode for receiving the clock signal, a first electrode for receiving the input signal, and a second electrode connected to the control node.

[0013] In an embodiment, the control node may include a first control node, a second control node, and a third control node, and the voltage limiting circuit may include: a second transistor including a gate electrode for receiving the high limit voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node. The voltage limiting circuit may further include: a third transistor including a gate electrode for receiving the low limit voltage, a first electrode connected to the second control node, and a second electrode connected to the third control node.

[0014] In an embodiment, the second transistor may be an NMOS transistor, and the third transistor may be a PMOS transistor.

[0015] In an embodiment, the control node may include a first control node, a second control node, and a third control node, and the voltage limiting circuit may include: a second transistor including a gate electrode for receiving the low limit voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node; and a third transistor including a gate electrode for receiving the high limit voltage, a first electrode connected to the second control node, and a second electrode connected to the third control node.

[0016] In an embodiment, the second transistor may be a PMOS transistor, and the third transistor may be an NMOS transistor.

[0017] In an embodiment, the high limit voltage may be different from the first high gate voltage and the second high gate voltage, and the low limit voltage may be different from the first low gate voltage and the second low gate voltage.

[0018] In an embodiment, the high limit voltage may be equal to the first high gate voltage, and the low limit voltage may be equal to the first low gate voltage.

[0019] In an embodiment, the high limit voltage may be equal to the first high gate voltage, and the low limit voltage may be equal to the second low gate voltage.

[0020] In an embodiment, the high limit voltage may be equal to the second high gate voltage, and the low limit voltage may be equal to the first low gate voltage.

[0021] In an embodiment, the high limit voltage may be equal to the second high gate voltage, and the low limit voltage may be equal to the second low gate voltage.

[0022] In an embodiment, the inverter circuit may include: a fourth transistor including a gate electrode connected to a control node, a first electrode configured to receive a second low gate voltage, and a second electrode connected to an inverted control node; and a fifth transistor including a gate electrode connected to the control node, a first electrode configured to receive a second high gate voltage, and a second electrode connected to the inverted control node.

[0023] In an embodiment, the fourth transistor may be an NMOS transistor, and the fifth transistor may be a PMOS transistor.

[0024] In an embodiment, the carry output circuit may include: a sixth transistor including a gate electrode connected to the control node, a first electrode configured to receive a first low gate voltage, and a second electrode connected to a carry output node; and a seventh transistor including a gate electrode connected to the inverted control node, a first electrode configured to receive a first high gate voltage, and a second electrode connected to the carry output node.

[0025] In an embodiment, the gate output circuit may include: an eighth transistor including a gate electrode connected to the control node, a first electrode configured to receive a second low gate voltage, and a second electrode connected to a gate output node; and a ninth transistor including a gate electrode connected to the inverted control node, a first electrode configured to receive a second high gate voltage, and a second electrode connected to the gate output node.

[0026] In an embodiment, the gate output circuit may further include: a first capacitor including a first electrode connected to the control node and a second electrode connected to the gate output node; and a second capacitor including a first electrode configured to receive a second high gate voltage and a second electrode connected to the inverted control node.

[0027] In an embodiment, a gate driver includes a plurality of stages, wherein each of the plurality of stages includes: a delay circuit configured to receive an input signal in response to a clock signal and output the input signal to a control node; a voltage limiting circuit configured to limit the voltage of the control node based on a low limit voltage; an inverter circuit configured to invert the voltage of the control node to output the inverted voltage to an inverted control node; a carry output circuit configured to output a first low gate voltage to a carry output node in response to the voltage of the control node, or output a high gate voltage to the carry output node in response to the voltage of the inverted control node; and a gate output circuit configured to output a second low gate voltage lower than the first low gate voltage to a gate output node in response to the voltage of the control node, or output a high gate voltage to the gate output node in response to the voltage of the inverted control node. The control node includes a first control node and a second control node. The voltage limiting circuit includes: a second transistor including a gate electrode for receiving the low limit voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node. The inverter circuit includes: a third transistor including a gate electrode connected to the second control node, a first electrode configured to receive the second low gate voltage, and a second electrode connected to the inverted control node; and a fourth transistor including a gate electrode connected to the first control node, a first electrode configured to receive the high gate voltage, and a second electrode connected to the inverted control node.

[0028] In an embodiment, the voltage swing width between the high gate voltage and the first low gate voltage may be less than the voltage swing width between the high gate voltage and the second low gate voltage.

[0029] In an embodiment, the low limit voltage may be equal to the first low gate voltage.

[0030] In an embodiment, the low limit voltage may be equal to the second low gate voltage.

[0031] In an embodiment, the second transistor may be a PMOS transistor.

[0032] In an embodiment, a display device includes: a display panel including a plurality of pixels; and a gate driver configured to provide gate signals to the plurality of pixels. The gate driver includes a plurality of stages, wherein each of the plurality of stages includes: a delay circuit configured to receive an input signal having a voltage swing width between a first high gate voltage and a first low gate voltage in response to a clock signal and output the input signal to a control node; a voltage limiting circuit configured to limit the voltage of the control node based on a high limit voltage and a low limit voltage; an inverter circuit configured to invert the voltage of the control node and output the inverted voltage to an inverted control node; a carry output circuit configured to output a carry signal to a carry output node in response to the voltage of the control node; and a gate output circuit configured to output a second low gate voltage lower than the first low gate voltage to a gate output node in response to the voltage of the control node, or output a second high gate voltage higher than the first high gate voltage to the gate output node in response to the voltage of the inverted control node.

[0033] In an embodiment, the voltage swing width between the first high gate voltage and the first low gate voltage may be smaller than the voltage swing width between the second high gate voltage and the second low gate voltage.

[0034] In an embodiment, the control node may include a first control node, a second control node, and a third control node, and the voltage limiting circuit may include: a second transistor including a gate electrode configured to receive the high limit voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node; and a third transistor including a gate electrode configured to receive the low limit voltage, a first electrode connected to the second control node, and a second electrode connected to the third control node.

[0035] In an embodiment, and according to the gate driver and the display device including the gate driver, the carry output circuit and the gate output circuit may be formed of PMOS transistors having high reliability and high mobility, thereby improving the reliability of the gate driver and reducing the useless space of the gate driver.

[0036] In an embodiment, since the voltage of the third control node can be bootstrapped and the sixth transistor and the eighth transistor can be fully turned on or off accordingly, the reliability of the gate driver can be improved.

[0037] In an embodiment, the bootstrap voltage of the third control node can be maintained by the voltage limiting circuit, thereby improving the reliability of the gate driver.

[0038] In an embodiment, an electronic device includes: a display panel including a plurality of pixels; a gate driver configured to provide gate signals to the plurality of pixels; a data driver configured to provide data voltages to the plurality of pixels; a driving controller configured to control the gate driver and the data driver; and a processor configured to control the driving controller. The gate driver includes a plurality of stages, wherein each of the plurality of stages includes: a delay circuit configured to receive an input signal having a voltage swing width between a first high gate voltage and a first low gate voltage in response to a clock signal and output the input signal to a control node; a voltage limiting circuit configured to limit the voltage of the control node based on a high limit voltage and a low limit voltage; an inverter circuit configured to invert the voltage of the control node and output the inverted voltage to an inverted control node; a carry output circuit configured to output a carry signal to a carry output node in response to the voltage of the control node; and a gate output circuit configured to output a second low gate voltage lower than the first low gate voltage to a gate output node in response to the voltage of the control node, or output a second high gate voltage higher than the first high gate voltage to the gate output node in response to the voltage of the inverted control node.

[0039] In an embodiment, the gate output circuit can output the second high gate voltage and the second low gate voltage, thereby improving the performance of the gate driver.

[0040] In an embodiment, since the voltage swing width between the first high gate voltage and the first low gate voltage received by the carry output circuit can be smaller than the voltage swing width between the second high gate voltage and the second low gate voltage received by the gate output circuit, the power consumption of the gate driver can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] By describing embodiments of the present invention in detail with reference to the accompanying drawings, the above and other features of the present invention will become more apparent. In the drawings:

[0042] Figure 1 is a schematic block diagram showing a display device according to an embodiment;

[0043] Figure 2 is a block diagram showing a gate driver included in the Figure 1 display device according to an embodiment;

[0044] Figure 3 is a schematic circuit diagram showing an example of a stage included in the Figure 2 gate driver according to an embodiment;

[0045] Figure 4 is a timing diagram showing an example of the operation of the Figure 3 stage according to an embodiment;

[0046] Figure 5 is a schematic circuit diagram showing an example of the operation of a voltage limiting circuit included in a stage of Figure 3 ;

[0047] Figure 6 is a schematic circuit diagram showing an example of a stage included in a gate driver of Figure 2 ;

[0048] Figure 7 is a schematic circuit diagram showing an example of a stage included in a gate driver of Figure 2 ;

[0049] Figure 8 is a schematic circuit diagram showing an example of a stage included in a gate driver of Figure 2 ;

[0050] Figure 9 is a schematic circuit diagram showing an example of a stage included in a gate driver of Figure 2 ;

[0051] Figure 10 is a schematic circuit diagram showing an example of a stage included in a gate driver of Figure 2 ;

[0052] Figure 11 is a schematic circuit diagram showing an example of a stage included in a gate driver of Figure 2 ;

[0053] Figure 12 is a timing diagram showing an example of the operation of a stage of Figure 11 according to an embodiment;

[0054] Figure 13 is a schematic circuit diagram showing an example of the operation of a voltage limiting circuit included in a stage of Figure 11 ;

[0055] Figure 14 is a block diagram of an electronic device according to an embodiment; and

[0056] Figure 15 is a diagram showing an embodiment in which the Figure 14 electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0057] Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0058] It will be understood that when an element (or region, layer, or portion, etc.) is referred to as being related to another element (such as "on" another element, "connected to" or "coupled to" another element), the element can be directly disposed on the other element, directly connected to or directly coupled to the other element, or an intervening element can be disposed between the element and the other element.

[0059] Like reference numerals or symbols always refer to like elements. In the drawings, the thickness, proportion, and dimensions of the elements are exaggerated for effective description of the technical content. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0060] The term "and / or" can include all combinations of one or more that can be defined by the relevant configuration.

[0061] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, without departing from the scope of the inventive concept, the first element, first component, first region, first layer, or first portion discussed below can be referred to as the second element, second component, second region, second layer, or second portion. Similarly, the second element, second component, second region, second layer, or second portion can be referred to as the first element, first component, first region, first layer, or first portion. As used herein, unless the context clearly indicates otherwise, the singular forms of "a", "an", and "the" are also intended to include the plural forms.

[0062] In addition, terms such as "below", "underneath", "above", or "on top of" etc. can be used to describe the relationship of the elements shown in the drawings. These terms have relative concepts and are described based on the directions indicated in the drawings.

[0063] It will also be understood that when used in this specification, the terms "comprises", "comprising", and / or "has" specify the presence of the stated features, integers, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. As used herein, "directly disposed on" can mean that there is no additional layer, film, region, or plate, etc. between a part such as a layer, film, region, or plate and another part. For example, "directly disposed on" can mean that two layers or two members are disposed without using an additional member (such as an adhesive member) therebetween.

[0064] As used herein, "about" or "approximately" includes the stated value and means within an acceptable deviation range of the specific value as determined by one of ordinary skill in the art in view of the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0065] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will also be understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0066] Figure 1 is a schematic block diagram showing a display device 10 according to an embodiment.

[0067] In an embodiment, and with reference to Figure 1 , the display device 10 may include a display panel 110 and a display panel driver. The display panel driver may include a driving controller 120, a gate driver 130, a gamma reference voltage generator 140, and a data driver 150.

[0068] The display panel 110 may include a display area for displaying an image and a peripheral area provided adjacent to the display area.

[0069] The display panel 110 may include gate lines GL, data lines DL, and pixels P electrically connected to the gate lines GL and the data lines DL. The gate lines GL may extend in a first direction, and the data lines DL may extend in a second direction intersecting the first direction.

[0070] The driving controller 120 may receive input image data IMG and an input control signal CONT from an external device (not shown). For example, the input image data IMG may include red image data, green image data, and blue image data. In other embodiments, the input image data IMG may include white image data and / or the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0071] The driving controller 120 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0072] The driving controller 120 can generate a first control signal CONT1 for controlling the operation of the gate driver 130 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 130. The first control signal CONT1 can include a vertical start signal and a gate clock signal.

[0073] The driving controller 120 can generate a second control signal CONT2 for controlling the operation of the data driver 150 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 150. The second control signal CONT2 can include a horizontal start signal and a load signal.

[0074] The driving controller 120 can generate a data signal DATA based on the input image data IMG. The driving controller 120 can output the data signal DATA to the data driver 150.

[0075] The driving controller 120 can generate a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 140 based on the input control signal CONT, and output the third control signal CONT3 to the gamma reference voltage generator 140.

[0076] The gate driver 130 can generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 120, and output the gate signal to the gate line GL.

[0077] The gamma reference voltage generator 140 can generate a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 120, and provide the gamma reference voltage VGREF to the data driver 150. The gamma reference voltage VGREF can have a value corresponding to each data signal DATA.

[0078] In an embodiment, the gamma reference voltage generator 140 can be provided in the driving controller 120 or can be provided in the data driver 150.

[0079] The data driver 150 may receive a second control signal CONT2 and a data signal DATA from the driving controller 120, and receive a gamma reference voltage VGREF from the gamma reference voltage generator 140. The data driver 150 may convert the data signal DATA into a data voltage of an analog type by using the gamma reference voltage VGREF. The data driver 150 may output the data voltage to the data line DL.

[0080] Figure 2 is a block diagram showing a gate driver 130 included in a Figure 1 display device 10 according to an embodiment.

[0081] In an embodiment, and referring to Figure 1 and Figure 2 , the gate driver 130 may include a plurality of stages STAGE1, STAGE2, STAGE3, STAGE4, ……, and the plurality of stages STAGE1, STAGE2, STAGE3, STAGE4, …… receive a gate start signal FLM and a clock signal CLK and output gate signals GS1, GS2, GS3, GS4, …… respectively. The first stage STAGE1 may receive the gate start signal FLM as an input signal, and subsequent stages STAGE2, STAGE3, STAGE4, …… may receive carry signals CR1, CR2, CR3, …… of respective previous stages as input signals.

[0082] The stages STAGE1, STAGE2, STAGE3, STAGE4, …… may sequentially output carry signals CR1, CR2, CR3, CR4, …… respectively, and sequentially output gate signals GS1, GS2, GS3, GS4, …… respectively. For example, the first stage STAGE1 may output a first carry signal CR1 and a first gate signal GS1 based on the gate start signal FLM, the second stage STAGE2 may output a second carry signal CR2 and a second gate signal GS2 based on the first carry signal CR1, the third stage STAGE3 may output a third carry signal CR3 and a third gate signal GS3 based on the second carry signal CR2, and the fourth stage STAGE4 may output a fourth carry signal CR4 and a fourth gate signal GS4 based on the third carry signal CR3.

[0083] Figure 3 is a schematic circuit diagram showing an example of a stage 200 included in a Figure 2 gate driver 130 according to an embodiment.

[0084] In an embodiment, and referring to Figures 1 to 3, the gate driver 130 may include multiple stages 200. Each stage 200 may include a delay circuit 210, a voltage limiting circuit 220, an inverter circuit 230, a carry output circuit 240, and a gate output circuit 250.

[0085] The delay circuit 210 may receive an input signal FLM / PCR in response to a clock signal CLK and output the input signal FLM / PCR to control nodes NQ1, NQ2, and NQ3.

[0086] In an embodiment, the delay circuit 210 may include a first transistor T1. The first transistor T1 may include a gate electrode for receiving the clock signal CLK, a first electrode for receiving the input signal FLM / PCR, and a second electrode connected to the control nodes NQ1, NQ2, and NQ3. The first transistor T1 may be a PMOS transistor.

[0087] The voltage limiting circuit 220 may limit the voltages of the control nodes NQ1, NQ2, and NQ3 based on a high limit voltage VGH_N and a low limit voltage VGL_P.

[0088] In an embodiment, the voltage limiting circuit 220 may include a second transistor T2 and a third transistor T3. The second transistor T2 may include a gate electrode for receiving the high limit voltage VGH_N, a first electrode connected to the first control node NQ1, and a second electrode connected to the second control node NQ2. The third transistor T3 may include a gate electrode for receiving the low limit voltage VGL_P, a first electrode connected to the second control node NQ2, and a second electrode connected to the third control node NQ3. The second transistor T2 may be an NMOS transistor, and the third transistor T3 may be a PMOS transistor.

[0089] The inverter circuit 230 may invert the voltages of the control nodes NQ1, NQ2, and NQ3 and output the inverted voltages to an inverted control node NQB.

[0090] In an embodiment, the inverter circuit 230 may include a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 may include a gate electrode connected to the control nodes NQ1, NQ2, and NQ3, a first electrode for receiving a second low gate voltage VGL2, and a second electrode connected to the inverted control node NQB. The fifth transistor T5 may include a gate electrode connected to the control nodes NQ1, NQ2, and NQ3, a first electrode for receiving a second high gate voltage VGH2, and a second electrode connected to the inverted control node NQB. The fourth transistor T4 may be an NMOS transistor, and the fifth transistor T5 may be a PMOS transistor.

[0091] The carry output circuit 240 can output a carry signal CR. The carry output circuit 240 can output a first low gate voltage VGL1 to the carry output node NCR in response to the voltages of the control nodes NQ1, NQ2, and NQ3, or can output a first high gate voltage VGH1 to the carry output node NCR in response to the voltage of the inverted control node NQB.

[0092] In an embodiment, the carry output circuit 240 can include a sixth transistor T6 and a seventh transistor T7. The sixth transistor T6 can include a gate electrode connected to the control nodes NQ1, NQ2, and NQ3, a first electrode for receiving the first low gate voltage VGL1, and a second electrode connected to the carry output node NCR. The seventh transistor T7 can include a gate electrode connected to the inverted control node NQB, a first electrode for receiving the first high gate voltage VGH1, and a second electrode connected to the carry output node NCR. The sixth transistor T6 and the seventh transistor T7 can be PMOS transistors.

[0093] The gate output circuit 250 can output a gate signal GS. The gate output circuit 250 can output a second low gate voltage VGL2 lower than the first low gate voltage VGL1 to the gate output node NGS in response to the voltages of the control nodes NQ1, NQ2, and NQ3, and can output a second high gate voltage VGH2 higher than the first high gate voltage VGH1 to the gate output node NGS in response to the voltage of the inverted control node NQB.

[0094] In an embodiment, the gate output circuit 250 can include an eighth transistor T8 and a ninth transistor T9. The eighth transistor T8 can include a gate electrode connected to the control nodes NQ1, NQ2, and NQ3, a first electrode for receiving the second low gate voltage VGL2, and a second electrode connected to the gate output node NGS. The ninth transistor T9 can include a gate electrode connected to the inverted control node NQB, a first electrode for receiving the second high gate voltage VGH2, and a second electrode connected to the gate output node NGS. The eighth transistor T8 and the ninth transistor T9 can be PMOS transistors.

[0095] In an embodiment, the gate output circuit 250 can further include a first capacitor C1 and a second capacitor C2. The first capacitor C1 can include a first electrode connected to the control nodes NQ1, NQ2, and NQ3 and a second electrode connected to the gate output node NGS. The second capacitor C2 can include a first electrode for receiving the second high gate voltage VGH2 and a second electrode connected to the inverted control node NQB.

[0096] In an embodiment, since the sixth transistor T6 of the carry output circuit 240 and the eighth transistor T8 of the gate output circuit 250 are PMOS transistors instead of NMOS transistors, a negative shift in the threshold voltages of the sixth transistor T6 and the eighth transistor T8 can be prevented, and an increase in the dead space of the gate driver 130 can be prevented, the dead space increasing by increasing the sizes of the sixth transistor T6 and the eighth transistor T8 to compensate for the mobility of the sixth transistor T6 and the eighth transistor T8.

[0097] Therefore, since each stage 200 includes nine transistors and two capacitors, the area occupied by each stage 200 can be reduced and the dead space of the gate driver 130 can be decreased.

[0098] Figure 4 is a timing diagram showing an example of the operation of the Figure 3 stage 200 according to an embodiment. Figure 5 is a schematic circuit diagram showing an example of the operation of the voltage limiting circuit 220 included in the Figure 3 stage 200 according to an embodiment.

[0099] In an embodiment, and with reference to Figures 1 to 5 , the control nodes NQ1, NQ2, and NQ3 may include a first control node NQ1, a second control node NQ2, and a third control node NQ3.

[0100] In an embodiment, the delay circuit 210 may receive an input signal FLM / PCR in response to a clock signal CLK and output the input signal FLM / PCR to the control nodes NQ1, NQ2, and NQ3. Specifically, the first transistor T1 may receive the input signal FLM / PCR in response to the clock signal CLK having a first low gate voltage VGL1 and output the input signal FLM / PCR to the first control node NQ1. Accordingly, the input signal FLM / PCR may be delayed by one horizontal period by the delay circuit 210 and output to the first control node NQ1.

[0101] For example, when the clock signal CLK has the first low gate voltage VGL1, the first transistor T1 may receive the input signal FLM / PCR having a first high gate voltage VGH1 in response to the clock signal CLK having the first low gate voltage VGL1, and may output the input signal FLM / PCR having the first high gate voltage VGH1 to the first control node NQ1. The first control node NQ1 may have the first high gate voltage VGH1.

[0102] The voltage limiting circuit 220 can output the voltage of the first control node NQ1 to the third control node NQ3. Specifically, the second transistor T2 can output the voltage of the first control node NQ1 to the second control node NQ2, and the third transistor T3 can output the voltage of the second control node NQ2 to the third control node NQ3.

[0103] For example, when the first control node NQ1 has a first high gate voltage VGH1, the second transistor T2 can output the voltage of the first control node NQ1 to the second control node NQ2, and the third transistor T3 can output the voltage of the second control node NQ2 to the third control node NQ3.

[0104] The third control node NQ3 can have a first high gate voltage VGH1.

[0105] The inverter circuit 230 can invert the voltages of the control nodes NQ1, NQ2, and NQ3 to output an inverted voltage to the inverted control node NQB. Specifically, when the third control node NQ3 has a high level, the fourth transistor T4 can output a second low gate voltage VGL2 to the inverted control node NQB in response to the third control node NQ3 having a high level. In addition, when the third control node NQ3 has a low level, the fifth transistor T5 can output a second high gate voltage VGH2 to the inverted control node NQB in response to the third control node NQ3 having a low level. Therefore, the inverted control node NQB can have a phase that is inverted with respect to the voltage of the third control node NQ3 through the inverter circuit 230.

[0106] In an embodiment, when the third control node NQ3 has a first high gate voltage VGH1, the fourth transistor T4 can output a second low gate voltage VGL2 to the inverted control node NQB in response to the third control node NQ3 having a first high gate voltage VGH1. The inverted control node NQB can then have a second low gate voltage VGL2.

[0107] In an embodiment, the carry output circuit 240 can output a carry signal CR. The carry output circuit 240 can output a first low gate voltage VGL1 to the carry output node NCR in response to the voltages of the control nodes NQ1, NQ2, and NQ3, or can output a first high gate voltage VGH1 to the carry output node NCR in response to the voltage of the inverted control node NQB. Specifically, when the inverted control node NQB has a low level, the seventh transistor T7 can output a first high gate voltage VGH1 to the carry output node NCR in response to the inverted control node NQB having a low level. Additionally, when the third control node NQ3 has a low level, the sixth transistor T6 can output a first low gate voltage VGL1 to the carry output node NCR in response to the third control node NQ3 having a low level.

[0108] For example, when the inverted control node NQB has the second low gate voltage VGL2, the seventh transistor T7 can output the first high gate voltage VGH1 to the carry output node NCR in response to the inverted control node NQB having the second low gate voltage VGL2. The carry output node NCR can then have the first high gate voltage VGH1.

[0109] In an embodiment, the gate output circuit 250 can output a gate signal GS. The gate output circuit 250 can output the second low gate voltage VGL2 to the gate output node NGS in response to the voltages of the control nodes NQ1, NQ2, and NQ3, and can output the second high gate voltage VGH2 to the gate output node NGS in response to the voltage of the inverted control node NQB. Specifically, when the inverted control node NQB has a low level, the ninth transistor T9 can output the second high gate voltage VGH2 to the gate output node NGS in response to the inverted control node NQB having a low level. Additionally, when the third control node NQ3 has a low level, the eighth transistor T8 can output the second low gate voltage VGL2 to the gate output node NGS in response to the third control node NQ3 having a low level.

[0110] For example, when the inverted control node NQB has the second low gate voltage VGL2, the ninth transistor T9 can output the second high gate voltage VGH2 to the gate output node NGS in response to the inverted control node NQB having the second low gate voltage VGL2. The gate output node NGS can then have the second high gate voltage VGH2.

[0111] In an embodiment, when the voltage of the third control node NQ3 (i.e., the first electrode of the first capacitor C1) is twice the first low gate voltage VGL1, and the voltage of the gate output node NGS (i.e., the second electrode of the first capacitor C1) is the second low gate voltage VGL2, the voltage stored between the electrodes of the first capacitor C1 can be given by "2 × VGL1 - VGL2". Here, VGL1 represents the voltage value of the first low gate voltage VGL1, and VGL2 represents the voltage value of the second low gate voltage VGL2.

[0112] In an embodiment, when the voltage of the gate output node NGS changes, the voltage of the third control node NQ3 can be bootstrapped while the stored voltage is maintained between the two electrodes of the first capacitor C1. When the voltage of the gate output node NGS increases by "VGH2 - VGL2" from the second low gate voltage VGL2 to the second high gate voltage VGH2, the voltage of the third control node NQ3 can increase by "VGH2 - VGL2" from twice the first low gate voltage VGL1, and the voltage of the third control node NQ3 can be bootstrapped to a voltage of "2×VGL1+(VGH2 - VGL2)". Here, VGH2 represents the voltage value of the second high gate voltage VGH2. In this way, when the voltage of the gate output node NGS increases to the second high gate voltage VGH2, the voltage of the third control node NQ3 can be bootstrapped to a voltage higher than the first high gate voltage VGH1 through the first capacitor C1. For example, the bootstrapped voltage of the third control node NQ3 (i.e., "2×VGL1+(VGH2 - VGL2)") can be approximately twice the first high gate voltage VGH1. In this embodiment, approximately twice the first high gate voltage VGH1 can be higher than the second high gate voltage VGH2. Since the bootstrapped voltage of the third control node NQ3 is a voltage higher than the second high gate voltage VGH2, the sixth transistor T6 and the eighth transistor T8 can be sufficiently turned off, and the operating reliability of the sixth transistor T6 and the eighth transistor T8 can be improved.

[0113] In an embodiment, the voltage limiting circuit 220 can limit the voltages of the control nodes NQ1, NQ2, and NQ3 based on the high limit voltage VGH_N and the low limit voltage VGL_P. Specifically, the voltage limiting circuit 220 can limit the flow of the bootstrapped voltage of the third control node NQ3 to the voltage of the first control node NQ1, and the bootstrapped voltage of the third control node NQ3 can be maintained. The operating reliability of the sixth transistor T6 and the eighth transistor T8 can be further improved.

[0114] In an embodiment, and as Figure 5 shown, the threshold voltage (VTH) of the second transistor T2 can be 1V, the threshold voltage of the third transistor T3 can be -2V, the high limit voltage VGH_N can be 4V, and the low limit voltage VGL_P can be -5V. However, Figure 5 the voltages shown are set to describe the operation of the voltage limiting circuit 220 and are not directly related to each stage 200 of Figure 3 and Figure 4 . In Figure 5 , the values of the voltages applied to the gate (G) electrode, source (S) electrode, and drain (D) electrode of the second transistor T2 and the gate (G) electrode, source (S) electrode, and drain (D) electrode of the third transistor T3 are shown as examples.

[0115] Figure 5 The embodiment represents the first case (Case 1) where the bootstrap voltage of the third control node NQ3 is at a high level. When the bootstrap voltage of the third control node NQ3 is 16V, the gate-source voltage of the third transistor T3 can be -21V. Since the gate-source voltage of the third transistor T3 is lower than the threshold voltage of the third transistor T3, the third transistor T3 can be turned on, and the voltage of the third control node NQ3 can be transmitted to the second control node NQ2. When the voltage of the first control node NQ1 is 3V and the voltage of the second control node NQ2 is 16V, the gate-source voltage of the second transistor T2 can be 1V. Since the gate-source voltage of the first transistor T1 is not higher than the threshold voltage of the first transistor T1, the first transistor T1 can be turned off, and the voltage of the second control node NQ2 can not be transmitted to the first control node NQ1. Therefore, the bootstrap voltage of the third control node NQ3 can be maintained at 16V.

[0116] Conversely, after the first high gate voltage VGH1 is output to the carry output node NCR and the second high gate voltage VGH2 is output to the gate output node NGS, the first transistor T1 can receive an input signal FLM / PCR having the first low gate voltage VGL1 in response to a clock signal CLK having the first low gate voltage VGL1, and can output the input signal FLM / PCR having the first low gate voltage VGL1 to the first control node NQ1. The first control node NQ1 can have the first low gate voltage VGL1.

[0117] When the first control node NQ1 has the first low gate voltage VGL1, the second transistor T2 can output the voltage of the first control node NQ1 to the second control node NQ2, and the third transistor T3 can output the voltage of the second control node NQ2 to the third control node NQ3. The third control node NQ3 can have the first low gate voltage VGL1.

[0118] When the third control node NQ3 has the first low gate voltage VGL1, the fifth transistor T5 can output the second high gate voltage VGH2 to the inverted control node NQB in response to the third control node NQ3 having the first low gate voltage VGL1. The inverted control node NQB can have the second high gate voltage VGH2.

[0119] When the third control node NQ3 has the first low gate voltage VGL1, the sixth transistor T6 can output the first low gate voltage VGL1 to the carry output node NCR in response to the third control node NQ3 having the first low gate voltage VGL1. The carry output node NCR can have the first low gate voltage VGL1.

[0120] When the third control node NQ3 has the first low gate voltage VGL1, the eighth transistor T8 can output the second low gate voltage VGL2 to the gate output node NGS in response to the third control node NQ3 having the first low gate voltage VGL1. The gate output node NGS can have the second low gate voltage VGL2.

[0121] When the voltage of the third control node NQ3 (i.e., the first electrode of the first capacitor C1) is twice the first high gate voltage VGH1 and the voltage of the gate output node NGS (i.e., the second electrode of the first capacitor C1) is the second high gate voltage VGH2, the voltage stored between the electrodes of the first capacitor C1 can be given by "2×VGH1 - VGH2".

[0122] In an embodiment, when the voltage of the gate output node NGS changes, the voltage of the third control node NQ3 can be bootstrapped while the stored voltage is maintained between the two electrodes of the first capacitor C1. When the voltage of the gate output node NGS decreases by "VGH2 - VGL2" from the second high gate voltage VGH2 to the second low gate voltage VGL2, the voltage of the third control node NQ3 can decrease by "VGH2 - VGL2" from twice the first high gate voltage VGH1, and the voltage of the third control node NQ3 can be bootstrapped to the voltage of "2×VGH1 - (VGH2 - VGL2)". In this way, when the voltage of the gate output node NGS decreases to the second low gate voltage VGL2, the voltage of the third control node NQ3 can be bootstrapped by the first capacitor C1 to a voltage lower than the first low gate voltage VGL1. For example, the bootstrapped voltage of the third control node NQ3 (i.e., "2×VGH1 - (VGH2 - VGL2)") can be approximately twice the first low gate voltage VGL1. In this case, approximately twice the first low gate voltage VGL1 can be lower than the second low gate voltage VGL2. Since the bootstrapped voltage of the third control node NQ3 is lower than the second low gate voltage VGL2, the sixth transistor T6 and the eighth transistor T8 can be fully turned on, and the operating reliability of the sixth transistor T6 and the eighth transistor T8 can be improved.

[0123] In an embodiment, and as Figure 5 shown, the threshold voltage of the second transistor T2 can be 1V, the threshold voltage of the third transistor T3 can be -2V, the high limit voltage VGH_N can be 4V, and the low limit voltage VGL_P can be -5V.

[0124] Figure 5The embodiment represents the second case (Case 2) where the bootstrap voltage of the third control node NQ3 is at a low level. When the voltage of the first control node NQ1 is -3V, the gate-source voltage of the second transistor T2 can be 7V. Since the gate-source voltage of the second transistor T2 is greater than the threshold voltage of the second transistor T2, the second transistor T2 can conduct and transfer the voltage of the first control node NQ1 to the second control node NQ2. When the voltage of the second control node NQ2 is -3V and the bootstrap voltage of the third control node NQ3 is -16V, the gate-source voltage of the third transistor T3 can be -2V. Since the gate-source voltage of the third transistor T3 is not lower than the threshold voltage of the third transistor T3, the third transistor T3 can be cut off and the bootstrap voltage of the third control node NQ3 may not be transferred to the second control node NQ2. Therefore, the bootstrap voltage of the third control node NQ3 can be maintained at -16V. The operational reliability of the sixth transistor T6 and the eighth transistor T8 can be further improved.

[0125] In the embodiment, since the gate output circuit 250 outputs the second high gate voltage VGH2 and the second low gate voltage VGL2, the performance of the gate driver 130 can be improved. In addition, since the voltage swing width between the first high gate voltage VGH1 and the first low gate voltage VGL1 received by the carry output circuit 240 is smaller than the voltage swing width between the second high gate voltage VGH2 and the second low gate voltage VGL2 received by the gate output circuit 250, the power consumption of the gate driver 130 can be reduced. Since the voltage swing width between the first high gate voltage VGH1 and the first low gate voltage VGL1 of the input signal FLM / PCR is smaller than the voltage swing width between the second high gate voltage VGH2 and the second low gate voltage VGL2 received by the gate output circuit 250, the power consumption of the gate driver 130 can be reduced.

[0126] Therefore, the carry output circuit 240 and the gate output circuit 250 are formed of PMOS transistors having high reliability and high mobility, thereby improving the reliability of the gate driver 130 and reducing the useless space of the gate driver 130.

[0127] In addition, since the voltage of the third control node NQ3 is bootstrapped and the sixth transistor T6 and the eighth transistor T8 are accordingly fully turned on or off, the reliability of the gate driver 130 can be improved.

[0128] In addition, the bootstrap voltage of the third control node NQ3 is maintained by the voltage limiting circuit 220, thereby improving the reliability of the gate driver 130.

[0129] In addition, the gate output circuit 250 outputs a second highest gate voltage VGH2 and a second lowest gate voltage VGL2, thereby improving the performance of the gate driver 130.

[0130] In addition, since the voltage swing width between the first highest gate voltage VGH1 and the first lowest gate voltage VGL1 received by the carry output circuit 240 is smaller than the voltage swing width between the second highest gate voltage VGH2 and the second lowest gate voltage VGL2 received by the gate output circuit 250, the power consumption of the gate driver 130 can be reduced.

[0131] Figure 6 is a schematic circuit diagram showing an example of stage 300 included in the Figure 2 gate driver 130.

[0132] Except for the configuration of the voltage limiting circuit, Figure 6 stage 300 of Figures 1 to 5 is substantially the same as stage 200 of the gate driver 130 of

[0133] In an embodiment, and referring to Figures 1 to 6 , the gate driver 130 may include a plurality of stages 300, where each stage 300 may include a delay circuit 310, a voltage limiting circuit 320, an inverter circuit 330, a carry output circuit 340, and a gate output circuit 350.

[0134] Figure 6 An embodiment is shown in which the gate electrode of the second transistor T2 receives a high limit voltage VGH_N equal to the first highest gate voltage VGH1 and the gate electrode of the third transistor T3 receives a low limit voltage VGL_P equal to the first lowest gate voltage VGL1.

[0135] Since the voltage limiting circuit 320 limits the voltage flow from the voltage of the third control node NQ3 to the voltage of the first control node NQ1 based on the high limit voltage VGH_N and the low limit voltage VGL_P, the voltage range in which the voltage of the third control node NQ3 is transmitted to the first control node NQ1 can be changed according to the high limit voltage VGH_N and the low limit voltage VGL_P.

[0136] Figure 7 is a schematic circuit diagram showing an example of stage 400 included in the Figure 2 gate driver 130.

[0137] Except for the configuration of the voltage limiting circuit, Figure 7 stage 400 of Figures 1 to 5is substantially the same as stage 200 of gate driver 130. Therefore, the same reference numerals will be used for the same or similar components, and repeated descriptions will be omitted.

[0138] In an embodiment, and with reference to Figures 1 to 5 and Figure 7 , gate driver 130 may include a plurality of stages 400, where each stage 400 may include a delay circuit 410, a voltage limiting circuit 420, an inverter circuit 430, a carry output circuit 440, and a gate output circuit 450.

[0139] Figure 7 An embodiment is shown in which the gate electrode of the second transistor T2 receives a high limit voltage VGH_N equal to the first high gate voltage VGH1 and the gate electrode of the third transistor T3 receives a low limit voltage VGL_P equal to the second low gate voltage VGL2.

[0140] Since the voltage limiting circuit 420 limits the voltage flow from the voltage of the third control node NQ3 to the voltage of the first control node NQ1 based on the high limit voltage VGH_N and the low limit voltage VGL_P, the voltage range in which the voltage of the third control node NQ3 is transmitted to the first control node NQ1 can be changed according to the high limit voltage VGH_N and the low limit voltage VGL_P.

[0141] Figure 8 is a schematic circuit diagram showing an example of stage 500 included in Figure 2 gate driver 130.

[0142] Except for the configuration of the voltage limiting circuit, Figure 8 stage 500 of Figures 1 to 5 is substantially the same as stage 200 of gate driver 130 of

[0143] In an embodiment, and with reference to Figures 1 to 5 and Figure 8 , gate driver 130 may include a plurality of stages 500, where each stage 500 may include a delay circuit 510, a voltage limiting circuit 520, an inverter circuit 530, a carry output circuit 540, and a gate output circuit 550.

[0144] Figure 8 An embodiment is shown in which the gate electrode of the second transistor T2 receives a high limit voltage VGH_N equal to the second high gate voltage VGH2 and the gate electrode of the third transistor T3 receives a low limit voltage VGL_P equal to the first low gate voltage VGL1.

[0145] Since the voltage limiting circuit 520 limits the voltage flow from the third control node NQ3 to the first control node NQ1 based on the high limit voltage VGH_N and the low limit voltage VGL_P, the voltage range in which the voltage of the third control node NQ3 is transmitted to the first control node NQ1 can be changed according to the high limit voltage VGH_N and the low limit voltage VGL_P.

[0146] Figure 9 is a schematic circuit diagram showing an example of stage 600 included in Figure 2 the gate driver 130 according to an embodiment.

[0147] Except for the configuration of the voltage limiting circuit, Figure 9 stage 600 of Figures 1 to 5 the gate driver 130 is substantially the same as stage 200 of

[0148] In an embodiment, and referring to Figures 1 to 5 and Figure 9 , the gate driver 130 may include a plurality of stages 600, where each stage 600 may include a delay circuit 610, a voltage limiting circuit 620, an inverter circuit 630, a carry output circuit 640, and a gate output circuit 650.

[0149] Figure 9 An embodiment is shown in which the gate electrode of the second transistor T2 receives the high limit voltage VGH_N equal to the second high gate voltage VGH2 and the gate electrode of the third transistor T3 receives the low limit voltage VGL_P equal to the second low gate voltage VGL2.

[0150] Since the voltage limiting circuit 620 limits the voltage flow from the third control node NQ3 to the first control node NQ1 based on the high limit voltage VGH_N and the low limit voltage VGL_P, the voltage range in which the voltage of the third control node NQ3 is transmitted to the first control node NQ1 can be changed according to the high limit voltage VGH_N and the low limit voltage VGL_P.

[0151] Figure 10 is a schematic circuit diagram showing an example of stage 700 included in Figure 2 the gate driver 130 according to an embodiment.

[0152] Except for the configuration of the voltage limiting circuit, Figure 10 stage 700 of Figures 1 to 5 the gate driver 130 is substantially the same as stage 200 of

[0153] In an embodiment, and referring to Figures 1 to 5 and Figure 10 , the voltage limiting circuit 720 may include a second transistor T2 and a third transistor T3. The second transistor T2 may include a gate electrode for receiving a low limit voltage VGL_P, a first electrode connected to a first control node NQ1, and a second electrode connected to a second control node NQ2. The third transistor T3 may include a gate electrode for receiving a high limit voltage VGH_N, a first electrode connected to the second control node NQ2, and a second electrode connected to a third control node NQ3. In an embodiment, the second transistor T2 may be a PMOS transistor, and the third transistor T3 may be an NMOS transistor.

[0154] Figure 11 is a schematic circuit diagram showing an example of a stage 800 included in Figure 2 the gate driver 130 according to an embodiment.

[0155] In an embodiment, and referring to Figure 1 , Figure 2 and Figure 11 , the gate driver 130 may include a plurality of stages 800. Each stage 800 may include a delay circuit 810, a voltage limiting circuit 820, an inverter circuit 830, a carry output circuit 840, and a gate output circuit 850.

[0156] The delay circuit 810 may receive an input signal FLM / PCR in response to a clock signal CLK and output the input signal FLM / PCR to the control nodes NQ1 and NQ2. The control nodes NQ1 and NQ2 may include a first control node NQ1 and a second control node NQ2.

[0157] In an embodiment, the delay circuit 810 may include a first transistor T1. The first transistor T1 may include a gate electrode for receiving the clock signal CLK, a first electrode for receiving the input signal FLM / PCR, and a second electrode connected to the first control node NQ1. The first transistor T1 may be a PMOS transistor.

[0158] The voltage limiting circuit 820 may limit the voltages of the control nodes NQ1 and NQ2 based on the low limit voltage VGL_P.

[0159] In an embodiment, the voltage limiting circuit 820 may include a second transistor T2. The second transistor T2 may include a gate electrode for receiving a low limit voltage VGL_P, a first electrode connected to the first control node NQ1, and a second electrode connected to the second control node NQ2. The second transistor T2 may be a PMOS transistor. The low limit voltage VGL_P may be a first low gate voltage VGL1 or a second low gate voltage VGL2. The second low gate voltage VGL2 may be lower than the first low gate voltage VGL1.

[0160] The inverter circuit 830 may invert the voltages of the control nodes NQ1 and NQ2 to output an inverted voltage to the inverted control node NQB.

[0161] In an embodiment, the inverter circuit 830 may include a third transistor T3 and a fourth transistor T4. The third transistor T3 may include a gate electrode connected to the second control node NQ2, a first electrode for receiving the second low gate voltage VGL2, and a second electrode connected to the inverted control node NQB. The fourth transistor T4 may include a gate electrode connected to the first control node NQ1, a first electrode for receiving a high gate voltage VGH, and a second electrode connected to the inverted control node NQB. The third transistor T3 may be an NMOS transistor, and the fourth transistor T4 may be a PMOS transistor.

[0162] In an embodiment, the carry output circuit 840 may output a carry signal CR. The carry output circuit 840 may output the first low gate voltage VGL1 to the carry output node NCR in response to the voltage of the second control node NQ2, or may output the high gate voltage VGH to the carry output node NCR in response to the voltage of the inverted control node NQB.

[0163] In an embodiment, the carry output circuit 840 may include a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 may include a gate electrode connected to the second control node NQ2, a first electrode for receiving the first low gate voltage VGL1, and a second electrode connected to the carry output node NCR. The sixth transistor T6 may include a gate electrode connected to the inverted control node NQB, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the carry output node NCR. The fifth transistor T5 and the sixth transistor T6 may be PMOS transistors.

[0164] In an embodiment, the gate output circuit 850 may output a gate signal GS. The gate output circuit 850 may output a second low gate voltage VGL2 lower than a first low gate voltage VGL1 to a gate output node NGS in response to a voltage of a second control node NQ2, and may output a high gate voltage VGH to the gate output node NGS in response to a voltage of an inverted control node NQB.

[0165] In an embodiment, the gate output circuit 850 may include a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 may include a gate electrode connected to the second control node NQ2, a first electrode for receiving the second low gate voltage VGL2, and a second electrode connected to the gate output node NGS. The eighth transistor T8 may include a gate electrode connected to the inverted control node NQB, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the gate output node NGS. The seventh transistor T7 and the eighth transistor T8 may be PMOS transistors.

[0166] In an embodiment, the gate output circuit 850 may further include a first capacitor C1 and a second capacitor C2. The first capacitor C1 may include a first electrode connected to the second control node NQ2 and a second electrode connected to the gate output node NGS. The second capacitor C2 may include a first electrode for receiving the high gate voltage VGH and a second electrode connected to the inverted control node NQB.

[0167] In an embodiment, since the fifth transistor T5 of the carry output circuit 840 and the seventh transistor T7 of the gate output circuit 850 are PMOS transistors instead of NMOS transistors, a negative shift of threshold voltages of the fifth transistor T5 and the seventh transistor T7 can be prevented, and an increase in useless space of the gate driver 130, which is increased by increasing sizes of the fifth transistor T5 and the seventh transistor T7 to compensate for mobilities of the fifth transistor T5 and the seventh transistor T7, can be prevented.

[0168] Since each stage 800 includes eight transistors and two capacitors, an area occupied by each stage 800 can be reduced, and useless space of the gate driver 130 can be reduced.

[0169] Figure 12 is a timing diagram showing an example of an operation of a stage 800 according to an embodiment Figure 11 of. Figure 13 is a schematic circuit diagram showing an example of an operation of a voltage limiting circuit 820 included in a stage 800 according to an embodiment Figure 11 of.

[0170] In an embodiment, and with reference to Figures 1 to 2 and Figures 11 to 13, the delay circuit 810 can receive an input signal FLM / PCR in response to a clock signal CLK and output the input signal FLM / PCR to control nodes NQ1 and NQ2. Specifically, the first transistor T1 can receive the input signal FLM / PCR in response to the clock signal CLK having a first low gate voltage VGL1 and output the input signal FLM / PCR to the first control node NQ1. Therefore, the input signal FLM / PCR can be delayed by one horizontal period through the delay circuit 810 and output to the first control node NQ1.

[0171] In an embodiment, when the clock signal CLK has a first low gate voltage VGL1, the first transistor T1 can receive an input signal FLM / PCR having a high gate voltage VGH in response to the clock signal CLK having a first low gate voltage VGL1 and output the input signal FLM / PCR having a high gate voltage VGH to the first control node NQ1. The first control node NQ1 can have a high gate voltage VGH.

[0172] In an embodiment, the voltage limiting circuit 820 can output the voltage of the first control node NQ1 to the second control node NQ2. Specifically, the second transistor T2 can output the voltage of the first control node NQ1 to the second control node NQ2. The second control node NQ2 can have a high gate voltage VGH.

[0173] In an embodiment, the inverter circuit 830 can invert the voltages of the control nodes NQ1 and NQ2 and output the inverted voltage to the inverted control node NQB. Specifically, when the second control node NQ2 has a high level, the third transistor T3 can output a second low gate voltage VGL2 to the inverted control node NQB in response to the second control node NQ2 having a high level. In addition, when the first control node NQ1 has a low level, the fourth transistor T4 can output a high gate voltage VGH to the inverted control node NQB in response to the first control node NQ1 having a low level. Therefore, the inverted control node NQB can have a phase that is inverted from the voltages of the control nodes NQ1 and NQ2 through the inverter circuit 830.

[0174] In an embodiment, when the second control node NQ2 has a high gate voltage VGH, the third transistor T3 can output a second low gate voltage VGL2 to the inverted control node NQB in response to the second control node NQ2 having a high gate voltage VGH. The inverted control node NQB can have a second low gate voltage VGL2.

[0175] In an embodiment, the carry output circuit 840 may output a carry signal CR. The carry output circuit 840 may output a first low gate voltage VGL1 to the carry output node NCR in response to the voltage of the second control node NQ2, or may output a high gate voltage VGH to the carry output node NCR in response to the voltage of the inverted control node NQB. Specifically, when the inverted control node NQB has a low level, the sixth transistor T6 may output the high gate voltage VGH to the carry output node NCR in response to the inverted control node NQB having a low level. Additionally, when the second control node NQ2 has a low level, the fifth transistor T5 may output the first low gate voltage VGL1 to the carry output node NCR in response to the second control node NQ2 having a low level.

[0176] In an embodiment, when the inverted control node NQB has a second low gate voltage VGL2, the sixth transistor T6 may output the high gate voltage VGH to the carry output node NCR in response to the inverted control node NQB having the second low gate voltage VGL2. The carry output node NCR may have the high gate voltage VGH.

[0177] In an embodiment, the gate output circuit 850 may output a gate signal GS, wherein the gate output circuit 850 may output a second low gate voltage VGL2 to the gate output node NGS in response to the voltage of the second control node NQ2, and may output a high gate voltage VGH to the gate output node NGS in response to the voltage of the inverted control node NQB. Specifically, when the inverted control node NQB has a low level, the eighth transistor T8 may output the high gate voltage VGH to the gate output node NGS in response to the inverted control node NQB having a low level. Furthermore, when the second control node NQ2 has a low level, the seventh transistor T7 may output the second low gate voltage VGL2 to the gate output node NGS in response to the second control node NQ2 having a low level.

[0178] In an embodiment, when the inverted control node NQB has a second low gate voltage VGL2, the eighth transistor T8 may output the high gate voltage VGH to the gate output node NGS in response to the inverted control node NQB having the second low gate voltage VGL2. The gate output node NGS may have the high gate voltage VGH.

[0179] In an embodiment, when the voltage of the gate output node NGS changes, the voltage of the second control node NQ2 may be bootstrapped while the stored voltage is maintained between the two electrodes of the first capacitor C1. When the voltage of the gate output node NGS decreases from the high gate voltage VGH to the second low gate voltage VGL2, the voltage of the second control node NQ2 may be bootstrapped to a third low gate voltage VGL3 lower than the second low gate voltage VGL2.

[0180] In an embodiment, since the bootstrap voltage of the second control node NQ2 is a voltage lower than the second low gate voltage VGL2, the fifth transistor T5 and the seventh transistor T7 can be fully turned on, and the operation reliability of the fifth transistor T5 and the seventh transistor T7 can be improved.

[0181] In an embodiment, the voltage limiting circuit 820 can limit the voltages of the control nodes NQ1 and NQ2 based on the low limit voltage VGL_P. Specifically, the voltage limiting circuit 820 can limit the voltage flow of the bootstrap voltage of the second control node NQ2 transmitted to the first control node NQ1, and the bootstrap voltage of the second control node NQ2 can be maintained. The operation reliability of the fifth transistor T5 and the seventh transistor T7 can be further improved.

[0182] In an embodiment, and as Figure 13 shown, the threshold voltage of the second transistor T2 can be -2V, and the low limit voltage VGL_P can be -5V. However, Figure 13 the voltages shown are set to describe the operation of the voltage limiting circuit 820 and are not directly related to each stage 800 of Figure 11 and Figure 12 .

[0183] Figure 13 The embodiment shown represents a case where the bootstrap voltage of the second control node NQ2 is at a low level. When the voltage of the first control node NQ1 is -3V and the bootstrap voltage of the second control node NQ2 is -16V, the gate-source voltage of the second transistor T2 can be -2V. Since the gate-source voltage of the second transistor T2 is not lower than the threshold voltage of the second transistor T2, the second transistor T2 can be turned off, and the bootstrap voltage of the second control node NQ2 can not be transmitted to the first control node NQ1. Therefore, the bootstrap voltage of the second control node NQ2 can be maintained at -16V. The operation reliability of the fifth transistor T5 and the seventh transistor T7 can be further improved.

[0184] In an embodiment, since the gate output circuit 850 outputs a high gate voltage VGH and a second low gate voltage VGL2, the performance of the gate driver 130 can be improved. In addition, since the voltage swing width between the high gate voltage VGH received by the carry output circuit 840 and the first low gate voltage VGL1 is smaller than the voltage swing width between the high gate voltage VGH received by the gate output circuit 850 and the second low gate voltage VGL2, the power consumption of the gate driver 130 can be reduced. Since the voltage swing width between the high gate voltage VGH and the first low gate voltage VGL1 of the input signal FLM / PCR is smaller than the voltage swing width between the high gate voltage VGH received by the gate output circuit 850 and the second low gate voltage VGL2, the power consumption of the gate driver 130 can be reduced.

[0185] Therefore, the carry output circuit 840 and the gate output circuit 850 are formed of PMOS transistors having high reliability and high mobility, so that the reliability of the gate driver 130 can be improved, and the useless space of the gate driver 130 can be reduced.

[0186] In addition, due to the voltage bootstrapping of the second control node NQ2, and the fifth transistor T5 and the seventh transistor T7 are fully turned on or off accordingly, the reliability of the gate driver 130 can be improved.

[0187] In addition, the bootstrapping voltage of the second control node NQ2 is maintained by the voltage limiting circuit 820, so that the reliability of the gate driver 130 can be improved.

[0188] In addition, the gate output circuit 850 outputs a high gate voltage VGH and a second low gate voltage VGL2, so that the performance of the gate driver 130 can be improved.

[0189] In addition, since the voltage swing width between the high gate voltage VGH received by the carry output circuit 840 and the first low gate voltage VGL1 is smaller than the voltage swing width between the high gate voltage VGH received by the gate output circuit 850 and the second low gate voltage VGL2, the power consumption of the gate driver 130 can be reduced.

[0190] Figure 14 is a block diagram showing an electronic device 1000 according to an embodiment. Figure 15 is shown Figure 14 a diagram of an embodiment in which the electronic device 1000 is implemented as a smart phone.

[0191] In an embodiment, and with reference to Figure 14 and Figure 15, the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Among them, the display device 1060 may be Figure 1 the display device 10. In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, and other electronic devices, etc.

[0192] In an embodiment, as Figure 15 shown, the electronic device 1000 may be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For example, in other embodiments, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart board, a smart watch, a tablet PC, a car navigation system, a computer monitor, a laptop computer, and a head-mounted display (HMD) device, etc.

[0193] In an embodiment, the processor 1010 may perform various computing functions. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0194] In an embodiment, the memory device 1020 may store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device.

[0195] In an embodiment, the storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a compact disc read-only memory (CD-ROM) device, etc.

[0196] In an embodiment, the I / O device 1040 may include input devices such as a keyboard, keypad, mouse device, touchpad, and touch screen, and output devices such as a printer and speaker. In some embodiments, the I / O device 1040 may include a display device 1060.

[0197] The power supply 1050 may provide power for the operation of the electronic device 1000.

[0198] The display device 1060 may be connected to other components via a bus or other communication link.

[0199] The present invention can be applied to any display device and any electronic device including a touch panel. For example, the present invention can be applied to mobile phones, smart phones, tablet computers, digital televisions (TVs), 3D TVs, personal computers (PCs), household appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0200] The foregoing is a description of the present invention and is not to be construed as limiting the present invention. Although some embodiments of the present invention have been described, those skilled in the art will readily understand that many modifications are possible in the present invention without departing from the novel teachings and advantages of the present invention in essence. Therefore, all such modifications are intended to be included within the scope of the present invention. Accordingly, it will be understood that the foregoing is a description of the present invention and is not to be construed as limited to the specific embodiments disclosed, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the present invention. In addition, embodiments or portions of embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A gate driver, the gate driver comprising a plurality of stages, wherein: Each of the plurality of stages comprises: a delay circuit configured to receive an input signal in response to a clock signal and output the input signal to a control node; a voltage limiting circuit configured to limit the voltage of the control node based on a high limit voltage and a low limit voltage; an inverter circuit configured to invert the voltage of the control node and output the inverted voltage to an inverting control node; a carry output circuit configured to output a first low gate voltage to a carry output node in response to the voltage of the control node, or to output a first high gate voltage to the carry output node in response to the voltage of the inverting control node; and A gate output circuit is configured to output a second low gate voltage lower than the first low gate voltage to a gate output node in response to the voltage of the control node, or to output a second high gate voltage higher than the first high gate voltage to the gate output node in response to the voltage of the inverting control node.

2. The gate driver according to claim 1, wherein: A voltage swing width between the first high gate voltage and the first low gate voltage is smaller than a voltage swing width between the second high gate voltage and the second low gate voltage.

3. The gate driver according to claim 1, wherein: The delay circuit includes a first transistor including a gate electrode for receiving the clock signal, a first electrode for receiving the input signal, and a second electrode connected to the control node.

4. The gate driver according to claim 1, wherein: The control nodes include a first control node, a second control node and a third control node, and the voltage limiting circuit includes: a second transistor including a gate electrode for receiving the high limiting voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node; and The third transistor includes a gate electrode for receiving the low limit voltage, a first electrode connected to the second control node, and a second electrode connected to the third control node.

5. The gate driver according to claim 4, wherein: The second transistor is an NMOS transistor, and the third transistor is a PMOS transistor.

6. The gate driver according to claim 1, wherein: The control nodes include a first control node, a second control node and a third control node, and the voltage limiting circuit includes: a second transistor including a gate electrode for receiving the low limit voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node; and The third transistor includes a gate electrode for receiving the high limit voltage, a first electrode connected to the second control node, and a second electrode connected to the third control node.

7. The gate driver according to claim 6, wherein: The second transistor is a PMOS transistor, and the third transistor is an NMOS transistor.

8. The gate driver according to claim 1, wherein: The high limit voltage is different from the first high gate voltage and the second high gate voltage, and the low limit voltage is different from the first low gate voltage and the second low gate voltage.

9. The gate driver according to claim 1, wherein: The high limit voltage is equal to the first high gate voltage, and the low limit voltage is equal to the first low gate voltage.

10. The gate driver according to claim 1, wherein: The high limit voltage is equal to the first high gate voltage, and the low limit voltage is equal to the second low gate voltage.

11. The gate driver according to claim 1, wherein: The high limit voltage is equal to the second high gate voltage, and the low limit voltage is equal to the first low gate voltage.

12. The gate driver according to claim 1, wherein: The high limit voltage is equal to the second high gate voltage, and the low limit voltage is equal to the second low gate voltage.

13. The gate driver according to claim 1, wherein: The inverter circuit comprises: a fourth transistor including a gate electrode connected to the control node, a first electrode configured to receive the second low gate voltage, and a second electrode connected to the inverting control node; and A fifth transistor includes a gate electrode connected to the control node, a first electrode configured to receive the second high gate voltage, and a second electrode connected to the inverting control node.

14. The gate driver according to claim 13, wherein: The fourth transistor is an NMOS transistor, and the fifth transistor is a PMOS transistor.

15. The gate driver according to claim 1, wherein: The carry output circuit comprises: a sixth transistor including a gate electrode connected to the control node, a first electrode configured to receive the first low gate voltage, and a second electrode connected to the carry output node; and A seventh transistor includes a gate electrode connected to the inverting control node, a first electrode configured to receive the first high gate voltage, and a second electrode connected to the carry output node.

16. The gate driver according to claim 1, wherein: The gate output circuit comprises: an eighth transistor including a gate electrode connected to the control node, a first electrode configured to receive the second low gate voltage, and a second electrode connected to the gate output node; and A ninth transistor includes a gate electrode connected to the inverting control node, a first electrode configured to receive the second high gate voltage, and a second electrode connected to the gate output node.

17. The gate driver according to claim 16, wherein: The gate output circuit further includes: a first capacitor including a first electrode connected to the control node and a second electrode connected to the gate output node; and A second capacitor includes a first electrode configured to receive the second high gate voltage and a second electrode connected to the inverting control node.

18. A gate driver comprising a plurality of stages, wherein: Each of the plurality of stages comprises: a delay circuit configured to receive an input signal in response to a clock signal and output the input signal to a control node; a voltage limiting circuit configured to limit a voltage of the control node based on a low limit voltage; an inverter circuit configured to invert the voltage of the control node to output the inverted voltage to an inverting control node; a carry output circuit configured to output a first low gate voltage to a carry output node in response to the voltage of the control node, or to output a high gate voltage to the carry output node in response to the voltage of the inverting control node; and a gate output circuit configured to output a second low gate voltage lower than the first low gate voltage to a gate output node in response to the voltage of the control node, or to output the high gate voltage to the gate output node in response to the voltage of the inverted control node, Wherein, the control node includes a first control node and a second control node, and the voltage limiting circuit includes: a second transistor including a gate electrode for receiving the low limit voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node, and Wherein, the inverter circuit comprises: a third transistor including a gate electrode connected to the second control node, a first electrode configured to receive the second low gate voltage, and a second electrode connected to the inverting control node; and A fourth transistor includes a gate electrode connected to the first control node, a first electrode configured to receive the high gate voltage, and a second electrode connected to the inverting control node.

19. The gate driver according to claim 18, wherein: A voltage swing width between the high gate voltage and the first low gate voltage is smaller than a voltage swing width between the high gate voltage and the second low gate voltage.

20. The gate driver according to claim 18, wherein The low limit voltage is equal to the first low gate voltage.

21. The gate driver according to claim 18, wherein: The low limit voltage is equal to the second low gate voltage.

22. The gate driver according to claim 18, wherein: The second transistor is a PMOS transistor.

23. A display device, wherein: The display device comprises: A display panel including a plurality of pixels; and a gate driver configured to provide gate signals to the plurality of pixels, Wherein, the gate driver comprises a plurality of stages, wherein each of the plurality of stages comprises: a delay circuit configured to receive an input signal having a voltage swing width between a first high gate voltage and a first low gate voltage in response to a clock signal, and output the input signal to a control node; a voltage limiting circuit configured to limit the voltage of the control node based on a high limit voltage and a low limit voltage; an inverter circuit configured to invert the voltage of the control node and output the inverted voltage to an inverting control node; a carry output circuit configured to output a carry signal to a carry output node in response to the voltage of the control node; and A gate output circuit is configured to output a second low gate voltage lower than the first low gate voltage to the gate output node in response to the voltage of the control node, or to output a second high gate voltage higher than the first high gate voltage to the gate output node in response to the voltage of the inverting control node.

24. The display device according to claim 23, wherein: The voltage swing width between the first high gate voltage and the first low gate voltage is smaller than a voltage swing width between the second high gate voltage and the second low gate voltage.

25. The display device according to claim 23, wherein: The control nodes include a first control node, a second control node and a third control node, and the voltage limiting circuit includes: a second transistor including a gate electrode configured to receive the high limiting voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node; and A third transistor includes a gate electrode configured to receive the low limit voltage, a first electrode connected to the second control node, and a second electrode connected to the third control node.

26. An electronic device, wherein: The electronic device comprises: A display panel including a plurality of pixels; a gate driver configured to provide gate signals to the plurality of pixels; a data driver configured to provide data voltages to the plurality of pixels; a driving controller configured to control the gate driver and the data driver; and a processor configured to control the drive controller, Wherein, the gate driver comprises a plurality of stages, wherein each of the plurality of stages comprises: a delay circuit configured to receive an input signal having a voltage swing width between a first high gate voltage and a first low gate voltage in response to a clock signal, and output the input signal to a control node; a voltage limiting circuit configured to limit the voltage of the control node based on a high limit voltage and a low limit voltage; an inverter circuit configured to invert the voltage of the control node and output the inverted voltage to an inverting control node; a carry output circuit configured to output a carry signal to a carry output node in response to the voltage of the control node; and A gate output circuit is configured to output a second low gate voltage lower than the first low gate voltage to the gate output node in response to the voltage of the control node, or to output a second high gate voltage higher than the first high gate voltage to the gate output node in response to the voltage of the inverting control node.

Images