Display device and operating method thereof

Abstract

The invention provides a display device and an operating method thereof. The display device comprises a pixel array, a timing controller and a source driver. The timing controller provides a bias control signal based on a pattern of screen image data. The source driver includes a latch circuit, a source channel, a source bias circuit, a charge sharing circuit, and a channel control circuit. The latch circuit provides a plurality of pixel data. The source channel provides a plurality of source voltages to the pixel array based on the pixel data. The source bias circuit provides a plurality of operating biases to the source channels based on a bias control signal. The charge sharing circuit determines whether each source channel performs charge sharing or not based on the charge sharing control signal. A channel control circuit provides the charge sharing control signals based on a comparison between rows of pixel data. Through the power saving scheme, the display device can display high image quality, and meanwhile, the power consumption is remarkably reduced, so that the endurance time of the device is prolonged.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a self-luminous type display device and an operation method thereof. Background Art

[0002] In recent years, self-luminous display technology has the advantages of low power consumption, good color performance, thin and light design, wide application, etc., and has gradually become the main product of displays. Moreover, in a self-luminous display device, charge sharing is used to reduce the overall power consumption of the display device, so as to further save the hardware cost of the display device and reduce the circuit area.

[0003] However, when charge sharing is performed on the source driver (SRC), all source channels enter the high impedance (HiZ) range, which results in additional delay, wastes the scanning time of a single horizontal line, and thus the source driver cannot reach a stable state (settle) in advance. And for an image showing a specific pattern, if charge sharing is performed on all source channels, the best power saving effect will not be achieved. Therefore, there is still considerable room for improvement in how to further improve the power saving effect of the source driver. Summary of the Invention

[0004] The present invention is directed to a display device and an operation method thereof. Based on the arrangement of pixel circuits, the driving mode can be automatically adjusted according to different image display scenarios to achieve the best power saving effect. Through these power saving solutions, the display device can significantly reduce power consumption while displaying high-quality images, thereby extending the battery life of the device.

[0005] According to an embodiment of the present invention, a display device includes a pixel array, a timing controller, and a source driver. The pixel array has a plurality of self-emitting pixel circuits. The timing controller receives picture image data to provide a plurality of sub-pixel data, and performs sub-line pixel data pattern detection on the picture image data to provide a bias control signal. The source driver includes: a first latch circuit, a second latch circuit, a plurality of source channels, a source bias circuit, a charge sharing circuit, and a channel control circuit. The first latch circuit is coupled to the timing controller to sequentially receive the sub-pixel data of a row and provide the sub-pixel data of the row and the next pixel data of the row. The second latch circuit is coupled to the first latch circuit to sequentially receive the sub-pixel data of the row and the next pixel data of the row, and provide the sub-pixel data of the row and the next sub-pixel data of the row. The source channels are coupled to the second latch circuit and the pixel array to provide a plurality of source voltages to the pixel array based on the sub-pixel data. The source bias circuit is coupled to the timing controller and the source channels to provide a plurality of operating biases to the source channels based on the bias control signal. The charge sharing circuit is coupled to the plurality of output terminals of the source channels and receives a plurality of charge sharing control signals to determine whether each of the source channels performs charge sharing based on the charge sharing control signals. The channel control circuit is coupled to the first latch circuit, the second latch circuit, the source channels, and the charge sharing circuit to provide the charge sharing control signals based on a comparison between the sub-pixel data of a row and the next sub-pixel data of the row, and provide a plurality of channel impedance signals to the source channels to determine the plurality of impedance states of the source channels.

[0006] According to an embodiment of the present invention, a method for operating a display device includes the following steps. Providing a plurality of sub-pixel data via a timing controller based on picture image data. Performing sub-line pixel data pattern detection on the picture image data via the timing controller to provide a bias control signal. Providing a plurality of source voltages to a pixel array via a plurality of source channels of a source driver based on the sub-pixel data. Providing a plurality of operating biases to the source channels via a source bias circuit of the source driver based on the bias control signal. Determining whether each of the source channels performs charge sharing via a charge sharing circuit of the source driver based on a plurality of charge sharing control signals. Providing the charge sharing control signals via a channel control circuit of the source driver based on a comparison between the sub-pixel data of a row and the next sub-pixel data of the row. Providing a plurality of channel impedance signals to the source channels via the channel control circuit of the source driver to determine the plurality of impedance states of the source channels.

[0007] Based on the above, in the display device and its operation method according to an embodiment of the present invention, the timing controller detects the pattern of the screen image data, determines whether the bias voltage of the source driver needs to be adjusted based on the detected pattern, and accordingly provides a bias voltage control signal to adjust the bias voltage of the source channel. Moreover, the channel control circuit compares the multiple sub-pixel data of each row to provide a charge sharing control signal to determine the source channel for which charge sharing is to be performed. Thus, the display device can reduce the power consumption of the source driver by adjusting the bias voltage and charge sharing, so as to further enhance the energy-saving effect.

[0008] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and detailed descriptions are made in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a system schematic diagram of a display device according to an embodiment of the present invention;

[0010] Figure 2 is a comparison schematic diagram of sub-row pixel data pattern detection according to an embodiment of the present invention;

[0011] Figure 3 is a flowchart of an operation method of a display device according to an embodiment of the present invention;

[0012] Figure 4 is a flowchart of an operation method of a display device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] Reference will now be made in detail to exemplary embodiments of the present invention. The examples of the exemplary embodiments are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] Figure 1 is a system schematic diagram of a display device according to an embodiment of the present invention. Please refer to Figure 1, in this embodiment, the display device 100 includes a timing controller 110, a source driver 120, and a pixel array 130. The source driver 120 is coupled between the timing controller 110 and the pixel array 130, and provides a plurality of source voltages Vsrc1~Vsrcn to the pixel array 130 based on the row pixel data provided by the timing controller 110 (such as the first row pixel data DATA_PR1 and the second row pixel data DATA_PR2). The pixel array 130 has a plurality of self-emitting pixel circuits arranged in an array (such as a red pixel circuit R (corresponding to the first color pixel circuit), a green pixel circuit G (corresponding to the second color pixel circuit), and a blue pixel circuit B (corresponding to the third color pixel circuit)), and the red pixel circuit R, the green pixel circuit G, and the blue pixel circuit B may be organic light-emitting diode (OLED) light-emitting pixel circuits, but the embodiments of the present invention are not limited thereto.

[0015] The timing controller 110 receives the frame image data DATAimfra, provides a plurality of sub-pixel data based on the frame image data DATAimfra (for example, including a plurality of row pixel data DATA_PRn), and performs sub-row pixel data pattern detection on the frame image data DATAimfra to determine whether the bias voltage of the source driver 120 needs to be adjusted based on the detected pattern, and accordingly provides a bias control signal SCbias.

[0016] The source driver 120 includes a source bias circuit 121, a first latch circuit 122, a second latch circuit 123, a channel control circuit 124, a source channel circuit 125, a charge sharing circuit 126, and a plurality of source output switches SWsrc1~SWsrcn, wherein the source channel circuit 125 has a plurality of source channels CH1~CHn (at least including operational amplifiers), and n is a positive integer.

[0017] The first latch circuit 122 is coupled to the timing controller 110 to sequentially receive the plurality of pixel data of each row provided by the timing controller 110, and sequentially provide the plurality of pixel data of each row received by the second latch circuit 123. The second latch circuit 123 is coupled to the first latch circuit 122 to sequentially receive the plurality of pixel data of each row, and sequentially provide the plurality of pixel data of each row of the source channels CH1~CHn.

[0018] The source channels CH1~CHn are coupled to the second latch circuit 123 and the pixel array 130 to provide a plurality of source voltages Vsrc1~Vsrcn to the pixel array 130 based on a plurality of pixel data of each received row. For example, when receiving the first row of pixel data DATA_PR1, the source voltages Vsrc1~Vsrcn are provided based on the pixel data DP11~DP1n of the first row of pixel data DATA_PR1; when receiving the second row of pixel data DATA_PR2, the source voltages Vsrc1~Vsrcn are provided based on the pixel data DP21~DP2n of the second row of pixel data DATA_PR2, and so on for the rest. The source output switches SWsrc1~SWsrcn are correspondingly coupled between the source channels CH1~CHn and the pixel array 130 to periodically conduct and provide the source voltages Vsrc1~Vsrcn to the pixel array 130.

[0019] The source bias circuit 121 is coupled to the timing controller 110 and the source channels CH1~CHn to provide operating biases Vbias_E, Vbias_O to the source channels CH1~CHn based on the bias control signal SCbias, where the operating bias Vbias_O can be provided to odd source channels (such as CH1, CH(n - 1)), and the operating bias Vbias_E can be provided to even source channels (such as CHn).

[0020] The charge sharing circuit 126 is coupled to multiple output terminals of the source channels CH1~CHn and receives a plurality of charge sharing control signals SSWcs1~SSWcsn to determine whether each of the source channels CH1~CHn performs charge sharing based on these charge sharing control signals SSWcs1~SSWcsn.

[0021] The channel control circuit 124 is coupled to the first latch circuit 122, the second latch circuit 123, the source channels CH1~CHn, and the charge sharing circuit 126 to provide these charge sharing control signals SSWcs1~SSWcsn based on the comparison of two consecutive sub-pixel data of each row, and provide a plurality of channel impedance signals CHz1~CHzn to these source channels CH1~CHn to determine the impedance state of each of these source channels CH1~CHn.

[0022] In this embodiment, the channel impedance signals CHz1~CHzn control the source channels that perform charge sharing to present a high impedance state and be idle, and control the source channels that do not perform charge sharing to selectively present a high impedance state or perform an output transition.

[0023] In this embodiment, the timing controller 110 includes a pattern detection circuit 111. The pattern detection circuit 111 performs sub - row pixel data pattern detection on the frame image data DATAimfra to generate a bias control signal SCbias. For example, when the bias control signal SCbias indicates that the odd - numbered column pixel data of the first row pixel data DATA_PR1 and the odd - numbered column pixel data of the multiple row pixel data DATA_PRn meet the first voltage - reduction condition, the source bias circuit 121 reduces the voltage level of the operating bias Vbias_O. Conversely, the operating bias Vbias_O is maintained at a predetermined voltage level.

[0024] When the bias control signal SCbias indicates that the even - numbered column pixel data of the first row pixel data DATA_PR1 and the even - numbered column pixel data of the multiple row pixel data DATA_PRn meet the second voltage - reduction condition, the source bias circuit 121 reduces a voltage level of the second operating bias Vbias_E.

[0025] According to the above, the timing controller 110 of the display device 100 detects the pattern of the frame image data DATAimfra, determines whether the bias of the source driver 120 needs to be adjusted based on the detected pattern, and provides the bias control signal SCbias to adjust the biases Vbias_E and Vbias_O of the source channels CH1~CHn. Moreover, the channel control circuit 124 of the display device 100 compares two consecutive sub - pixel data of each row to provide charge - sharing control signals SSWcs1~SSWcsn to determine the source channels CH1~CHn for which charge sharing is to be performed. Thus, the display device 100 can adjust the power consumption of the source channels CH1~CHn to further enhance the energy - saving effect.

[0026] Figure 2 is a comparison schematic diagram of sub - row pixel data pattern detection according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2, in this embodiment, each row pixel data (such as the first row pixel data DATA_PR1 and the second row pixel data DATA_PR2) can be divided into multiple groups of sub-row pixel data. For example, the row pixel data R01, R02, and R03 are respectively divided into multiple groups of sub-row pixel data (GP11, GP12, GP21, GP22, GP31, GP32). That is, the sub-row pixel data pattern detection is performed based on multiple groups of sub-row pixel data (GP11, GP12, GP21, GP22, GP31, GP32). Each group of sub-row pixel data includes one red pixel data, two green pixel data, and one blue pixel data. The red pixel data and the blue pixel data are set in odd-numbered columns, and the green pixel data is set in even-numbered columns, but the embodiments of the present invention are not limited thereto. In other words, the pixel data received by each of the odd source channels CH1, CH3, …, CH(n - 1) is formed by arranging the red pixel data (such as R1~R6) and the blue pixel data (such as B1~B6) in sequence, and the pixel data received by each of the even source channels CH2, CH4, …, CHn is formed by arranging the green pixel data (such as G1~G12) in sequence. This can be understood with reference to Figure 2 and will not be elaborated here.

[0027] Next, the sub-row pixel data GP11 is used as the reference row pixel data, and the sub-row pixel data GP12 is used as the comparison row pixel data. Similarly, the sub-row pixel data GP11 is used as the reference row pixel data, and the sub-row pixel data GP21 is used as the comparison row pixel data. The sub-row pixel data GP21 is used as the reference row pixel data, and the sub-row pixel data GP31 is used as the comparison row pixel data.

[0028] Furthermore, the pattern detection circuit 111 can compare the red pixel data R1 and the blue pixel data B1 with the red pixel data R2 and the blue pixel data B2, and determine whether the difference between the red pixel data R1 and the red pixel data R2 and the difference between the blue pixel data B1 and the blue pixel data B2 are less than the detection threshold Threshold_PD; when the difference is less than the detection threshold Threshold_PD, continue to compare the red pixel data and the blue pixel data of the sub-row pixel data in the same row; otherwise, end the comparison, that is, abandon the adjustment of the operating bias Vbias_O.

[0029] After the comparison of the in-line pixel data R01 is completely executed, the red pixel data R1 can be compared with the blue pixel data B3. Similarly, when the difference between the red pixel data R1 and the blue pixel data B3 is less than the detection threshold Threshold_PD, the comparison of the red pixel data and the blue pixel data of the sub-line pixel data of the next line is continued; otherwise, the comparison is ended, that is, the adjustment of the operating bias Vbias_O is abandoned. When the comparison of the in-line pixel data and the comparison difference of each line of pixel data are both less than the detection threshold Threshold_PD based on the above complete execution, it means that the odd-column pixel data is the same pixel data.

[0030] In other words, the sub-line pixel data GP11 is compared with GP12, the sub-line pixel data GP11 is compared with GP21, and the sub-line pixel data GP21 is compared with GP31. When the difference of each comparison is less than the detection threshold Threshold_PD, the odd-column pixel data of the first column (such as pixel data R1, B3, R5), the third column (such as pixel data B1, R3, B5), the fifth column (such as pixel data R2, B4, R6) and the seventh column (such as pixel data B2, R4, B6) meet the first step-down condition. Therefore, the bias Vbias_O can be lowered when providing the source voltage (such as Vsrc1~Vsrcn).

[0031] On the other hand, the pattern detection circuit 111 can compare the green pixel data G1 and G2 with the green pixel data G3 and G4, and determine whether the difference between the green pixel data G1 and G3 and the difference between the green pixel data G2 and G4 are less than the detection threshold Threshold_PD; when the difference is less than the detection threshold Threshold_PD, the comparison of the green pixel data of the sub-line pixel data of the same row is continued; otherwise, the comparison is ended, that is, the adjustment of the operating bias Vbias_E is abandoned.

[0032] After the comparison of the in-line pixel data R01 is completely executed, the green pixel data G1 and G2 can be compared with the green pixel data G5 and G6. Similarly, when the difference between the green pixel data G1, G2 and the green pixel data G5, G6 is less than the detection threshold Threshold_PD, the comparison of the green pixel data and the green pixel data of the sub-line pixel data of the next line is continued; otherwise, the comparison is ended, that is, the adjustment of the operating bias Vbias_E is abandoned. When the comparison of the in-line pixel data and the comparison difference of each line of pixel data are both less than the detection threshold Threshold_PD based on the above complete execution, it means that the even-column pixel data is the same pixel data.

[0033] In other words, the sub-row pixel data GP11 is compared with GP12, the sub-row pixel data GP11 is compared with GP21, and the sub-row pixel data GP21 is compared with GP31. When the difference of each comparison is less than the detection threshold Threshold_PD, the pixel data in the even columns such as the pixel data in the 2nd column (such as pixel data G1, G5, G9), the 4th column (such as pixel data G2, G6, G10), the 6th column (such as pixel data G3, G7, G11), and the 8th column (such as pixel data G4, G8, G12) meet the second step-down condition. Therefore, the bias voltage Vbias_E can be lowered when the source voltage (such as Vsrc1~Vsrcn) is provided.

[0034] In other words, the above comparison method uses a set of pixel data (for example, the first set of pixel data) of each row pixel data as a judgment benchmark to compare the sub-row pixel data. Further, the pixel data in the odd columns and the pixel data in the even columns are compared horizontally to detect whether the pixel data of the entire row pixel data is the same, and the vertically adjacent row pixel data must also be the same. After the horizontal comparison and the vertical comparison, when the pixel data in the odd columns are all the same or the pixel data in the even columns are all the same, the bias adjustment of the source driver 120 can be triggered; otherwise, when the pixel data in the odd columns are not completely the same or the pixel data in the even columns are not completely the same, the bias adjustment of the source driver 120 will not be triggered. When the condition is met, the bias currents of the source channels CH1~CHn in the odd columns and the even columns can be respectively adjusted downward to achieve the power-saving effect. Moreover, once it is detected that there is inconsistent pixel data, the trigger state will be immediately exited and restored to the original bias setting. In the embodiment of the present invention, the sub-row pixel data may only include 4 pixel data. Therefore, when comparing, it is not necessary to store the entire row of pixel data for comparison, which can save the memory space used for comparison.

[0035] The above detection of the sub-row pixel data pattern can not only achieve the power-saving effect on the black-and-white screen, but also be effective for the screen with the same pixel data in the odd and even columns. Moreover, considering that after the algorithm, the actual switching voltage difference (delta V) of the source driver 120 will be different in the solid-color screen, a multi-bit (for example, 9-bit ([9:0])) adjustable voltage difference threshold (such as the detection threshold Threshold_PD) can be added to make the system more flexible in adjustment.

[0036] Please refer to Figure 1, in this embodiment, the channel control circuit 124 includes a pixel data comparison circuit 124a, a charge sharing circuit 124b, a resistance state circuit 124c, and a control output circuit 124d. The pixel data comparison circuit 124a is coupled to the first latch circuit 122 and the second latch circuit 123 to receive a plurality of sub-pixel data for each row (such as the first row pixel data DATA_PR1 and the second row pixel data DATA_PR2). Then, the pixel data comparison circuit 124a respectively compares a plurality of first pixel data DP11~DP1n in the first row pixel data DATA_PR1 to confirm whether two consecutive sub-pixel data among the plurality of first pixel data DP11~DP1n change, so as to provide a plurality of comparison results RTcmp with a first logic level (executing charge sharing) or a second logic level (not executing charge sharing).

[0037] The charge sharing circuit 124b is coupled to the pixel data comparison circuit 124a to provide charge sharing channel signals CHcs indicating which of the source channels CH1~CHn are to perform charge sharing based on these comparison results RTcmp. For example, charge sharing is respectively performed for odd source channels CH1, CH3, …, CH(n - 1), and charge sharing is not performed for even source channels CH2, CH4, …, CHn. The resistance state circuit 124c provides a channel resistance state indication signal CHhz indicating that these source channels (such as CH2, CH4, …, CHn) that do not perform charge sharing are to present a high resistance state and be idle or perform an output state transition.

[0038] The control output circuit 124d is coupled to the charge sharing circuit 124b and the resistance state circuit 124c to receive the charge sharing channel signal CHcs and the channel resistance state indication signal CHhz. Among them, the control output circuit 124d generates charge sharing control signals SSWcs1~SSWcsn based on the charge sharing channel signal CHcs, and the control output circuit 124d provides these channel resistance state signals CHz1~CHzn based on the channel resistance state indication signal CHhz.

[0039] In an embodiment of the present invention, the pixel data comparison circuit 124a can compare at least one most significant bit of successive first row sub-pixel data DP11~DP1n respectively to provide these comparison results RTcmp. For example, when the most significant bit of the first row sub-pixel data DP11 is different from the most significant bit of the first row sub-pixel data DP12, for example, the sub-pixel data DP11 is 000 and the sub-pixel data DP12 is 111, a comparison result RTcmp of the first logic level can be provided (charge sharing is performed); when the most significant bit of the first row sub-pixel data DP11 is the same as the most significant bit of the first row sub-pixel data DP12, for example, the sub-pixel data DP11 is 100 and the sub-pixel data DP12 is 111, a comparison result RTcmp of the second logic level can be provided (charge sharing is not performed). Or, when two most significant bits of the first row sub-pixel data DP11 are not completely the same as two most significant bits of the first row sub-pixel data DP12, for example, the sub-pixel data DP11 is 100 and the sub-pixel data DP12 is 111, a comparison result RTcmp of the first logic level can be provided; when two most significant bits of the first row sub-pixel data DP11 are completely the same as two most significant bits of the first row sub-pixel data DP12, for example, the sub-pixel data DP11 is 110 and the sub-pixel data DP12 is 111, a comparison result RTcmp of the second logic level can be provided, and so on, which will not be elaborated here.

[0040] In an embodiment of the present invention, the number of bits for comparison of at least one most significant bit can be set via the charge sharing threshold signal Threshold_CS.

[0041] According to the above, in an embodiment of the present invention, it can make a judgment based on pixel data (the pixel data is, for example, 10-bit data). And by setting the digital charge sharing threshold signal Threshold_CS, it is possible to select whether a certain bit in the pixel data has changed, so as to determine whether the source channels (such as CH1~CHn) participate in charge sharing. Appropriately adjusting the value of the charge sharing threshold signal Threshold_CS can effectively distinguish the source channels CH1~CHn participating in charge sharing, further improving the efficiency.

[0042] In addition, when the source channels that need to participate in charge sharing enter the high impedance state, the operational amplifiers of the source channels that do not need to participate in charge sharing can immediately perform output transition. For this purpose, via the channel high impedance indication signal CHhz provided by the high impedance circuit 124c, it is allowed to select whether the source channels that do not participate in charge sharing enter the high impedance idle state, or directly perform output switching by the operational amplifiers of the source channels, thereby accelerating the settling time of the source channels.

[0043] In this embodiment, the charge sharing circuit 126 includes, for example, a plurality of charge sharing switches SWcs1 to SWcs and a charge sharing line LTcs. The charge sharing switches SWcs1 to SWcs are correspondingly coupled between the output ends of the source channels CH1 to CHn and the charge sharing line LTcs, and respectively receive a corresponding one of the charge sharing control signals SSWcs1 to SSWcsn to determine whether charge sharing is performed for each of the source channels CH1 to CHn.

[0044] Figure 3 It is a flowchart of an operation method of a display device according to an embodiment of the present invention. Please refer to Figure 3 , in this embodiment, the operation method of the display device includes the following steps. In step S110, a plurality of sub-pixel data are provided via a timing controller based on the frame image data. In step S120, sub-row pixel data pattern detection of the frame image data is performed via the timing controller to provide a bias control signal. In step S130, a plurality of operation biases are provided to the source channels via a source bias circuit of the source driver based on the bias control signal.

[0045] In step S140, a charge sharing control signal is provided via a channel control circuit of the source driver based on the comparison result of two consecutive sub-pixel data in each row. In step S150, it is determined via the charge sharing circuit of the source driver whether charge sharing is performed for each of the source channels based on the charge sharing control signal. In step S160, a channel impedance signal is provided to the source channels via the channel control circuit of the source driver to determine a plurality of impedance states of the source channels.

[0046] In step S170, a plurality of source voltages are provided to the pixel array via the source channels of the source driver based on the sub-pixel data.

[0047] Figure 4 It is a flowchart of an operation method of a display device according to another embodiment of the present invention. In step S201, it is compared whether the difference between the odd pixel data of each sub-pixel row data is less than a detection threshold. When the comparison result is "yes", step S202 is executed; otherwise, when the comparison result is "no", step S207 is executed. In step S202, it is compared whether the difference between the odd pixel data of each sub-pixel row data and the odd pixel data of the next sub-pixel row data is less than the detection threshold. When the comparison result is "yes", step S203 is executed; otherwise, when the comparison result is "no", step S207 is executed. In step S203, the bias of the odd source channels is adjusted, and then step S207 is executed.

[0048] In step S204, it is determined whether the difference between the even pixel data of each sub-pixel row data is less than a detection threshold. When the comparison result is "yes", step S205 is executed; conversely, when the comparison result is "no", step S207 is executed. In step S205, it is determined whether the difference between the even pixel data of each sub-pixel row data and the even pixel data of the next sub-pixel row data is less than the detection threshold. When the comparison result is "yes", step S206 is executed; conversely, when the comparison result is "no", step S207 is executed. In step S206, the bias voltage of the even source channels is adjusted downward, and then step S207 is executed.

[0049] In step S207, it is determined whether the difference between two consecutive sub-pixel data of each row is greater than a charge sharing threshold. When the comparison result is "yes", step S208 is executed; conversely, when the comparison result is "no", step S209 is executed. In step S208, it is determined that charge sharing occurs in the source channel corresponding to the sub-pixel data, and then in step S211, the source channel is switched to the output state.

[0050] In step S209, it is determined whether the source channels that do not perform charge sharing need to be in a high-impedance idle state. When the comparison result is "yes", step S210 is executed; conversely, when the comparison result is "no", step S211 is executed. In step S210, the high-impedance idle state is maintained to wait for the completion of charge sharing, and then step S211 is executed.

[0051] In summary, for the display device and its operation method according to the embodiments of the present invention, the timing controller detects the pattern of the screen image data, determines whether the bias voltage of the source driver needs to be adjusted based on the detected pattern, and accordingly provides a bias control signal to adjust the bias voltage of the source channels. Moreover, the channel control circuit compares multiple sub-pixel data of each row to provide a charge sharing control signal to determine the source channels for which charge sharing is to occur. Thus, the display device can adjust the power consumption of the source driver by reducing the bias voltage and charge sharing, thereby further improving the energy-saving effect.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, comprising: A pixel array having a plurality of self-luminous pixel circuits; A timing controller receives screen image data to provide a plurality of sub-pixel data, and performs sub-row pixel data pattern detection of the screen image data to provide a bias control signal; as well as Source driver, including: A first latch circuit is coupled to the timing controller, sequentially receives the plurality of sub-pixel data of a row, and sequentially provides the sub-pixel data of the row and the next sub-pixel data of the row; A second latch circuit, coupled to the first latch circuit, sequentially receives the plurality of sub-pixel data of the row, and sequentially provides the sub-pixel data of the row and the next sub-pixel data of the row; A plurality of source channels coupled to the second latch circuit and the pixel array to provide a plurality of source voltages to the pixel array based on the plurality of sub-pixel data; a source bias circuit coupled to the timing controller and the plurality of source channels to provide a plurality of operating biases to the plurality of source channels based on the bias control signal; a charge sharing circuit coupled to the output terminals of the plurality of source channels and receiving a plurality of charge sharing control signals to determine whether each of the plurality of source channels performs charge sharing based on the plurality of charge sharing control signals; and A channel control circuit is coupled to the first latch circuit, the second latch circuit, the multiple source channels and the charge sharing circuit to provide the multiple charge sharing control signals based on the comparison results of the sub-pixel data of the row and the next sub-pixel data of the row, and to provide multiple channel impedance signals to the multiple source channels to determine the multiple impedance states of the multiple source channels.

2. The display device according to claim 1, wherein the timing controller comprises a pattern detection circuit, which performs the sub-row pixel data pattern detection on the screen image data to generate the bias control signal, wherein the sub-row pixel data pattern detection is performed based on multiple groups of sub-row pixel data, each group of sub-row pixel data includes one red pixel data, two green pixel data and one blue pixel data.

3. The display device according to claim 2, wherein the multiple sub-pixel data received by each of the multiple odd-numbered source channels of the multiple source channels are composed of a plurality of the red pixel data and a plurality of the blue pixel data arranged in sequence, and the multiple sub-pixel data received by each of the multiple even-numbered source channels of the multiple source channels are composed of a plurality of the multiple green pixel data arranged in sequence.

4. The display device according to claim 2, wherein the source bias circuit provides a first operating bias among a plurality of operating biases to a plurality of odd-numbered source channels, and provides a second operating bias among a plurality of operating biases to a plurality of even-numbered source channels, When the bias control signal indicates that the plurality of odd pixel data of the plurality of sub-row pixel data are the same pixel data, the source bias circuit reduces the voltage level of the first operation bias, and When the bias control signal indicates that a plurality of even-numbered pixel data of the plurality of sub-row pixel data are identical pixel data, the source bias circuit reduces the voltage level of the second operation bias.

5. The display device according to claim 2, wherein the source bias circuit provides a first operating bias among a plurality of operating biases to a plurality of odd-numbered source channels, and provides a second operating bias among a plurality of operating biases to a plurality of even-numbered source channels, When a plurality of differences between a plurality of odd-numbered pixel data of the plurality of sub-row pixel data are less than a detection threshold, the source bias circuit reduces a voltage level of the first operating bias voltage, and When a plurality of difference values ​​compared between a plurality of even-numbered pixel data of the plurality of sub-row pixel data are smaller than the detection threshold, the source bias circuit reduces the voltage level of the second operation bias.

6. The display device according to claim 2, wherein the sub-row pixel data pattern is detected by dividing the multiple pixel data into multiple groups of sub-row pixel data, and using one group of sub-row pixel data as a judgment basis to compare the multiple sub-row pixel data to detect whether multiple odd pixel data of the multiple sub-pixel data and multiple even pixel data of the multiple sub-pixel data are the same.

7. The display device according to claim 1, wherein the channel control circuit comprises: A pixel data comparison circuit, coupled to the first latch circuit and the second latch circuit, to compare the sub-pixel data of the row with the next pixel data of the row, to provide a plurality of comparison results having a first logic level or a second logic level; A charge sharing circuit, coupled to the pixel data comparison circuit, to determine whether to perform charge sharing for the plurality of source channels respectively based on the plurality of comparison results, so as to provide a charge sharing channel signal; A resistance circuit, providing a channel resistance indication signal; as well as The control output circuit is coupled to the charge sharing circuit and the blocking circuit to generate the plurality of charge sharing control signals based on the charge sharing channel signal and provide the plurality of channel blocking signals based on the channel blocking indication signal.

8. The display device according to claim 7, wherein the pixel data comparison circuit compares at least one most significant bit of the sub-pixel data of the row with at least one most significant bit of the next sub-pixel data of the row to provide the plurality of comparison results.

9. The display device according to claim 8, wherein the pixel data comparison circuit compares the at least one most significant bit set by the charge sharing threshold signal in the sub-pixel data of the row with the at least one most significant bit in the next sub-pixel data of the row to provide the multiple comparison results.

10. The display device according to claim 7, wherein the channel impedance indication signal indicates that the plurality of source channels performing charge sharing are in a high impedance state, and the plurality of source channels not performing charge sharing are in the high impedance state or in an output transition state.

11. A method for operating a display device, comprising: providing a plurality of sub-pixel data based on the picture image data via a timing controller; Performing sub-row pixel data pattern detection of the screen image data via the timing controller to provide a bias control signal; Providing a plurality of source voltages to the pixel array based on the plurality of sub-pixel data via a plurality of source channels of a source driver; providing a plurality of operating bias voltages to the plurality of source channels based on the bias control signal via a source bias circuit of the source driver; Determining, via a charge sharing circuit of the source driver based on a plurality of charge sharing control signals, whether each of the plurality of source channels performs charge sharing; providing the plurality of charge sharing control signals via a channel control circuit of the source driver based on a comparison of sub-pixel data of a row with next sub-pixel data of the row; as well as The channel control circuit of the source driver provides a plurality of channel impedance signals to the plurality of source channels to determine a plurality of impedance states of the plurality of source channels.

12. The operating method according to claim 11, wherein performing the sub-row pixel data pattern detection of the screen image data via the timing controller to provide the bias control signal comprises: The sub-row pixel data pattern detection is performed on the screen image data via the pattern detection circuit of the timing controller to generate the bias control signal, wherein the sub-row pixel data pattern detection is performed based on multiple groups of sub-row pixel data, each group of sub-row pixel data includes one red pixel data, two green pixel data and one blue pixel data.

13. The operating method according to claim 12, wherein the multiple sub-pixel data received by each of the multiple odd-numbered source channels of the multiple source channels are composed of multiple red pixel data and multiple blue pixel data arranged in sequence, and the multiple sub-pixel data received by each of the multiple even-numbered source channels of the multiple source channels are composed of multiple green pixel data arranged in sequence.

14. The operating method according to claim 12, wherein the plurality of operating biases include a first operating bias provided to a plurality of odd-numbered source channels and a second operating bias provided to a plurality of even-numbered source channels, Wherein providing the plurality of operating biases to the plurality of source channels based on the bias control signal via the source bias circuit of the source driver comprises: When the bias control signal indicates that the plurality of odd-numbered pixel data of the plurality of sub-row pixel data are the same pixel data, the source bias circuit reduces the voltage level of the first operation bias; as well as When the bias control signal indicates that a plurality of even-numbered pixel data of the plurality of sub-row pixel data coincide with the same pixel data, the source bias circuit reduces the voltage level of the second operation bias.

15. The operating method according to claim 12, wherein the plurality of operating biases include a first operating bias provided to a plurality of odd-numbered source channels and a second operating bias provided to a plurality of even-numbered source channels, Wherein providing the plurality of operating biases to the plurality of source channels based on the bias control signal via the source bias circuit of the source driver comprises: When a plurality of differences between a plurality of odd-numbered pixel data of the plurality of sub-row pixel data are smaller than a detection threshold, reducing a voltage level of the first operation bias voltage via the source bias circuit; as well as When a plurality of differences between a plurality of even-numbered pixel data of the plurality of sub-row pixel data are smaller than the detection threshold, the voltage level of the second operation bias is reduced via the source bias circuit.

16. The operating method according to claim 12, wherein performing the sub-row pixel data pattern detection of the screen image data comprises: The multiple sub-pixel data are divided into multiple groups of sub-row pixel data, and one group of sub-row pixel data is used as a judgment basis to compare the multiple sub-row pixel data to detect whether the multiple odd pixel data of the multiple sub-pixel data and the multiple even pixel data of the multiple sub-pixel data are the same.

17. The operating method according to claim 11, wherein providing the plurality of charge sharing control signals based on the comparison of the sub-pixel data of the row with the next pixel data of the row via the channel control circuit of the source driver comprises: The channel control circuit of the source driver compares at least one most significant bit of the sub-pixel data of the row with at least one most significant bit of the next sub-pixel data of the row to provide a plurality of comparison results having a first logic level or a second logic level.

18. The operating method according to claim 17, wherein the channel control circuit of the source driver compares at least one most significant bit of the sub-pixel data of the row with at least one most significant bit of the next pixel data of the row to provide the plurality of comparison results, comprising: The at least one most significant bit set by the charge sharing threshold signal in the sub-pixel data of the row is compared with the at least one most significant bit of the next pixel data of the row to provide the plurality of comparison results.

19. The operating method according to claim 11, wherein the plurality of channel impedance signals control the plurality of source channels that perform charge sharing to be in a high impedance state, and control the plurality of source channels that do not perform charge sharing to be in the high impedance state or to perform an output transition state.

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